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drm/amdgpu: Use correct gfx deferred error count

In the case of parsing GFX deferred error from SMU corrected error
channel, the error count should be set to 1 instead of parsing from
MISC0 register, which is 0.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Xiang Liu and committed by
Alex Deucher
f3f05a0e 704bc361

+4 -3
+4 -3
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
··· 872 872 break; 873 873 case ACA_SMU_TYPE_CE: 874 874 bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank); 875 - ret = aca_error_cache_log_bank_error(handle, &info, 876 - bank->aca_err_type, 877 - ACA_REG__MISC0__ERRCNT(misc0)); 875 + ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 876 + (bank->aca_err_type == ACA_ERROR_TYPE_CE) ? 877 + ACA_REG__MISC0__ERRCNT(misc0) : 878 + 1); 878 879 break; 879 880 default: 880 881 return -EINVAL;