Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pci-v6.18-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci fixes from Bjorn Helgaas:
- Restore custom qcom ASPM enablement code so L1 PM Substates are
enabled as they were in v6.17 even though the PCI core now enables
just L0s and L1 by default (Bjorn Helgaas)
- Size prefetchable bridge windows only when they actually exist, to
avoid a WARN_ON() regression (Ilpo Järvinen)
* tag 'pci-v6.18-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
PCI: Do not size non-existing prefetchable window
Revert "PCI: qcom: Remove custom ASPM enablement code"
+33
-1
+32
drivers/pci/controller/dwc/pcie-qcom.c
+32
drivers/pci/controller/dwc/pcie-qcom.c
···
247
247
int (*get_resources)(struct qcom_pcie *pcie);
248
248
int (*init)(struct qcom_pcie *pcie);
249
249
int (*post_init)(struct qcom_pcie *pcie);
250
+
void (*host_post_init)(struct qcom_pcie *pcie);
250
251
void (*deinit)(struct qcom_pcie *pcie);
251
252
void (*ltssm_enable)(struct qcom_pcie *pcie);
252
253
int (*config_sid)(struct qcom_pcie *pcie);
···
1039
1038
return 0;
1040
1039
}
1041
1040
1041
+
static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata)
1042
+
{
1043
+
/*
1044
+
* Downstream devices need to be in D0 state before enabling PCI PM
1045
+
* substates.
1046
+
*/
1047
+
pci_set_power_state_locked(pdev, PCI_D0);
1048
+
pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
1049
+
1050
+
return 0;
1051
+
}
1052
+
1053
+
static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)
1054
+
{
1055
+
struct dw_pcie_rp *pp = &pcie->pci->pp;
1056
+
1057
+
pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL);
1058
+
}
1059
+
1042
1060
static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1043
1061
{
1044
1062
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
···
1332
1312
pcie->cfg->ops->deinit(pcie);
1333
1313
}
1334
1314
1315
+
static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp)
1316
+
{
1317
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1318
+
struct qcom_pcie *pcie = to_qcom_pcie(pci);
1319
+
1320
+
if (pcie->cfg->ops->host_post_init)
1321
+
pcie->cfg->ops->host_post_init(pcie);
1322
+
}
1323
+
1335
1324
static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1336
1325
.init = qcom_pcie_host_init,
1337
1326
.deinit = qcom_pcie_host_deinit,
1327
+
.post_init = qcom_pcie_host_post_init,
1338
1328
};
1339
1329
1340
1330
/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
···
1406
1376
.get_resources = qcom_pcie_get_resources_2_7_0,
1407
1377
.init = qcom_pcie_init_2_7_0,
1408
1378
.post_init = qcom_pcie_post_init_2_7_0,
1379
+
.host_post_init = qcom_pcie_host_post_init_2_7_0,
1409
1380
.deinit = qcom_pcie_deinit_2_7_0,
1410
1381
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1411
1382
.config_sid = qcom_pcie_config_sid_1_9_0,
···
1417
1386
.get_resources = qcom_pcie_get_resources_2_7_0,
1418
1387
.init = qcom_pcie_init_2_7_0,
1419
1388
.post_init = qcom_pcie_post_init_2_7_0,
1389
+
.host_post_init = qcom_pcie_host_post_init_2_7_0,
1420
1390
.deinit = qcom_pcie_deinit_2_7_0,
1421
1391
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1422
1392
};
+1
-1
drivers/pci/setup-bus.c
+1
-1
drivers/pci/setup-bus.c
···
1604
1604
pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1605
1605
additional_io_size, realloc_head);
1606
1606
1607
-
if (pref) {
1607
+
if (pref && (pref->flags & IORESOURCE_PREFETCH)) {
1608
1608
pbus_size_mem(bus,
1609
1609
IORESOURCE_MEM | IORESOURCE_PREFETCH |
1610
1610
(pref->flags & IORESOURCE_MEM_64),