+10 -3

drivers/gpu/drm/drm_drv.c

reviewed

··· 434 434 * Looks up the ioctl function in the ::ioctls table, checking for root 435 435 * previleges if so required, and dispatches to the respective function. 436 436 */ 437 437 - int drm_ioctl(struct inode *inode, struct file *filp, 437 437 + long drm_ioctl(struct file *filp, 438 438 unsigned int cmd, unsigned long arg) 439 439 { 440 440 struct drm_file *file_priv = filp->private_data; 441 441 - struct drm_device *dev = file_priv->minor->dev; 441 441 + struct drm_device *dev; 442 442 struct drm_ioctl_desc *ioctl; 443 443 drm_ioctl_t *func; 444 444 unsigned int nr = DRM_IOCTL_NR(cmd); ··· 446 446 char stack_kdata[128]; 447 447 char *kdata = NULL; 448 448 449 449 + dev = file_priv->minor->dev; 449 450 atomic_inc(&dev->ioctl_count); 450 451 atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]); 451 452 ++file_priv->ioctl_count; ··· 502 501 goto err_i1; 503 502 } 504 503 } 505 505 - retcode = func(dev, kdata, file_priv); 504 504 + if (ioctl->flags & DRM_UNLOCKED) 505 505 + retcode = func(dev, kdata, file_priv); 506 506 + else { 507 507 + lock_kernel(); 508 508 + retcode = func(dev, kdata, file_priv); 509 509 + unlock_kernel(); 510 510 + } 506 511 507 512 if (cmd & IOC_OUT) { 508 513 if (copy_to_user((void __user *)arg, kdata,

+1 -1

drivers/gpu/drm/drm_edid.c

reviewed

··· 913 913 const int rates[] = { 60, 85, 75, 60, 50 }; 914 914 915 915 for (i = 0; i < 4; i++) { 916 916 - int width, height; 916 916 + int uninitialized_var(width), height; 917 917 cvt = &(timing->data.other_data.data.cvt[i]); 918 918 919 919 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 8) + 1) * 2;

+30 -59

drivers/gpu/drm/drm_ioc32.c

reviewed

··· 104 104 &version->desc)) 105 105 return -EFAULT; 106 106 107 107 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 107 107 + err = drm_ioctl(file, 108 108 DRM_IOCTL_VERSION, (unsigned long)version); 109 109 if (err) 110 110 return err; ··· 145 145 &u->unique)) 146 146 return -EFAULT; 147 147 148 148 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 149 149 - DRM_IOCTL_GET_UNIQUE, (unsigned long)u); 148 148 + err = drm_ioctl(file, DRM_IOCTL_GET_UNIQUE, (unsigned long)u); 150 149 if (err) 151 150 return err; 152 151 ··· 173 174 &u->unique)) 174 175 return -EFAULT; 175 176 176 176 - return drm_ioctl(file->f_path.dentry->d_inode, file, 177 177 - DRM_IOCTL_SET_UNIQUE, (unsigned long)u); 177 177 + return drm_ioctl(file, DRM_IOCTL_SET_UNIQUE, (unsigned long)u); 178 178 } 179 179 180 180 typedef struct drm_map32 { ··· 203 205 if (__put_user(idx, &map->offset)) 204 206 return -EFAULT; 205 207 206 206 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 207 207 - DRM_IOCTL_GET_MAP, (unsigned long)map); 208 208 + err = drm_ioctl(file, DRM_IOCTL_GET_MAP, (unsigned long)map); 208 209 if (err) 209 210 return err; 210 211 ··· 243 246 || __put_user(m32.flags, &map->flags)) 244 247 return -EFAULT; 245 248 246 246 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 247 247 - DRM_IOCTL_ADD_MAP, (unsigned long)map); 249 249 + err = drm_ioctl(file, DRM_IOCTL_ADD_MAP, (unsigned long)map); 248 250 if (err) 249 251 return err; 250 252 ··· 280 284 if (__put_user((void *)(unsigned long)handle, &map->handle)) 281 285 return -EFAULT; 282 286 283 283 - return drm_ioctl(file->f_path.dentry->d_inode, file, 284 284 - DRM_IOCTL_RM_MAP, (unsigned long)map); 287 287 + return drm_ioctl(file, DRM_IOCTL_RM_MAP, (unsigned long)map); 285 288 } 286 289 287 290 typedef struct drm_client32 { ··· 309 314 if (__put_user(idx, &client->idx)) 310 315 return -EFAULT; 311 316 312 312 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 313 313 - DRM_IOCTL_GET_CLIENT, (unsigned long)client); 317 317 + err = drm_ioctl(file, DRM_IOCTL_GET_CLIENT, (unsigned long)client); 314 318 if (err) 315 319 return err; 316 320 ··· 345 351 if (!access_ok(VERIFY_WRITE, stats, sizeof(*stats))) 346 352 return -EFAULT; 347 353 348 348 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 349 349 - DRM_IOCTL_GET_STATS, (unsigned long)stats); 354 354 + err = drm_ioctl(file, DRM_IOCTL_GET_STATS, (unsigned long)stats); 350 355 if (err) 351 356 return err; 352 357 ··· 388 395 || __put_user(agp_start, &buf->agp_start)) 389 396 return -EFAULT; 390 397 391 391 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 392 392 - DRM_IOCTL_ADD_BUFS, (unsigned long)buf); 398 398 + err = drm_ioctl(file, DRM_IOCTL_ADD_BUFS, (unsigned long)buf); 393 399 if (err) 394 400 return err; 395 401 ··· 419 427 || __put_user(b32.high_mark, &buf->high_mark)) 420 428 return -EFAULT; 421 429 422 422 - return drm_ioctl(file->f_path.dentry->d_inode, file, 423 423 - DRM_IOCTL_MARK_BUFS, (unsigned long)buf); 430 430 + return drm_ioctl(file, DRM_IOCTL_MARK_BUFS, (unsigned long)buf); 424 431 } 425 432 426 433 typedef struct drm_buf_info32 { ··· 460 469 || __put_user(list, &request->list)) 461 470 return -EFAULT; 462 471 463 463 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 464 464 - DRM_IOCTL_INFO_BUFS, (unsigned long)request); 472 472 + err = drm_ioctl(file, DRM_IOCTL_INFO_BUFS, (unsigned long)request); 465 473 if (err) 466 474 return err; 467 475 ··· 521 531 || __put_user(list, &request->list)) 522 532 return -EFAULT; 523 533 524 524 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 525 525 - DRM_IOCTL_MAP_BUFS, (unsigned long)request); 534 534 + err = drm_ioctl(file, DRM_IOCTL_MAP_BUFS, (unsigned long)request); 526 535 if (err) 527 536 return err; 528 537 ··· 567 578 &request->list)) 568 579 return -EFAULT; 569 580 570 570 - return drm_ioctl(file->f_path.dentry->d_inode, file, 571 571 - DRM_IOCTL_FREE_BUFS, (unsigned long)request); 581 581 + return drm_ioctl(file, DRM_IOCTL_FREE_BUFS, (unsigned long)request); 572 582 } 573 583 574 584 typedef struct drm_ctx_priv_map32 { ··· 593 605 &request->handle)) 594 606 return -EFAULT; 595 607 596 596 - return drm_ioctl(file->f_path.dentry->d_inode, file, 597 597 - DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request); 608 608 + return drm_ioctl(file, DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request); 598 609 } 599 610 600 611 static int compat_drm_getsareactx(struct file *file, unsigned int cmd, ··· 615 628 if (__put_user(ctx_id, &request->ctx_id)) 616 629 return -EFAULT; 617 630 618 618 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 619 619 - DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request); 631 631 + err = drm_ioctl(file, DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request); 620 632 if (err) 621 633 return err; 622 634 ··· 650 664 &res->contexts)) 651 665 return -EFAULT; 652 666 653 653 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 654 654 - DRM_IOCTL_RES_CTX, (unsigned long)res); 667 667 + err = drm_ioctl(file, DRM_IOCTL_RES_CTX, (unsigned long)res); 655 668 if (err) 656 669 return err; 657 670 ··· 703 718 &d->request_sizes)) 704 719 return -EFAULT; 705 720 706 706 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 707 707 - DRM_IOCTL_DMA, (unsigned long)d); 721 721 + err = drm_ioctl(file, DRM_IOCTL_DMA, (unsigned long)d); 708 722 if (err) 709 723 return err; 710 724 ··· 735 751 if (put_user(m32.mode, &mode->mode)) 736 752 return -EFAULT; 737 753 738 738 - return drm_ioctl(file->f_path.dentry->d_inode, file, 739 739 - DRM_IOCTL_AGP_ENABLE, (unsigned long)mode); 754 754 + return drm_ioctl(file, DRM_IOCTL_AGP_ENABLE, (unsigned long)mode); 740 755 } 741 756 742 757 typedef struct drm_agp_info32 { ··· 764 781 if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) 765 782 return -EFAULT; 766 783 767 767 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 768 768 - DRM_IOCTL_AGP_INFO, (unsigned long)info); 784 784 + err = drm_ioctl(file, DRM_IOCTL_AGP_INFO, (unsigned long)info); 769 785 if (err) 770 786 return err; 771 787 ··· 809 827 || __put_user(req32.type, &request->type)) 810 828 return -EFAULT; 811 829 812 812 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 813 813 - DRM_IOCTL_AGP_ALLOC, (unsigned long)request); 830 830 + err = drm_ioctl(file, DRM_IOCTL_AGP_ALLOC, (unsigned long)request); 814 831 if (err) 815 832 return err; 816 833 817 834 if (__get_user(req32.handle, &request->handle) 818 835 || __get_user(req32.physical, &request->physical) 819 836 || copy_to_user(argp, &req32, sizeof(req32))) { 820 820 - drm_ioctl(file->f_path.dentry->d_inode, file, 821 821 - DRM_IOCTL_AGP_FREE, (unsigned long)request); 837 837 + drm_ioctl(file, DRM_IOCTL_AGP_FREE, (unsigned long)request); 822 838 return -EFAULT; 823 839 } 824 840 ··· 836 856 || __put_user(handle, &request->handle)) 837 857 return -EFAULT; 838 858 839 839 - return drm_ioctl(file->f_path.dentry->d_inode, file, 840 840 - DRM_IOCTL_AGP_FREE, (unsigned long)request); 859 859 + return drm_ioctl(file, DRM_IOCTL_AGP_FREE, (unsigned long)request); 841 860 } 842 861 843 862 typedef struct drm_agp_binding32 { ··· 860 881 || __put_user(req32.offset, &request->offset)) 861 882 return -EFAULT; 862 883 863 863 - return drm_ioctl(file->f_path.dentry->d_inode, file, 864 864 - DRM_IOCTL_AGP_BIND, (unsigned long)request); 884 884 + return drm_ioctl(file, DRM_IOCTL_AGP_BIND, (unsigned long)request); 865 885 } 866 886 867 887 static int compat_drm_agp_unbind(struct file *file, unsigned int cmd, ··· 876 898 || __put_user(handle, &request->handle)) 877 899 return -EFAULT; 878 900 879 879 - return drm_ioctl(file->f_path.dentry->d_inode, file, 880 880 - DRM_IOCTL_AGP_UNBIND, (unsigned long)request); 901 901 + return drm_ioctl(file, DRM_IOCTL_AGP_UNBIND, (unsigned long)request); 881 902 } 882 903 #endif /* __OS_HAS_AGP */ 883 904 ··· 900 923 || __put_user(x, &request->size)) 901 924 return -EFAULT; 902 925 903 903 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 904 904 - DRM_IOCTL_SG_ALLOC, (unsigned long)request); 926 926 + err = drm_ioctl(file, DRM_IOCTL_SG_ALLOC, (unsigned long)request); 905 927 if (err) 906 928 return err; 907 929 ··· 926 950 || __put_user(x << PAGE_SHIFT, &request->handle)) 927 951 return -EFAULT; 928 952 929 929 - return drm_ioctl(file->f_path.dentry->d_inode, file, 930 930 - DRM_IOCTL_SG_FREE, (unsigned long)request); 953 953 + return drm_ioctl(file, DRM_IOCTL_SG_FREE, (unsigned long)request); 931 954 } 932 955 933 956 #if defined(CONFIG_X86) || defined(CONFIG_IA64) ··· 956 981 __put_user(update32.data, &request->data)) 957 982 return -EFAULT; 958 983 959 959 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 960 960 - DRM_IOCTL_UPDATE_DRAW, (unsigned long)request); 984 984 + err = drm_ioctl(file, DRM_IOCTL_UPDATE_DRAW, (unsigned long)request); 961 985 return err; 962 986 } 963 987 #endif ··· 997 1023 || __put_user(req32.request.signal, &request->request.signal)) 998 1024 return -EFAULT; 999 1025 1000 1000 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 1001 1001 - DRM_IOCTL_WAIT_VBLANK, (unsigned long)request); 1026 1026 + err = drm_ioctl(file, DRM_IOCTL_WAIT_VBLANK, (unsigned long)request); 1002 1027 if (err) 1003 1028 return err; 1004 1029 ··· 1067 1094 * than always failing. 1068 1095 */ 1069 1096 if (nr >= ARRAY_SIZE(drm_compat_ioctls)) 1070 1070 - return drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 1097 1097 + return drm_ioctl(filp, cmd, arg); 1071 1098 1072 1099 fn = drm_compat_ioctls[nr]; 1073 1100 1074 1074 - lock_kernel(); /* XXX for now */ 1075 1101 if (fn != NULL) 1076 1102 ret = (*fn) (filp, cmd, arg); 1077 1103 else 1078 1078 - ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 1079 1079 - unlock_kernel(); 1104 1104 + ret = drm_ioctl(filp, cmd, arg); 1080 1105 1081 1106 return ret; 1082 1107 }

+2 -2

drivers/gpu/drm/drm_mm.c

reviewed

··· 358 358 if (entry->size >= size + wasted) { 359 359 if (!best_match) 360 360 return entry; 361 361 - if (size < best_size) { 361 361 + if (entry->size < best_size) { 362 362 best = entry; 363 363 best_size = entry->size; 364 364 } ··· 408 408 if (entry->size >= size + wasted) { 409 409 if (!best_match) 410 410 return entry; 411 411 - if (size < best_size) { 411 411 + if (entry->size < best_size) { 412 412 best = entry; 413 413 best_size = entry->size; 414 414 }

+5

drivers/gpu/drm/i2c/ch7006_drv.c

reviewed

··· 408 408 409 409 ch7006_info(client, "Detected version ID: %x\n", val); 410 410 411 411 + /* I don't know what this is for, but otherwise I get no 412 412 + * signal. 413 413 + */ 414 414 + ch7006_write(client, 0x3d, 0x0); 415 415 + 411 416 return 0; 412 417 413 418 fail:

-5

drivers/gpu/drm/i2c/ch7006_mode.c

reviewed

··· 427 427 ch7006_load_reg(client, state, CH7006_SUBC_INC7); 428 428 ch7006_load_reg(client, state, CH7006_PLL_CONTROL); 429 429 ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0); 430 430 - 431 431 - /* I don't know what this is for, but otherwise I get no 432 432 - * signal. 433 433 - */ 434 434 - ch7006_write(client, 0x3d, 0x0); 435 430 } 436 431 437 432 void ch7006_state_save(struct i2c_client *client,

+1 -1

drivers/gpu/drm/i810/i810_dma.c

reviewed

··· 115 115 static const struct file_operations i810_buffer_fops = { 116 116 .open = drm_open, 117 117 .release = drm_release, 118 118 - .ioctl = drm_ioctl, 118 118 + .unlocked_ioctl = drm_ioctl, 119 119 .mmap = i810_mmap_buffers, 120 120 .fasync = drm_fasync, 121 121 };

+1 -1

drivers/gpu/drm/i810/i810_drv.c

reviewed

··· 59 59 .owner = THIS_MODULE, 60 60 .open = drm_open, 61 61 .release = drm_release, 62 62 - .ioctl = drm_ioctl, 62 62 + .unlocked_ioctl = drm_ioctl, 63 63 .mmap = drm_mmap, 64 64 .poll = drm_poll, 65 65 .fasync = drm_fasync,

+1 -1

drivers/gpu/drm/i830/i830_dma.c

reviewed

··· 117 117 static const struct file_operations i830_buffer_fops = { 118 118 .open = drm_open, 119 119 .release = drm_release, 120 120 - .ioctl = drm_ioctl, 120 120 + .unlocked_ioctl = drm_ioctl, 121 121 .mmap = i830_mmap_buffers, 122 122 .fasync = drm_fasync, 123 123 };

+1 -1

drivers/gpu/drm/i830/i830_drv.c

reviewed

··· 70 70 .owner = THIS_MODULE, 71 71 .open = drm_open, 72 72 .release = drm_release, 73 73 - .ioctl = drm_ioctl, 73 73 + .unlocked_ioctl = drm_ioctl, 74 74 .mmap = drm_mmap, 75 75 .poll = drm_poll, 76 76 .fasync = drm_fasync,

+1 -1

drivers/gpu/drm/i915/i915_drv.c

reviewed

··· 329 329 .owner = THIS_MODULE, 330 330 .open = drm_open, 331 331 .release = drm_release, 332 332 - .ioctl = drm_ioctl, 332 332 + .unlocked_ioctl = drm_ioctl, 333 333 .mmap = drm_gem_mmap, 334 334 .poll = drm_poll, 335 335 .fasync = drm_fasync,

+10 -13

drivers/gpu/drm/i915/i915_ioc32.c

reviewed

··· 66 66 &batchbuffer->cliprects)) 67 67 return -EFAULT; 68 68 69 69 - return drm_ioctl(file->f_path.dentry->d_inode, file, 70 70 - DRM_IOCTL_I915_BATCHBUFFER, 69 69 + return drm_ioctl(file, DRM_IOCTL_I915_BATCHBUFFER, 71 70 (unsigned long)batchbuffer); 72 71 } 73 72 ··· 101 102 &cmdbuffer->cliprects)) 102 103 return -EFAULT; 103 104 104 104 - return drm_ioctl(file->f_path.dentry->d_inode, file, 105 105 - DRM_IOCTL_I915_CMDBUFFER, (unsigned long)cmdbuffer); 105 105 + return drm_ioctl(file, DRM_IOCTL_I915_CMDBUFFER, 106 106 + (unsigned long)cmdbuffer); 106 107 } 107 108 108 109 typedef struct drm_i915_irq_emit32 { ··· 124 125 &request->irq_seq)) 125 126 return -EFAULT; 126 127 127 127 - return drm_ioctl(file->f_path.dentry->d_inode, file, 128 128 - DRM_IOCTL_I915_IRQ_EMIT, (unsigned long)request); 128 128 + return drm_ioctl(file, DRM_IOCTL_I915_IRQ_EMIT, 129 129 + (unsigned long)request); 129 130 } 130 131 typedef struct drm_i915_getparam32 { 131 132 int param; ··· 148 149 &request->value)) 149 150 return -EFAULT; 150 151 151 151 - return drm_ioctl(file->f_path.dentry->d_inode, file, 152 152 - DRM_IOCTL_I915_GETPARAM, (unsigned long)request); 152 152 + return drm_ioctl(file, DRM_IOCTL_I915_GETPARAM, 153 153 + (unsigned long)request); 153 154 } 154 155 155 156 typedef struct drm_i915_mem_alloc32 { ··· 177 178 &request->region_offset)) 178 179 return -EFAULT; 179 180 180 180 - return drm_ioctl(file->f_path.dentry->d_inode, file, 181 181 - DRM_IOCTL_I915_ALLOC, (unsigned long)request); 181 181 + return drm_ioctl(file, DRM_IOCTL_I915_ALLOC, 182 182 + (unsigned long)request); 182 183 } 183 184 184 185 drm_ioctl_compat_t *i915_compat_ioctls[] = { ··· 210 211 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls)) 211 212 fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE]; 212 213 213 213 - lock_kernel(); /* XXX for now */ 214 214 if (fn != NULL) 215 215 ret = (*fn) (filp, cmd, arg); 216 216 else 217 217 - ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 218 218 - unlock_kernel(); 217 217 + ret = drm_ioctl(filp, cmd, arg); 219 218 220 219 return ret; 221 220 }

+1 -1

drivers/gpu/drm/mga/mga_drv.c

reviewed

··· 68 68 .owner = THIS_MODULE, 69 69 .open = drm_open, 70 70 .release = drm_release, 71 71 - .ioctl = drm_ioctl, 71 71 + .unlocked_ioctl = drm_ioctl, 72 72 .mmap = drm_mmap, 73 73 .poll = drm_poll, 74 74 .fasync = drm_fasync,

+4 -9

drivers/gpu/drm/mga/mga_ioc32.c

reviewed

··· 100 100 if (err) 101 101 return -EFAULT; 102 102 103 103 - return drm_ioctl(file->f_path.dentry->d_inode, file, 104 104 - DRM_IOCTL_MGA_INIT, (unsigned long)init); 103 103 + return drm_ioctl(file, DRM_IOCTL_MGA_INIT, (unsigned long)init); 105 104 } 106 105 107 106 typedef struct drm_mga_getparam32 { ··· 124 125 &getparam->value)) 125 126 return -EFAULT; 126 127 127 127 - return drm_ioctl(file->f_path.dentry->d_inode, file, 128 128 - DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam); 128 128 + return drm_ioctl(file, DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam); 129 129 } 130 130 131 131 typedef struct drm_mga_drm_bootstrap32 { ··· 164 166 || __put_user(dma_bootstrap32.agp_size, &dma_bootstrap->agp_size)) 165 167 return -EFAULT; 166 168 167 167 - err = drm_ioctl(file->f_path.dentry->d_inode, file, 168 168 - DRM_IOCTL_MGA_DMA_BOOTSTRAP, 169 169 + err = drm_ioctl(file, DRM_IOCTL_MGA_DMA_BOOTSTRAP, 169 170 (unsigned long)dma_bootstrap); 170 171 if (err) 171 172 return err; ··· 217 220 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls)) 218 221 fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE]; 219 222 220 220 - lock_kernel(); /* XXX for now */ 221 223 if (fn != NULL) 222 224 ret = (*fn) (filp, cmd, arg); 223 225 else 224 224 - ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 225 225 - unlock_kernel(); 226 226 + ret = drm_ioctl(filp, cmd, arg); 226 227 227 228 return ret; 228 229 }

+3 -2

drivers/gpu/drm/nouveau/Makefile

reviewed

··· 8 8 nouveau_sgdma.o nouveau_dma.o \ 9 9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \ 10 10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ 11 11 - nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ 12 12 - nouveau_dp.o \ 11 11 + nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ 12 12 + nouveau_dp.o nouveau_grctx.o \ 13 13 nv04_timer.o \ 14 14 nv04_mc.o nv40_mc.o nv50_mc.o \ 15 15 nv04_fb.o nv10_fb.o nv40_fb.o \ 16 16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \ 17 17 nv04_graph.o nv10_graph.o nv20_graph.o \ 18 18 nv40_graph.o nv50_graph.o \ 19 19 + nv40_grctx.o \ 19 20 nv04_instmem.o nv50_instmem.o \ 20 21 nv50_crtc.o nv50_dac.o nv50_sor.o \ 21 22 nv50_cursor.o nv50_display.o nv50_fbcon.o \

+302 -319

drivers/gpu/drm/nouveau/nouveau_bios.c

reviewed

··· 181 181 const char desc[8]; 182 182 void (*loadbios)(struct drm_device *, uint8_t *); 183 183 const bool rw; 184 184 - int score; 185 184 }; 186 185 187 186 static struct methods nv04_methods[] = { 188 187 { "PROM", load_vbios_prom, false }, 189 188 { "PRAMIN", load_vbios_pramin, true }, 190 189 { "PCIROM", load_vbios_pci, true }, 191 191 - { } 192 190 }; 193 191 194 192 static struct methods nv50_methods[] = { 195 193 { "PRAMIN", load_vbios_pramin, true }, 196 194 { "PROM", load_vbios_prom, false }, 197 195 { "PCIROM", load_vbios_pci, true }, 198 198 - { } 199 196 }; 197 197 + 198 198 + #define METHODCNT 3 200 199 201 200 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 202 201 { 203 202 struct drm_nouveau_private *dev_priv = dev->dev_private; 204 204 - struct methods *methods, *method; 203 203 + struct methods *methods; 204 204 + int i; 205 205 int testscore = 3; 206 206 + int scores[METHODCNT]; 206 207 207 208 if (nouveau_vbios) { 208 208 - method = nv04_methods; 209 209 - while (method->loadbios) { 210 210 - if (!strcasecmp(nouveau_vbios, method->desc)) 209 209 + methods = nv04_methods; 210 210 + for (i = 0; i < METHODCNT; i++) 211 211 + if (!strcasecmp(nouveau_vbios, methods[i].desc)) 211 212 break; 212 212 - method++; 213 213 - } 214 213 215 215 - if (method->loadbios) { 214 214 + if (i < METHODCNT) { 216 215 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 217 217 - method->desc); 216 216 + methods[i].desc); 218 217 219 219 - method->loadbios(dev, data); 220 220 - if (score_vbios(dev, data, method->rw)) 218 218 + methods[i].loadbios(dev, data); 219 219 + if (score_vbios(dev, data, methods[i].rw)) 221 220 return true; 222 221 } 223 222 ··· 228 229 else 229 230 methods = nv50_methods; 230 231 231 231 - method = methods; 232 232 - while (method->loadbios) { 232 232 + for (i = 0; i < METHODCNT; i++) { 233 233 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 234 234 - method->desc); 234 234 + methods[i].desc); 235 235 data[0] = data[1] = 0; /* avoid reuse of previous image */ 236 236 - method->loadbios(dev, data); 237 237 - method->score = score_vbios(dev, data, method->rw); 238 238 - if (method->score == testscore) 236 236 + methods[i].loadbios(dev, data); 237 237 + scores[i] = score_vbios(dev, data, methods[i].rw); 238 238 + if (scores[i] == testscore) 239 239 return true; 240 240 - method++; 241 240 } 242 241 243 242 while (--testscore > 0) { 244 244 - method = methods; 245 245 - while (method->loadbios) { 246 246 - if (method->score == testscore) { 243 243 + for (i = 0; i < METHODCNT; i++) { 244 244 + if (scores[i] == testscore) { 247 245 NV_TRACE(dev, "Using BIOS image from %s\n", 248 248 - method->desc); 249 249 - method->loadbios(dev, data); 246 246 + methods[i].desc); 247 247 + methods[i].loadbios(dev, data); 250 248 return true; 251 249 } 252 252 - method++; 253 250 } 254 251 } 255 252 ··· 256 261 struct init_tbl_entry { 257 262 char *name; 258 263 uint8_t id; 259 259 - int length; 260 260 - int length_offset; 261 261 - int length_multiplier; 262 262 - bool (*handler)(struct nvbios *, uint16_t, struct init_exec *); 264 264 + int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 263 265 }; 264 266 265 267 struct bit_entry { ··· 812 820 } 813 821 } 814 822 815 815 - static bool 823 823 + static int 816 824 init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 817 825 struct init_exec *iexec) 818 826 { ··· 844 852 uint32_t reg = ROM32(bios->data[offset + 7]); 845 853 uint8_t config; 846 854 uint32_t configval; 855 855 + int len = 11 + count * 4; 847 856 848 857 if (!iexec->execute) 849 849 - return true; 858 858 + return len; 850 859 851 860 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 852 861 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", ··· 858 865 NV_ERROR(bios->dev, 859 866 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 860 867 offset, config, count); 861 861 - return false; 868 868 + return 0; 862 869 } 863 870 864 871 configval = ROM32(bios->data[offset + 11 + config * 4]); ··· 867 874 868 875 bios_wr32(bios, reg, configval); 869 876 870 870 - return true; 877 877 + return len; 871 878 } 872 879 873 873 - static bool 880 880 + static int 874 881 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 875 882 { 876 883 /* ··· 905 912 906 913 iexec->repeat = false; 907 914 908 908 - return true; 915 915 + return 2; 909 916 } 910 917 911 911 - static bool 918 918 + static int 912 919 init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 913 920 struct init_exec *iexec) 914 921 { ··· 944 951 uint32_t reg = ROM32(bios->data[offset + 8]); 945 952 uint8_t config; 946 953 uint16_t freq; 954 954 + int len = 12 + count * 2; 947 955 948 956 if (!iexec->execute) 949 949 - return true; 957 957 + return len; 950 958 951 959 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 952 960 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " ··· 960 966 NV_ERROR(bios->dev, 961 967 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 962 968 offset, config, count); 963 963 - return false; 969 969 + return 0; 964 970 } 965 971 966 972 freq = ROM16(bios->data[offset + 12 + config * 2]); ··· 980 986 981 987 setPLL(bios, reg, freq * 10); 982 988 983 983 - return true; 989 989 + return len; 984 990 } 985 991 986 986 - static bool 992 992 + static int 987 993 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 988 994 { 989 995 /* ··· 1001 1007 * we're not in repeat mode 1002 1008 */ 1003 1009 if (iexec->repeat) 1004 1004 - return false; 1010 1010 + return 0; 1005 1011 1006 1006 - return true; 1012 1012 + return 1; 1007 1013 } 1008 1014 1009 1009 - static bool 1015 1015 + static int 1010 1016 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1011 1017 { 1012 1018 /* ··· 1035 1041 uint8_t crtcdata; 1036 1042 1037 1043 if (!iexec->execute) 1038 1038 - return true; 1044 1044 + return 11; 1039 1045 1040 1046 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1041 1047 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", ··· 1054 1060 crtcdata |= (uint8_t)data; 1055 1061 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1056 1062 1057 1057 - return true; 1063 1063 + return 11; 1058 1064 } 1059 1065 1060 1060 - static bool 1066 1066 + static int 1061 1067 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1062 1068 { 1063 1069 /* ··· 1073 1079 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1074 1080 1075 1081 iexec->execute = !iexec->execute; 1076 1076 - return true; 1082 1082 + return 1; 1077 1083 } 1078 1084 1079 1079 - static bool 1085 1085 + static int 1080 1086 init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1081 1087 struct init_exec *iexec) 1082 1088 { ··· 1094 1100 uint8_t cond = bios->data[offset + 1]; 1095 1101 1096 1102 if (!iexec->execute) 1097 1097 - return true; 1103 1103 + return 2; 1098 1104 1099 1105 if (io_flag_condition_met(bios, offset, cond)) 1100 1106 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); ··· 1103 1109 iexec->execute = false; 1104 1110 } 1105 1111 1106 1106 - return true; 1112 1112 + return 2; 1107 1113 } 1108 1114 1109 1109 - static bool 1115 1115 + static int 1110 1116 init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1111 1117 struct init_exec *iexec) 1112 1118 { ··· 1134 1140 uint32_t mask = ROM32(bios->data[offset + 9]); 1135 1141 uint32_t data = ROM32(bios->data[offset + 13]); 1136 1142 uint8_t count = bios->data[offset + 17]; 1143 1143 + int len = 18 + count * 2; 1137 1144 uint32_t value; 1138 1145 int i; 1139 1146 1140 1147 if (!iexec->execute) 1141 1141 - return true; 1148 1148 + return len; 1142 1149 1143 1150 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1144 1151 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", ··· 1159 1164 bios_wr32(bios, controlreg, value); 1160 1165 } 1161 1166 1162 1162 - return true; 1167 1167 + return len; 1163 1168 } 1164 1169 1165 1165 - static bool 1170 1170 + static int 1166 1171 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1167 1172 struct init_exec *iexec) 1168 1173 { ··· 1191 1196 uint8_t shift = bios->data[offset + 5]; 1192 1197 uint8_t count = bios->data[offset + 6]; 1193 1198 uint32_t reg = ROM32(bios->data[offset + 7]); 1199 1199 + int len = 11 + count * 4; 1194 1200 uint8_t config; 1195 1201 uint32_t freq; 1196 1202 1197 1203 if (!iexec->execute) 1198 1198 - return true; 1204 1204 + return len; 1199 1205 1200 1206 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1201 1207 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1202 1208 offset, crtcport, crtcindex, mask, shift, count, reg); 1203 1209 1204 1210 if (!reg) 1205 1205 - return true; 1211 1211 + return len; 1206 1212 1207 1213 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1208 1214 if (config > count) { 1209 1215 NV_ERROR(bios->dev, 1210 1216 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1211 1217 offset, config, count); 1212 1212 - return false; 1218 1218 + return 0; 1213 1219 } 1214 1220 1215 1221 freq = ROM32(bios->data[offset + 11 + config * 4]); ··· 1220 1224 1221 1225 setPLL(bios, reg, freq); 1222 1226 1223 1223 - return true; 1227 1227 + return len; 1224 1228 } 1225 1229 1226 1226 - static bool 1230 1230 + static int 1227 1231 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1228 1232 { 1229 1233 /* ··· 1240 1244 uint32_t freq = ROM32(bios->data[offset + 5]); 1241 1245 1242 1246 if (!iexec->execute) 1243 1243 - return true; 1247 1247 + return 9; 1244 1248 1245 1249 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1246 1250 offset, reg, freq); 1247 1251 1248 1252 setPLL(bios, reg, freq); 1249 1249 - return true; 1253 1253 + return 9; 1250 1254 } 1251 1255 1252 1252 - static bool 1256 1256 + static int 1253 1257 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1254 1258 { 1255 1259 /* ··· 1273 1277 uint8_t i2c_index = bios->data[offset + 1]; 1274 1278 uint8_t i2c_address = bios->data[offset + 2]; 1275 1279 uint8_t count = bios->data[offset + 3]; 1280 1280 + int len = 4 + count * 3; 1276 1281 struct nouveau_i2c_chan *chan; 1277 1282 struct i2c_msg msg; 1278 1283 int i; 1279 1284 1280 1285 if (!iexec->execute) 1281 1281 - return true; 1286 1286 + return len; 1282 1287 1283 1288 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1284 1289 "Count: 0x%02X\n", ··· 1287 1290 1288 1291 chan = init_i2c_device_find(bios->dev, i2c_index); 1289 1292 if (!chan) 1290 1290 - return false; 1293 1293 + return 0; 1291 1294 1292 1295 for (i = 0; i < count; i++) { 1293 1296 uint8_t i2c_reg = bios->data[offset + 4 + i * 3]; ··· 1300 1303 msg.len = 1; 1301 1304 msg.buf = &value; 1302 1305 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1303 1303 - return false; 1306 1306 + return 0; 1304 1307 1305 1308 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1306 1309 "Mask: 0x%02X, Data: 0x%02X\n", ··· 1314 1317 msg.len = 1; 1315 1318 msg.buf = &value; 1316 1319 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1317 1317 - return false; 1320 1320 + return 0; 1318 1321 } 1319 1322 } 1320 1323 1321 1321 - return true; 1324 1324 + return len; 1322 1325 } 1323 1326 1324 1324 - static bool 1327 1327 + static int 1325 1328 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1326 1329 { 1327 1330 /* ··· 1343 1346 uint8_t i2c_index = bios->data[offset + 1]; 1344 1347 uint8_t i2c_address = bios->data[offset + 2]; 1345 1348 uint8_t count = bios->data[offset + 3]; 1349 1349 + int len = 4 + count * 2; 1346 1350 struct nouveau_i2c_chan *chan; 1347 1351 struct i2c_msg msg; 1348 1352 int i; 1349 1353 1350 1354 if (!iexec->execute) 1351 1351 - return true; 1355 1355 + return len; 1352 1356 1353 1357 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1354 1358 "Count: 0x%02X\n", ··· 1357 1359 1358 1360 chan = init_i2c_device_find(bios->dev, i2c_index); 1359 1361 if (!chan) 1360 1360 - return false; 1362 1362 + return 0; 1361 1363 1362 1364 for (i = 0; i < count; i++) { 1363 1365 uint8_t i2c_reg = bios->data[offset + 4 + i * 2]; ··· 1372 1374 msg.len = 1; 1373 1375 msg.buf = &data; 1374 1376 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1375 1375 - return false; 1377 1377 + return 0; 1376 1378 } 1377 1379 } 1378 1380 1379 1379 - return true; 1381 1381 + return len; 1380 1382 } 1381 1383 1382 1382 - static bool 1384 1384 + static int 1383 1385 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1384 1386 { 1385 1387 /* ··· 1399 1401 uint8_t i2c_index = bios->data[offset + 1]; 1400 1402 uint8_t i2c_address = bios->data[offset + 2]; 1401 1403 uint8_t count = bios->data[offset + 3]; 1404 1404 + int len = 4 + count; 1402 1405 struct nouveau_i2c_chan *chan; 1403 1406 struct i2c_msg msg; 1404 1407 uint8_t data[256]; 1405 1408 int i; 1406 1409 1407 1410 if (!iexec->execute) 1408 1408 - return true; 1411 1411 + return len; 1409 1412 1410 1413 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1411 1414 "Count: 0x%02X\n", ··· 1414 1415 1415 1416 chan = init_i2c_device_find(bios->dev, i2c_index); 1416 1417 if (!chan) 1417 1417 - return false; 1418 1418 + return 0; 1418 1419 1419 1420 for (i = 0; i < count; i++) { 1420 1421 data[i] = bios->data[offset + 4 + i]; ··· 1428 1429 msg.len = count; 1429 1430 msg.buf = data; 1430 1431 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1431 1431 - return false; 1432 1432 + return 0; 1432 1433 } 1433 1434 1434 1434 - return true; 1435 1435 + return len; 1435 1436 } 1436 1437 1437 1437 - static bool 1438 1438 + static int 1438 1439 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1439 1440 { 1440 1441 /* ··· 1459 1460 uint32_t reg, value; 1460 1461 1461 1462 if (!iexec->execute) 1462 1462 - return true; 1463 1463 + return 5; 1463 1464 1464 1465 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1465 1466 "Mask: 0x%02X, Data: 0x%02X\n", ··· 1467 1468 1468 1469 reg = get_tmds_index_reg(bios->dev, mlv); 1469 1470 if (!reg) 1470 1470 - return false; 1471 1471 + return 0; 1471 1472 1472 1473 bios_wr32(bios, reg, 1473 1474 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); ··· 1475 1476 bios_wr32(bios, reg + 4, value); 1476 1477 bios_wr32(bios, reg, tmdsaddr); 1477 1478 1478 1478 - return true; 1479 1479 + return 5; 1479 1480 } 1480 1481 1481 1481 - static bool 1482 1482 + static int 1482 1483 init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1483 1484 struct init_exec *iexec) 1484 1485 { ··· 1499 1500 1500 1501 uint8_t mlv = bios->data[offset + 1]; 1501 1502 uint8_t count = bios->data[offset + 2]; 1503 1503 + int len = 3 + count * 2; 1502 1504 uint32_t reg; 1503 1505 int i; 1504 1506 1505 1507 if (!iexec->execute) 1506 1506 - return true; 1508 1508 + return len; 1507 1509 1508 1510 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1509 1511 offset, mlv, count); 1510 1512 1511 1513 reg = get_tmds_index_reg(bios->dev, mlv); 1512 1514 if (!reg) 1513 1513 - return false; 1515 1515 + return 0; 1514 1516 1515 1517 for (i = 0; i < count; i++) { 1516 1518 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; ··· 1521 1521 bios_wr32(bios, reg, tmdsaddr); 1522 1522 } 1523 1523 1524 1524 - return true; 1524 1524 + return len; 1525 1525 } 1526 1526 1527 1527 - static bool 1527 1527 + static int 1528 1528 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1529 1529 struct init_exec *iexec) 1530 1530 { ··· 1547 1547 uint8_t crtcindex2 = bios->data[offset + 2]; 1548 1548 uint8_t baseaddr = bios->data[offset + 3]; 1549 1549 uint8_t count = bios->data[offset + 4]; 1550 1550 + int len = 5 + count; 1550 1551 uint8_t oldaddr, data; 1551 1552 int i; 1552 1553 1553 1554 if (!iexec->execute) 1554 1554 - return true; 1555 1555 + return len; 1555 1556 1556 1557 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1557 1558 "BaseAddr: 0x%02X, Count: 0x%02X\n", ··· 1569 1568 1570 1569 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1571 1570 1572 1572 - return true; 1571 1571 + return len; 1573 1572 } 1574 1573 1575 1575 - static bool 1574 1574 + static int 1576 1575 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1577 1576 { 1578 1577 /* ··· 1593 1592 uint8_t value; 1594 1593 1595 1594 if (!iexec->execute) 1596 1596 - return true; 1595 1595 + return 4; 1597 1596 1598 1597 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1599 1598 offset, crtcindex, mask, data); ··· 1602 1601 value |= data; 1603 1602 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1604 1603 1605 1605 - return true; 1604 1604 + return 4; 1606 1605 } 1607 1606 1608 1608 - static bool 1607 1607 + static int 1609 1608 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1610 1609 { 1611 1610 /* ··· 1622 1621 uint8_t data = bios->data[offset + 2]; 1623 1622 1624 1623 if (!iexec->execute) 1625 1625 - return true; 1624 1624 + return 3; 1626 1625 1627 1626 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1628 1627 1629 1629 - return true; 1628 1628 + return 3; 1630 1629 } 1631 1630 1632 1632 - static bool 1631 1631 + static int 1633 1632 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1634 1633 { 1635 1634 /* ··· 1646 1645 */ 1647 1646 1648 1647 uint8_t count = bios->data[offset + 1]; 1648 1648 + int len = 2 + count * 2; 1649 1649 int i; 1650 1650 1651 1651 if (!iexec->execute) 1652 1652 - return true; 1652 1652 + return len; 1653 1653 1654 1654 for (i = 0; i < count; i++) 1655 1655 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1656 1656 1657 1657 - return true; 1657 1657 + return len; 1658 1658 } 1659 1659 1660 1660 - static bool 1660 1660 + static int 1661 1661 init_condition_time(struct nvbios *bios, uint16_t offset, 1662 1662 struct init_exec *iexec) 1663 1663 { ··· 1682 1680 unsigned cnt; 1683 1681 1684 1682 if (!iexec->execute) 1685 1685 - return true; 1683 1683 + return 3; 1686 1684 1687 1685 if (retries > 100) 1688 1686 retries = 100; ··· 1713 1711 iexec->execute = false; 1714 1712 } 1715 1713 1716 1716 - return true; 1714 1714 + return 3; 1717 1715 } 1718 1716 1719 1719 - static bool 1717 1717 + static int 1720 1718 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1721 1719 struct init_exec *iexec) 1722 1720 { ··· 1736 1734 1737 1735 uint32_t basereg = ROM32(bios->data[offset + 1]); 1738 1736 uint32_t count = bios->data[offset + 5]; 1737 1737 + int len = 6 + count * 4; 1739 1738 int i; 1740 1739 1741 1740 if (!iexec->execute) 1742 1742 - return true; 1741 1741 + return len; 1743 1742 1744 1743 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1745 1744 offset, basereg, count); ··· 1752 1749 bios_wr32(bios, reg, data); 1753 1750 } 1754 1751 1755 1755 - return true; 1752 1752 + return len; 1756 1753 } 1757 1754 1758 1758 - static bool 1755 1755 + static int 1759 1756 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1760 1757 { 1761 1758 /* ··· 1771 1768 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1772 1769 1773 1770 if (!iexec->execute) 1774 1774 - return true; 1771 1771 + return 3; 1775 1772 1776 1773 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1777 1774 offset, sub_offset); ··· 1780 1777 1781 1778 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1782 1779 1783 1783 - return true; 1780 1780 + return 3; 1784 1781 } 1785 1782 1786 1786 - static bool 1783 1783 + static int 1787 1784 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1788 1785 { 1789 1786 /* ··· 1811 1808 uint32_t srcvalue, dstvalue; 1812 1809 1813 1810 if (!iexec->execute) 1814 1814 - return true; 1811 1811 + return 22; 1815 1812 1816 1813 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 1817 1814 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", ··· 1830 1827 1831 1828 bios_wr32(bios, dstreg, dstvalue | srcvalue); 1832 1829 1833 1833 - return true; 1830 1830 + return 22; 1834 1831 } 1835 1832 1836 1836 - static bool 1833 1833 + static int 1837 1834 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1838 1835 { 1839 1836 /* ··· 1851 1848 uint8_t data = bios->data[offset + 4]; 1852 1849 1853 1850 if (!iexec->execute) 1854 1854 - return true; 1851 1851 + return 5; 1855 1852 1856 1853 bios_idxprt_wr(bios, crtcport, crtcindex, data); 1857 1854 1858 1858 - return true; 1855 1855 + return 5; 1859 1856 } 1860 1857 1861 1861 - static bool 1858 1858 + static int 1862 1859 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1863 1860 { 1864 1861 /* ··· 1907 1904 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 1908 1905 1909 1906 if (dev_priv->card_type >= NV_50) 1910 1910 - return true; 1907 1907 + return 1; 1911 1908 1912 1909 /* 1913 1910 * On every card I've seen, this step gets done for us earlier in ··· 1925 1922 /* write back the saved configuration value */ 1926 1923 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 1927 1924 1928 1928 - return true; 1925 1925 + return 1; 1929 1926 } 1930 1927 1931 1931 - static bool 1928 1928 + static int 1932 1929 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1933 1930 { 1934 1931 /* ··· 1962 1959 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 1963 1960 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 1964 1961 1965 1965 - return true; 1962 1962 + return 13; 1966 1963 } 1967 1964 1968 1968 - static bool 1965 1965 + static int 1969 1966 init_configure_mem(struct nvbios *bios, uint16_t offset, 1970 1967 struct init_exec *iexec) 1971 1968 { ··· 1986 1983 uint32_t reg, data; 1987 1984 1988 1985 if (bios->major_version > 2) 1989 1989 - return false; 1986 1986 + return 0; 1990 1987 1991 1988 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 1992 1989 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); ··· 2018 2015 bios_wr32(bios, reg, data); 2019 2016 } 2020 2017 2021 2021 - return true; 2018 2018 + return 1; 2022 2019 } 2023 2020 2024 2024 - static bool 2021 2021 + static int 2025 2022 init_configure_clk(struct nvbios *bios, uint16_t offset, 2026 2023 struct init_exec *iexec) 2027 2024 { ··· 2041 2038 int clock; 2042 2039 2043 2040 if (bios->major_version > 2) 2044 2044 - return false; 2041 2041 + return 0; 2045 2042 2046 2043 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2047 2044 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); ··· 2051 2048 clock *= 2; 2052 2049 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2053 2050 2054 2054 - return true; 2051 2051 + return 1; 2055 2052 } 2056 2053 2057 2057 - static bool 2054 2054 + static int 2058 2055 init_configure_preinit(struct nvbios *bios, uint16_t offset, 2059 2056 struct init_exec *iexec) 2060 2057 { ··· 2074 2071 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2075 2072 2076 2073 if (bios->major_version > 2) 2077 2077 - return false; 2074 2074 + return 0; 2078 2075 2079 2076 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2080 2077 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2081 2078 2082 2082 - return true; 2079 2079 + return 1; 2083 2080 } 2084 2081 2085 2085 - static bool 2082 2082 + static int 2086 2083 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2087 2084 { 2088 2085 /* ··· 2102 2099 uint8_t data = bios->data[offset + 4]; 2103 2100 2104 2101 if (!iexec->execute) 2105 2105 - return true; 2102 2102 + return 5; 2106 2103 2107 2104 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2108 2105 offset, crtcport, mask, data); ··· 2161 2158 for (i = 0; i < 2; i++) 2162 2159 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2163 2160 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2164 2164 - return true; 2161 2161 + return 5; 2165 2162 } 2166 2163 2167 2164 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2168 2165 data); 2169 2169 - return true; 2166 2166 + return 5; 2170 2167 } 2171 2168 2172 2172 - static bool 2169 2169 + static int 2173 2170 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2174 2171 { 2175 2172 /* ··· 2184 2181 uint8_t sub = bios->data[offset + 1]; 2185 2182 2186 2183 if (!iexec->execute) 2187 2187 - return true; 2184 2184 + return 2; 2188 2185 2189 2186 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2190 2187 ··· 2194 2191 2195 2192 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2196 2193 2197 2197 - return true; 2194 2194 + return 2; 2198 2195 } 2199 2196 2200 2200 - static bool 2197 2197 + static int 2201 2198 init_ram_condition(struct nvbios *bios, uint16_t offset, 2202 2199 struct init_exec *iexec) 2203 2200 { ··· 2218 2215 uint8_t data; 2219 2216 2220 2217 if (!iexec->execute) 2221 2221 - return true; 2218 2218 + return 3; 2222 2219 2223 2220 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2224 2221 ··· 2232 2229 iexec->execute = false; 2233 2230 } 2234 2231 2235 2235 - return true; 2232 2232 + return 3; 2236 2233 } 2237 2234 2238 2238 - static bool 2235 2235 + static int 2239 2236 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2240 2237 { 2241 2238 /* ··· 2254 2251 uint32_t data = ROM32(bios->data[offset + 9]); 2255 2252 2256 2253 if (!iexec->execute) 2257 2257 - return true; 2254 2254 + return 13; 2258 2255 2259 2256 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2260 2257 offset, reg, mask, data); 2261 2258 2262 2259 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2263 2260 2264 2264 - return true; 2261 2261 + return 13; 2265 2262 } 2266 2263 2267 2267 - static bool 2264 2264 + static int 2268 2265 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2269 2266 { 2270 2267 /* ··· 2288 2285 int i; 2289 2286 2290 2287 if (!iexec->execute) 2291 2291 - return true; 2288 2288 + return 2; 2292 2289 2293 2290 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2294 2291 "Count: 0x%02X\n", ··· 2303 2300 bios_wr32(bios, reg, data); 2304 2301 } 2305 2302 2306 2306 - return true; 2303 2303 + return 2; 2307 2304 } 2308 2305 2309 2309 - static bool 2306 2306 + static int 2310 2307 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2311 2308 { 2312 2309 /* ··· 2318 2315 */ 2319 2316 2320 2317 /* mild retval abuse to stop parsing this table */ 2321 2321 - return false; 2318 2318 + return 0; 2322 2319 } 2323 2320 2324 2324 - static bool 2321 2321 + static int 2325 2322 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2326 2323 { 2327 2324 /* ··· 2333 2330 */ 2334 2331 2335 2332 if (iexec->execute) 2336 2336 - return true; 2333 2333 + return 1; 2337 2334 2338 2335 iexec->execute = true; 2339 2336 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2340 2337 2341 2341 - return true; 2338 2338 + return 1; 2342 2339 } 2343 2340 2344 2344 - static bool 2341 2341 + static int 2345 2342 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2346 2343 { 2347 2344 /* ··· 2356 2353 unsigned time = ROM16(bios->data[offset + 1]); 2357 2354 2358 2355 if (!iexec->execute) 2359 2359 - return true; 2356 2356 + return 3; 2360 2357 2361 2358 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2362 2359 offset, time); ··· 2366 2363 else 2367 2364 msleep((time + 900) / 1000); 2368 2365 2369 2369 - return true; 2366 2366 + return 3; 2370 2367 } 2371 2368 2372 2372 - static bool 2369 2369 + static int 2373 2370 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2374 2371 { 2375 2372 /* ··· 2386 2383 uint8_t cond = bios->data[offset + 1]; 2387 2384 2388 2385 if (!iexec->execute) 2389 2389 - return true; 2386 2386 + return 2; 2390 2387 2391 2388 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2392 2389 ··· 2397 2394 iexec->execute = false; 2398 2395 } 2399 2396 2400 2400 - return true; 2397 2397 + return 2; 2401 2398 } 2402 2399 2403 2403 - static bool 2400 2400 + static int 2404 2401 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2405 2402 { 2406 2403 /* ··· 2417 2414 uint8_t cond = bios->data[offset + 1]; 2418 2415 2419 2416 if (!iexec->execute) 2420 2420 - return true; 2417 2417 + return 2; 2421 2418 2422 2419 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2423 2420 ··· 2428 2425 iexec->execute = false; 2429 2426 } 2430 2427 2431 2431 - return true; 2428 2428 + return 2; 2432 2429 } 2433 2430 2434 2434 - static bool 2431 2431 + static int 2435 2432 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2436 2433 { 2437 2434 /* ··· 2454 2451 uint8_t value; 2455 2452 2456 2453 if (!iexec->execute) 2457 2457 - return true; 2454 2454 + return 6; 2458 2455 2459 2456 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2460 2457 "Data: 0x%02X\n", ··· 2463 2460 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2464 2461 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2465 2462 2466 2466 - return true; 2463 2463 + return 6; 2467 2464 } 2468 2465 2469 2469 - static bool 2466 2466 + static int 2470 2467 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2471 2468 { 2472 2469 /* ··· 2484 2481 uint16_t freq = ROM16(bios->data[offset + 5]); 2485 2482 2486 2483 if (!iexec->execute) 2487 2487 - return true; 2484 2484 + return 7; 2488 2485 2489 2486 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 2490 2487 2491 2488 setPLL(bios, reg, freq * 10); 2492 2489 2493 2493 - return true; 2490 2490 + return 7; 2494 2491 } 2495 2492 2496 2496 - static bool 2493 2493 + static int 2497 2494 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2498 2495 { 2499 2496 /* ··· 2510 2507 uint32_t value = ROM32(bios->data[offset + 5]); 2511 2508 2512 2509 if (!iexec->execute) 2513 2513 - return true; 2510 2510 + return 9; 2514 2511 2515 2512 if (reg == 0x000200) 2516 2513 value |= 1; 2517 2514 2518 2515 bios_wr32(bios, reg, value); 2519 2516 2520 2520 - return true; 2517 2517 + return 9; 2521 2518 } 2522 2519 2523 2523 - static bool 2520 2520 + static int 2524 2521 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 2525 2522 struct init_exec *iexec) 2526 2523 { ··· 2546 2543 uint8_t type = bios->data[offset + 1]; 2547 2544 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 2548 2545 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 2546 2546 + int len = 2 + bios->ram_restrict_group_count * 4; 2549 2547 int i; 2550 2548 2551 2549 if (!iexec->execute) 2552 2552 - return true; 2550 2550 + return len; 2553 2551 2554 2552 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 2555 2553 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 2556 2556 - return true; /* deliberate, allow default clocks to remain */ 2554 2554 + return len; /* deliberate, allow default clocks to remain */ 2557 2555 } 2558 2556 2559 2557 entry = pll_limits + pll_limits[1]; ··· 2567 2563 offset, type, reg, freq); 2568 2564 2569 2565 setPLL(bios, reg, freq); 2570 2570 - return true; 2566 2566 + return len; 2571 2567 } 2572 2568 } 2573 2569 2574 2570 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 2575 2575 - return true; 2571 2571 + return len; 2576 2572 } 2577 2573 2578 2578 - static bool 2574 2574 + static int 2579 2575 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2580 2576 { 2581 2577 /* ··· 2585 2581 * 2586 2582 */ 2587 2583 2588 2588 - return true; 2584 2584 + return 1; 2589 2585 } 2590 2586 2591 2591 - static bool 2587 2587 + static int 2592 2588 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2593 2589 { 2594 2590 /* ··· 2598 2594 * 2599 2595 */ 2600 2596 2601 2601 - return true; 2597 2597 + return 1; 2602 2598 } 2603 2599 2604 2604 - static bool 2600 2600 + static int 2605 2601 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2606 2602 { 2607 2603 /* ··· 2619 2615 const uint8_t *gpio_entry; 2620 2616 int i; 2621 2617 2618 2618 + if (!iexec->execute) 2619 2619 + return 1; 2620 2620 + 2622 2621 if (bios->bdcb.version != 0x40) { 2623 2622 NV_ERROR(bios->dev, "DCB table not version 4.0\n"); 2624 2624 - return false; 2623 2623 + return 0; 2625 2624 } 2626 2625 2627 2626 if (!bios->bdcb.gpio_table_ptr) { 2628 2627 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n"); 2629 2629 - return false; 2628 2628 + return 0; 2630 2629 } 2631 2630 2632 2631 gpio_entry = gpio_table + gpio_table[1]; ··· 2667 2660 bios_wr32(bios, r, v); 2668 2661 } 2669 2662 2670 2670 - return true; 2663 2663 + return 1; 2671 2664 } 2672 2665 2673 2673 - /* hack to avoid moving the itbl_entry array before this function */ 2674 2674 - int init_ram_restrict_zm_reg_group_blocklen; 2675 2675 - 2676 2676 - static bool 2666 2666 + static int 2677 2667 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 2678 2668 struct init_exec *iexec) 2679 2669 { ··· 2696 2692 uint8_t regincrement = bios->data[offset + 5]; 2697 2693 uint8_t count = bios->data[offset + 6]; 2698 2694 uint32_t strap_ramcfg, data; 2699 2699 - uint16_t blocklen; 2695 2695 + /* previously set by 'M' BIT table */ 2696 2696 + uint16_t blocklen = bios->ram_restrict_group_count * 4; 2697 2697 + int len = 7 + count * blocklen; 2700 2698 uint8_t index; 2701 2699 int i; 2702 2700 2703 2703 - /* previously set by 'M' BIT table */ 2704 2704 - blocklen = init_ram_restrict_zm_reg_group_blocklen; 2705 2701 2706 2702 if (!iexec->execute) 2707 2707 - return true; 2703 2703 + return len; 2708 2704 2709 2705 if (!blocklen) { 2710 2706 NV_ERROR(bios->dev, 2711 2707 "0x%04X: Zero block length - has the M table " 2712 2708 "been parsed?\n", offset); 2713 2713 - return false; 2709 2709 + return 0; 2714 2710 } 2715 2711 2716 2712 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; ··· 2728 2724 reg += regincrement; 2729 2725 } 2730 2726 2731 2731 - return true; 2727 2727 + return len; 2732 2728 } 2733 2729 2734 2734 - static bool 2730 2730 + static int 2735 2731 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2736 2732 { 2737 2733 /* ··· 2748 2744 uint32_t dstreg = ROM32(bios->data[offset + 5]); 2749 2745 2750 2746 if (!iexec->execute) 2751 2751 - return true; 2747 2747 + return 9; 2752 2748 2753 2749 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 2754 2750 2755 2755 - return true; 2751 2751 + return 9; 2756 2752 } 2757 2753 2758 2758 - static bool 2754 2754 + static int 2759 2755 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 2760 2756 struct init_exec *iexec) 2761 2757 { ··· 2773 2769 2774 2770 uint32_t reg = ROM32(bios->data[offset + 1]); 2775 2771 uint8_t count = bios->data[offset + 5]; 2772 2772 + int len = 6 + count * 4; 2776 2773 int i; 2777 2774 2778 2775 if (!iexec->execute) 2779 2779 - return true; 2776 2776 + return len; 2780 2777 2781 2778 for (i = 0; i < count; i++) { 2782 2779 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 2783 2780 bios_wr32(bios, reg, data); 2784 2781 } 2785 2782 2786 2786 - return true; 2783 2783 + return len; 2787 2784 } 2788 2785 2789 2789 - static bool 2786 2786 + static int 2790 2787 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2791 2788 { 2792 2789 /* ··· 2798 2793 * Seemingly does nothing 2799 2794 */ 2800 2795 2801 2801 - return true; 2796 2796 + return 1; 2802 2797 } 2803 2798 2804 2804 - static bool 2799 2799 + static int 2805 2800 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2806 2801 { 2807 2802 /* ··· 2834 2829 val <<= bios->data[offset + 16]; 2835 2830 2836 2831 if (!iexec->execute) 2837 2837 - return true; 2832 2832 + return 17; 2838 2833 2839 2834 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 2840 2840 - return true; 2835 2835 + return 17; 2841 2836 } 2842 2837 2843 2843 - static bool 2838 2838 + static int 2844 2839 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2845 2840 { 2846 2841 /* ··· 2864 2859 val = (val & mask) | ((val + add) & ~mask); 2865 2860 2866 2861 if (!iexec->execute) 2867 2867 - return true; 2862 2862 + return 13; 2868 2863 2869 2864 bios_wr32(bios, reg, val); 2870 2870 - return true; 2865 2865 + return 13; 2871 2866 } 2872 2867 2873 2873 - static bool 2868 2868 + static int 2874 2869 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2875 2870 { 2876 2871 /* ··· 2888 2883 struct drm_device *dev = bios->dev; 2889 2884 struct nouveau_i2c_chan *auxch; 2890 2885 uint32_t addr = ROM32(bios->data[offset + 1]); 2891 2891 - uint8_t len = bios->data[offset + 5]; 2886 2886 + uint8_t count = bios->data[offset + 5]; 2887 2887 + int len = 6 + count * 2; 2892 2888 int ret, i; 2893 2889 2894 2890 if (!bios->display.output) { 2895 2891 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 2896 2896 - return false; 2892 2892 + return 0; 2897 2893 } 2898 2894 2899 2895 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2900 2896 if (!auxch) { 2901 2897 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 2902 2898 bios->display.output->i2c_index); 2903 2903 - return false; 2899 2899 + return 0; 2904 2900 } 2905 2901 2906 2902 if (!iexec->execute) 2907 2907 - return true; 2903 2903 + return len; 2908 2904 2909 2905 offset += 6; 2910 2910 - for (i = 0; i < len; i++, offset += 2) { 2906 2906 + for (i = 0; i < count; i++, offset += 2) { 2911 2907 uint8_t data; 2912 2908 2913 2909 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 2914 2910 if (ret) { 2915 2911 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 2916 2916 - return false; 2912 2912 + return 0; 2917 2913 } 2918 2914 2919 2915 data &= bios->data[offset + 0]; ··· 2923 2917 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 2924 2918 if (ret) { 2925 2919 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 2926 2926 - return false; 2920 2920 + return 0; 2927 2921 } 2928 2922 } 2929 2923 2930 2930 - return true; 2924 2924 + return len; 2931 2925 } 2932 2926 2933 2933 - static bool 2927 2927 + static int 2934 2928 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2935 2929 { 2936 2930 /* ··· 2947 2941 struct drm_device *dev = bios->dev; 2948 2942 struct nouveau_i2c_chan *auxch; 2949 2943 uint32_t addr = ROM32(bios->data[offset + 1]); 2950 2950 - uint8_t len = bios->data[offset + 5]; 2944 2944 + uint8_t count = bios->data[offset + 5]; 2945 2945 + int len = 6 + count; 2951 2946 int ret, i; 2952 2947 2953 2948 if (!bios->display.output) { 2954 2949 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 2955 2955 - return false; 2950 2950 + return 0; 2956 2951 } 2957 2952 2958 2953 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2959 2954 if (!auxch) { 2960 2955 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 2961 2956 bios->display.output->i2c_index); 2962 2962 - return false; 2957 2957 + return 0; 2963 2958 } 2964 2959 2965 2960 if (!iexec->execute) 2966 2966 - return true; 2961 2961 + return len; 2967 2962 2968 2963 offset += 6; 2969 2969 - for (i = 0; i < len; i++, offset++) { 2964 2964 + for (i = 0; i < count; i++, offset++) { 2970 2965 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 2971 2966 if (ret) { 2972 2967 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 2973 2973 - return false; 2968 2968 + return 0; 2974 2969 } 2975 2970 } 2976 2971 2977 2977 - return true; 2972 2972 + return len; 2978 2973 } 2979 2974 2980 2975 static struct init_tbl_entry itbl_entry[] = { 2981 2976 /* command name , id , length , offset , mult , command handler */ 2982 2977 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 2983 2983 - { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog }, 2984 2984 - { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat }, 2985 2985 - { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll }, 2986 2986 - { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat }, 2987 2987 - { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy }, 2988 2988 - { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not }, 2989 2989 - { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition }, 2990 2990 - { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched }, 2991 2991 - { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 }, 2992 2992 - { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 }, 2993 2993 - { "INIT_I2C_BYTE" , 0x4C, 4 , 3 , 3 , init_i2c_byte }, 2994 2994 - { "INIT_ZM_I2C_BYTE" , 0x4D, 4 , 3 , 2 , init_zm_i2c_byte }, 2995 2995 - { "INIT_ZM_I2C" , 0x4E, 4 , 3 , 1 , init_zm_i2c }, 2996 2996 - { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds }, 2997 2997 - { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group }, 2998 2998 - { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch }, 2999 2999 - { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr }, 3000 3000 - { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr }, 3001 3001 - { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group }, 3002 3002 - { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time }, 3003 3003 - { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence }, 2978 2978 + { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 2979 2979 + { "INIT_REPEAT" , 0x33, init_repeat }, 2980 2980 + { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 2981 2981 + { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 2982 2982 + { "INIT_COPY" , 0x37, init_copy }, 2983 2983 + { "INIT_NOT" , 0x38, init_not }, 2984 2984 + { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 2985 2985 + { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 2986 2986 + { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 2987 2987 + { "INIT_PLL2" , 0x4B, init_pll2 }, 2988 2988 + { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 2989 2989 + { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 2990 2990 + { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 2991 2991 + { "INIT_TMDS" , 0x4F, init_tmds }, 2992 2992 + { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 2993 2993 + { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 2994 2994 + { "INIT_CR" , 0x52, init_cr }, 2995 2995 + { "INIT_ZM_CR" , 0x53, init_zm_cr }, 2996 2996 + { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 2997 2997 + { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 2998 2998 + { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3004 2999 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3005 3005 - { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct }, 3006 3006 - { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg }, 3007 3007 - { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io }, 3008 3008 - { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem }, 3009 3009 - { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset }, 3010 3010 - { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem }, 3011 3011 - { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk }, 3012 3012 - { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit }, 3013 3013 - { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io }, 3014 3014 - { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub }, 3015 3015 - { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition }, 3016 3016 - { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg }, 3017 3017 - { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro }, 3018 3018 - { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done }, 3019 3019 - { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume }, 3000 3000 + { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3001 3001 + { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3002 3002 + { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3003 3003 + { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3004 3004 + { "INIT_RESET" , 0x65, init_reset }, 3005 3005 + { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3006 3006 + { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3007 3007 + { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3008 3008 + { "INIT_IO" , 0x69, init_io }, 3009 3009 + { "INIT_SUB" , 0x6B, init_sub }, 3010 3010 + { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3011 3011 + { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3012 3012 + { "INIT_MACRO" , 0x6F, init_macro }, 3013 3013 + { "INIT_DONE" , 0x71, init_done }, 3014 3014 + { "INIT_RESUME" , 0x72, init_resume }, 3020 3015 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3021 3021 - { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time }, 3022 3022 - { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition }, 3023 3023 - { "INIT_IO_CONDITION" , 0x76, 2 , 0 , 0 , init_io_condition }, 3024 3024 - { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io }, 3025 3025 - { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll }, 3026 3026 - { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg }, 3027 3027 - /* INIT_RAM_RESTRICT_PLL's length is adjusted by the BIT M table */ 3028 3028 - { "INIT_RAM_RESTRICT_PLL" , 0x87, 2 , 0 , 0 , init_ram_restrict_pll }, 3029 3029 - { "INIT_8C" , 0x8C, 1 , 0 , 0 , init_8c }, 3030 3030 - { "INIT_8D" , 0x8D, 1 , 0 , 0 , init_8d }, 3031 3031 - { "INIT_GPIO" , 0x8E, 1 , 0 , 0 , init_gpio }, 3032 3032 - /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */ 3033 3033 - { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group }, 3034 3034 - { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg }, 3035 3035 - { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched }, 3036 3036 - { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved }, 3037 3037 - { "INIT_96" , 0x96, 17 , 0 , 0 , init_96 }, 3038 3038 - { "INIT_97" , 0x97, 13 , 0 , 0 , init_97 }, 3039 3039 - { "INIT_AUXCH" , 0x98, 6 , 5 , 2 , init_auxch }, 3040 3040 - { "INIT_ZM_AUXCH" , 0x99, 6 , 5 , 1 , init_zm_auxch }, 3041 3041 - { NULL , 0 , 0 , 0 , 0 , NULL } 3016 3016 + { "INIT_TIME" , 0x74, init_time }, 3017 3017 + { "INIT_CONDITION" , 0x75, init_condition }, 3018 3018 + { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3019 3019 + { "INIT_INDEX_IO" , 0x78, init_index_io }, 3020 3020 + { "INIT_PLL" , 0x79, init_pll }, 3021 3021 + { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3022 3022 + { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3023 3023 + { "INIT_8C" , 0x8C, init_8c }, 3024 3024 + { "INIT_8D" , 0x8D, init_8d }, 3025 3025 + { "INIT_GPIO" , 0x8E, init_gpio }, 3026 3026 + { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3027 3027 + { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3028 3028 + { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3029 3029 + { "INIT_RESERVED" , 0x92, init_reserved }, 3030 3030 + { "INIT_96" , 0x96, init_96 }, 3031 3031 + { "INIT_97" , 0x97, init_97 }, 3032 3032 + { "INIT_AUXCH" , 0x98, init_auxch }, 3033 3033 + { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3034 3034 + { NULL , 0 , NULL } 3042 3035 }; 3043 3043 - 3044 3044 - static unsigned int get_init_table_entry_length(struct nvbios *bios, unsigned int offset, int i) 3045 3045 - { 3046 3046 - /* Calculates the length of a given init table entry. */ 3047 3047 - return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier; 3048 3048 - } 3049 3036 3050 3037 #define MAX_TABLE_OPS 1000 3051 3038 ··· 3055 3056 * is changed back to EXECUTE. 3056 3057 */ 3057 3058 3058 3058 - int count = 0, i; 3059 3059 + int count = 0, i, res; 3059 3060 uint8_t id; 3060 3061 3061 3062 /* ··· 3075 3076 offset, itbl_entry[i].id, itbl_entry[i].name); 3076 3077 3077 3078 /* execute eventual command handler */ 3078 3078 - if (itbl_entry[i].handler) 3079 3079 - if (!(*itbl_entry[i].handler)(bios, offset, iexec)) 3080 3080 - break; 3079 3079 + res = (*itbl_entry[i].handler)(bios, offset, iexec); 3080 3080 + if (!res) 3081 3081 + break; 3082 3082 + /* 3083 3083 + * Add the offset of the current command including all data 3084 3084 + * of that command. The offset will then be pointing on the 3085 3085 + * next op code. 3086 3086 + */ 3087 3087 + offset += res; 3081 3088 } else { 3082 3089 NV_ERROR(bios->dev, 3083 3090 "0x%04X: Init table command not found: " 3084 3091 "0x%02X\n", offset, id); 3085 3092 return -ENOENT; 3086 3093 } 3087 3087 - 3088 3088 - /* 3089 3089 - * Add the offset of the current command including all data 3090 3090 - * of that command. The offset will then be pointing on the 3091 3091 - * next op code. 3092 3092 - */ 3093 3093 - offset += get_init_table_entry_length(bios, offset, i); 3094 3094 } 3095 3095 3096 3096 if (offset >= bios->length) ··· 3852 3854 * script tables is a pointer to the script to execute. 3853 3855 */ 3854 3856 3855 3855 - NV_DEBUG(dev, "Searching for output entry for %d %d %d\n", 3857 3857 + NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 3856 3858 dcbent->type, dcbent->location, dcbent->or); 3857 3859 otable = bios_output_config_match(dev, dcbent, table[1] + 3858 3860 bios->display.script_table_ptr, ··· 3882 3884 if (pxclk == 0) { 3883 3885 script = ROM16(otable[6]); 3884 3886 if (!script) { 3885 3885 - NV_DEBUG(dev, "output script 0 not found\n"); 3887 3887 + NV_DEBUG_KMS(dev, "output script 0 not found\n"); 3886 3888 return 1; 3887 3889 } 3888 3890 ··· 3892 3894 if (pxclk == -1) { 3893 3895 script = ROM16(otable[8]); 3894 3896 if (!script) { 3895 3895 - NV_DEBUG(dev, "output script 1 not found\n"); 3897 3897 + NV_DEBUG_KMS(dev, "output script 1 not found\n"); 3896 3898 return 1; 3897 3899 } 3898 3900 ··· 3905 3907 else 3906 3908 script = 0; 3907 3909 if (!script) { 3908 3908 - NV_DEBUG(dev, "output script 2 not found\n"); 3910 3910 + NV_DEBUG_KMS(dev, "output script 2 not found\n"); 3909 3911 return 1; 3910 3912 } 3911 3913 ··· 3929 3931 if (script) 3930 3932 script = clkcmptable(bios, script, -pxclk); 3931 3933 if (!script) { 3932 3932 - NV_DEBUG(dev, "clock script 1 not found\n"); 3934 3934 + NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 3933 3935 return 1; 3934 3936 } 3935 3937 ··· 4604 4606 * stuff that we don't use - their use currently unknown 4605 4607 */ 4606 4608 4607 4607 - uint16_t rr_strap_xlat; 4608 4608 - uint8_t rr_group_count; 4609 4609 - int i; 4610 4610 - 4611 4609 /* 4612 4610 * Older bios versions don't have a sufficiently long table for 4613 4611 * what we want ··· 4612 4618 return 0; 4613 4619 4614 4620 if (bitentry->id[1] < 2) { 4615 4615 - rr_group_count = bios->data[bitentry->offset + 2]; 4616 4616 - rr_strap_xlat = ROM16(bios->data[bitentry->offset + 3]); 4621 4621 + bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 4622 4622 + bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 4617 4623 } else { 4618 4618 - rr_group_count = bios->data[bitentry->offset + 0]; 4619 4619 - rr_strap_xlat = ROM16(bios->data[bitentry->offset + 1]); 4624 4624 + bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 4625 4625 + bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 4620 4626 } 4621 4621 - 4622 4622 - /* adjust length of INIT_87 */ 4623 4623 - for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x87); i++); 4624 4624 - itbl_entry[i].length += rr_group_count * 4; 4625 4625 - 4626 4626 - /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */ 4627 4627 - for (; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++); 4628 4628 - itbl_entry[i].length_multiplier = rr_group_count * 4; 4629 4629 - 4630 4630 - init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier; 4631 4631 - bios->ram_restrict_tbl_ptr = rr_strap_xlat; 4632 4627 4633 4628 return 0; 4634 4629 } ··· 5217 5234 int i; 5218 5235 5219 5236 if (!bios->bdcb.connector_table_ptr) { 5220 5220 - NV_DEBUG(dev, "No DCB connector table present\n"); 5237 5237 + NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5221 5238 return; 5222 5239 } 5223 5240

+1

drivers/gpu/drm/nouveau/nouveau_bios.h

reviewed

··· 227 227 228 228 uint16_t pll_limit_tbl_ptr; 229 229 uint16_t ram_restrict_tbl_ptr; 230 230 + uint8_t ram_restrict_group_count; 230 231 231 232 uint16_t some_script_ptr; /* BIT I + 14 */ 232 233 uint16_t init96_tbl_ptr; /* BIT I + 16 */

+14 -5

drivers/gpu/drm/nouveau/nouveau_bo.c

reviewed

··· 154 154 nvbo->placement.busy_placement = nvbo->placements; 155 155 nvbo->placement.num_placement = n; 156 156 nvbo->placement.num_busy_placement = n; 157 157 + 158 158 + if (nvbo->pin_refcnt) { 159 159 + while (n--) 160 160 + nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT; 161 161 + } 157 162 } 158 163 159 164 int ··· 405 400 struct nouveau_bo *nvbo = nouveau_bo(bo); 406 401 407 402 switch (bo->mem.mem_type) { 403 403 + case TTM_PL_VRAM: 404 404 + nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT | 405 405 + TTM_PL_FLAG_SYSTEM); 406 406 + break; 408 407 default: 409 408 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); 410 409 break; 411 410 } 411 411 + 412 412 + *pl = nvbo->placement; 412 413 } 413 414 414 415 ··· 466 455 int ret; 467 456 468 457 chan = nvbo->channel; 469 469 - if (!chan || nvbo->tile_flags || nvbo->no_vm) { 458 458 + if (!chan || nvbo->tile_flags || nvbo->no_vm) 470 459 chan = dev_priv->channel; 471 471 - if (!chan) 472 472 - return -EINVAL; 473 473 - } 474 460 475 461 src_offset = old_mem->mm_node->start << PAGE_SHIFT; 476 462 dst_offset = new_mem->mm_node->start << PAGE_SHIFT; ··· 633 625 return ret; 634 626 } 635 627 636 636 - if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE) 628 628 + if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE || 629 629 + !dev_priv->channel) 637 630 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 638 631 639 632 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {

+4 -4

drivers/gpu/drm/nouveau/nouveau_connector.c

reviewed

··· 86 86 struct nouveau_connector *connector = nouveau_connector(drm_connector); 87 87 struct drm_device *dev = connector->base.dev; 88 88 89 89 - NV_DEBUG(dev, "\n"); 89 89 + NV_DEBUG_KMS(dev, "\n"); 90 90 91 91 if (!connector) 92 92 return; ··· 420 420 /* Use preferred mode if there is one.. */ 421 421 list_for_each_entry(mode, &connector->base.probed_modes, head) { 422 422 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 423 423 - NV_DEBUG(dev, "native mode from preferred\n"); 423 423 + NV_DEBUG_KMS(dev, "native mode from preferred\n"); 424 424 return drm_mode_duplicate(dev, mode); 425 425 } 426 426 } ··· 445 445 largest = mode; 446 446 } 447 447 448 448 - NV_DEBUG(dev, "native mode from largest: %dx%d@%d\n", 448 448 + NV_DEBUG_KMS(dev, "native mode from largest: %dx%d@%d\n", 449 449 high_w, high_h, high_v); 450 450 return largest ? drm_mode_duplicate(dev, largest) : NULL; 451 451 } ··· 725 725 struct drm_encoder *encoder; 726 726 int ret; 727 727 728 728 - NV_DEBUG(dev, "\n"); 728 728 + NV_DEBUG_KMS(dev, "\n"); 729 729 730 730 nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL); 731 731 if (!nv_connector)

+14 -14

drivers/gpu/drm/nouveau/nouveau_dp.c

reviewed

··· 187 187 if (ret) 188 188 return false; 189 189 190 190 - NV_DEBUG(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]); 190 190 + NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]); 191 191 192 192 /* Keep all lanes at the same level.. */ 193 193 for (i = 0; i < nv_encoder->dp.link_nr; i++) { ··· 228 228 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); 229 229 int dpe_headerlen, ret, i; 230 230 231 231 - NV_DEBUG(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n", 231 231 + NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n", 232 232 config[0], config[1], config[2], config[3]); 233 233 234 234 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); ··· 276 276 bool cr_done, cr_max_vs, eq_done; 277 277 int ret = 0, i, tries, voltage; 278 278 279 279 - NV_DEBUG(dev, "link training!!\n"); 279 279 + NV_DEBUG_KMS(dev, "link training!!\n"); 280 280 train: 281 281 cr_done = eq_done = false; 282 282 283 283 /* set link configuration */ 284 284 - NV_DEBUG(dev, "\tbegin train: bw %d, lanes %d\n", 284 284 + NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n", 285 285 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr); 286 286 287 287 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw); ··· 297 297 return false; 298 298 299 299 /* clock recovery */ 300 300 - NV_DEBUG(dev, "\tbegin cr\n"); 300 300 + NV_DEBUG_KMS(dev, "\tbegin cr\n"); 301 301 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1); 302 302 if (ret) 303 303 goto stop; ··· 314 314 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2); 315 315 if (ret) 316 316 break; 317 317 - NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n", 317 317 + NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n", 318 318 status[0], status[1]); 319 319 320 320 cr_done = true; ··· 346 346 goto stop; 347 347 348 348 /* channel equalisation */ 349 349 - NV_DEBUG(dev, "\tbegin eq\n"); 349 349 + NV_DEBUG_KMS(dev, "\tbegin eq\n"); 350 350 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2); 351 351 if (ret) 352 352 goto stop; ··· 357 357 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3); 358 358 if (ret) 359 359 break; 360 360 - NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n", 360 360 + NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n", 361 361 status[0], status[1]); 362 362 363 363 eq_done = true; ··· 395 395 396 396 /* retry at a lower setting, if possible */ 397 397 if (!ret && !(eq_done && cr_done)) { 398 398 - NV_DEBUG(dev, "\twe failed\n"); 398 398 + NV_DEBUG_KMS(dev, "\twe failed\n"); 399 399 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) { 400 400 - NV_DEBUG(dev, "retry link training at low rate\n"); 400 400 + NV_DEBUG_KMS(dev, "retry link training at low rate\n"); 401 401 nv_encoder->dp.link_bw = DP_LINK_BW_1_62; 402 402 goto train; 403 403 } ··· 418 418 if (ret) 419 419 return false; 420 420 421 421 - NV_DEBUG(dev, "encoder: link_bw %d, link_nr %d\n" 421 421 + NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n" 422 422 "display: link_bw %d, link_nr %d version 0x%02x\n", 423 423 nv_encoder->dcb->dpconf.link_bw, 424 424 nv_encoder->dcb->dpconf.link_nr, ··· 446 446 uint32_t tmp, ctrl, stat = 0, data32[4] = {}; 447 447 int ret = 0, i, index = auxch->rd; 448 448 449 449 - NV_DEBUG(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr); 449 449 + NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr); 450 450 451 451 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); 452 452 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000); ··· 472 472 if (!(cmd & 1)) { 473 473 memcpy(data32, data, data_nr); 474 474 for (i = 0; i < 4; i++) { 475 475 - NV_DEBUG(dev, "wr %d: 0x%08x\n", i, data32[i]); 475 475 + NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]); 476 476 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]); 477 477 } 478 478 } ··· 504 504 if (cmd & 1) { 505 505 for (i = 0; i < 4; i++) { 506 506 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i)); 507 507 - NV_DEBUG(dev, "rd %d: 0x%08x\n", i, data32[i]); 507 507 + NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]); 508 508 } 509 509 memcpy(data, data32, data_nr); 510 510 }

+6 -2

drivers/gpu/drm/nouveau/nouveau_drv.c

reviewed

··· 35 35 36 36 #include "drm_pciids.h" 37 37 38 38 + MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)"); 39 39 + int nouveau_ctxfw = 0; 40 40 + module_param_named(ctxfw, nouveau_ctxfw, int, 0400); 41 41 + 38 42 MODULE_PARM_DESC(noagp, "Disable AGP"); 39 43 int nouveau_noagp; 40 44 module_param_named(noagp, nouveau_noagp, int, 0400); ··· 277 273 278 274 for (i = 0; i < dev_priv->engine.fifo.channels; i++) { 279 275 chan = dev_priv->fifos[i]; 280 280 - if (!chan) 276 276 + if (!chan || !chan->pushbuf_bo) 281 277 continue; 282 278 283 279 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++) ··· 345 341 .owner = THIS_MODULE, 346 342 .open = drm_open, 347 343 .release = drm_release, 348 348 - .ioctl = drm_ioctl, 344 344 + .unlocked_ioctl = drm_ioctl, 349 345 .mmap = nouveau_ttm_mmap, 350 346 .poll = drm_poll, 351 347 .fasync = drm_fasync,

+22 -5

drivers/gpu/drm/nouveau/nouveau_drv.h

reviewed

··· 54 54 #include "nouveau_drm.h" 55 55 #include "nouveau_reg.h" 56 56 #include "nouveau_bios.h" 57 57 + struct nouveau_grctx; 57 58 58 59 #define MAX_NUM_DCB_ENTRIES 16 59 60 ··· 318 317 bool accel_blocked; 319 318 void *ctxprog; 320 319 void *ctxvals; 320 320 + int grctx_size; 321 321 322 322 int (*init)(struct drm_device *); 323 323 void (*takedown)(struct drm_device *); ··· 649 647 extern char *nouveau_tv_norm; 650 648 extern int nouveau_reg_debug; 651 649 extern char *nouveau_vbios; 650 650 + extern int nouveau_ctxfw; 652 651 653 652 /* nouveau_state.c */ 654 653 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); ··· 962 959 extern void nv40_graph_destroy_context(struct nouveau_channel *); 963 960 extern int nv40_graph_load_context(struct nouveau_channel *); 964 961 extern int nv40_graph_unload_context(struct drm_device *); 965 965 - extern int nv40_grctx_init(struct drm_device *); 966 966 - extern void nv40_grctx_fini(struct drm_device *); 967 967 - extern void nv40_grctx_vals_load(struct drm_device *, struct nouveau_gpuobj *); 962 962 + extern void nv40_grctx_init(struct nouveau_grctx *); 968 963 969 964 /* nv50_graph.c */ 970 965 extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; ··· 975 974 extern int nv50_graph_load_context(struct nouveau_channel *); 976 975 extern int nv50_graph_unload_context(struct drm_device *); 977 976 extern void nv50_graph_context_switch(struct drm_device *); 977 977 + 978 978 + /* nouveau_grctx.c */ 979 979 + extern int nouveau_grctx_prog_load(struct drm_device *); 980 980 + extern void nouveau_grctx_vals_load(struct drm_device *, 981 981 + struct nouveau_gpuobj *); 982 982 + extern void nouveau_grctx_fini(struct drm_device *); 978 983 979 984 /* nv04_instmem.c */ 980 985 extern int nv04_instmem_init(struct drm_device *); ··· 1214 1207 pci_name(d->pdev), ##arg) 1215 1208 #ifndef NV_DEBUG_NOTRACE 1216 1209 #define NV_DEBUG(d, fmt, arg...) do { \ 1217 1217 - if (drm_debug) { \ 1210 1210 + if (drm_debug & DRM_UT_DRIVER) { \ 1211 1211 + NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1212 1212 + __LINE__, ##arg); \ 1213 1213 + } \ 1214 1214 + } while (0) 1215 1215 + #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1216 1216 + if (drm_debug & DRM_UT_KMS) { \ 1218 1217 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1219 1218 __LINE__, ##arg); \ 1220 1219 } \ 1221 1220 } while (0) 1222 1221 #else 1223 1222 #define NV_DEBUG(d, fmt, arg...) do { \ 1224 1224 - if (drm_debug) \ 1223 1223 + if (drm_debug & DRM_UT_DRIVER) \ 1224 1224 + NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1225 1225 + } while (0) 1226 1226 + #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1227 1227 + if (drm_debug & DRM_UT_KMS) \ 1225 1228 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1226 1229 } while (0) 1227 1230 #endif

+12 -10

drivers/gpu/drm/nouveau/nouveau_fbcon.c

reviewed

··· 58 58 struct nouveau_channel *chan = dev_priv->channel; 59 59 int ret, i; 60 60 61 61 - if (!chan->accel_done || 61 61 + if (!chan || !chan->accel_done || 62 62 info->state != FBINFO_STATE_RUNNING || 63 63 info->flags & FBINFO_HWACCEL_DISABLED) 64 64 return 0; ··· 318 318 par->nouveau_fb = nouveau_fb; 319 319 par->dev = dev; 320 320 321 321 - switch (dev_priv->card_type) { 322 322 - case NV_50: 323 323 - nv50_fbcon_accel_init(info); 324 324 - break; 325 325 - default: 326 326 - nv04_fbcon_accel_init(info); 327 327 - break; 328 328 - }; 321 321 + if (dev_priv->channel) { 322 322 + switch (dev_priv->card_type) { 323 323 + case NV_50: 324 324 + nv50_fbcon_accel_init(info); 325 325 + break; 326 326 + default: 327 327 + nv04_fbcon_accel_init(info); 328 328 + break; 329 329 + }; 330 330 + } 329 331 330 332 nouveau_fbcon_zfill(dev); 331 333 ··· 349 347 int 350 348 nouveau_fbcon_probe(struct drm_device *dev) 351 349 { 352 352 - NV_DEBUG(dev, "\n"); 350 350 + NV_DEBUG_KMS(dev, "\n"); 353 351 354 352 return drm_fb_helper_single_fb_probe(dev, 32, nouveau_fbcon_create); 355 353 }

+161

drivers/gpu/drm/nouveau/nouveau_grctx.c

reviewed

··· 1 1 + /* 2 2 + * Copyright 2009 Red Hat Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included in 12 12 + * all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 21 + * 22 22 + * Authors: Ben Skeggs 23 23 + */ 24 24 + 25 25 + #include <linux/firmware.h> 26 26 + 27 27 + #include "drmP.h" 28 28 + #include "nouveau_drv.h" 29 29 + 30 30 + struct nouveau_ctxprog { 31 31 + uint32_t signature; 32 32 + uint8_t version; 33 33 + uint16_t length; 34 34 + uint32_t data[]; 35 35 + } __attribute__ ((packed)); 36 36 + 37 37 + struct nouveau_ctxvals { 38 38 + uint32_t signature; 39 39 + uint8_t version; 40 40 + uint32_t length; 41 41 + struct { 42 42 + uint32_t offset; 43 43 + uint32_t value; 44 44 + } data[]; 45 45 + } __attribute__ ((packed)); 46 46 + 47 47 + int 48 48 + nouveau_grctx_prog_load(struct drm_device *dev) 49 49 + { 50 50 + struct drm_nouveau_private *dev_priv = dev->dev_private; 51 51 + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 52 52 + const int chipset = dev_priv->chipset; 53 53 + const struct firmware *fw; 54 54 + const struct nouveau_ctxprog *cp; 55 55 + const struct nouveau_ctxvals *cv; 56 56 + char name[32]; 57 57 + int ret, i; 58 58 + 59 59 + if (pgraph->accel_blocked) 60 60 + return -ENODEV; 61 61 + 62 62 + if (!pgraph->ctxprog) { 63 63 + sprintf(name, "nouveau/nv%02x.ctxprog", chipset); 64 64 + ret = request_firmware(&fw, name, &dev->pdev->dev); 65 65 + if (ret) { 66 66 + NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset); 67 67 + return ret; 68 68 + } 69 69 + 70 70 + pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL); 71 71 + if (!pgraph->ctxprog) { 72 72 + NV_ERROR(dev, "OOM copying ctxprog\n"); 73 73 + release_firmware(fw); 74 74 + return -ENOMEM; 75 75 + } 76 76 + memcpy(pgraph->ctxprog, fw->data, fw->size); 77 77 + 78 78 + cp = pgraph->ctxprog; 79 79 + if (le32_to_cpu(cp->signature) != 0x5043564e || 80 80 + cp->version != 0 || 81 81 + le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) { 82 82 + NV_ERROR(dev, "ctxprog invalid\n"); 83 83 + release_firmware(fw); 84 84 + nouveau_grctx_fini(dev); 85 85 + return -EINVAL; 86 86 + } 87 87 + release_firmware(fw); 88 88 + } 89 89 + 90 90 + if (!pgraph->ctxvals) { 91 91 + sprintf(name, "nouveau/nv%02x.ctxvals", chipset); 92 92 + ret = request_firmware(&fw, name, &dev->pdev->dev); 93 93 + if (ret) { 94 94 + NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset); 95 95 + nouveau_grctx_fini(dev); 96 96 + return ret; 97 97 + } 98 98 + 99 99 + pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL); 100 100 + if (!pgraph->ctxprog) { 101 101 + NV_ERROR(dev, "OOM copying ctxprog\n"); 102 102 + release_firmware(fw); 103 103 + nouveau_grctx_fini(dev); 104 104 + return -ENOMEM; 105 105 + } 106 106 + memcpy(pgraph->ctxvals, fw->data, fw->size); 107 107 + 108 108 + cv = (void *)pgraph->ctxvals; 109 109 + if (le32_to_cpu(cv->signature) != 0x5643564e || 110 110 + cv->version != 0 || 111 111 + le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) { 112 112 + NV_ERROR(dev, "ctxvals invalid\n"); 113 113 + release_firmware(fw); 114 114 + nouveau_grctx_fini(dev); 115 115 + return -EINVAL; 116 116 + } 117 117 + release_firmware(fw); 118 118 + } 119 119 + 120 120 + cp = pgraph->ctxprog; 121 121 + 122 122 + nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 123 123 + for (i = 0; i < le16_to_cpu(cp->length); i++) 124 124 + nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, 125 125 + le32_to_cpu(cp->data[i])); 126 126 + 127 127 + return 0; 128 128 + } 129 129 + 130 130 + void 131 131 + nouveau_grctx_fini(struct drm_device *dev) 132 132 + { 133 133 + struct drm_nouveau_private *dev_priv = dev->dev_private; 134 134 + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 135 135 + 136 136 + if (pgraph->ctxprog) { 137 137 + kfree(pgraph->ctxprog); 138 138 + pgraph->ctxprog = NULL; 139 139 + } 140 140 + 141 141 + if (pgraph->ctxvals) { 142 142 + kfree(pgraph->ctxprog); 143 143 + pgraph->ctxvals = NULL; 144 144 + } 145 145 + } 146 146 + 147 147 + void 148 148 + nouveau_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx) 149 149 + { 150 150 + struct drm_nouveau_private *dev_priv = dev->dev_private; 151 151 + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 152 152 + struct nouveau_ctxvals *cv = pgraph->ctxvals; 153 153 + int i; 154 154 + 155 155 + if (!cv) 156 156 + return; 157 157 + 158 158 + for (i = 0; i < le32_to_cpu(cv->length); i++) 159 159 + nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset), 160 160 + le32_to_cpu(cv->data[i].value)); 161 161 + }

+133

drivers/gpu/drm/nouveau/nouveau_grctx.h

reviewed

··· 1 1 + #ifndef __NOUVEAU_GRCTX_H__ 2 2 + #define __NOUVEAU_GRCTX_H__ 3 3 + 4 4 + struct nouveau_grctx { 5 5 + struct drm_device *dev; 6 6 + 7 7 + enum { 8 8 + NOUVEAU_GRCTX_PROG, 9 9 + NOUVEAU_GRCTX_VALS 10 10 + } mode; 11 11 + void *data; 12 12 + 13 13 + uint32_t ctxprog_max; 14 14 + uint32_t ctxprog_len; 15 15 + uint32_t ctxprog_reg; 16 16 + int ctxprog_label[32]; 17 17 + uint32_t ctxvals_pos; 18 18 + uint32_t ctxvals_base; 19 19 + }; 20 20 + 21 21 + #ifdef CP_CTX 22 22 + static inline void 23 23 + cp_out(struct nouveau_grctx *ctx, uint32_t inst) 24 24 + { 25 25 + uint32_t *ctxprog = ctx->data; 26 26 + 27 27 + if (ctx->mode != NOUVEAU_GRCTX_PROG) 28 28 + return; 29 29 + 30 30 + BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max); 31 31 + ctxprog[ctx->ctxprog_len++] = inst; 32 32 + } 33 33 + 34 34 + static inline void 35 35 + cp_lsr(struct nouveau_grctx *ctx, uint32_t val) 36 36 + { 37 37 + cp_out(ctx, CP_LOAD_SR | val); 38 38 + } 39 39 + 40 40 + static inline void 41 41 + cp_ctx(struct nouveau_grctx *ctx, uint32_t reg, uint32_t length) 42 42 + { 43 43 + ctx->ctxprog_reg = (reg - 0x00400000) >> 2; 44 44 + 45 45 + ctx->ctxvals_base = ctx->ctxvals_pos; 46 46 + ctx->ctxvals_pos = ctx->ctxvals_base + length; 47 47 + 48 48 + if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) { 49 49 + cp_lsr(ctx, length); 50 50 + length = 0; 51 51 + } 52 52 + 53 53 + cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg); 54 54 + } 55 55 + 56 56 + static inline void 57 57 + cp_name(struct nouveau_grctx *ctx, int name) 58 58 + { 59 59 + uint32_t *ctxprog = ctx->data; 60 60 + int i; 61 61 + 62 62 + if (ctx->mode != NOUVEAU_GRCTX_PROG) 63 63 + return; 64 64 + 65 65 + ctx->ctxprog_label[name] = ctx->ctxprog_len; 66 66 + for (i = 0; i < ctx->ctxprog_len; i++) { 67 67 + if ((ctxprog[i] & 0xfff00000) != 0xff400000) 68 68 + continue; 69 69 + if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT)) 70 70 + continue; 71 71 + ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | 72 72 + (ctx->ctxprog_len << CP_BRA_IP_SHIFT); 73 73 + } 74 74 + } 75 75 + 76 76 + static inline void 77 77 + _cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name) 78 78 + { 79 79 + int ip = 0; 80 80 + 81 81 + if (mod != 2) { 82 82 + ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT; 83 83 + if (ip == 0) 84 84 + ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); 85 85 + } 86 86 + 87 87 + cp_out(ctx, CP_BRA | (mod << 18) | ip | flag | 88 88 + (state ? 0 : CP_BRA_IF_CLEAR)); 89 89 + } 90 90 + #define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 91 91 + #ifdef CP_BRA_MOD 92 92 + #define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 93 93 + #define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) 94 94 + #endif 95 95 + 96 96 + static inline void 97 97 + _cp_wait(struct nouveau_grctx *ctx, int flag, int state) 98 98 + { 99 99 + cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); 100 100 + } 101 101 + #define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 102 102 + 103 103 + static inline void 104 104 + _cp_set(struct nouveau_grctx *ctx, int flag, int state) 105 105 + { 106 106 + cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); 107 107 + } 108 108 + #define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 109 109 + 110 110 + static inline void 111 111 + cp_pos(struct nouveau_grctx *ctx, int offset) 112 112 + { 113 113 + ctx->ctxvals_pos = offset; 114 114 + ctx->ctxvals_base = ctx->ctxvals_pos; 115 115 + 116 116 + cp_lsr(ctx, ctx->ctxvals_pos); 117 117 + cp_out(ctx, CP_SET_CONTEXT_POINTER); 118 118 + } 119 119 + 120 120 + static inline void 121 121 + gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val) 122 122 + { 123 123 + if (ctx->mode != NOUVEAU_GRCTX_VALS) 124 124 + return; 125 125 + 126 126 + reg = (reg - 0x00400000) / 4; 127 127 + reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; 128 128 + 129 129 + nv_wo32(ctx->dev, ctx->data, reg, val); 130 130 + } 131 131 + #endif 132 132 + 133 133 + #endif

+1 -3

drivers/gpu/drm/nouveau/nouveau_ioc32.c

reviewed

··· 61 61 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls)) 62 62 fn = nouveau_compat_ioctls[nr - DRM_COMMAND_BASE]; 63 63 #endif 64 64 - lock_kernel(); /* XXX for now */ 65 64 if (fn != NULL) 66 65 ret = (*fn)(filp, cmd, arg); 67 66 else 68 68 - ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 69 69 - unlock_kernel(); 67 67 + ret = drm_ioctl(filp, cmd, arg); 70 68 71 69 return ret; 72 70 }

+138 -99

drivers/gpu/drm/nouveau/nouveau_state.c

reviewed

··· 299 299 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 300 300 } 301 301 302 302 - int 303 303 - nouveau_card_init(struct drm_device *dev) 302 302 + static int 303 303 + nouveau_card_init_channel(struct drm_device *dev) 304 304 { 305 305 struct drm_nouveau_private *dev_priv = dev->dev_private; 306 306 - struct nouveau_engine *engine; 307 306 struct nouveau_gpuobj *gpuobj; 308 307 int ret; 309 309 - 310 310 - NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state); 311 311 - 312 312 - if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE) 313 313 - return 0; 314 314 - 315 315 - vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); 316 316 - 317 317 - /* Initialise internal driver API hooks */ 318 318 - ret = nouveau_init_engine_ptrs(dev); 319 319 - if (ret) 320 320 - return ret; 321 321 - engine = &dev_priv->engine; 322 322 - dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; 323 323 - 324 324 - /* Parse BIOS tables / Run init tables if card not POSTed */ 325 325 - if (drm_core_check_feature(dev, DRIVER_MODESET)) { 326 326 - ret = nouveau_bios_init(dev); 327 327 - if (ret) 328 328 - return ret; 329 329 - } 330 330 - 331 331 - ret = nouveau_gpuobj_early_init(dev); 332 332 - if (ret) 333 333 - return ret; 334 334 - 335 335 - /* Initialise instance memory, must happen before mem_init so we 336 336 - * know exactly how much VRAM we're able to use for "normal" 337 337 - * purposes. 338 338 - */ 339 339 - ret = engine->instmem.init(dev); 340 340 - if (ret) 341 341 - return ret; 342 342 - 343 343 - /* Setup the memory manager */ 344 344 - ret = nouveau_mem_init(dev); 345 345 - if (ret) 346 346 - return ret; 347 347 - 348 348 - ret = nouveau_gpuobj_init(dev); 349 349 - if (ret) 350 350 - return ret; 351 351 - 352 352 - /* PMC */ 353 353 - ret = engine->mc.init(dev); 354 354 - if (ret) 355 355 - return ret; 356 356 - 357 357 - /* PTIMER */ 358 358 - ret = engine->timer.init(dev); 359 359 - if (ret) 360 360 - return ret; 361 361 - 362 362 - /* PFB */ 363 363 - ret = engine->fb.init(dev); 364 364 - if (ret) 365 365 - return ret; 366 366 - 367 367 - /* PGRAPH */ 368 368 - ret = engine->graph.init(dev); 369 369 - if (ret) 370 370 - return ret; 371 371 - 372 372 - /* PFIFO */ 373 373 - ret = engine->fifo.init(dev); 374 374 - if (ret) 375 375 - return ret; 376 376 - 377 377 - /* this call irq_preinstall, register irq handler and 378 378 - * call irq_postinstall 379 379 - */ 380 380 - ret = drm_irq_install(dev); 381 381 - if (ret) 382 382 - return ret; 383 383 - 384 384 - ret = drm_vblank_init(dev, 0); 385 385 - if (ret) 386 386 - return ret; 387 387 - 388 388 - /* what about PVIDEO/PCRTC/PRAMDAC etc? */ 389 308 390 309 ret = nouveau_channel_alloc(dev, &dev_priv->channel, 391 310 (struct drm_file *)-2, ··· 318 399 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM, 319 400 &gpuobj); 320 401 if (ret) 321 321 - return ret; 402 402 + goto out_err; 322 403 323 404 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM, 324 405 gpuobj, NULL); 325 325 - if (ret) { 326 326 - nouveau_gpuobj_del(dev, &gpuobj); 327 327 - return ret; 328 328 - } 406 406 + if (ret) 407 407 + goto out_err; 329 408 330 409 gpuobj = NULL; 331 410 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0, 332 411 dev_priv->gart_info.aper_size, 333 412 NV_DMA_ACCESS_RW, &gpuobj, NULL); 334 413 if (ret) 335 335 - return ret; 414 414 + goto out_err; 336 415 337 416 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART, 338 417 gpuobj, NULL); 339 339 - if (ret) { 340 340 - nouveau_gpuobj_del(dev, &gpuobj); 341 341 - return ret; 418 418 + if (ret) 419 419 + goto out_err; 420 420 + 421 421 + return 0; 422 422 + out_err: 423 423 + nouveau_gpuobj_del(dev, &gpuobj); 424 424 + nouveau_channel_free(dev_priv->channel); 425 425 + dev_priv->channel = NULL; 426 426 + return ret; 427 427 + } 428 428 + 429 429 + int 430 430 + nouveau_card_init(struct drm_device *dev) 431 431 + { 432 432 + struct drm_nouveau_private *dev_priv = dev->dev_private; 433 433 + struct nouveau_engine *engine; 434 434 + int ret; 435 435 + 436 436 + NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state); 437 437 + 438 438 + if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE) 439 439 + return 0; 440 440 + 441 441 + vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); 442 442 + 443 443 + /* Initialise internal driver API hooks */ 444 444 + ret = nouveau_init_engine_ptrs(dev); 445 445 + if (ret) 446 446 + goto out; 447 447 + engine = &dev_priv->engine; 448 448 + dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; 449 449 + 450 450 + /* Parse BIOS tables / Run init tables if card not POSTed */ 451 451 + if (drm_core_check_feature(dev, DRIVER_MODESET)) { 452 452 + ret = nouveau_bios_init(dev); 453 453 + if (ret) 454 454 + goto out; 455 455 + } 456 456 + 457 457 + ret = nouveau_gpuobj_early_init(dev); 458 458 + if (ret) 459 459 + goto out_bios; 460 460 + 461 461 + /* Initialise instance memory, must happen before mem_init so we 462 462 + * know exactly how much VRAM we're able to use for "normal" 463 463 + * purposes. 464 464 + */ 465 465 + ret = engine->instmem.init(dev); 466 466 + if (ret) 467 467 + goto out_gpuobj_early; 468 468 + 469 469 + /* Setup the memory manager */ 470 470 + ret = nouveau_mem_init(dev); 471 471 + if (ret) 472 472 + goto out_instmem; 473 473 + 474 474 + ret = nouveau_gpuobj_init(dev); 475 475 + if (ret) 476 476 + goto out_mem; 477 477 + 478 478 + /* PMC */ 479 479 + ret = engine->mc.init(dev); 480 480 + if (ret) 481 481 + goto out_gpuobj; 482 482 + 483 483 + /* PTIMER */ 484 484 + ret = engine->timer.init(dev); 485 485 + if (ret) 486 486 + goto out_mc; 487 487 + 488 488 + /* PFB */ 489 489 + ret = engine->fb.init(dev); 490 490 + if (ret) 491 491 + goto out_timer; 492 492 + 493 493 + /* PGRAPH */ 494 494 + ret = engine->graph.init(dev); 495 495 + if (ret) 496 496 + goto out_fb; 497 497 + 498 498 + /* PFIFO */ 499 499 + ret = engine->fifo.init(dev); 500 500 + if (ret) 501 501 + goto out_graph; 502 502 + 503 503 + /* this call irq_preinstall, register irq handler and 504 504 + * call irq_postinstall 505 505 + */ 506 506 + ret = drm_irq_install(dev); 507 507 + if (ret) 508 508 + goto out_fifo; 509 509 + 510 510 + ret = drm_vblank_init(dev, 0); 511 511 + if (ret) 512 512 + goto out_irq; 513 513 + 514 514 + /* what about PVIDEO/PCRTC/PRAMDAC etc? */ 515 515 + 516 516 + if (!engine->graph.accel_blocked) { 517 517 + ret = nouveau_card_init_channel(dev); 518 518 + if (ret) 519 519 + goto out_irq; 342 520 } 343 521 344 522 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 345 345 - if (dev_priv->card_type >= NV_50) { 523 523 + if (dev_priv->card_type >= NV_50) 346 524 ret = nv50_display_create(dev); 347 347 - if (ret) 348 348 - return ret; 349 349 - } else { 525 525 + else 350 526 ret = nv04_display_create(dev); 351 351 - if (ret) 352 352 - return ret; 353 353 - } 527 527 + if (ret) 528 528 + goto out_irq; 354 529 } 355 530 356 531 ret = nouveau_backlight_init(dev); ··· 457 444 drm_helper_initial_config(dev); 458 445 459 446 return 0; 447 447 + 448 448 + out_irq: 449 449 + drm_irq_uninstall(dev); 450 450 + out_fifo: 451 451 + engine->fifo.takedown(dev); 452 452 + out_graph: 453 453 + engine->graph.takedown(dev); 454 454 + out_fb: 455 455 + engine->fb.takedown(dev); 456 456 + out_timer: 457 457 + engine->timer.takedown(dev); 458 458 + out_mc: 459 459 + engine->mc.takedown(dev); 460 460 + out_gpuobj: 461 461 + nouveau_gpuobj_takedown(dev); 462 462 + out_mem: 463 463 + nouveau_mem_close(dev); 464 464 + out_instmem: 465 465 + engine->instmem.takedown(dev); 466 466 + out_gpuobj_early: 467 467 + nouveau_gpuobj_late_takedown(dev); 468 468 + out_bios: 469 469 + nouveau_bios_takedown(dev); 470 470 + out: 471 471 + vga_client_register(dev->pdev, NULL, NULL, NULL); 472 472 + return ret; 460 473 } 461 474 462 475 static void nouveau_card_takedown(struct drm_device *dev)

+5 -5

drivers/gpu/drm/nouveau/nv04_crtc.c

reviewed

··· 143 143 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 144 144 145 145 if (pv->NM2) 146 146 - NV_TRACE(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 146 146 + NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 147 147 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 148 148 else 149 149 - NV_TRACE(dev, "vpll: n %d m %d log2p %d\n", 149 149 + NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n", 150 150 pv->N1, pv->M1, pv->log2P); 151 151 152 152 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); ··· 160 160 unsigned char seq1 = 0, crtc17 = 0; 161 161 unsigned char crtc1A; 162 162 163 163 - NV_TRACE(dev, "Setting dpms mode %d on CRTC %d\n", mode, 163 163 + NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode, 164 164 nv_crtc->index); 165 165 166 166 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */ ··· 603 603 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 604 604 struct drm_nouveau_private *dev_priv = dev->dev_private; 605 605 606 606 - NV_DEBUG(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); 606 606 + NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); 607 607 drm_mode_debug_printmodeline(adjusted_mode); 608 608 609 609 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ ··· 703 703 { 704 704 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 705 705 706 706 - NV_DEBUG(crtc->dev, "\n"); 706 706 + NV_DEBUG_KMS(crtc->dev, "\n"); 707 707 708 708 if (!nv_crtc) 709 709 return;

+2 -6

drivers/gpu/drm/nouveau/nv04_dac.c

reviewed

··· 205 205 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1); 206 206 207 207 if (blue == 0x18) { 208 208 - NV_TRACE(dev, "Load detected on head A\n"); 208 208 + NV_INFO(dev, "Load detected on head A\n"); 209 209 return connector_status_connected; 210 210 } 211 211 ··· 350 350 struct drm_display_mode *mode, 351 351 struct drm_display_mode *adjusted_mode) 352 352 { 353 353 - struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 354 353 struct drm_device *dev = encoder->dev; 355 354 struct drm_nouveau_private *dev_priv = dev->dev_private; 356 355 int head = nouveau_crtc(encoder->crtc)->index; 357 357 - 358 358 - NV_TRACE(dev, "%s called for encoder %d\n", __func__, 359 359 - nv_encoder->dcb->index); 360 356 361 357 if (nv_gf4_disp_arch(dev)) { 362 358 struct drm_encoder *rebind; ··· 462 466 { 463 467 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 464 468 465 465 - NV_DEBUG(encoder->dev, "\n"); 469 469 + NV_DEBUG_KMS(encoder->dev, "\n"); 466 470 467 471 drm_encoder_cleanup(encoder); 468 472 kfree(nv_encoder);

+5 -3

drivers/gpu/drm/nouveau/nv04_dfp.c

reviewed

··· 261 261 struct drm_display_mode *output_mode = &nv_encoder->mode; 262 262 uint32_t mode_ratio, panel_ratio; 263 263 264 264 - NV_DEBUG(dev, "Output mode on CRTC %d:\n", nv_crtc->index); 264 264 + NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index); 265 265 drm_mode_debug_printmodeline(output_mode); 266 266 267 267 /* Initialize the FP registers in this CRTC. */ ··· 413 413 struct dcb_entry *dcbe = nv_encoder->dcb; 414 414 int head = nouveau_crtc(encoder->crtc)->index; 415 415 416 416 - NV_TRACE(dev, "%s called for encoder %d\n", __func__, nv_encoder->dcb->index); 416 416 + NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", 417 417 + drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), 418 418 + nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 417 419 418 420 if (dcbe->type == OUTPUT_TMDS) 419 421 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); ··· 552 550 { 553 551 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 554 552 555 555 - NV_DEBUG(encoder->dev, "\n"); 553 553 + NV_DEBUG_KMS(encoder->dev, "\n"); 556 554 557 555 drm_encoder_cleanup(encoder); 558 556 kfree(nv_encoder);

+5 -6

drivers/gpu/drm/nouveau/nv04_display.c

reviewed

··· 99 99 uint16_t connector[16] = { 0 }; 100 100 int i, ret; 101 101 102 102 - NV_DEBUG(dev, "\n"); 102 102 + NV_DEBUG_KMS(dev, "\n"); 103 103 104 104 if (nv_two_heads(dev)) 105 105 nv04_display_store_initial_head_owner(dev); 106 106 + nouveau_hw_save_vga_fonts(dev, 1); 106 107 107 108 drm_mode_config_init(dev); 108 109 drm_mode_create_scaling_mode_property(dev); ··· 204 203 /* Save previous state */ 205 204 NVLockVgaCrtcs(dev, false); 206 205 207 207 - nouveau_hw_save_vga_fonts(dev, 1); 208 208 - 209 206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 210 207 crtc->funcs->save(crtc); 211 208 ··· 222 223 struct drm_encoder *encoder; 223 224 struct drm_crtc *crtc; 224 225 225 225 - NV_DEBUG(dev, "\n"); 226 226 + NV_DEBUG_KMS(dev, "\n"); 226 227 227 228 /* Turn every CRTC off. */ 228 229 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ··· 245 246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 246 247 crtc->funcs->restore(crtc); 247 248 248 248 - nouveau_hw_save_vga_fonts(dev, 0); 249 249 - 250 249 drm_mode_config_cleanup(dev); 250 250 + 251 251 + nouveau_hw_save_vga_fonts(dev, 0); 251 252 } 252 253 253 254 void

+1 -1

drivers/gpu/drm/nouveau/nv04_graph.c

reviewed

··· 543 543 544 544 nv_wi32(dev, instance, tmp); 545 545 nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp); 546 546 - nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + subc, tmp); 546 546 + nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); 547 547 return 0; 548 548 } 549 549

+153 -42

drivers/gpu/drm/nouveau/nv10_graph.c

reviewed

··· 389 389 int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)]; 390 390 int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)]; 391 391 struct pipe_state pipe_state; 392 392 + uint32_t lma_window[4]; 392 393 }; 394 394 + 395 395 + #define PIPE_SAVE(dev, state, addr) \ 396 396 + do { \ 397 397 + int __i; \ 398 398 + nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \ 399 399 + for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ 400 400 + state[__i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \ 401 401 + } while (0) 402 402 + 403 403 + #define PIPE_RESTORE(dev, state, addr) \ 404 404 + do { \ 405 405 + int __i; \ 406 406 + nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \ 407 407 + for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ 408 408 + nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, state[__i]); \ 409 409 + } while (0) 393 410 394 411 static void nv10_graph_save_pipe(struct nouveau_channel *chan) 395 412 { 396 413 struct drm_device *dev = chan->dev; 397 414 struct graph_state *pgraph_ctx = chan->pgraph_ctx; 398 398 - struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; 399 399 - int i; 400 400 - #define PIPE_SAVE(addr) \ 401 401 - do { \ 402 402 - nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \ 403 403 - for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \ 404 404 - fifo_pipe_state->pipe_##addr[i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \ 405 405 - } while (0) 415 415 + struct pipe_state *pipe = &pgraph_ctx->pipe_state; 406 416 407 407 - PIPE_SAVE(0x4400); 408 408 - PIPE_SAVE(0x0200); 409 409 - PIPE_SAVE(0x6400); 410 410 - PIPE_SAVE(0x6800); 411 411 - PIPE_SAVE(0x6c00); 412 412 - PIPE_SAVE(0x7000); 413 413 - PIPE_SAVE(0x7400); 414 414 - PIPE_SAVE(0x7800); 415 415 - PIPE_SAVE(0x0040); 416 416 - PIPE_SAVE(0x0000); 417 417 - 418 418 - #undef PIPE_SAVE 417 417 + PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400); 418 418 + PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200); 419 419 + PIPE_SAVE(dev, pipe->pipe_0x6400, 0x6400); 420 420 + PIPE_SAVE(dev, pipe->pipe_0x6800, 0x6800); 421 421 + PIPE_SAVE(dev, pipe->pipe_0x6c00, 0x6c00); 422 422 + PIPE_SAVE(dev, pipe->pipe_0x7000, 0x7000); 423 423 + PIPE_SAVE(dev, pipe->pipe_0x7400, 0x7400); 424 424 + PIPE_SAVE(dev, pipe->pipe_0x7800, 0x7800); 425 425 + PIPE_SAVE(dev, pipe->pipe_0x0040, 0x0040); 426 426 + PIPE_SAVE(dev, pipe->pipe_0x0000, 0x0000); 419 427 } 420 428 421 429 static void nv10_graph_load_pipe(struct nouveau_channel *chan) 422 430 { 423 431 struct drm_device *dev = chan->dev; 424 432 struct graph_state *pgraph_ctx = chan->pgraph_ctx; 425 425 - struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; 426 426 - int i; 433 433 + struct pipe_state *pipe = &pgraph_ctx->pipe_state; 427 434 uint32_t xfmode0, xfmode1; 428 428 - #define PIPE_RESTORE(addr) \ 429 429 - do { \ 430 430 - nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \ 431 431 - for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \ 432 432 - nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \ 433 433 - } while (0) 434 434 - 435 435 + int i; 435 436 436 437 nouveau_wait_for_idle(dev); 437 438 /* XXX check haiku comments */ ··· 458 457 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008); 459 458 460 459 461 461 - PIPE_RESTORE(0x0200); 460 460 + PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200); 462 461 nouveau_wait_for_idle(dev); 463 462 464 463 /* restore XFMODE */ 465 464 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0); 466 465 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1); 467 467 - PIPE_RESTORE(0x6400); 468 468 - PIPE_RESTORE(0x6800); 469 469 - PIPE_RESTORE(0x6c00); 470 470 - PIPE_RESTORE(0x7000); 471 471 - PIPE_RESTORE(0x7400); 472 472 - PIPE_RESTORE(0x7800); 473 473 - PIPE_RESTORE(0x4400); 474 474 - PIPE_RESTORE(0x0000); 475 475 - PIPE_RESTORE(0x0040); 466 466 + PIPE_RESTORE(dev, pipe->pipe_0x6400, 0x6400); 467 467 + PIPE_RESTORE(dev, pipe->pipe_0x6800, 0x6800); 468 468 + PIPE_RESTORE(dev, pipe->pipe_0x6c00, 0x6c00); 469 469 + PIPE_RESTORE(dev, pipe->pipe_0x7000, 0x7000); 470 470 + PIPE_RESTORE(dev, pipe->pipe_0x7400, 0x7400); 471 471 + PIPE_RESTORE(dev, pipe->pipe_0x7800, 0x7800); 472 472 + PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400); 473 473 + PIPE_RESTORE(dev, pipe->pipe_0x0000, 0x0000); 474 474 + PIPE_RESTORE(dev, pipe->pipe_0x0040, 0x0040); 476 475 nouveau_wait_for_idle(dev); 477 477 - 478 478 - #undef PIPE_RESTORE 479 476 } 480 477 481 478 static void nv10_graph_create_pipe(struct nouveau_channel *chan) ··· 831 832 (1<<31)); 832 833 if (dev_priv->chipset >= 0x17) { 833 834 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000); 835 835 + nv_wr32(dev, 0x400a10, 0x3ff3fb6); 836 836 + nv_wr32(dev, 0x400838, 0x2f8684); 837 837 + nv_wr32(dev, 0x40083c, 0x115f3f); 834 838 nv_wr32(dev, 0x004006b0, 0x40000020); 835 839 } else 836 840 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000); ··· 869 867 { 870 868 } 871 869 870 870 + static int 871 871 + nv17_graph_mthd_lma_window(struct nouveau_channel *chan, int grclass, 872 872 + int mthd, uint32_t data) 873 873 + { 874 874 + struct drm_device *dev = chan->dev; 875 875 + struct graph_state *ctx = chan->pgraph_ctx; 876 876 + struct pipe_state *pipe = &ctx->pipe_state; 877 877 + struct drm_nouveau_private *dev_priv = dev->dev_private; 878 878 + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 879 879 + uint32_t pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; 880 880 + uint32_t xfmode0, xfmode1; 881 881 + int i; 882 882 + 883 883 + ctx->lma_window[(mthd - 0x1638) / 4] = data; 884 884 + 885 885 + if (mthd != 0x1644) 886 886 + return 0; 887 887 + 888 888 + nouveau_wait_for_idle(dev); 889 889 + 890 890 + PIPE_SAVE(dev, pipe_0x0040, 0x0040); 891 891 + PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200); 892 892 + 893 893 + PIPE_RESTORE(dev, ctx->lma_window, 0x6790); 894 894 + 895 895 + nouveau_wait_for_idle(dev); 896 896 + 897 897 + xfmode0 = nv_rd32(dev, NV10_PGRAPH_XFMODE0); 898 898 + xfmode1 = nv_rd32(dev, NV10_PGRAPH_XFMODE1); 899 899 + 900 900 + PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400); 901 901 + PIPE_SAVE(dev, pipe_0x64c0, 0x64c0); 902 902 + PIPE_SAVE(dev, pipe_0x6ab0, 0x6ab0); 903 903 + PIPE_SAVE(dev, pipe_0x6a80, 0x6a80); 904 904 + 905 905 + nouveau_wait_for_idle(dev); 906 906 + 907 907 + nv_wr32(dev, NV10_PGRAPH_XFMODE0, 0x10000000); 908 908 + nv_wr32(dev, NV10_PGRAPH_XFMODE1, 0x00000000); 909 909 + nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); 910 910 + for (i = 0; i < 4; i++) 911 911 + nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000); 912 912 + for (i = 0; i < 4; i++) 913 913 + nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000); 914 914 + 915 915 + nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); 916 916 + for (i = 0; i < 3; i++) 917 917 + nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000); 918 918 + 919 919 + nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); 920 920 + for (i = 0; i < 3; i++) 921 921 + nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000); 922 922 + 923 923 + nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); 924 924 + nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008); 925 925 + 926 926 + PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200); 927 927 + 928 928 + nouveau_wait_for_idle(dev); 929 929 + 930 930 + PIPE_RESTORE(dev, pipe_0x0040, 0x0040); 931 931 + 932 932 + nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0); 933 933 + nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1); 934 934 + 935 935 + PIPE_RESTORE(dev, pipe_0x64c0, 0x64c0); 936 936 + PIPE_RESTORE(dev, pipe_0x6ab0, 0x6ab0); 937 937 + PIPE_RESTORE(dev, pipe_0x6a80, 0x6a80); 938 938 + PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400); 939 939 + 940 940 + nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); 941 941 + nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000); 942 942 + 943 943 + nouveau_wait_for_idle(dev); 944 944 + 945 945 + pgraph->fifo_access(dev, true); 946 946 + 947 947 + return 0; 948 948 + } 949 949 + 950 950 + static int 951 951 + nv17_graph_mthd_lma_enable(struct nouveau_channel *chan, int grclass, 952 952 + int mthd, uint32_t data) 953 953 + { 954 954 + struct drm_device *dev = chan->dev; 955 955 + struct drm_nouveau_private *dev_priv = dev->dev_private; 956 956 + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 957 957 + 958 958 + nouveau_wait_for_idle(dev); 959 959 + 960 960 + nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 961 961 + nv_rd32(dev, NV10_PGRAPH_DEBUG_4) | 0x1 << 8); 962 962 + nv_wr32(dev, 0x004006b0, 963 963 + nv_rd32(dev, 0x004006b0) | 0x8 << 24); 964 964 + 965 965 + pgraph->fifo_access(dev, true); 966 966 + 967 967 + return 0; 968 968 + } 969 969 + 970 970 + static struct nouveau_pgraph_object_method nv17_graph_celsius_mthds[] = { 971 971 + { 0x1638, nv17_graph_mthd_lma_window }, 972 972 + { 0x163c, nv17_graph_mthd_lma_window }, 973 973 + { 0x1640, nv17_graph_mthd_lma_window }, 974 974 + { 0x1644, nv17_graph_mthd_lma_window }, 975 975 + { 0x1658, nv17_graph_mthd_lma_enable }, 976 976 + {} 977 977 + }; 978 978 + 872 979 struct nouveau_pgraph_object_class nv10_graph_grclass[] = { 873 980 { 0x0030, false, NULL }, /* null */ 874 981 { 0x0039, false, NULL }, /* m2mf */ ··· 998 887 { 0x0095, false, NULL }, /* multitex_tri */ 999 888 { 0x0056, false, NULL }, /* celcius (nv10) */ 1000 889 { 0x0096, false, NULL }, /* celcius (nv11) */ 1001 1001 - { 0x0099, false, NULL }, /* celcius (nv17) */ 890 890 + { 0x0099, false, nv17_graph_celsius_mthds }, /* celcius (nv17) */ 1002 891 {} 1003 892 };

+2 -2

drivers/gpu/drm/nouveau/nv17_tv.c

reviewed

··· 219 219 return; 220 220 nouveau_encoder(encoder)->last_dpms = mode; 221 221 222 222 - NV_TRACE(dev, "Setting dpms mode %d on TV encoder (output %d)\n", 222 222 + NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n", 223 223 mode, nouveau_encoder(encoder)->dcb->index); 224 224 225 225 regs->ptv_200 &= ~1; ··· 619 619 { 620 620 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 621 621 622 622 - NV_DEBUG(encoder->dev, "\n"); 622 622 + NV_DEBUG_KMS(encoder->dev, "\n"); 623 623 624 624 drm_encoder_cleanup(encoder); 625 625 kfree(tv_enc);

+38 -174

drivers/gpu/drm/nouveau/nv40_graph.c

reviewed

··· 24 24 * 25 25 */ 26 26 27 27 - #include <linux/firmware.h> 28 28 - 29 27 #include "drmP.h" 30 28 #include "drm.h" 31 29 #include "nouveau_drv.h" 32 32 - 33 33 - MODULE_FIRMWARE("nouveau/nv40.ctxprog"); 34 34 - MODULE_FIRMWARE("nouveau/nv40.ctxvals"); 35 35 - MODULE_FIRMWARE("nouveau/nv41.ctxprog"); 36 36 - MODULE_FIRMWARE("nouveau/nv41.ctxvals"); 37 37 - MODULE_FIRMWARE("nouveau/nv42.ctxprog"); 38 38 - MODULE_FIRMWARE("nouveau/nv42.ctxvals"); 39 39 - MODULE_FIRMWARE("nouveau/nv43.ctxprog"); 40 40 - MODULE_FIRMWARE("nouveau/nv43.ctxvals"); 41 41 - MODULE_FIRMWARE("nouveau/nv44.ctxprog"); 42 42 - MODULE_FIRMWARE("nouveau/nv44.ctxvals"); 43 43 - MODULE_FIRMWARE("nouveau/nv46.ctxprog"); 44 44 - MODULE_FIRMWARE("nouveau/nv46.ctxvals"); 45 45 - MODULE_FIRMWARE("nouveau/nv47.ctxprog"); 46 46 - MODULE_FIRMWARE("nouveau/nv47.ctxvals"); 47 47 - MODULE_FIRMWARE("nouveau/nv49.ctxprog"); 48 48 - MODULE_FIRMWARE("nouveau/nv49.ctxvals"); 49 49 - MODULE_FIRMWARE("nouveau/nv4a.ctxprog"); 50 50 - MODULE_FIRMWARE("nouveau/nv4a.ctxvals"); 51 51 - MODULE_FIRMWARE("nouveau/nv4b.ctxprog"); 52 52 - MODULE_FIRMWARE("nouveau/nv4b.ctxvals"); 53 53 - MODULE_FIRMWARE("nouveau/nv4c.ctxprog"); 54 54 - MODULE_FIRMWARE("nouveau/nv4c.ctxvals"); 55 55 - MODULE_FIRMWARE("nouveau/nv4e.ctxprog"); 56 56 - MODULE_FIRMWARE("nouveau/nv4e.ctxvals"); 30 30 + #include "nouveau_grctx.h" 57 31 58 32 struct nouveau_channel * 59 33 nv40_graph_channel(struct drm_device *dev) ··· 57 83 { 58 84 struct drm_device *dev = chan->dev; 59 85 struct drm_nouveau_private *dev_priv = dev->dev_private; 60 60 - struct nouveau_gpuobj *ctx; 86 86 + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 61 87 int ret; 62 88 63 63 - /* Allocate a 175KiB block of PRAMIN to store the context. This 64 64 - * is massive overkill for a lot of chipsets, but it should be safe 65 65 - * until we're able to implement this properly (will happen at more 66 66 - * or less the same time we're able to write our own context programs. 67 67 - */ 68 68 - ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 175*1024, 16, 69 69 - NVOBJ_FLAG_ZERO_ALLOC, 70 70 - &chan->ramin_grctx); 89 89 + ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size, 90 90 + 16, NVOBJ_FLAG_ZERO_ALLOC, 91 91 + &chan->ramin_grctx); 71 92 if (ret) 72 93 return ret; 73 73 - ctx = chan->ramin_grctx->gpuobj; 74 94 75 95 /* Initialise default context values */ 76 96 dev_priv->engine.instmem.prepare_access(dev, true); 77 77 - nv40_grctx_vals_load(dev, ctx); 78 78 - nv_wo32(dev, ctx, 0, ctx->im_pramin->start); 79 79 - dev_priv->engine.instmem.finish_access(dev); 97 97 + if (!pgraph->ctxprog) { 98 98 + struct nouveau_grctx ctx = {}; 80 99 100 100 + ctx.dev = chan->dev; 101 101 + ctx.mode = NOUVEAU_GRCTX_VALS; 102 102 + ctx.data = chan->ramin_grctx->gpuobj; 103 103 + nv40_grctx_init(&ctx); 104 104 + } else { 105 105 + nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj); 106 106 + } 107 107 + nv_wo32(dev, chan->ramin_grctx->gpuobj, 0, 108 108 + chan->ramin_grctx->gpuobj->im_pramin->start); 109 109 + dev_priv->engine.instmem.finish_access(dev); 81 110 return 0; 82 111 } 83 112 ··· 181 204 return ret; 182 205 } 183 206 184 184 - struct nouveau_ctxprog { 185 185 - uint32_t signature; 186 186 - uint8_t version; 187 187 - uint16_t length; 188 188 - uint32_t data[]; 189 189 - } __attribute__ ((packed)); 190 190 - 191 191 - struct nouveau_ctxvals { 192 192 - uint32_t signature; 193 193 - uint8_t version; 194 194 - uint32_t length; 195 195 - struct { 196 196 - uint32_t offset; 197 197 - uint32_t value; 198 198 - } data[]; 199 199 - } __attribute__ ((packed)); 200 200 - 201 201 - int 202 202 - nv40_grctx_init(struct drm_device *dev) 203 203 - { 204 204 - struct drm_nouveau_private *dev_priv = dev->dev_private; 205 205 - struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 206 206 - const int chipset = dev_priv->chipset; 207 207 - const struct firmware *fw; 208 208 - const struct nouveau_ctxprog *cp; 209 209 - const struct nouveau_ctxvals *cv; 210 210 - char name[32]; 211 211 - int ret, i; 212 212 - 213 213 - pgraph->accel_blocked = true; 214 214 - 215 215 - if (!pgraph->ctxprog) { 216 216 - sprintf(name, "nouveau/nv%02x.ctxprog", chipset); 217 217 - ret = request_firmware(&fw, name, &dev->pdev->dev); 218 218 - if (ret) { 219 219 - NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset); 220 220 - return ret; 221 221 - } 222 222 - 223 223 - pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL); 224 224 - if (!pgraph->ctxprog) { 225 225 - NV_ERROR(dev, "OOM copying ctxprog\n"); 226 226 - release_firmware(fw); 227 227 - return -ENOMEM; 228 228 - } 229 229 - memcpy(pgraph->ctxprog, fw->data, fw->size); 230 230 - 231 231 - cp = pgraph->ctxprog; 232 232 - if (le32_to_cpu(cp->signature) != 0x5043564e || 233 233 - cp->version != 0 || 234 234 - le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) { 235 235 - NV_ERROR(dev, "ctxprog invalid\n"); 236 236 - release_firmware(fw); 237 237 - nv40_grctx_fini(dev); 238 238 - return -EINVAL; 239 239 - } 240 240 - release_firmware(fw); 241 241 - } 242 242 - 243 243 - if (!pgraph->ctxvals) { 244 244 - sprintf(name, "nouveau/nv%02x.ctxvals", chipset); 245 245 - ret = request_firmware(&fw, name, &dev->pdev->dev); 246 246 - if (ret) { 247 247 - NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset); 248 248 - nv40_grctx_fini(dev); 249 249 - return ret; 250 250 - } 251 251 - 252 252 - pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL); 253 253 - if (!pgraph->ctxprog) { 254 254 - NV_ERROR(dev, "OOM copying ctxprog\n"); 255 255 - release_firmware(fw); 256 256 - nv40_grctx_fini(dev); 257 257 - return -ENOMEM; 258 258 - } 259 259 - memcpy(pgraph->ctxvals, fw->data, fw->size); 260 260 - 261 261 - cv = (void *)pgraph->ctxvals; 262 262 - if (le32_to_cpu(cv->signature) != 0x5643564e || 263 263 - cv->version != 0 || 264 264 - le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) { 265 265 - NV_ERROR(dev, "ctxvals invalid\n"); 266 266 - release_firmware(fw); 267 267 - nv40_grctx_fini(dev); 268 268 - return -EINVAL; 269 269 - } 270 270 - release_firmware(fw); 271 271 - } 272 272 - 273 273 - cp = pgraph->ctxprog; 274 274 - 275 275 - nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 276 276 - for (i = 0; i < le16_to_cpu(cp->length); i++) 277 277 - nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, 278 278 - le32_to_cpu(cp->data[i])); 279 279 - 280 280 - pgraph->accel_blocked = false; 281 281 - return 0; 282 282 - } 283 283 - 284 284 - void 285 285 - nv40_grctx_fini(struct drm_device *dev) 286 286 - { 287 287 - struct drm_nouveau_private *dev_priv = dev->dev_private; 288 288 - struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 289 289 - 290 290 - if (pgraph->ctxprog) { 291 291 - kfree(pgraph->ctxprog); 292 292 - pgraph->ctxprog = NULL; 293 293 - } 294 294 - 295 295 - if (pgraph->ctxvals) { 296 296 - kfree(pgraph->ctxprog); 297 297 - pgraph->ctxvals = NULL; 298 298 - } 299 299 - } 300 300 - 301 301 - void 302 302 - nv40_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx) 303 303 - { 304 304 - struct drm_nouveau_private *dev_priv = dev->dev_private; 305 305 - struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 306 306 - struct nouveau_ctxvals *cv = pgraph->ctxvals; 307 307 - int i; 308 308 - 309 309 - if (!cv) 310 310 - return; 311 311 - 312 312 - for (i = 0; i < le32_to_cpu(cv->length); i++) 313 313 - nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset), 314 314 - le32_to_cpu(cv->data[i].value)); 315 315 - } 316 316 - 317 207 /* 318 208 * G70 0x47 319 209 * G71 0x49 ··· 203 359 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | 204 360 NV_PMC_ENABLE_PGRAPH); 205 361 206 206 - nv40_grctx_init(dev); 362 362 + if (nouveau_ctxfw) { 363 363 + nouveau_grctx_prog_load(dev); 364 364 + dev_priv->engine.graph.grctx_size = 175 * 1024; 365 365 + } 366 366 + 367 367 + if (!dev_priv->engine.graph.ctxprog) { 368 368 + struct nouveau_grctx ctx = {}; 369 369 + uint32_t cp[256]; 370 370 + 371 371 + ctx.dev = dev; 372 372 + ctx.mode = NOUVEAU_GRCTX_PROG; 373 373 + ctx.data = cp; 374 374 + ctx.ctxprog_max = 256; 375 375 + nv40_grctx_init(&ctx); 376 376 + dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4; 377 377 + 378 378 + nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 379 379 + for (i = 0; i < ctx.ctxprog_len; i++) 380 380 + nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]); 381 381 + } 207 382 208 383 /* No context present currently */ 209 384 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); ··· 402 539 403 540 void nv40_graph_takedown(struct drm_device *dev) 404 541 { 542 542 + nouveau_grctx_fini(dev); 405 543 } 406 544 407 545 struct nouveau_pgraph_object_class nv40_graph_grclass[] = {

+678

drivers/gpu/drm/nouveau/nv40_grctx.c

reviewed

··· 1 1 + /* 2 2 + * Copyright 2009 Red Hat Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included in 12 12 + * all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 21 + * 22 22 + * Authors: Ben Skeggs 23 23 + */ 24 24 + 25 25 + /* NVIDIA context programs handle a number of other conditions which are 26 26 + * not implemented in our versions. It's not clear why NVIDIA context 27 27 + * programs have this code, nor whether it's strictly necessary for 28 28 + * correct operation. We'll implement additional handling if/when we 29 29 + * discover it's necessary. 30 30 + * 31 31 + * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" 32 32 + * flag is set, this gets saved into the context. 33 33 + * - On context save, the context program for all cards load nsource 34 34 + * into a flag register and check for ILLEGAL_MTHD. If it's set, 35 35 + * opcode 0x60000d is called before resuming normal operation. 36 36 + * - Some context programs check more conditions than the above. NV44 37 37 + * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) 38 38 + * and calls 0x60000d before resuming normal operation. 39 39 + * - At the very beginning of NVIDIA's context programs, flag 9 is checked 40 40 + * and if true 0x800001 is called with count=0, pos=0, the flag is cleared 41 41 + * and then the ctxprog is aborted. It looks like a complicated NOP, 42 42 + * its purpose is unknown. 43 43 + * - In the section of code that loads the per-vs state, NVIDIA check 44 44 + * flag 10. If it's set, they only transfer the small 0x300 byte block 45 45 + * of state + the state for a single vs as opposed to the state for 46 46 + * all vs units. It doesn't seem likely that it'll occur in normal 47 47 + * operation, especially seeing as it appears NVIDIA may have screwed 48 48 + * up the ctxprogs for some cards and have an invalid instruction 49 49 + * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. 50 50 + * - There's a number of places where context offset 0 (where we place 51 51 + * the PRAMIN offset of the context) is loaded into either 0x408000, 52 52 + * 0x408004 or 0x408008. Not sure what's up there either. 53 53 + * - The ctxprogs for some cards save 0x400a00 again during the cleanup 54 54 + * path for auto-loadctx. 55 55 + */ 56 56 + 57 57 + #define CP_FLAG_CLEAR 0 58 58 + #define CP_FLAG_SET 1 59 59 + #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) 60 60 + #define CP_FLAG_SWAP_DIRECTION_LOAD 0 61 61 + #define CP_FLAG_SWAP_DIRECTION_SAVE 1 62 62 + #define CP_FLAG_USER_SAVE ((0 * 32) + 5) 63 63 + #define CP_FLAG_USER_SAVE_NOT_PENDING 0 64 64 + #define CP_FLAG_USER_SAVE_PENDING 1 65 65 + #define CP_FLAG_USER_LOAD ((0 * 32) + 6) 66 66 + #define CP_FLAG_USER_LOAD_NOT_PENDING 0 67 67 + #define CP_FLAG_USER_LOAD_PENDING 1 68 68 + #define CP_FLAG_STATUS ((3 * 32) + 0) 69 69 + #define CP_FLAG_STATUS_IDLE 0 70 70 + #define CP_FLAG_STATUS_BUSY 1 71 71 + #define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) 72 72 + #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 73 73 + #define CP_FLAG_AUTO_SAVE_PENDING 1 74 74 + #define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) 75 75 + #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 76 76 + #define CP_FLAG_AUTO_LOAD_PENDING 1 77 77 + #define CP_FLAG_UNK54 ((3 * 32) + 6) 78 78 + #define CP_FLAG_UNK54_CLEAR 0 79 79 + #define CP_FLAG_UNK54_SET 1 80 80 + #define CP_FLAG_ALWAYS ((3 * 32) + 8) 81 81 + #define CP_FLAG_ALWAYS_FALSE 0 82 82 + #define CP_FLAG_ALWAYS_TRUE 1 83 83 + #define CP_FLAG_UNK57 ((3 * 32) + 9) 84 84 + #define CP_FLAG_UNK57_CLEAR 0 85 85 + #define CP_FLAG_UNK57_SET 1 86 86 + 87 87 + #define CP_CTX 0x00100000 88 88 + #define CP_CTX_COUNT 0x000fc000 89 89 + #define CP_CTX_COUNT_SHIFT 14 90 90 + #define CP_CTX_REG 0x00003fff 91 91 + #define CP_LOAD_SR 0x00200000 92 92 + #define CP_LOAD_SR_VALUE 0x000fffff 93 93 + #define CP_BRA 0x00400000 94 94 + #define CP_BRA_IP 0x0000ff00 95 95 + #define CP_BRA_IP_SHIFT 8 96 96 + #define CP_BRA_IF_CLEAR 0x00000080 97 97 + #define CP_BRA_FLAG 0x0000007f 98 98 + #define CP_WAIT 0x00500000 99 99 + #define CP_WAIT_SET 0x00000080 100 100 + #define CP_WAIT_FLAG 0x0000007f 101 101 + #define CP_SET 0x00700000 102 102 + #define CP_SET_1 0x00000080 103 103 + #define CP_SET_FLAG 0x0000007f 104 104 + #define CP_NEXT_TO_SWAP 0x00600007 105 105 + #define CP_NEXT_TO_CURRENT 0x00600009 106 106 + #define CP_SET_CONTEXT_POINTER 0x0060000a 107 107 + #define CP_END 0x0060000e 108 108 + #define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ 109 109 + #define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ 110 110 + #define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ 111 111 + 112 112 + #include "drmP.h" 113 113 + #include "nouveau_drv.h" 114 114 + #include "nouveau_grctx.h" 115 115 + 116 116 + /* TODO: 117 117 + * - get vs count from 0x1540 118 118 + * - document unimplemented bits compared to nvidia 119 119 + * - nsource handling 120 120 + * - R0 & 0x0200 handling 121 121 + * - single-vs handling 122 122 + * - 400314 bit 0 123 123 + */ 124 124 + 125 125 + static int 126 126 + nv40_graph_4097(struct drm_device *dev) 127 127 + { 128 128 + struct drm_nouveau_private *dev_priv = dev->dev_private; 129 129 + 130 130 + if ((dev_priv->chipset & 0xf0) == 0x60) 131 131 + return 0; 132 132 + 133 133 + return !!(0x0baf & (1 << dev_priv->chipset)); 134 134 + } 135 135 + 136 136 + static int 137 137 + nv40_graph_vs_count(struct drm_device *dev) 138 138 + { 139 139 + struct drm_nouveau_private *dev_priv = dev->dev_private; 140 140 + 141 141 + switch (dev_priv->chipset) { 142 142 + case 0x47: 143 143 + case 0x49: 144 144 + case 0x4b: 145 145 + return 8; 146 146 + case 0x40: 147 147 + return 6; 148 148 + case 0x41: 149 149 + case 0x42: 150 150 + return 5; 151 151 + case 0x43: 152 152 + case 0x44: 153 153 + case 0x46: 154 154 + case 0x4a: 155 155 + return 3; 156 156 + case 0x4c: 157 157 + case 0x4e: 158 158 + case 0x67: 159 159 + default: 160 160 + return 1; 161 161 + } 162 162 + } 163 163 + 164 164 + 165 165 + enum cp_label { 166 166 + cp_check_load = 1, 167 167 + cp_setup_auto_load, 168 168 + cp_setup_load, 169 169 + cp_setup_save, 170 170 + cp_swap_state, 171 171 + cp_swap_state3d_3_is_save, 172 172 + cp_prepare_exit, 173 173 + cp_exit, 174 174 + }; 175 175 + 176 176 + static void 177 177 + nv40_graph_construct_general(struct nouveau_grctx *ctx) 178 178 + { 179 179 + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; 180 180 + int i; 181 181 + 182 182 + cp_ctx(ctx, 0x4000a4, 1); 183 183 + gr_def(ctx, 0x4000a4, 0x00000008); 184 184 + cp_ctx(ctx, 0x400144, 58); 185 185 + gr_def(ctx, 0x400144, 0x00000001); 186 186 + cp_ctx(ctx, 0x400314, 1); 187 187 + gr_def(ctx, 0x400314, 0x00000000); 188 188 + cp_ctx(ctx, 0x400400, 10); 189 189 + cp_ctx(ctx, 0x400480, 10); 190 190 + cp_ctx(ctx, 0x400500, 19); 191 191 + gr_def(ctx, 0x400514, 0x00040000); 192 192 + gr_def(ctx, 0x400524, 0x55555555); 193 193 + gr_def(ctx, 0x400528, 0x55555555); 194 194 + gr_def(ctx, 0x40052c, 0x55555555); 195 195 + gr_def(ctx, 0x400530, 0x55555555); 196 196 + cp_ctx(ctx, 0x400560, 6); 197 197 + gr_def(ctx, 0x400568, 0x0000ffff); 198 198 + gr_def(ctx, 0x40056c, 0x0000ffff); 199 199 + cp_ctx(ctx, 0x40057c, 5); 200 200 + cp_ctx(ctx, 0x400710, 3); 201 201 + gr_def(ctx, 0x400710, 0x20010001); 202 202 + gr_def(ctx, 0x400714, 0x0f73ef00); 203 203 + cp_ctx(ctx, 0x400724, 1); 204 204 + gr_def(ctx, 0x400724, 0x02008821); 205 205 + cp_ctx(ctx, 0x400770, 3); 206 206 + if (dev_priv->chipset == 0x40) { 207 207 + cp_ctx(ctx, 0x400814, 4); 208 208 + cp_ctx(ctx, 0x400828, 5); 209 209 + cp_ctx(ctx, 0x400840, 5); 210 210 + gr_def(ctx, 0x400850, 0x00000040); 211 211 + cp_ctx(ctx, 0x400858, 4); 212 212 + gr_def(ctx, 0x400858, 0x00000040); 213 213 + gr_def(ctx, 0x40085c, 0x00000040); 214 214 + gr_def(ctx, 0x400864, 0x80000000); 215 215 + cp_ctx(ctx, 0x40086c, 9); 216 216 + gr_def(ctx, 0x40086c, 0x80000000); 217 217 + gr_def(ctx, 0x400870, 0x80000000); 218 218 + gr_def(ctx, 0x400874, 0x80000000); 219 219 + gr_def(ctx, 0x400878, 0x80000000); 220 220 + gr_def(ctx, 0x400888, 0x00000040); 221 221 + gr_def(ctx, 0x40088c, 0x80000000); 222 222 + cp_ctx(ctx, 0x4009c0, 8); 223 223 + gr_def(ctx, 0x4009cc, 0x80000000); 224 224 + gr_def(ctx, 0x4009dc, 0x80000000); 225 225 + } else { 226 226 + cp_ctx(ctx, 0x400840, 20); 227 227 + if (!nv40_graph_4097(ctx->dev)) { 228 228 + for (i = 0; i < 8; i++) 229 229 + gr_def(ctx, 0x400860 + (i * 4), 0x00000001); 230 230 + } 231 231 + gr_def(ctx, 0x400880, 0x00000040); 232 232 + gr_def(ctx, 0x400884, 0x00000040); 233 233 + gr_def(ctx, 0x400888, 0x00000040); 234 234 + cp_ctx(ctx, 0x400894, 11); 235 235 + gr_def(ctx, 0x400894, 0x00000040); 236 236 + if (nv40_graph_4097(ctx->dev)) { 237 237 + for (i = 0; i < 8; i++) 238 238 + gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); 239 239 + } 240 240 + cp_ctx(ctx, 0x4008e0, 2); 241 241 + cp_ctx(ctx, 0x4008f8, 2); 242 242 + if (dev_priv->chipset == 0x4c || 243 243 + (dev_priv->chipset & 0xf0) == 0x60) 244 244 + cp_ctx(ctx, 0x4009f8, 1); 245 245 + } 246 246 + cp_ctx(ctx, 0x400a00, 73); 247 247 + gr_def(ctx, 0x400b0c, 0x0b0b0b0c); 248 248 + cp_ctx(ctx, 0x401000, 4); 249 249 + cp_ctx(ctx, 0x405004, 1); 250 250 + switch (dev_priv->chipset) { 251 251 + case 0x47: 252 252 + case 0x49: 253 253 + case 0x4b: 254 254 + cp_ctx(ctx, 0x403448, 1); 255 255 + gr_def(ctx, 0x403448, 0x00001010); 256 256 + break; 257 257 + default: 258 258 + cp_ctx(ctx, 0x403440, 1); 259 259 + switch (dev_priv->chipset) { 260 260 + case 0x40: 261 261 + gr_def(ctx, 0x403440, 0x00000010); 262 262 + break; 263 263 + case 0x44: 264 264 + case 0x46: 265 265 + case 0x4a: 266 266 + gr_def(ctx, 0x403440, 0x00003010); 267 267 + break; 268 268 + case 0x41: 269 269 + case 0x42: 270 270 + case 0x43: 271 271 + case 0x4c: 272 272 + case 0x4e: 273 273 + case 0x67: 274 274 + default: 275 275 + gr_def(ctx, 0x403440, 0x00001010); 276 276 + break; 277 277 + } 278 278 + break; 279 279 + } 280 280 + } 281 281 + 282 282 + static void 283 283 + nv40_graph_construct_state3d(struct nouveau_grctx *ctx) 284 284 + { 285 285 + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; 286 286 + int i; 287 287 + 288 288 + if (dev_priv->chipset == 0x40) { 289 289 + cp_ctx(ctx, 0x401880, 51); 290 290 + gr_def(ctx, 0x401940, 0x00000100); 291 291 + } else 292 292 + if (dev_priv->chipset == 0x46 || dev_priv->chipset == 0x47 || 293 293 + dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) { 294 294 + cp_ctx(ctx, 0x401880, 32); 295 295 + for (i = 0; i < 16; i++) 296 296 + gr_def(ctx, 0x401880 + (i * 4), 0x00000111); 297 297 + if (dev_priv->chipset == 0x46) 298 298 + cp_ctx(ctx, 0x401900, 16); 299 299 + cp_ctx(ctx, 0x401940, 3); 300 300 + } 301 301 + cp_ctx(ctx, 0x40194c, 18); 302 302 + gr_def(ctx, 0x401954, 0x00000111); 303 303 + gr_def(ctx, 0x401958, 0x00080060); 304 304 + gr_def(ctx, 0x401974, 0x00000080); 305 305 + gr_def(ctx, 0x401978, 0xffff0000); 306 306 + gr_def(ctx, 0x40197c, 0x00000001); 307 307 + gr_def(ctx, 0x401990, 0x46400000); 308 308 + if (dev_priv->chipset == 0x40) { 309 309 + cp_ctx(ctx, 0x4019a0, 2); 310 310 + cp_ctx(ctx, 0x4019ac, 5); 311 311 + } else { 312 312 + cp_ctx(ctx, 0x4019a0, 1); 313 313 + cp_ctx(ctx, 0x4019b4, 3); 314 314 + } 315 315 + gr_def(ctx, 0x4019bc, 0xffff0000); 316 316 + switch (dev_priv->chipset) { 317 317 + case 0x46: 318 318 + case 0x47: 319 319 + case 0x49: 320 320 + case 0x4b: 321 321 + cp_ctx(ctx, 0x4019c0, 18); 322 322 + for (i = 0; i < 16; i++) 323 323 + gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); 324 324 + break; 325 325 + } 326 326 + cp_ctx(ctx, 0x401a08, 8); 327 327 + gr_def(ctx, 0x401a10, 0x0fff0000); 328 328 + gr_def(ctx, 0x401a14, 0x0fff0000); 329 329 + gr_def(ctx, 0x401a1c, 0x00011100); 330 330 + cp_ctx(ctx, 0x401a2c, 4); 331 331 + cp_ctx(ctx, 0x401a44, 26); 332 332 + for (i = 0; i < 16; i++) 333 333 + gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); 334 334 + gr_def(ctx, 0x401a8c, 0x4b7fffff); 335 335 + if (dev_priv->chipset == 0x40) { 336 336 + cp_ctx(ctx, 0x401ab8, 3); 337 337 + } else { 338 338 + cp_ctx(ctx, 0x401ab8, 1); 339 339 + cp_ctx(ctx, 0x401ac0, 1); 340 340 + } 341 341 + cp_ctx(ctx, 0x401ad0, 8); 342 342 + gr_def(ctx, 0x401ad0, 0x30201000); 343 343 + gr_def(ctx, 0x401ad4, 0x70605040); 344 344 + gr_def(ctx, 0x401ad8, 0xb8a89888); 345 345 + gr_def(ctx, 0x401adc, 0xf8e8d8c8); 346 346 + cp_ctx(ctx, 0x401b10, dev_priv->chipset == 0x40 ? 2 : 1); 347 347 + gr_def(ctx, 0x401b10, 0x40100000); 348 348 + cp_ctx(ctx, 0x401b18, dev_priv->chipset == 0x40 ? 6 : 5); 349 349 + gr_def(ctx, 0x401b28, dev_priv->chipset == 0x40 ? 350 350 + 0x00000004 : 0x00000000); 351 351 + cp_ctx(ctx, 0x401b30, 25); 352 352 + gr_def(ctx, 0x401b34, 0x0000ffff); 353 353 + gr_def(ctx, 0x401b68, 0x435185d6); 354 354 + gr_def(ctx, 0x401b6c, 0x2155b699); 355 355 + gr_def(ctx, 0x401b70, 0xfedcba98); 356 356 + gr_def(ctx, 0x401b74, 0x00000098); 357 357 + gr_def(ctx, 0x401b84, 0xffffffff); 358 358 + gr_def(ctx, 0x401b88, 0x00ff7000); 359 359 + gr_def(ctx, 0x401b8c, 0x0000ffff); 360 360 + if (dev_priv->chipset != 0x44 && dev_priv->chipset != 0x4a && 361 361 + dev_priv->chipset != 0x4e) 362 362 + cp_ctx(ctx, 0x401b94, 1); 363 363 + cp_ctx(ctx, 0x401b98, 8); 364 364 + gr_def(ctx, 0x401b9c, 0x00ff0000); 365 365 + cp_ctx(ctx, 0x401bc0, 9); 366 366 + gr_def(ctx, 0x401be0, 0x00ffff00); 367 367 + cp_ctx(ctx, 0x401c00, 192); 368 368 + for (i = 0; i < 16; i++) { /* fragment texture units */ 369 369 + gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); 370 370 + gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); 371 371 + gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); 372 372 + gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); 373 373 + gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); 374 374 + gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); 375 375 + } 376 376 + for (i = 0; i < 4; i++) { /* vertex texture units */ 377 377 + gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); 378 378 + gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); 379 379 + gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); 380 380 + gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); 381 381 + } 382 382 + cp_ctx(ctx, 0x400f5c, 3); 383 383 + gr_def(ctx, 0x400f5c, 0x00000002); 384 384 + cp_ctx(ctx, 0x400f84, 1); 385 385 + } 386 386 + 387 387 + static void 388 388 + nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) 389 389 + { 390 390 + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; 391 391 + int i; 392 392 + 393 393 + cp_ctx(ctx, 0x402000, 1); 394 394 + cp_ctx(ctx, 0x402404, dev_priv->chipset == 0x40 ? 1 : 2); 395 395 + switch (dev_priv->chipset) { 396 396 + case 0x40: 397 397 + gr_def(ctx, 0x402404, 0x00000001); 398 398 + break; 399 399 + case 0x4c: 400 400 + case 0x4e: 401 401 + case 0x67: 402 402 + gr_def(ctx, 0x402404, 0x00000020); 403 403 + break; 404 404 + case 0x46: 405 405 + case 0x49: 406 406 + case 0x4b: 407 407 + gr_def(ctx, 0x402404, 0x00000421); 408 408 + break; 409 409 + default: 410 410 + gr_def(ctx, 0x402404, 0x00000021); 411 411 + } 412 412 + if (dev_priv->chipset != 0x40) 413 413 + gr_def(ctx, 0x402408, 0x030c30c3); 414 414 + switch (dev_priv->chipset) { 415 415 + case 0x44: 416 416 + case 0x46: 417 417 + case 0x4a: 418 418 + case 0x4c: 419 419 + case 0x4e: 420 420 + case 0x67: 421 421 + cp_ctx(ctx, 0x402440, 1); 422 422 + gr_def(ctx, 0x402440, 0x00011001); 423 423 + break; 424 424 + default: 425 425 + break; 426 426 + } 427 427 + cp_ctx(ctx, 0x402480, dev_priv->chipset == 0x40 ? 8 : 9); 428 428 + gr_def(ctx, 0x402488, 0x3e020200); 429 429 + gr_def(ctx, 0x40248c, 0x00ffffff); 430 430 + switch (dev_priv->chipset) { 431 431 + case 0x40: 432 432 + gr_def(ctx, 0x402490, 0x60103f00); 433 433 + break; 434 434 + case 0x47: 435 435 + gr_def(ctx, 0x402490, 0x40103f00); 436 436 + break; 437 437 + case 0x41: 438 438 + case 0x42: 439 439 + case 0x49: 440 440 + case 0x4b: 441 441 + gr_def(ctx, 0x402490, 0x20103f00); 442 442 + break; 443 443 + default: 444 444 + gr_def(ctx, 0x402490, 0x0c103f00); 445 445 + break; 446 446 + } 447 447 + gr_def(ctx, 0x40249c, dev_priv->chipset <= 0x43 ? 448 448 + 0x00020000 : 0x00040000); 449 449 + cp_ctx(ctx, 0x402500, 31); 450 450 + gr_def(ctx, 0x402530, 0x00008100); 451 451 + if (dev_priv->chipset == 0x40) 452 452 + cp_ctx(ctx, 0x40257c, 6); 453 453 + cp_ctx(ctx, 0x402594, 16); 454 454 + cp_ctx(ctx, 0x402800, 17); 455 455 + gr_def(ctx, 0x402800, 0x00000001); 456 456 + switch (dev_priv->chipset) { 457 457 + case 0x47: 458 458 + case 0x49: 459 459 + case 0x4b: 460 460 + cp_ctx(ctx, 0x402864, 1); 461 461 + gr_def(ctx, 0x402864, 0x00001001); 462 462 + cp_ctx(ctx, 0x402870, 3); 463 463 + gr_def(ctx, 0x402878, 0x00000003); 464 464 + if (dev_priv->chipset != 0x47) { /* belong at end!! */ 465 465 + cp_ctx(ctx, 0x402900, 1); 466 466 + cp_ctx(ctx, 0x402940, 1); 467 467 + cp_ctx(ctx, 0x402980, 1); 468 468 + cp_ctx(ctx, 0x4029c0, 1); 469 469 + cp_ctx(ctx, 0x402a00, 1); 470 470 + cp_ctx(ctx, 0x402a40, 1); 471 471 + cp_ctx(ctx, 0x402a80, 1); 472 472 + cp_ctx(ctx, 0x402ac0, 1); 473 473 + } 474 474 + break; 475 475 + case 0x40: 476 476 + cp_ctx(ctx, 0x402844, 1); 477 477 + gr_def(ctx, 0x402844, 0x00000001); 478 478 + cp_ctx(ctx, 0x402850, 1); 479 479 + break; 480 480 + default: 481 481 + cp_ctx(ctx, 0x402844, 1); 482 482 + gr_def(ctx, 0x402844, 0x00001001); 483 483 + cp_ctx(ctx, 0x402850, 2); 484 484 + gr_def(ctx, 0x402854, 0x00000003); 485 485 + break; 486 486 + } 487 487 + 488 488 + cp_ctx(ctx, 0x402c00, 4); 489 489 + gr_def(ctx, 0x402c00, dev_priv->chipset == 0x40 ? 490 490 + 0x80800001 : 0x00888001); 491 491 + switch (dev_priv->chipset) { 492 492 + case 0x47: 493 493 + case 0x49: 494 494 + case 0x4b: 495 495 + cp_ctx(ctx, 0x402c20, 40); 496 496 + for (i = 0; i < 32; i++) 497 497 + gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); 498 498 + cp_ctx(ctx, 0x4030b8, 13); 499 499 + gr_def(ctx, 0x4030dc, 0x00000005); 500 500 + gr_def(ctx, 0x4030e8, 0x0000ffff); 501 501 + break; 502 502 + default: 503 503 + cp_ctx(ctx, 0x402c10, 4); 504 504 + if (dev_priv->chipset == 0x40) 505 505 + cp_ctx(ctx, 0x402c20, 36); 506 506 + else 507 507 + if (dev_priv->chipset <= 0x42) 508 508 + cp_ctx(ctx, 0x402c20, 24); 509 509 + else 510 510 + if (dev_priv->chipset <= 0x4a) 511 511 + cp_ctx(ctx, 0x402c20, 16); 512 512 + else 513 513 + cp_ctx(ctx, 0x402c20, 8); 514 514 + cp_ctx(ctx, 0x402cb0, dev_priv->chipset == 0x40 ? 12 : 13); 515 515 + gr_def(ctx, 0x402cd4, 0x00000005); 516 516 + if (dev_priv->chipset != 0x40) 517 517 + gr_def(ctx, 0x402ce0, 0x0000ffff); 518 518 + break; 519 519 + } 520 520 + 521 521 + cp_ctx(ctx, 0x403400, dev_priv->chipset == 0x40 ? 4 : 3); 522 522 + cp_ctx(ctx, 0x403410, dev_priv->chipset == 0x40 ? 4 : 3); 523 523 + cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->dev)); 524 524 + for (i = 0; i < nv40_graph_vs_count(ctx->dev); i++) 525 525 + gr_def(ctx, 0x403420 + (i * 4), 0x00005555); 526 526 + 527 527 + if (dev_priv->chipset != 0x40) { 528 528 + cp_ctx(ctx, 0x403600, 1); 529 529 + gr_def(ctx, 0x403600, 0x00000001); 530 530 + } 531 531 + cp_ctx(ctx, 0x403800, 1); 532 532 + 533 533 + cp_ctx(ctx, 0x403c18, 1); 534 534 + gr_def(ctx, 0x403c18, 0x00000001); 535 535 + switch (dev_priv->chipset) { 536 536 + case 0x46: 537 537 + case 0x47: 538 538 + case 0x49: 539 539 + case 0x4b: 540 540 + cp_ctx(ctx, 0x405018, 1); 541 541 + gr_def(ctx, 0x405018, 0x08e00001); 542 542 + cp_ctx(ctx, 0x405c24, 1); 543 543 + gr_def(ctx, 0x405c24, 0x000e3000); 544 544 + break; 545 545 + } 546 546 + if (dev_priv->chipset != 0x4e) 547 547 + cp_ctx(ctx, 0x405800, 11); 548 548 + cp_ctx(ctx, 0x407000, 1); 549 549 + } 550 550 + 551 551 + static void 552 552 + nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) 553 553 + { 554 554 + int len = nv40_graph_4097(ctx->dev) ? 0x0684 : 0x0084; 555 555 + 556 556 + cp_out (ctx, 0x300000); 557 557 + cp_lsr (ctx, len - 4); 558 558 + cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); 559 559 + cp_lsr (ctx, len); 560 560 + cp_name(ctx, cp_swap_state3d_3_is_save); 561 561 + cp_out (ctx, 0x800001); 562 562 + 563 563 + ctx->ctxvals_pos += len; 564 564 + } 565 565 + 566 566 + static void 567 567 + nv40_graph_construct_shader(struct nouveau_grctx *ctx) 568 568 + { 569 569 + struct drm_device *dev = ctx->dev; 570 570 + struct drm_nouveau_private *dev_priv = dev->dev_private; 571 571 + struct nouveau_gpuobj *obj = ctx->data; 572 572 + int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; 573 573 + int offset, i; 574 574 + 575 575 + vs_nr = nv40_graph_vs_count(ctx->dev); 576 576 + vs_nr_b0 = 363; 577 577 + vs_nr_b1 = dev_priv->chipset == 0x40 ? 128 : 64; 578 578 + if (dev_priv->chipset == 0x40) { 579 579 + b0_offset = 0x2200/4; /* 33a0 */ 580 580 + b1_offset = 0x55a0/4; /* 1500 */ 581 581 + vs_len = 0x6aa0/4; 582 582 + } else 583 583 + if (dev_priv->chipset == 0x41 || dev_priv->chipset == 0x42) { 584 584 + b0_offset = 0x2200/4; /* 2200 */ 585 585 + b1_offset = 0x4400/4; /* 0b00 */ 586 586 + vs_len = 0x4f00/4; 587 587 + } else { 588 588 + b0_offset = 0x1d40/4; /* 2200 */ 589 589 + b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ 590 590 + vs_len = nv40_graph_4097(dev) ? 0x4a40/4 : 0x4980/4; 591 591 + } 592 592 + 593 593 + cp_lsr(ctx, vs_len * vs_nr + 0x300/4); 594 594 + cp_out(ctx, nv40_graph_4097(dev) ? 0x800041 : 0x800029); 595 595 + 596 596 + offset = ctx->ctxvals_pos; 597 597 + ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); 598 598 + 599 599 + if (ctx->mode != NOUVEAU_GRCTX_VALS) 600 600 + return; 601 601 + 602 602 + offset += 0x0280/4; 603 603 + for (i = 0; i < 16; i++, offset += 2) 604 604 + nv_wo32(dev, obj, offset, 0x3f800000); 605 605 + 606 606 + for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { 607 607 + for (i = 0; i < vs_nr_b0 * 6; i += 6) 608 608 + nv_wo32(dev, obj, offset + b0_offset + i, 0x00000001); 609 609 + for (i = 0; i < vs_nr_b1 * 4; i += 4) 610 610 + nv_wo32(dev, obj, offset + b1_offset + i, 0x3f800000); 611 611 + } 612 612 + } 613 613 + 614 614 + void 615 615 + nv40_grctx_init(struct nouveau_grctx *ctx) 616 616 + { 617 617 + /* decide whether we're loading/unloading the context */ 618 618 + cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); 619 619 + cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); 620 620 + 621 621 + cp_name(ctx, cp_check_load); 622 622 + cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); 623 623 + cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); 624 624 + cp_bra (ctx, ALWAYS, TRUE, cp_exit); 625 625 + 626 626 + /* setup for context load */ 627 627 + cp_name(ctx, cp_setup_auto_load); 628 628 + cp_wait(ctx, STATUS, IDLE); 629 629 + cp_out (ctx, CP_NEXT_TO_SWAP); 630 630 + cp_name(ctx, cp_setup_load); 631 631 + cp_wait(ctx, STATUS, IDLE); 632 632 + cp_set (ctx, SWAP_DIRECTION, LOAD); 633 633 + cp_out (ctx, 0x00910880); /* ?? */ 634 634 + cp_out (ctx, 0x00901ffe); /* ?? */ 635 635 + cp_out (ctx, 0x01940000); /* ?? */ 636 636 + cp_lsr (ctx, 0x20); 637 637 + cp_out (ctx, 0x0060000b); /* ?? */ 638 638 + cp_wait(ctx, UNK57, CLEAR); 639 639 + cp_out (ctx, 0x0060000c); /* ?? */ 640 640 + cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); 641 641 + 642 642 + /* setup for context save */ 643 643 + cp_name(ctx, cp_setup_save); 644 644 + cp_set (ctx, SWAP_DIRECTION, SAVE); 645 645 + 646 646 + /* general PGRAPH state */ 647 647 + cp_name(ctx, cp_swap_state); 648 648 + cp_pos (ctx, 0x00020/4); 649 649 + nv40_graph_construct_general(ctx); 650 650 + cp_wait(ctx, STATUS, IDLE); 651 651 + 652 652 + /* 3D state, block 1 */ 653 653 + cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); 654 654 + nv40_graph_construct_state3d(ctx); 655 655 + cp_wait(ctx, STATUS, IDLE); 656 656 + 657 657 + /* 3D state, block 2 */ 658 658 + nv40_graph_construct_state3d_2(ctx); 659 659 + 660 660 + /* Some other block of "random" state */ 661 661 + nv40_graph_construct_state3d_3(ctx); 662 662 + 663 663 + /* Per-vertex shader state */ 664 664 + cp_pos (ctx, ctx->ctxvals_pos); 665 665 + nv40_graph_construct_shader(ctx); 666 666 + 667 667 + /* pre-exit state updates */ 668 668 + cp_name(ctx, cp_prepare_exit); 669 669 + cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); 670 670 + cp_bra (ctx, USER_SAVE, PENDING, cp_exit); 671 671 + cp_out (ctx, CP_NEXT_TO_CURRENT); 672 672 + 673 673 + cp_name(ctx, cp_exit); 674 674 + cp_set (ctx, USER_SAVE, NOT_PENDING); 675 675 + cp_set (ctx, USER_LOAD, NOT_PENDING); 676 676 + cp_out (ctx, CP_END); 677 677 + } 678 678 +

+11 -11

drivers/gpu/drm/nouveau/nv50_crtc.c

reviewed

··· 45 45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); 46 46 int i; 47 47 48 48 - NV_DEBUG(crtc->dev, "\n"); 48 48 + NV_DEBUG_KMS(crtc->dev, "\n"); 49 49 50 50 for (i = 0; i < 256; i++) { 51 51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); ··· 68 68 struct nouveau_channel *evo = dev_priv->evo; 69 69 int index = nv_crtc->index, ret; 70 70 71 71 - NV_DEBUG(dev, "index %d\n", nv_crtc->index); 72 72 - NV_DEBUG(dev, "%s\n", blanked ? "blanked" : "unblanked"); 71 71 + NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 72 72 + NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked"); 73 73 74 74 if (blanked) { 75 75 nv_crtc->cursor.hide(nv_crtc, false); ··· 139 139 struct nouveau_channel *evo = dev_priv->evo; 140 140 int ret; 141 141 142 142 - NV_DEBUG(dev, "\n"); 142 142 + NV_DEBUG_KMS(dev, "\n"); 143 143 144 144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); 145 145 if (ret) { ··· 193 193 uint32_t outX, outY, horiz, vert; 194 194 int ret; 195 195 196 196 - NV_DEBUG(dev, "\n"); 196 196 + NV_DEBUG_KMS(dev, "\n"); 197 197 198 198 switch (scaling_mode) { 199 199 case DRM_MODE_SCALE_NONE: ··· 301 301 struct drm_device *dev = crtc->dev; 302 302 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 303 303 304 304 - NV_DEBUG(dev, "\n"); 304 304 + NV_DEBUG_KMS(dev, "\n"); 305 305 306 306 if (!crtc) 307 307 return; ··· 433 433 struct drm_device *dev = crtc->dev; 434 434 struct drm_encoder *encoder; 435 435 436 436 - NV_DEBUG(dev, "index %d\n", nv_crtc->index); 436 436 + NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 437 437 438 438 /* Disconnect all unused encoders. */ 439 439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ··· 458 458 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 459 459 int ret; 460 460 461 461 - NV_DEBUG(dev, "index %d\n", nv_crtc->index); 461 461 + NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 462 462 463 463 nv50_crtc_blank(nv_crtc, false); 464 464 ··· 497 497 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); 498 498 int ret, format; 499 499 500 500 - NV_DEBUG(dev, "index %d\n", nv_crtc->index); 500 500 + NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 501 501 502 502 switch (drm_fb->depth) { 503 503 case 8: ··· 612 612 613 613 *nv_crtc->mode = *adjusted_mode; 614 614 615 615 - NV_DEBUG(dev, "index %d\n", nv_crtc->index); 615 615 + NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 616 616 617 617 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 618 618 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start; ··· 706 706 struct nouveau_crtc *nv_crtc = NULL; 707 707 int ret, i; 708 708 709 709 - NV_DEBUG(dev, "\n"); 709 709 + NV_DEBUG_KMS(dev, "\n"); 710 710 711 711 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 712 712 if (!nv_crtc)

+4 -4

drivers/gpu/drm/nouveau/nv50_cursor.c

reviewed

··· 41 41 struct drm_device *dev = nv_crtc->base.dev; 42 42 int ret; 43 43 44 44 - NV_DEBUG(dev, "\n"); 44 44 + NV_DEBUG_KMS(dev, "\n"); 45 45 46 46 if (update && nv_crtc->cursor.visible) 47 47 return; ··· 76 76 struct drm_device *dev = nv_crtc->base.dev; 77 77 int ret; 78 78 79 79 - NV_DEBUG(dev, "\n"); 79 79 + NV_DEBUG_KMS(dev, "\n"); 80 80 81 81 if (update && !nv_crtc->cursor.visible) 82 82 return; ··· 116 116 static void 117 117 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 118 118 { 119 119 - NV_DEBUG(nv_crtc->base.dev, "\n"); 119 119 + NV_DEBUG_KMS(nv_crtc->base.dev, "\n"); 120 120 if (offset == nv_crtc->cursor.offset) 121 121 return; 122 122 ··· 143 143 struct drm_device *dev = nv_crtc->base.dev; 144 144 int idx = nv_crtc->index; 145 145 146 146 - NV_DEBUG(dev, "\n"); 146 146 + NV_DEBUG_KMS(dev, "\n"); 147 147 148 148 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 0); 149 149 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx),

+10 -10

drivers/gpu/drm/nouveau/nv50_dac.c

reviewed

··· 44 44 struct nouveau_channel *evo = dev_priv->evo; 45 45 int ret; 46 46 47 47 - NV_DEBUG(dev, "Disconnecting DAC %d\n", nv_encoder->or); 47 47 + NV_DEBUG_KMS(dev, "Disconnecting DAC %d\n", nv_encoder->or); 48 48 49 49 ret = RING_SPACE(evo, 2); 50 50 if (ret) { ··· 81 81 /* Use bios provided value if possible. */ 82 82 if (dev_priv->vbios->dactestval) { 83 83 load_pattern = dev_priv->vbios->dactestval; 84 84 - NV_DEBUG(dev, "Using bios provided load_pattern of %d\n", 84 84 + NV_DEBUG_KMS(dev, "Using bios provided load_pattern of %d\n", 85 85 load_pattern); 86 86 } else { 87 87 load_pattern = 340; 88 88 - NV_DEBUG(dev, "Using default load_pattern of %d\n", 88 88 + NV_DEBUG_KMS(dev, "Using default load_pattern of %d\n", 89 89 load_pattern); 90 90 } 91 91 ··· 103 103 status = connector_status_connected; 104 104 105 105 if (status == connector_status_connected) 106 106 - NV_DEBUG(dev, "Load was detected on output with or %d\n", or); 106 106 + NV_DEBUG_KMS(dev, "Load was detected on output with or %d\n", or); 107 107 else 108 108 - NV_DEBUG(dev, "Load was not detected on output with or %d\n", or); 108 108 + NV_DEBUG_KMS(dev, "Load was not detected on output with or %d\n", or); 109 109 110 110 return status; 111 111 } ··· 118 118 uint32_t val; 119 119 int or = nv_encoder->or; 120 120 121 121 - NV_DEBUG(dev, "or %d mode %d\n", or, mode); 121 121 + NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode); 122 122 123 123 /* wait for it to be done */ 124 124 if (!nv_wait(NV50_PDISPLAY_DAC_DPMS_CTRL(or), ··· 173 173 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 174 174 struct nouveau_connector *connector; 175 175 176 176 - NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or); 176 176 + NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or); 177 177 178 178 connector = nouveau_encoder_connector_get(nv_encoder); 179 179 if (!connector) { ··· 213 213 uint32_t mode_ctl = 0, mode_ctl2 = 0; 214 214 int ret; 215 215 216 216 - NV_DEBUG(dev, "or %d\n", nv_encoder->or); 216 216 + NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or); 217 217 218 218 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); 219 219 ··· 264 264 if (!encoder) 265 265 return; 266 266 267 267 - NV_DEBUG(encoder->dev, "\n"); 267 267 + NV_DEBUG_KMS(encoder->dev, "\n"); 268 268 269 269 drm_encoder_cleanup(encoder); 270 270 kfree(nv_encoder); ··· 280 280 struct nouveau_encoder *nv_encoder; 281 281 struct drm_encoder *encoder; 282 282 283 283 - NV_DEBUG(dev, "\n"); 283 283 + NV_DEBUG_KMS(dev, "\n"); 284 284 NV_INFO(dev, "Detected a DAC output\n"); 285 285 286 286 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);

+10 -10

drivers/gpu/drm/nouveau/nv50_display.c

reviewed

··· 188 188 uint64_t start; 189 189 int ret, i; 190 190 191 191 - NV_DEBUG(dev, "\n"); 191 191 + NV_DEBUG_KMS(dev, "\n"); 192 192 193 193 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); 194 194 /* ··· 232 232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); 233 233 /* RAM is clamped to 256 MiB. */ 234 234 ram_amount = nouveau_mem_fb_amount(dev); 235 235 - NV_DEBUG(dev, "ram_amount %d\n", ram_amount); 235 235 + NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount); 236 236 if (ram_amount > 256*1024*1024) 237 237 ram_amount = 256*1024*1024; 238 238 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1); ··· 398 398 struct drm_crtc *drm_crtc; 399 399 int ret, i; 400 400 401 401 - NV_DEBUG(dev, "\n"); 401 401 + NV_DEBUG_KMS(dev, "\n"); 402 402 403 403 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 404 404 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); ··· 469 469 uint32_t connector[16] = {}; 470 470 int ret, i; 471 471 472 472 - NV_DEBUG(dev, "\n"); 472 472 + NV_DEBUG_KMS(dev, "\n"); 473 473 474 474 /* init basic kernel modesetting */ 475 475 drm_mode_config_init(dev); ··· 573 573 { 574 574 struct drm_nouveau_private *dev_priv = dev->dev_private; 575 575 576 576 - NV_DEBUG(dev, "\n"); 576 576 + NV_DEBUG_KMS(dev, "\n"); 577 577 578 578 drm_mode_config_cleanup(dev); 579 579 ··· 617 617 * CRTC separately, and submission will be blocked by the GPU 618 618 * until we handle each in turn. 619 619 */ 620 620 - NV_DEBUG(dev, "0x610030: 0x%08x\n", unk30); 620 620 + NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 621 621 head = ffs((unk30 >> 9) & 3) - 1; 622 622 if (head < 0) 623 623 return -EINVAL; ··· 661 661 or = i; 662 662 } 663 663 664 664 - NV_DEBUG(dev, "type %d, or %d\n", type, or); 664 664 + NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or); 665 665 if (type == OUTPUT_ANY) { 666 666 NV_ERROR(dev, "unknown encoder!!\n"); 667 667 return -1; ··· 811 811 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff; 812 812 script = nv50_display_script_select(dev, dcbent, pclk); 813 813 814 814 - NV_DEBUG(dev, "head %d pxclk: %dKHz\n", head, pclk); 814 814 + NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk); 815 815 816 816 if (dcbent->type != OUTPUT_DP) 817 817 nouveau_bios_run_display_table(dev, dcbent, 0, -2); ··· 870 870 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 871 871 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 872 872 873 873 - NV_DEBUG(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 873 873 + NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 874 874 875 875 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 876 876 nv50_display_unk10_handler(dev); ··· 974 974 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 975 975 uint32_t clock; 976 976 977 977 - NV_DEBUG(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 977 977 + NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 978 978 979 979 if (!intr0 && !(intr1 & ~delayed)) 980 980 break;

+1 -1

drivers/gpu/drm/nouveau/nv50_fifo.c

reviewed

··· 416 416 NV_DEBUG(dev, "\n"); 417 417 418 418 chid = pfifo->channel_id(dev); 419 419 - if (chid < 0 || chid >= dev_priv->engine.fifo.channels) 419 419 + if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1) 420 420 return 0; 421 421 422 422 chan = dev_priv->fifos[chid];

+7 -3

drivers/gpu/drm/nouveau/nv50_graph.c

reviewed

··· 107 107 static int 108 108 nv50_graph_init_ctxctl(struct drm_device *dev) 109 109 { 110 110 + struct drm_nouveau_private *dev_priv = dev->dev_private; 111 111 + 110 112 NV_DEBUG(dev, "\n"); 111 113 112 112 - nv40_grctx_init(dev); 114 114 + nouveau_grctx_prog_load(dev); 115 115 + if (!dev_priv->engine.graph.ctxprog) 116 116 + dev_priv->engine.graph.accel_blocked = true; 113 117 114 118 nv_wr32(dev, 0x400320, 4); 115 119 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); ··· 144 140 nv50_graph_takedown(struct drm_device *dev) 145 141 { 146 142 NV_DEBUG(dev, "\n"); 147 147 - nv40_grctx_fini(dev); 143 143 + nouveau_grctx_fini(dev); 148 144 } 149 145 150 146 void ··· 211 207 dev_priv->engine.instmem.finish_access(dev); 212 208 213 209 dev_priv->engine.instmem.prepare_access(dev, true); 214 214 - nv40_grctx_vals_load(dev, ctx); 210 210 + nouveau_grctx_vals_load(dev, ctx); 215 211 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12); 216 212 if ((dev_priv->chipset & 0xf0) == 0xa0) 217 213 nv_wo32(dev, ctx, 0x00004/4, 0x00000000);

+8 -8

drivers/gpu/drm/nouveau/nv50_sor.c

reviewed

··· 44 44 struct nouveau_channel *evo = dev_priv->evo; 45 45 int ret; 46 46 47 47 - NV_DEBUG(dev, "Disconnecting SOR %d\n", nv_encoder->or); 47 47 + NV_DEBUG_KMS(dev, "Disconnecting SOR %d\n", nv_encoder->or); 48 48 49 49 ret = RING_SPACE(evo, 2); 50 50 if (ret) { ··· 70 70 } 71 71 72 72 if (dpe->script0) { 73 73 - NV_DEBUG(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); 73 73 + NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); 74 74 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0), 75 75 nv_encoder->dcb); 76 76 } ··· 79 79 NV_ERROR(dev, "SOR-%d: link training failed\n", nv_encoder->or); 80 80 81 81 if (dpe->script1) { 82 82 - NV_DEBUG(dev, "SOR-%d: running DP script 1\n", nv_encoder->or); 82 82 + NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or); 83 83 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1), 84 84 nv_encoder->dcb); 85 85 } ··· 93 93 uint32_t val; 94 94 int or = nv_encoder->or; 95 95 96 96 - NV_DEBUG(dev, "or %d mode %d\n", or, mode); 96 96 + NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode); 97 97 98 98 /* wait for it to be done */ 99 99 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or), ··· 142 142 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 143 143 struct nouveau_connector *connector; 144 144 145 145 - NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or); 145 145 + NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or); 146 146 147 147 connector = nouveau_encoder_connector_get(nv_encoder); 148 148 if (!connector) { ··· 182 182 uint32_t mode_ctl = 0; 183 183 int ret; 184 184 185 185 - NV_DEBUG(dev, "or %d\n", nv_encoder->or); 185 185 + NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or); 186 186 187 187 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); 188 188 ··· 246 246 if (!encoder) 247 247 return; 248 248 249 249 - NV_DEBUG(encoder->dev, "\n"); 249 249 + NV_DEBUG_KMS(encoder->dev, "\n"); 250 250 251 251 drm_encoder_cleanup(encoder); 252 252 ··· 265 265 bool dum; 266 266 int type; 267 267 268 268 - NV_DEBUG(dev, "\n"); 268 268 + NV_DEBUG_KMS(dev, "\n"); 269 269 270 270 switch (entry->type) { 271 271 case OUTPUT_TMDS:

+1 -1

drivers/gpu/drm/r128/r128_drv.c

reviewed

··· 64 64 .owner = THIS_MODULE, 65 65 .open = drm_open, 66 66 .release = drm_release, 67 67 - .ioctl = drm_ioctl, 67 67 + .unlocked_ioctl = drm_ioctl, 68 68 .mmap = drm_mmap, 69 69 .poll = drm_poll, 70 70 .fasync = drm_fasync,

+5 -11

drivers/gpu/drm/r128/r128_ioc32.c

reviewed

··· 95 95 &init->agp_textures_offset)) 96 96 return -EFAULT; 97 97 98 98 - return drm_ioctl(file->f_path.dentry->d_inode, file, 99 99 - DRM_IOCTL_R128_INIT, (unsigned long)init); 98 98 + return drm_ioctl(file, DRM_IOCTL_R128_INIT, (unsigned long)init); 100 99 } 101 100 102 101 typedef struct drm_r128_depth32 { ··· 128 129 &depth->mask)) 129 130 return -EFAULT; 130 131 131 131 - return drm_ioctl(file->f_path.dentry->d_inode, file, 132 132 - DRM_IOCTL_R128_DEPTH, (unsigned long)depth); 132 132 + return drm_ioctl(file, DRM_IOCTL_R128_DEPTH, (unsigned long)depth); 133 133 134 134 } 135 135 ··· 151 153 &stipple->mask)) 152 154 return -EFAULT; 153 155 154 154 - return drm_ioctl(file->f_path.dentry->d_inode, file, 155 155 - DRM_IOCTL_R128_STIPPLE, (unsigned long)stipple); 156 156 + return drm_ioctl(file, DRM_IOCTL_R128_STIPPLE, (unsigned long)stipple); 156 157 } 157 158 158 159 typedef struct drm_r128_getparam32 { ··· 175 178 &getparam->value)) 176 179 return -EFAULT; 177 180 178 178 - return drm_ioctl(file->f_path.dentry->d_inode, file, 179 179 - DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam); 181 181 + return drm_ioctl(file, DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam); 180 182 } 181 183 182 184 drm_ioctl_compat_t *r128_compat_ioctls[] = { ··· 206 210 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(r128_compat_ioctls)) 207 211 fn = r128_compat_ioctls[nr - DRM_COMMAND_BASE]; 208 212 209 209 - lock_kernel(); /* XXX for now */ 210 213 if (fn != NULL) 211 214 ret = (*fn) (filp, cmd, arg); 212 215 else 213 213 - ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 214 214 - unlock_kernel(); 216 216 + ret = drm_ioctl(filp, cmd, arg); 215 217 216 218 return ret; 217 219 }

+10 -2

drivers/gpu/drm/radeon/atom.c

reviewed

··· 58 58 } atom_exec_context; 59 59 60 60 int atom_debug = 0; 61 61 + static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); 61 62 void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 62 63 63 64 static uint32_t atom_arg_mask[8] = ··· 574 573 else 575 574 SDEBUG(" table: %d\n", idx); 576 575 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 577 577 - atom_execute_table(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 576 576 + atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 578 577 } 579 578 580 579 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) ··· 1041 1040 atom_op_shr, ATOM_ARG_MC}, { 1042 1041 atom_op_debug, 0},}; 1043 1042 1044 1044 - void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1043 1043 + static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) 1045 1044 { 1046 1045 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1047 1046 int len, ws, ps, ptr; ··· 1091 1090 1092 1091 if (ws) 1093 1092 kfree(ectx.ws); 1093 1093 + } 1094 1094 + 1095 1095 + void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1096 1096 + { 1097 1097 + mutex_lock(&ctx->mutex); 1098 1098 + atom_execute_table_locked(ctx, index, params); 1099 1099 + mutex_unlock(&ctx->mutex); 1094 1100 } 1095 1101 1096 1102 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };

+1

drivers/gpu/drm/radeon/atom.h

reviewed

··· 120 120 121 121 struct atom_context { 122 122 struct card_info *card; 123 123 + struct mutex mutex; 123 124 void *bios; 124 125 uint32_t cmd_table, data_table; 125 126 uint16_t *iio;

+199

drivers/gpu/drm/radeon/atombios.h

reviewed

··· 4690 4690 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 4691 4691 } ATOM_POWERPLAY_INFO_V3; 4692 4692 4693 4693 + /* New PPlib */ 4694 4694 + /**************************************************************************/ 4695 4695 + typedef struct _ATOM_PPLIB_THERMALCONTROLLER 4696 4696 + 4697 4697 + { 4698 4698 + UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 4699 4699 + UCHAR ucI2cLine; // as interpreted by DAL I2C 4700 4700 + UCHAR ucI2cAddress; 4701 4701 + UCHAR ucFanParameters; // Fan Control Parameters. 4702 4702 + UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 4703 4703 + UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 4704 4704 + UCHAR ucReserved; // ---- 4705 4705 + UCHAR ucFlags; // to be defined 4706 4706 + } ATOM_PPLIB_THERMALCONTROLLER; 4707 4707 + 4708 4708 + #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 4709 4709 + #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 4710 4710 + 4711 4711 + #define ATOM_PP_THERMALCONTROLLER_NONE 0 4712 4712 + #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 4713 4713 + #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 4714 4714 + #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 4715 4715 + #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 4716 4716 + #define ATOM_PP_THERMALCONTROLLER_LM64 5 4717 4717 + #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 4718 4718 + #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 4719 4719 + #define ATOM_PP_THERMALCONTROLLER_RV770 8 4720 4720 + #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 4721 4721 + 4722 4722 + typedef struct _ATOM_PPLIB_STATE 4723 4723 + { 4724 4724 + UCHAR ucNonClockStateIndex; 4725 4725 + UCHAR ucClockStateIndices[1]; // variable-sized 4726 4726 + } ATOM_PPLIB_STATE; 4727 4727 + 4728 4728 + //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 4729 4729 + #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 4730 4730 + #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 4731 4731 + #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 4732 4732 + #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 4733 4733 + #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 4734 4734 + #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 4735 4735 + #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 4736 4736 + #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 4737 4737 + #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 4738 4738 + #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 4739 4739 + #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 4740 4740 + #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 4741 4741 + 4742 4742 + typedef struct _ATOM_PPLIB_POWERPLAYTABLE 4743 4743 + { 4744 4744 + ATOM_COMMON_TABLE_HEADER sHeader; 4745 4745 + 4746 4746 + UCHAR ucDataRevision; 4747 4747 + 4748 4748 + UCHAR ucNumStates; 4749 4749 + UCHAR ucStateEntrySize; 4750 4750 + UCHAR ucClockInfoSize; 4751 4751 + UCHAR ucNonClockSize; 4752 4752 + 4753 4753 + // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 4754 4754 + USHORT usStateArrayOffset; 4755 4755 + 4756 4756 + // offset from start of this table to array of ASIC-specific structures, 4757 4757 + // currently ATOM_PPLIB_CLOCK_INFO. 4758 4758 + USHORT usClockInfoArrayOffset; 4759 4759 + 4760 4760 + // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 4761 4761 + USHORT usNonClockInfoArrayOffset; 4762 4762 + 4763 4763 + USHORT usBackbiasTime; // in microseconds 4764 4764 + USHORT usVoltageTime; // in microseconds 4765 4765 + USHORT usTableSize; //the size of this structure, or the extended structure 4766 4766 + 4767 4767 + ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 4768 4768 + 4769 4769 + ATOM_PPLIB_THERMALCONTROLLER sThermalController; 4770 4770 + 4771 4771 + USHORT usBootClockInfoOffset; 4772 4772 + USHORT usBootNonClockInfoOffset; 4773 4773 + 4774 4774 + } ATOM_PPLIB_POWERPLAYTABLE; 4775 4775 + 4776 4776 + //// ATOM_PPLIB_NONCLOCK_INFO::usClassification 4777 4777 + #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 4778 4778 + #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 4779 4779 + #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 4780 4780 + #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 4781 4781 + #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 4782 4782 + #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 4783 4783 + // 2, 4, 6, 7 are reserved 4784 4784 + 4785 4785 + #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 4786 4786 + #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 4787 4787 + #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 4788 4788 + #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 4789 4789 + #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 4790 4790 + #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 4791 4791 + #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 4792 4792 + #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 4793 4793 + #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 4794 4794 + #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 4795 4795 + // remaining 3 bits are reserved 4796 4796 + 4797 4797 + //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 4798 4798 + #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 4799 4799 + #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 4800 4800 + 4801 4801 + // 0 is 2.5Gb/s, 1 is 5Gb/s 4802 4802 + #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 4803 4803 + #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 4804 4804 + 4805 4805 + // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 4806 4806 + #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 4807 4807 + #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 4808 4808 + 4809 4809 + // lookup into reduced refresh-rate table 4810 4810 + #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 4811 4811 + #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 4812 4812 + 4813 4813 + #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 4814 4814 + #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 4815 4815 + // 2-15 TBD as needed. 4816 4816 + 4817 4817 + #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 4818 4818 + #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 4819 4819 + #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 4820 4820 + 4821 4821 + #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 4822 4822 + 4823 4823 + // Contained in an array starting at the offset 4824 4824 + // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 4825 4825 + // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 4826 4826 + typedef struct _ATOM_PPLIB_NONCLOCK_INFO 4827 4827 + { 4828 4828 + USHORT usClassification; 4829 4829 + UCHAR ucMinTemperature; 4830 4830 + UCHAR ucMaxTemperature; 4831 4831 + ULONG ulCapsAndSettings; 4832 4832 + UCHAR ucRequiredPower; 4833 4833 + UCHAR ucUnused1[3]; 4834 4834 + } ATOM_PPLIB_NONCLOCK_INFO; 4835 4835 + 4836 4836 + // Contained in an array starting at the offset 4837 4837 + // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 4838 4838 + // referenced from ATOM_PPLIB_STATE::ucClockStateIndices 4839 4839 + typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 4840 4840 + { 4841 4841 + USHORT usEngineClockLow; 4842 4842 + UCHAR ucEngineClockHigh; 4843 4843 + 4844 4844 + USHORT usMemoryClockLow; 4845 4845 + UCHAR ucMemoryClockHigh; 4846 4846 + 4847 4847 + USHORT usVDDC; 4848 4848 + USHORT usUnused1; 4849 4849 + USHORT usUnused2; 4850 4850 + 4851 4851 + ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 4852 4852 + 4853 4853 + } ATOM_PPLIB_R600_CLOCK_INFO; 4854 4854 + 4855 4855 + // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 4856 4856 + #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 4857 4857 + #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 4858 4858 + #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 4859 4859 + #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 4860 4860 + #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 4861 4861 + 4862 4862 + typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 4863 4863 + 4864 4864 + { 4865 4865 + USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 4866 4866 + UCHAR ucLowEngineClockHigh; 4867 4867 + USHORT usHighEngineClockLow; // High Engine clock in MHz. 4868 4868 + UCHAR ucHighEngineClockHigh; 4869 4869 + USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 4870 4870 + UCHAR ucMemoryClockHigh; // Currentyl unused. 4871 4871 + UCHAR ucPadding; // For proper alignment and size. 4872 4872 + USHORT usVDDC; // For the 780, use: None, Low, High, Variable 4873 4873 + UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 4874 4874 + UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. 4875 4875 + USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 4876 4876 + ULONG ulFlags; 4877 4877 + } ATOM_PPLIB_RS780_CLOCK_INFO; 4878 4878 + 4879 4879 + #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 4880 4880 + #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 4881 4881 + #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 4882 4882 + #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 4883 4883 + 4884 4884 + #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 4885 4885 + #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 4886 4886 + #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 4887 4887 + 4888 4888 + #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 4889 4889 + #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 4890 4890 + #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 4891 4891 + 4693 4892 /**************************************************************************/ 4694 4893 4695 4894 /* Following definitions are for compatiblity issue in different SW components. */

+4

drivers/gpu/drm/radeon/r100.c

reviewed

··· 2881 2881 2882 2882 for (i = 0; i < track->num_cb; i++) { 2883 2883 if (track->cb[i].robj == NULL) { 2884 2884 + if (!(track->fastfill || track->color_channel_mask || 2885 2885 + track->blend_read_enable)) { 2886 2886 + continue; 2887 2887 + } 2884 2888 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2885 2889 return -EINVAL; 2886 2890 }

+3 -1

drivers/gpu/drm/radeon/r100_track.h

reviewed

··· 67 67 unsigned immd_dwords; 68 68 unsigned num_arrays; 69 69 unsigned max_indx; 70 70 + unsigned color_channel_mask; 70 71 struct r100_cs_track_array arrays[11]; 71 72 struct r100_cs_track_cb cb[R300_MAX_CB]; 72 73 struct r100_cs_track_cb zb; 73 74 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 74 75 bool z_enabled; 75 76 bool separate_cube; 76 76 - 77 77 + bool fastfill; 78 78 + bool blend_read_enable; 77 79 }; 78 80 79 81 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);

+30

drivers/gpu/drm/radeon/r300.c

reviewed

··· 887 887 track->textures[i].cpp = 1; 888 888 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 889 889 break; 890 890 + case R300_TX_FORMAT_ATI2N: 891 891 + if (p->rdev->family < CHIP_R420) { 892 892 + DRM_ERROR("Invalid texture format %u\n", 893 893 + (idx_value & 0x1F)); 894 894 + return -EINVAL; 895 895 + } 896 896 + /* The same rules apply as for DXT3/5. */ 897 897 + /* Pass through. */ 890 898 case R300_TX_FORMAT_DXT3: 891 899 case R300_TX_FORMAT_DXT5: 892 900 track->textures[i].cpp = 1; ··· 959 951 track->textures[i].width_11 = tmp; 960 952 tmp = ((idx_value >> 16) & 1) << 11; 961 953 track->textures[i].height_11 = tmp; 954 954 + 955 955 + /* ATI1N */ 956 956 + if (idx_value & (1 << 14)) { 957 957 + /* The same rules apply as for DXT1. */ 958 958 + track->textures[i].compress_format = 959 959 + R100_TRACK_COMP_DXT1; 960 960 + } 961 961 + } else if (idx_value & (1 << 14)) { 962 962 + DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 963 963 + return -EINVAL; 962 964 } 963 965 break; 964 966 case 0x4480: ··· 1009 991 return r; 1010 992 } 1011 993 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 994 994 + break; 995 995 + case 0x4e0c: 996 996 + /* RB3D_COLOR_CHANNEL_MASK */ 997 997 + track->color_channel_mask = idx_value; 998 998 + break; 999 999 + case 0x4d1c: 1000 1000 + /* ZB_BW_CNTL */ 1001 1001 + track->fastfill = !!(idx_value & (1 << 2)); 1002 1002 + break; 1003 1003 + case 0x4e04: 1004 1004 + /* RB3D_BLENDCNTL */ 1005 1005 + track->blend_read_enable = !!(idx_value & (1 << 2)); 1012 1006 break; 1013 1007 case 0x4be8: 1014 1008 /* valid register only on RV530 */

+3 -3

drivers/gpu/drm/radeon/r300_cmdbuf.c

reviewed

··· 990 990 int sz; 991 991 int addr; 992 992 int type; 993 993 - int clamp; 993 993 + int isclamp; 994 994 int stride; 995 995 RING_LOCALS; 996 996 ··· 999 999 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo; 1000 1000 1001 1001 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); 1002 1002 - clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); 1002 1002 + isclamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); 1003 1003 1004 1004 addr |= (type << 16); 1005 1005 - addr |= (clamp << 17); 1005 1005 + addr |= (isclamp << 17); 1006 1006 1007 1007 stride = type ? 4 : 6; 1008 1008

+1

drivers/gpu/drm/radeon/r300_reg.h

reviewed

··· 900 900 # define R300_TX_FORMAT_FL_I32 0x1B 901 901 # define R300_TX_FORMAT_FL_I32A32 0x1C 902 902 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D 903 903 + # define R300_TX_FORMAT_ATI2N 0x1F 903 904 /* alpha modes, convenience mostly */ 904 905 /* if you have alpha, pick constant appropriate to the 905 906 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */

+2 -2

drivers/gpu/drm/radeon/r600_cs.c

reviewed

··· 170 170 idx, relocs_chunk->length_dw); 171 171 return -EINVAL; 172 172 } 173 173 - *cs_reloc = &p->relocs[0]; 173 173 + *cs_reloc = p->relocs; 174 174 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; 175 175 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 176 176 return 0; ··· 717 717 if (p->chunk_relocs_idx == -1) { 718 718 return 0; 719 719 } 720 720 - p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL); 720 720 + p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL); 721 721 if (p->relocs == NULL) { 722 722 return -ENOMEM; 723 723 }

+3 -1

drivers/gpu/drm/radeon/radeon.h

reviewed

··· 162 162 struct list_head created; 163 163 struct list_head emited; 164 164 struct list_head signaled; 165 165 + bool initialized; 165 166 }; 166 167 167 168 struct radeon_fence { ··· 203 202 struct radeon_mman { 204 203 struct ttm_bo_global_ref bo_global_ref; 205 204 struct ttm_global_reference mem_global_ref; 206 206 - bool mem_global_referenced; 207 205 struct ttm_bo_device bdev; 206 206 + bool mem_global_referenced; 207 207 + bool initialized; 208 208 }; 209 209 210 210 struct radeon_bo {

+4 -3

drivers/gpu/drm/radeon/radeon_asic.h

reviewed

··· 33 33 */ 34 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 36 + uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 36 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 37 38 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); ··· 107 106 .copy = &r100_copy_blit, 108 107 .get_engine_clock = &radeon_legacy_get_engine_clock, 109 108 .set_engine_clock = &radeon_legacy_set_engine_clock, 110 110 - .get_memory_clock = NULL, 109 109 + .get_memory_clock = &radeon_legacy_get_memory_clock, 111 110 .set_memory_clock = NULL, 112 111 .set_pcie_lanes = NULL, 113 112 .set_clock_gating = &radeon_legacy_set_clock_gating, ··· 167 166 .copy = &r100_copy_blit, 168 167 .get_engine_clock = &radeon_legacy_get_engine_clock, 169 168 .set_engine_clock = &radeon_legacy_set_engine_clock, 170 170 - .get_memory_clock = NULL, 169 169 + .get_memory_clock = &radeon_legacy_get_memory_clock, 171 170 .set_memory_clock = NULL, 172 171 .set_pcie_lanes = &rv370_set_pcie_lanes, 173 172 .set_clock_gating = &radeon_legacy_set_clock_gating, ··· 260 259 .copy = &r100_copy_blit, 261 260 .get_engine_clock = &radeon_legacy_get_engine_clock, 262 261 .set_engine_clock = &radeon_legacy_set_engine_clock, 263 263 - .get_memory_clock = NULL, 262 262 + .get_memory_clock = &radeon_legacy_get_memory_clock, 264 263 .set_memory_clock = NULL, 265 264 .set_pcie_lanes = NULL, 266 265 .set_clock_gating = &radeon_legacy_set_clock_gating,

+79 -26

drivers/gpu/drm/radeon/radeon_atombios.c

reviewed

··· 745 745 else 746 746 radeon_add_legacy_encoder(dev, 747 747 radeon_get_encoder_id(dev, 748 748 - (1 << 749 749 - i), 748 748 + (1 << i), 750 749 dac), 751 750 (1 << i)); 752 751 } ··· 757 758 if (bios_connectors[j].valid && (i != j)) { 758 759 if (bios_connectors[i].line_mux == 759 760 bios_connectors[j].line_mux) { 760 760 - if (((bios_connectors[i]. 761 761 - devices & 762 762 - (ATOM_DEVICE_DFP_SUPPORT)) 763 763 - && (bios_connectors[j]. 764 764 - devices & 765 765 - (ATOM_DEVICE_CRT_SUPPORT))) 766 766 - || 767 767 - ((bios_connectors[j]. 768 768 - devices & 769 769 - (ATOM_DEVICE_DFP_SUPPORT)) 770 770 - && (bios_connectors[i]. 771 771 - devices & 772 772 - (ATOM_DEVICE_CRT_SUPPORT)))) { 773 773 - bios_connectors[i]. 774 774 - devices |= 775 775 - bios_connectors[j]. 776 776 - devices; 777 777 - bios_connectors[i]. 778 778 - connector_type = 779 779 - DRM_MODE_CONNECTOR_DVII; 780 780 - if (bios_connectors[j].devices & 781 781 - (ATOM_DEVICE_DFP_SUPPORT)) 761 761 + /* make sure not to combine LVDS */ 762 762 + if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 763 763 + bios_connectors[i].line_mux = 53; 764 764 + bios_connectors[i].ddc_bus.valid = false; 765 765 + continue; 766 766 + } 767 767 + if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 768 768 + bios_connectors[j].line_mux = 53; 769 769 + bios_connectors[j].ddc_bus.valid = false; 770 770 + continue; 771 771 + } 772 772 + /* combine analog and digital for DVI-I */ 773 773 + if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 774 774 + (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 775 775 + ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 776 776 + (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 777 777 + bios_connectors[i].devices |= 778 778 + bios_connectors[j].devices; 779 779 + bios_connectors[i].connector_type = 780 780 + DRM_MODE_CONNECTOR_DVII; 781 781 + if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 782 782 bios_connectors[i].hpd = 783 783 bios_connectors[j].hpd; 784 784 - bios_connectors[j]. 785 785 - valid = false; 784 784 + bios_connectors[j].valid = false; 786 785 } 787 786 } 788 787 } ··· 1231 1234 return true; 1232 1235 } 1233 1236 1237 1237 + enum radeon_tv_std 1238 1238 + radeon_atombios_get_tv_info(struct radeon_device *rdev) 1239 1239 + { 1240 1240 + struct radeon_mode_info *mode_info = &rdev->mode_info; 1241 1241 + int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1242 1242 + uint16_t data_offset; 1243 1243 + uint8_t frev, crev; 1244 1244 + struct _ATOM_ANALOG_TV_INFO *tv_info; 1245 1245 + enum radeon_tv_std tv_std = TV_STD_NTSC; 1246 1246 + 1247 1247 + atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); 1248 1248 + 1249 1249 + tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1250 1250 + 1251 1251 + switch (tv_info->ucTV_BootUpDefaultStandard) { 1252 1252 + case ATOM_TV_NTSC: 1253 1253 + tv_std = TV_STD_NTSC; 1254 1254 + DRM_INFO("Default TV standard: NTSC\n"); 1255 1255 + break; 1256 1256 + case ATOM_TV_NTSCJ: 1257 1257 + tv_std = TV_STD_NTSC_J; 1258 1258 + DRM_INFO("Default TV standard: NTSC-J\n"); 1259 1259 + break; 1260 1260 + case ATOM_TV_PAL: 1261 1261 + tv_std = TV_STD_PAL; 1262 1262 + DRM_INFO("Default TV standard: PAL\n"); 1263 1263 + break; 1264 1264 + case ATOM_TV_PALM: 1265 1265 + tv_std = TV_STD_PAL_M; 1266 1266 + DRM_INFO("Default TV standard: PAL-M\n"); 1267 1267 + break; 1268 1268 + case ATOM_TV_PALN: 1269 1269 + tv_std = TV_STD_PAL_N; 1270 1270 + DRM_INFO("Default TV standard: PAL-N\n"); 1271 1271 + break; 1272 1272 + case ATOM_TV_PALCN: 1273 1273 + tv_std = TV_STD_PAL_CN; 1274 1274 + DRM_INFO("Default TV standard: PAL-CN\n"); 1275 1275 + break; 1276 1276 + case ATOM_TV_PAL60: 1277 1277 + tv_std = TV_STD_PAL_60; 1278 1278 + DRM_INFO("Default TV standard: PAL-60\n"); 1279 1279 + break; 1280 1280 + case ATOM_TV_SECAM: 1281 1281 + tv_std = TV_STD_SECAM; 1282 1282 + DRM_INFO("Default TV standard: SECAM\n"); 1283 1283 + break; 1284 1284 + default: 1285 1285 + tv_std = TV_STD_NTSC; 1286 1286 + DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); 1287 1287 + break; 1288 1288 + } 1289 1289 + return tv_std; 1290 1290 + } 1291 1291 + 1234 1292 struct radeon_encoder_tv_dac * 1235 1293 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1236 1294 { ··· 1321 1269 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1322 1270 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1323 1271 1272 1272 + tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1324 1273 } 1325 1274 return tv_dac; 1326 1275 }

+1 -1

drivers/gpu/drm/radeon/radeon_clocks.c

reviewed

··· 62 62 } 63 63 64 64 /* 10 khz */ 65 65 - static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) 65 65 + uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) 66 66 { 67 67 struct radeon_pll *mpll = &rdev->clock.mpll; 68 68 uint32_t fb_div, ref_div, post_div, mclk;

+4 -5

drivers/gpu/drm/radeon/radeon_combios.c

reviewed

··· 634 634 return p_dac; 635 635 } 636 636 637 637 - static enum radeon_tv_std 638 638 - radeon_combios_get_tv_info(struct radeon_encoder *encoder) 637 637 + enum radeon_tv_std 638 638 + radeon_combios_get_tv_info(struct radeon_device *rdev) 639 639 { 640 640 - struct drm_device *dev = encoder->base.dev; 641 641 - struct radeon_device *rdev = dev->dev_private; 640 640 + struct drm_device *dev = rdev->ddev; 642 641 uint16_t tv_info; 643 642 enum radeon_tv_std tv_std = TV_STD_NTSC; 644 643 ··· 778 779 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 779 780 found = 1; 780 781 } 781 781 - tv_dac->tv_std = radeon_combios_get_tv_info(encoder); 782 782 + tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 782 783 } 783 784 if (!found) { 784 785 /* then check CRT table */

+14 -2

drivers/gpu/drm/radeon/radeon_connectors.c

reviewed

··· 208 208 drm_mode_set_name(mode); 209 209 210 210 DRM_DEBUG("Adding native panel mode %s\n", mode->name); 211 211 + } else if (native_mode->hdisplay != 0 && 212 212 + native_mode->vdisplay != 0) { 213 213 + /* mac laptops without an edid */ 214 214 + /* Note that this is not necessarily the exact panel mode, 215 215 + * but an approximation based on the cvt formula. For these 216 216 + * systems we should ideally read the mode info out of the 217 217 + * registers or add a mode table, but this works and is much 218 218 + * simpler. 219 219 + */ 220 220 + mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 221 221 + mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 222 222 + DRM_DEBUG("Adding cvt approximation of native panel mode %s\n", mode->name); 211 223 } 212 224 return mode; 213 225 } ··· 1183 1171 1); 1184 1172 drm_connector_attach_property(&radeon_connector->base, 1185 1173 rdev->mode_info.tv_std_property, 1186 1186 - 1); 1174 1174 + radeon_atombios_get_tv_info(rdev)); 1187 1175 } 1188 1176 break; 1189 1177 case DRM_MODE_CONNECTOR_LVDS: ··· 1327 1315 1); 1328 1316 drm_connector_attach_property(&radeon_connector->base, 1329 1317 rdev->mode_info.tv_std_property, 1330 1330 - 1); 1318 1318 + radeon_combios_get_tv_info(rdev)); 1331 1319 } 1332 1320 break; 1333 1321 case DRM_MODE_CONNECTOR_LVDS:

+75 -5

drivers/gpu/drm/radeon/radeon_device.c

reviewed

··· 391 391 /* FIXME: not supported yet */ 392 392 return -EINVAL; 393 393 } 394 394 + 395 395 + if (rdev->flags & RADEON_IS_IGP) { 396 396 + rdev->asic->get_memory_clock = NULL; 397 397 + rdev->asic->set_memory_clock = NULL; 398 398 + } 399 399 + 394 400 return 0; 395 401 } 396 402 ··· 487 481 atom_card_info->pll_write = cail_pll_write; 488 482 489 483 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 484 484 + mutex_init(&rdev->mode_info.atom_context->mutex); 490 485 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 491 486 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 492 487 return 0; ··· 546 539 } 547 540 } 548 541 549 549 - /* 550 550 - * Radeon device. 551 551 - */ 542 542 + void radeon_check_arguments(struct radeon_device *rdev) 543 543 + { 544 544 + /* vramlimit must be a power of two */ 545 545 + switch (radeon_vram_limit) { 546 546 + case 0: 547 547 + case 4: 548 548 + case 8: 549 549 + case 16: 550 550 + case 32: 551 551 + case 64: 552 552 + case 128: 553 553 + case 256: 554 554 + case 512: 555 555 + case 1024: 556 556 + case 2048: 557 557 + case 4096: 558 558 + break; 559 559 + default: 560 560 + dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 561 561 + radeon_vram_limit); 562 562 + radeon_vram_limit = 0; 563 563 + break; 564 564 + } 565 565 + radeon_vram_limit = radeon_vram_limit << 20; 566 566 + /* gtt size must be power of two and greater or equal to 32M */ 567 567 + switch (radeon_gart_size) { 568 568 + case 4: 569 569 + case 8: 570 570 + case 16: 571 571 + dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 572 572 + radeon_gart_size); 573 573 + radeon_gart_size = 512; 574 574 + break; 575 575 + case 32: 576 576 + case 64: 577 577 + case 128: 578 578 + case 256: 579 579 + case 512: 580 580 + case 1024: 581 581 + case 2048: 582 582 + case 4096: 583 583 + break; 584 584 + default: 585 585 + dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 586 586 + radeon_gart_size); 587 587 + radeon_gart_size = 512; 588 588 + break; 589 589 + } 590 590 + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 591 591 + /* AGP mode can only be -1, 1, 2, 4, 8 */ 592 592 + switch (radeon_agpmode) { 593 593 + case -1: 594 594 + case 0: 595 595 + case 1: 596 596 + case 2: 597 597 + case 4: 598 598 + case 8: 599 599 + break; 600 600 + default: 601 601 + dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 602 602 + "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 603 603 + radeon_agpmode = 0; 604 604 + break; 605 605 + } 606 606 + } 607 607 + 552 608 int radeon_device_init(struct radeon_device *rdev, 553 609 struct drm_device *ddev, 554 610 struct pci_dev *pdev, ··· 650 580 651 581 /* Set asic functions */ 652 582 r = radeon_asic_init(rdev); 653 653 - if (r) { 583 583 + if (r) 654 584 return r; 655 655 - } 585 585 + radeon_check_arguments(rdev); 656 586 657 587 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 658 588 radeon_agp_disable(rdev);

+1 -1

drivers/gpu/drm/radeon/radeon_display.c

reviewed

··· 739 739 { TV_STD_SECAM, "secam" }, 740 740 }; 741 741 742 742 - int radeon_modeset_create_props(struct radeon_device *rdev) 742 742 + static int radeon_modeset_create_props(struct radeon_device *rdev) 743 743 { 744 744 int i, sz; 745 745

+2 -2

drivers/gpu/drm/radeon/radeon_drv.c

reviewed

··· 196 196 .owner = THIS_MODULE, 197 197 .open = drm_open, 198 198 .release = drm_release, 199 199 - .ioctl = drm_ioctl, 199 199 + .unlocked_ioctl = drm_ioctl, 200 200 .mmap = drm_mmap, 201 201 .poll = drm_poll, 202 202 .fasync = drm_fasync, ··· 284 284 .owner = THIS_MODULE, 285 285 .open = drm_open, 286 286 .release = drm_release, 287 287 - .ioctl = drm_ioctl, 287 287 + .unlocked_ioctl = drm_ioctl, 288 288 .mmap = radeon_mmap, 289 289 .poll = drm_poll, 290 290 .fasync = drm_fasync,

+10 -8

drivers/gpu/drm/radeon/radeon_encoders.c

reviewed

··· 233 233 if (!ASIC_IS_AVIVO(rdev)) { 234 234 adjusted_mode->hdisplay = mode->hdisplay; 235 235 adjusted_mode->vdisplay = mode->vdisplay; 236 236 + adjusted_mode->crtc_hdisplay = mode->hdisplay; 237 237 + adjusted_mode->crtc_vdisplay = mode->vdisplay; 236 238 } 237 239 adjusted_mode->base.id = mode_id; 238 240 } ··· 497 495 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 498 496 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 499 497 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 500 500 - if (dig->lvds_misc & (1 << 0)) 498 498 + if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) 501 499 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 502 502 - if (dig->lvds_misc & (1 << 1)) 500 500 + if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 503 501 args.v1.ucMisc |= (1 << 1); 504 502 } else { 505 503 if (dig_connector->linkb) ··· 526 524 args.v2.ucTemporal = 0; 527 525 args.v2.ucFRC = 0; 528 526 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 529 529 - if (dig->lvds_misc & (1 << 0)) 527 527 + if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) 530 528 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 531 531 - if (dig->lvds_misc & (1 << 5)) { 529 529 + if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) { 532 530 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 533 533 - if (dig->lvds_misc & (1 << 1)) 531 531 + if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 534 532 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 535 533 } 536 536 - if (dig->lvds_misc & (1 << 6)) { 534 534 + if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) { 537 535 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 538 538 - if (dig->lvds_misc & (1 << 1)) 536 536 + if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 539 537 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 540 540 - if (((dig->lvds_misc >> 2) & 0x3) == 2) 538 538 + if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 541 539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 542 540 } 543 541 } else {

+6 -3

drivers/gpu/drm/radeon/radeon_fence.c

reviewed

··· 324 324 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); 325 325 r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); 326 326 if (r) { 327 327 - DRM_ERROR("Fence failed to get a scratch register."); 327 327 + dev_err(rdev->dev, "fence failed to get scratch register\n"); 328 328 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 329 329 return r; 330 330 } ··· 335 335 INIT_LIST_HEAD(&rdev->fence_drv.signaled); 336 336 rdev->fence_drv.count_timeout = 0; 337 337 init_waitqueue_head(&rdev->fence_drv.queue); 338 338 + rdev->fence_drv.initialized = true; 338 339 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 339 340 if (radeon_debugfs_fence_init(rdev)) { 340 340 - DRM_ERROR("Failed to register debugfs file for fence !\n"); 341 341 + dev_err(rdev->dev, "fence debugfs file creation failed\n"); 341 342 } 342 343 return 0; 343 344 } ··· 347 346 { 348 347 unsigned long irq_flags; 349 348 349 349 + if (!rdev->fence_drv.initialized) 350 350 + return; 350 351 wake_up_all(&rdev->fence_drv.queue); 351 352 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); 352 353 radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); 353 354 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 354 354 - DRM_INFO("radeon: fence finalized\n"); 355 355 + rdev->fence_drv.initialized = false; 355 356 } 356 357 357 358

+12 -26

drivers/gpu/drm/radeon/radeon_ioc32.c

reviewed

··· 92 92 &init->gart_textures_offset)) 93 93 return -EFAULT; 94 94 95 95 - return drm_ioctl(file->f_path.dentry->d_inode, file, 96 96 - DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init); 95 95 + return drm_ioctl(file, DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init); 97 96 } 98 97 99 98 typedef struct drm_radeon_clear32 { ··· 124 125 &clr->depth_boxes)) 125 126 return -EFAULT; 126 127 127 127 - return drm_ioctl(file->f_path.dentry->d_inode, file, 128 128 - DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr); 128 128 + return drm_ioctl(file, DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr); 129 129 } 130 130 131 131 typedef struct drm_radeon_stipple32 { ··· 147 149 &request->mask)) 148 150 return -EFAULT; 149 151 150 150 - return drm_ioctl(file->f_path.dentry->d_inode, file, 151 151 - DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request); 152 152 + return drm_ioctl(file, DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request); 152 153 } 153 154 154 155 typedef struct drm_radeon_tex_image32 { ··· 201 204 &image->data)) 202 205 return -EFAULT; 203 206 204 204 - return drm_ioctl(file->f_path.dentry->d_inode, file, 205 205 - DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request); 207 207 + return drm_ioctl(file, DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request); 206 208 } 207 209 208 210 typedef struct drm_radeon_vertex2_32 { ··· 234 238 &request->prim)) 235 239 return -EFAULT; 236 240 237 237 - return drm_ioctl(file->f_path.dentry->d_inode, file, 238 238 - DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request); 241 241 + return drm_ioctl(file, DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request); 239 242 } 240 243 241 244 typedef struct drm_radeon_cmd_buffer32 { ··· 263 268 &request->boxes)) 264 269 return -EFAULT; 265 270 266 266 - return drm_ioctl(file->f_path.dentry->d_inode, file, 267 267 - DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request); 271 271 + return drm_ioctl(file, DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request); 268 272 } 269 273 270 274 typedef struct drm_radeon_getparam32 { ··· 287 293 &request->value)) 288 294 return -EFAULT; 289 295 290 290 - return drm_ioctl(file->f_path.dentry->d_inode, file, 291 291 - DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request); 296 296 + return drm_ioctl(file, DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request); 292 297 } 293 298 294 299 typedef struct drm_radeon_mem_alloc32 { ··· 315 322 &request->region_offset)) 316 323 return -EFAULT; 317 324 318 318 - return drm_ioctl(file->f_path.dentry->d_inode, file, 319 319 - DRM_IOCTL_RADEON_ALLOC, (unsigned long)request); 325 325 + return drm_ioctl(file, DRM_IOCTL_RADEON_ALLOC, (unsigned long)request); 320 326 } 321 327 322 328 typedef struct drm_radeon_irq_emit32 { ··· 337 345 &request->irq_seq)) 338 346 return -EFAULT; 339 347 340 340 - return drm_ioctl(file->f_path.dentry->d_inode, file, 341 341 - DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request); 348 348 + return drm_ioctl(file, DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request); 342 349 } 343 350 344 351 /* The two 64-bit arches where alignof(u64)==4 in 32-bit code */ ··· 363 372 &request->value)) 364 373 return -EFAULT; 365 374 366 366 - return drm_ioctl(file->f_dentry->d_inode, file, 367 367 - DRM_IOCTL_RADEON_SETPARAM, (unsigned long) request); 375 375 + return drm_ioctl(file, DRM_IOCTL_RADEON_SETPARAM, (unsigned long) request); 368 376 } 369 377 #else 370 378 #define compat_radeon_cp_setparam NULL ··· 403 413 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(radeon_compat_ioctls)) 404 414 fn = radeon_compat_ioctls[nr - DRM_COMMAND_BASE]; 405 415 406 406 - lock_kernel(); /* XXX for now */ 407 416 if (fn != NULL) 408 417 ret = (*fn) (filp, cmd, arg); 409 418 else 410 410 - ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 411 411 - unlock_kernel(); 419 419 + ret = drm_ioctl(filp, cmd, arg); 412 420 413 421 return ret; 414 422 } ··· 419 431 if (nr < DRM_COMMAND_BASE) 420 432 return drm_compat_ioctl(filp, cmd, arg); 421 433 422 422 - lock_kernel(); /* XXX for now */ 423 423 - ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 424 424 - unlock_kernel(); 434 434 + ret = drm_ioctl(filp, cmd, arg); 425 435 426 436 return ret; 427 437 }

+2 -3

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

reviewed

··· 43 43 } 44 44 45 45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 46 46 - struct drm_display_mode *mode, 47 47 - struct drm_display_mode *adjusted_mode) 46 46 + struct drm_display_mode *mode) 48 47 { 49 48 struct drm_device *dev = crtc->dev; 50 49 struct radeon_device *rdev = dev->dev_private; ··· 1058 1059 radeon_set_pll(crtc, adjusted_mode); 1059 1060 radeon_overscan_setup(crtc, adjusted_mode); 1060 1061 if (radeon_crtc->crtc_id == 0) { 1061 1061 - radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); 1062 1062 + radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1062 1063 } else { 1063 1064 if (radeon_crtc->rmx_type != RMX_OFF) { 1064 1065 /* FIXME: only first crtc has rmx what should we

+2

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

reviewed

··· 207 207 *adjusted_mode = *native_mode; 208 208 adjusted_mode->hdisplay = mode->hdisplay; 209 209 adjusted_mode->vdisplay = mode->vdisplay; 210 210 + adjusted_mode->crtc_hdisplay = mode->hdisplay; 211 211 + adjusted_mode->crtc_vdisplay = mode->vdisplay; 210 212 adjusted_mode->base.id = mode_id; 211 213 } 212 214

+6

drivers/gpu/drm/radeon/radeon_mode.h

reviewed

··· 88 88 TV_STD_SCART_PAL, 89 89 TV_STD_SECAM, 90 90 TV_STD_PAL_CN, 91 91 + TV_STD_PAL_N, 91 92 }; 92 93 93 94 /* radeon gpio-based i2c ··· 395 394 struct drm_framebuffer base; 396 395 struct drm_gem_object *obj; 397 396 }; 397 397 + 398 398 + extern enum radeon_tv_std 399 399 + radeon_combios_get_tv_info(struct radeon_device *rdev); 400 400 + extern enum radeon_tv_std 401 401 + radeon_atombios_get_tv_info(struct radeon_device *rdev); 398 402 399 403 extern void radeon_connector_hotplug(struct drm_connector *connector); 400 404 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);

+2 -2

drivers/gpu/drm/radeon/radeon_test.c

reviewed

··· 42 42 /* Number of tests = 43 43 * (Total GTT - IB pool - writeback page - ring buffer) / test size 44 44 */ 45 45 - n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE - 46 46 - rdev->cp.ring_size) / size; 45 45 + n = ((u32)(rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE - 46 46 + rdev->cp.ring_size)) / size; 47 47 48 48 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); 49 49 if (!gtt_obj) {

+4

drivers/gpu/drm/radeon/radeon_ttm.c

reviewed

··· 494 494 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 495 495 return r; 496 496 } 497 497 + rdev->mman.initialized = true; 497 498 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 498 499 rdev->mc.real_vram_size >> PAGE_SHIFT); 499 500 if (r) { ··· 542 541 { 543 542 int r; 544 543 544 544 + if (!rdev->mman.initialized) 545 545 + return; 545 546 if (rdev->stollen_vga_memory) { 546 547 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 547 548 if (r == 0) { ··· 557 554 ttm_bo_device_release(&rdev->mman.bdev); 558 555 radeon_gart_fini(rdev); 559 556 radeon_ttm_global_fini(rdev); 557 557 + rdev->mman.initialized = false; 560 558 DRM_INFO("radeon: ttm finalized\n"); 561 559 } 562 560

+1 -1

drivers/gpu/drm/savage/savage_drv.c

reviewed

··· 50 50 .owner = THIS_MODULE, 51 51 .open = drm_open, 52 52 .release = drm_release, 53 53 - .ioctl = drm_ioctl, 53 53 + .unlocked_ioctl = drm_ioctl, 54 54 .mmap = drm_mmap, 55 55 .poll = drm_poll, 56 56 .fasync = drm_fasync,

+1 -1

drivers/gpu/drm/sis/sis_drv.c

reviewed

··· 80 80 .owner = THIS_MODULE, 81 81 .open = drm_open, 82 82 .release = drm_release, 83 83 - .ioctl = drm_ioctl, 83 83 + .unlocked_ioctl = drm_ioctl, 84 84 .mmap = drm_mmap, 85 85 .poll = drm_poll, 86 86 .fasync = drm_fasync,

+1 -1

drivers/gpu/drm/tdfx/tdfx_drv.c

reviewed

··· 48 48 .owner = THIS_MODULE, 49 49 .open = drm_open, 50 50 .release = drm_release, 51 51 - .ioctl = drm_ioctl, 51 51 + .unlocked_ioctl = drm_ioctl, 52 52 .mmap = drm_mmap, 53 53 .poll = drm_poll, 54 54 .fasync = drm_fasync,

+1 -1

drivers/gpu/drm/via/via_drv.c

reviewed

··· 58 58 .owner = THIS_MODULE, 59 59 .open = drm_open, 60 60 .release = drm_release, 61 61 - .ioctl = drm_ioctl, 61 61 + .unlocked_ioctl = drm_ioctl, 62 62 .mmap = drm_mmap, 63 63 .poll = drm_poll, 64 64 .fasync = drm_fasync,

+19 -28

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

reviewed

··· 103 103 */ 104 104 105 105 static struct drm_ioctl_desc vmw_ioctls[] = { 106 106 - VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl, 0), 106 106 + VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl, 107 107 + DRM_AUTH | DRM_UNLOCKED), 107 108 VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 108 108 - 0), 109 109 + DRM_AUTH | DRM_UNLOCKED), 109 110 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 110 110 - 0), 111 111 + DRM_AUTH | DRM_UNLOCKED), 111 112 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS, 112 112 - vmw_kms_cursor_bypass_ioctl, 0), 113 113 + vmw_kms_cursor_bypass_ioctl, 114 114 + DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 113 115 114 116 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl, 115 115 - 0), 117 117 + DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 116 118 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 117 117 - 0), 119 119 + DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 118 120 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 119 119 - 0), 121 121 + DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 120 122 121 123 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 122 122 - 0), 124 124 + DRM_AUTH | DRM_UNLOCKED), 123 125 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 124 124 - 0), 126 126 + DRM_AUTH | DRM_UNLOCKED), 125 127 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 126 126 - 0), 128 128 + DRM_AUTH | DRM_UNLOCKED), 127 129 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 128 128 - 0), 130 130 + DRM_AUTH | DRM_UNLOCKED), 129 131 VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl, 130 130 - 0), 132 132 + DRM_AUTH | DRM_UNLOCKED), 131 133 VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl, 132 132 - 0), 134 134 + DRM_AUTH | DRM_UNLOCKED), 133 135 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl, 134 134 - 0), 136 136 + DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED), 135 137 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl, 136 136 - 0) 138 138 + DRM_AUTH | DRM_UNLOCKED) 137 139 }; 138 140 139 141 static struct pci_device_id vmw_pci_id_list[] = { ··· 462 460 struct drm_file *file_priv = filp->private_data; 463 461 struct drm_device *dev = file_priv->minor->dev; 464 462 unsigned int nr = DRM_IOCTL_NR(cmd); 465 465 - long ret; 466 463 467 464 /* 468 468 - * The driver private ioctls and TTM ioctls should be 469 469 - * thread-safe. 465 465 + * Do extra checking on driver private ioctls. 470 466 */ 471 467 472 468 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) ··· 477 477 nr - DRM_COMMAND_BASE); 478 478 return -EINVAL; 479 479 } 480 480 - return drm_ioctl(filp->f_path.dentry->d_inode, 481 481 - filp, cmd, arg); 482 480 } 483 481 484 484 - /* 485 485 - * Not all old drm ioctls are thread-safe. 486 486 - */ 487 487 - 488 488 - lock_kernel(); 489 489 - ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 490 490 - unlock_kernel(); 491 491 - return ret; 482 482 + return drm_ioctl(filp, cmd, arg); 492 483 } 493 484 494 485 static int vmw_firstopen(struct drm_device *dev)

+6 -4

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

reviewed

··· 123 123 uint32_t last_cid; 124 124 bool cid_valid; 125 125 uint32_t last_sid; 126 126 + uint32_t sid_translation; 126 127 bool sid_valid; 127 128 struct ttm_object_file *tfile; 128 129 struct list_head validate_nodes; ··· 318 317 extern int vmw_surface_init(struct vmw_private *dev_priv, 319 318 struct vmw_surface *srf, 320 319 void (*res_free) (struct vmw_resource *res)); 321 321 - extern int vmw_user_surface_lookup(struct vmw_private *dev_priv, 322 322 - struct ttm_object_file *tfile, 323 323 - int sid, struct vmw_surface **out); 320 320 + extern int vmw_user_surface_lookup_handle(struct vmw_private *dev_priv, 321 321 + struct ttm_object_file *tfile, 322 322 + uint32_t handle, 323 323 + struct vmw_surface **out); 324 324 extern int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data, 325 325 struct drm_file *file_priv); 326 326 extern int vmw_surface_define_ioctl(struct drm_device *dev, void *data, ··· 330 328 struct drm_file *file_priv); 331 329 extern int vmw_surface_check(struct vmw_private *dev_priv, 332 330 struct ttm_object_file *tfile, 333 333 - int id); 331 331 + uint32_t handle, int *id); 334 332 extern void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo); 335 333 extern int vmw_dmabuf_init(struct vmw_private *dev_priv, 336 334 struct vmw_dma_buffer *vmw_bo,

+131 -26

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

reviewed

··· 73 73 74 74 static int vmw_cmd_sid_check(struct vmw_private *dev_priv, 75 75 struct vmw_sw_context *sw_context, 76 76 - uint32_t sid) 76 76 + uint32_t *sid) 77 77 { 78 78 - if (unlikely((!sw_context->sid_valid || sid != sw_context->last_sid) && 79 79 - sid != SVGA3D_INVALID_ID)) { 80 80 - int ret = vmw_surface_check(dev_priv, sw_context->tfile, sid); 78 78 + if (*sid == SVGA3D_INVALID_ID) 79 79 + return 0; 80 80 + 81 81 + if (unlikely((!sw_context->sid_valid || 82 82 + *sid != sw_context->last_sid))) { 83 83 + int real_id; 84 84 + int ret = vmw_surface_check(dev_priv, sw_context->tfile, 85 85 + *sid, &real_id); 81 86 82 87 if (unlikely(ret != 0)) { 83 83 - DRM_ERROR("Could ot find or use surface %u\n", 84 84 - (unsigned) sid); 88 88 + DRM_ERROR("Could ot find or use surface 0x%08x " 89 89 + "address 0x%08lx\n", 90 90 + (unsigned int) *sid, 91 91 + (unsigned long) sid); 85 92 return ret; 86 93 } 87 94 88 88 - sw_context->last_sid = sid; 95 95 + sw_context->last_sid = *sid; 89 96 sw_context->sid_valid = true; 90 90 - } 97 97 + *sid = real_id; 98 98 + sw_context->sid_translation = real_id; 99 99 + } else 100 100 + *sid = sw_context->sid_translation; 101 101 + 91 102 return 0; 92 103 } 93 104 ··· 118 107 return ret; 119 108 120 109 cmd = container_of(header, struct vmw_sid_cmd, header); 121 121 - return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.target.sid); 110 110 + ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.target.sid); 111 111 + return ret; 122 112 } 123 113 124 114 static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv, ··· 133 121 int ret; 134 122 135 123 cmd = container_of(header, struct vmw_sid_cmd, header); 136 136 - ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.src.sid); 124 124 + ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid); 137 125 if (unlikely(ret != 0)) 138 126 return ret; 139 139 - return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.dest.sid); 127 127 + return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid); 140 128 } 141 129 142 130 static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv, ··· 150 138 int ret; 151 139 152 140 cmd = container_of(header, struct vmw_sid_cmd, header); 153 153 - ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.src.sid); 141 141 + ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid); 154 142 if (unlikely(ret != 0)) 155 143 return ret; 156 156 - return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.dest.sid); 144 144 + return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid); 157 145 } 158 146 159 147 static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv, ··· 166 154 } *cmd; 167 155 168 156 cmd = container_of(header, struct vmw_sid_cmd, header); 169 169 - return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.srcImage.sid); 157 157 + return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.srcImage.sid); 170 158 } 171 159 172 160 static int vmw_cmd_present_check(struct vmw_private *dev_priv, ··· 179 167 } *cmd; 180 168 181 169 cmd = container_of(header, struct vmw_sid_cmd, header); 182 182 - return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.sid); 170 170 + return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.sid); 183 171 } 184 172 185 173 static int vmw_cmd_dma(struct vmw_private *dev_priv, ··· 199 187 uint32_t cur_validate_node; 200 188 struct ttm_validate_buffer *val_buf; 201 189 202 202 - 203 190 cmd = container_of(header, struct vmw_dma_cmd, header); 204 204 - ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->dma.host.sid); 205 205 - if (unlikely(ret != 0)) 206 206 - return ret; 207 207 - 208 191 handle = cmd->dma.guest.ptr.gmrId; 209 192 ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo); 210 193 if (unlikely(ret != 0)) { ··· 235 228 ++sw_context->cur_val_buf; 236 229 } 237 230 238 238 - ret = vmw_user_surface_lookup(dev_priv, sw_context->tfile, 239 239 - cmd->dma.host.sid, &srf); 231 231 + ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile, 232 232 + cmd->dma.host.sid, &srf); 240 233 if (ret) { 241 234 DRM_ERROR("could not find surface\n"); 242 235 goto out_no_reloc; 243 236 } 244 237 238 238 + /** 239 239 + * Patch command stream with device SID. 240 240 + */ 241 241 + 242 242 + cmd->dma.host.sid = srf->res.id; 245 243 vmw_kms_cursor_snoop(srf, sw_context->tfile, bo, header); 244 244 + /** 245 245 + * FIXME: May deadlock here when called from the 246 246 + * command parsing code. 247 247 + */ 246 248 vmw_surface_unreference(&srf); 247 249 248 250 out_no_reloc: 249 251 vmw_dmabuf_unreference(&vmw_bo); 250 252 return ret; 253 253 + } 254 254 + 255 255 + static int vmw_cmd_draw(struct vmw_private *dev_priv, 256 256 + struct vmw_sw_context *sw_context, 257 257 + SVGA3dCmdHeader *header) 258 258 + { 259 259 + struct vmw_draw_cmd { 260 260 + SVGA3dCmdHeader header; 261 261 + SVGA3dCmdDrawPrimitives body; 262 262 + } *cmd; 263 263 + SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)( 264 264 + (unsigned long)header + sizeof(*cmd)); 265 265 + SVGA3dPrimitiveRange *range; 266 266 + uint32_t i; 267 267 + uint32_t maxnum; 268 268 + int ret; 269 269 + 270 270 + ret = vmw_cmd_cid_check(dev_priv, sw_context, header); 271 271 + if (unlikely(ret != 0)) 272 272 + return ret; 273 273 + 274 274 + cmd = container_of(header, struct vmw_draw_cmd, header); 275 275 + maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl); 276 276 + 277 277 + if (unlikely(cmd->body.numVertexDecls > maxnum)) { 278 278 + DRM_ERROR("Illegal number of vertex declarations.\n"); 279 279 + return -EINVAL; 280 280 + } 281 281 + 282 282 + for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) { 283 283 + ret = vmw_cmd_sid_check(dev_priv, sw_context, 284 284 + &decl->array.surfaceId); 285 285 + if (unlikely(ret != 0)) 286 286 + return ret; 287 287 + } 288 288 + 289 289 + maxnum = (header->size - sizeof(cmd->body) - 290 290 + cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range); 291 291 + if (unlikely(cmd->body.numRanges > maxnum)) { 292 292 + DRM_ERROR("Illegal number of index ranges.\n"); 293 293 + return -EINVAL; 294 294 + } 295 295 + 296 296 + range = (SVGA3dPrimitiveRange *) decl; 297 297 + for (i = 0; i < cmd->body.numRanges; ++i, ++range) { 298 298 + ret = vmw_cmd_sid_check(dev_priv, sw_context, 299 299 + &range->indexArray.surfaceId); 300 300 + if (unlikely(ret != 0)) 301 301 + return ret; 302 302 + } 303 303 + return 0; 304 304 + } 305 305 + 306 306 + 307 307 + static int vmw_cmd_tex_state(struct vmw_private *dev_priv, 308 308 + struct vmw_sw_context *sw_context, 309 309 + SVGA3dCmdHeader *header) 310 310 + { 311 311 + struct vmw_tex_state_cmd { 312 312 + SVGA3dCmdHeader header; 313 313 + SVGA3dCmdSetTextureState state; 314 314 + }; 315 315 + 316 316 + SVGA3dTextureState *last_state = (SVGA3dTextureState *) 317 317 + ((unsigned long) header + header->size + sizeof(header)); 318 318 + SVGA3dTextureState *cur_state = (SVGA3dTextureState *) 319 319 + ((unsigned long) header + sizeof(struct vmw_tex_state_cmd)); 320 320 + int ret; 321 321 + 322 322 + ret = vmw_cmd_cid_check(dev_priv, sw_context, header); 323 323 + if (unlikely(ret != 0)) 324 324 + return ret; 325 325 + 326 326 + for (; cur_state < last_state; ++cur_state) { 327 327 + if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE)) 328 328 + continue; 329 329 + 330 330 + ret = vmw_cmd_sid_check(dev_priv, sw_context, 331 331 + &cur_state->value); 332 332 + if (unlikely(ret != 0)) 333 333 + return ret; 334 334 + } 335 335 + 336 336 + return 0; 251 337 } 252 338 253 339 ··· 364 264 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check), 365 265 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET, 366 266 &vmw_cmd_set_render_target_check), 367 367 - VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_cid_check), 267 267 + VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state), 368 268 VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check), 369 269 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check), 370 270 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check), ··· 376 276 VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_cid_check), 377 277 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_cid_check), 378 278 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_cid_check), 379 379 - VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_cid_check), 279 279 + VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw), 380 280 VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check), 381 281 VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check), 382 282 VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_cid_check), ··· 391 291 void *buf, uint32_t *size) 392 292 { 393 293 uint32_t cmd_id; 294 294 + uint32_t size_remaining = *size; 394 295 SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf; 395 296 int ret; 396 297 ··· 405 304 *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader); 406 305 407 306 cmd_id -= SVGA_3D_CMD_BASE; 307 307 + if (unlikely(*size > size_remaining)) 308 308 + goto out_err; 309 309 + 408 310 if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE)) 409 311 goto out_err; 410 312 ··· 430 326 int ret; 431 327 432 328 while (cur_size > 0) { 329 329 + size = cur_size; 433 330 ret = vmw_cmd_check(dev_priv, sw_context, buf, &size); 434 331 if (unlikely(ret != 0)) 435 332 return ret; ··· 491 386 return 0; 492 387 493 388 ret = vmw_gmr_bind(dev_priv, bo); 494 494 - if (likely(ret == 0 || ret == -ERESTART)) 389 389 + if (likely(ret == 0 || ret == -ERESTARTSYS)) 495 390 return ret; 496 391 497 392 ··· 534 429 535 430 ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex); 536 431 if (unlikely(ret != 0)) { 537 537 - ret = -ERESTART; 432 432 + ret = -ERESTARTSYS; 538 433 goto out_no_cmd_mutex; 539 434 } 540 435

+2 -4

drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c

reviewed

··· 191 191 } 192 192 schedule_timeout(1); 193 193 if (interruptible && signal_pending(current)) { 194 194 - ret = -ERESTART; 194 194 + ret = -ERESTARTSYS; 195 195 break; 196 196 } 197 197 } ··· 237 237 (dev_priv->fifo_queue, 238 238 !vmw_fifo_is_full(dev_priv, bytes), timeout); 239 239 240 240 - if (unlikely(ret == -ERESTARTSYS)) 241 241 - ret = -ERESTART; 242 242 - else if (unlikely(ret == 0)) 240 240 + if (unlikely(ret == 0)) 243 241 ret = -EBUSY; 244 242 else if (likely(ret > 0)) 245 243 ret = 0;

+2 -4

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c

reviewed

··· 155 155 TASK_UNINTERRUPTIBLE); 156 156 } 157 157 if (interruptible && signal_pending(current)) { 158 158 - ret = -ERESTART; 158 158 + ret = -ERESTARTSYS; 159 159 break; 160 160 } 161 161 } ··· 218 218 vmw_fence_signaled(dev_priv, sequence), 219 219 timeout); 220 220 221 221 - if (unlikely(ret == -ERESTARTSYS)) 222 222 - ret = -ERESTART; 223 223 - else if (unlikely(ret == 0)) 221 221 + if (unlikely(ret == 0)) 224 222 ret = -EBUSY; 225 223 else if (likely(ret > 0)) 226 224 ret = 0;

+4 -4

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

reviewed

··· 106 106 int ret; 107 107 108 108 if (handle) { 109 109 - ret = vmw_user_surface_lookup(dev_priv, tfile, 110 110 - handle, &surface); 109 109 + ret = vmw_user_surface_lookup_handle(dev_priv, tfile, 110 110 + handle, &surface); 111 111 if (!ret) { 112 112 if (!surface->snooper.image) { 113 113 DRM_ERROR("surface not suitable for cursor\n"); ··· 704 704 struct vmw_dma_buffer *bo = NULL; 705 705 int ret; 706 706 707 707 - ret = vmw_user_surface_lookup(dev_priv, tfile, 708 708 - mode_cmd->handle, &surface); 707 707 + ret = vmw_user_surface_lookup_handle(dev_priv, tfile, 708 708 + mode_cmd->handle, &surface); 709 709 if (ret) 710 710 goto try_dmabuf; 711 711

+70 -79

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

reviewed

··· 488 488 kfree(user_srf); 489 489 } 490 490 491 491 - int vmw_user_surface_lookup(struct vmw_private *dev_priv, 492 492 - struct ttm_object_file *tfile, 493 493 - int sid, struct vmw_surface **out) 491 491 + int vmw_user_surface_lookup_handle(struct vmw_private *dev_priv, 492 492 + struct ttm_object_file *tfile, 493 493 + uint32_t handle, struct vmw_surface **out) 494 494 { 495 495 struct vmw_resource *res; 496 496 struct vmw_surface *srf; 497 497 struct vmw_user_surface *user_srf; 498 498 + struct ttm_base_object *base; 499 499 + int ret = -EINVAL; 498 500 499 499 - res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, sid); 500 500 - if (unlikely(res == NULL)) 501 501 + base = ttm_base_object_lookup(tfile, handle); 502 502 + if (unlikely(base == NULL)) 501 503 return -EINVAL; 502 504 503 503 - if (res->res_free != &vmw_user_surface_free) 504 504 - return -EINVAL; 505 505 + if (unlikely(base->object_type != VMW_RES_SURFACE)) 506 506 + goto out_bad_resource; 505 507 506 506 - srf = container_of(res, struct vmw_surface, res); 507 507 - user_srf = container_of(srf, struct vmw_user_surface, srf); 508 508 - if (user_srf->base.tfile != tfile && !user_srf->base.shareable) 509 509 - return -EPERM; 508 508 + user_srf = container_of(base, struct vmw_user_surface, base); 509 509 + srf = &user_srf->srf; 510 510 + res = &srf->res; 511 511 + 512 512 + read_lock(&dev_priv->resource_lock); 513 513 + 514 514 + if (!res->avail || res->res_free != &vmw_user_surface_free) { 515 515 + read_unlock(&dev_priv->resource_lock); 516 516 + goto out_bad_resource; 517 517 + } 518 518 + 519 519 + kref_get(&res->kref); 520 520 + read_unlock(&dev_priv->resource_lock); 510 521 511 522 *out = srf; 512 512 - return 0; 523 523 + ret = 0; 524 524 + 525 525 + out_bad_resource: 526 526 + ttm_base_object_unref(&base); 527 527 + 528 528 + return ret; 513 529 } 514 530 515 531 static void vmw_user_surface_base_release(struct ttm_base_object **p_base) ··· 542 526 int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data, 543 527 struct drm_file *file_priv) 544 528 { 545 545 - struct vmw_private *dev_priv = vmw_priv(dev); 546 546 - struct vmw_resource *res; 547 547 - struct vmw_surface *srf; 548 548 - struct vmw_user_surface *user_srf; 549 529 struct drm_vmw_surface_arg *arg = (struct drm_vmw_surface_arg *)data; 550 530 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile; 551 551 - int ret = 0; 552 531 553 553 - res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, arg->sid); 554 554 - if (unlikely(res == NULL)) 555 555 - return -EINVAL; 556 556 - 557 557 - if (res->res_free != &vmw_user_surface_free) { 558 558 - ret = -EINVAL; 559 559 - goto out; 560 560 - } 561 561 - 562 562 - srf = container_of(res, struct vmw_surface, res); 563 563 - user_srf = container_of(srf, struct vmw_user_surface, srf); 564 564 - if (user_srf->base.tfile != tfile && !user_srf->base.shareable) { 565 565 - ret = -EPERM; 566 566 - goto out; 567 567 - } 568 568 - 569 569 - ttm_ref_object_base_unref(tfile, user_srf->base.hash.key, 570 570 - TTM_REF_USAGE); 571 571 - out: 572 572 - vmw_resource_unreference(&res); 573 573 - return ret; 532 532 + return ttm_ref_object_base_unref(tfile, arg->sid, TTM_REF_USAGE); 574 533 } 575 534 576 535 int vmw_surface_define_ioctl(struct drm_device *dev, void *data, ··· 640 649 } 641 650 srf->snooper.crtc = NULL; 642 651 643 643 - rep->sid = res->id; 652 652 + rep->sid = user_srf->base.hash.key; 653 653 + if (rep->sid == SVGA3D_INVALID_ID) 654 654 + DRM_ERROR("Created bad Surface ID.\n"); 655 655 + 644 656 vmw_resource_unreference(&res); 645 657 return 0; 646 658 out_err1: ··· 656 662 int vmw_surface_reference_ioctl(struct drm_device *dev, void *data, 657 663 struct drm_file *file_priv) 658 664 { 659 659 - struct vmw_private *dev_priv = vmw_priv(dev); 660 665 union drm_vmw_surface_reference_arg *arg = 661 666 (union drm_vmw_surface_reference_arg *)data; 662 667 struct drm_vmw_surface_arg *req = &arg->req; 663 668 struct drm_vmw_surface_create_req *rep = &arg->rep; 664 669 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile; 665 665 - struct vmw_resource *res; 666 670 struct vmw_surface *srf; 667 671 struct vmw_user_surface *user_srf; 668 672 struct drm_vmw_size __user *user_sizes; 669 669 - int ret; 673 673 + struct ttm_base_object *base; 674 674 + int ret = -EINVAL; 670 675 671 671 - res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, req->sid); 672 672 - if (unlikely(res == NULL)) 676 676 + base = ttm_base_object_lookup(tfile, req->sid); 677 677 + if (unlikely(base == NULL)) { 678 678 + DRM_ERROR("Could not find surface to reference.\n"); 673 679 return -EINVAL; 674 674 - 675 675 - if (res->res_free != &vmw_user_surface_free) { 676 676 - ret = -EINVAL; 677 677 - goto out; 678 680 } 679 681 680 680 - srf = container_of(res, struct vmw_surface, res); 681 681 - user_srf = container_of(srf, struct vmw_user_surface, srf); 682 682 - if (user_srf->base.tfile != tfile && !user_srf->base.shareable) { 683 683 - DRM_ERROR("Tried to reference none shareable surface\n"); 684 684 - ret = -EPERM; 685 685 - goto out; 686 686 - } 682 682 + if (unlikely(base->object_type != VMW_RES_SURFACE)) 683 683 + goto out_bad_resource; 684 684 + 685 685 + user_srf = container_of(base, struct vmw_user_surface, base); 686 686 + srf = &user_srf->srf; 687 687 688 688 ret = ttm_ref_object_add(tfile, &user_srf->base, TTM_REF_USAGE, NULL); 689 689 if (unlikely(ret != 0)) { 690 690 DRM_ERROR("Could not add a reference to a surface.\n"); 691 691 - goto out; 691 691 + goto out_no_reference; 692 692 } 693 693 694 694 rep->flags = srf->flags; ··· 694 706 if (user_sizes) 695 707 ret = copy_to_user(user_sizes, srf->sizes, 696 708 srf->num_sizes * sizeof(*srf->sizes)); 697 697 - if (unlikely(ret != 0)) { 709 709 + if (unlikely(ret != 0)) 698 710 DRM_ERROR("copy_to_user failed %p %u\n", 699 711 user_sizes, srf->num_sizes); 700 700 - /** 701 701 - * FIXME: Unreference surface here? 702 702 - */ 703 703 - goto out; 704 704 - } 705 705 - out: 706 706 - vmw_resource_unreference(&res); 712 712 + out_bad_resource: 713 713 + out_no_reference: 714 714 + ttm_base_object_unref(&base); 715 715 + 707 716 return ret; 708 717 } 709 718 710 719 int vmw_surface_check(struct vmw_private *dev_priv, 711 720 struct ttm_object_file *tfile, 712 712 - int id) 721 721 + uint32_t handle, int *id) 713 722 { 714 714 - struct vmw_resource *res; 715 715 - int ret = 0; 723 723 + struct ttm_base_object *base; 724 724 + struct vmw_user_surface *user_srf; 716 725 717 717 - read_lock(&dev_priv->resource_lock); 718 718 - res = idr_find(&dev_priv->surface_idr, id); 719 719 - if (res && res->avail) { 720 720 - struct vmw_surface *srf = 721 721 - container_of(res, struct vmw_surface, res); 722 722 - struct vmw_user_surface *usrf = 723 723 - container_of(srf, struct vmw_user_surface, srf); 726 726 + int ret = -EPERM; 724 727 725 725 - if (usrf->base.tfile != tfile && !usrf->base.shareable) 726 726 - ret = -EPERM; 727 727 - } else 728 728 - ret = -EINVAL; 729 729 - read_unlock(&dev_priv->resource_lock); 728 728 + base = ttm_base_object_lookup(tfile, handle); 729 729 + if (unlikely(base == NULL)) 730 730 + return -EINVAL; 730 731 732 732 + if (unlikely(base->object_type != VMW_RES_SURFACE)) 733 733 + goto out_bad_surface; 734 734 + 735 735 + user_srf = container_of(base, struct vmw_user_surface, base); 736 736 + *id = user_srf->srf.res.id; 737 737 + ret = 0; 738 738 + 739 739 + out_bad_surface: 740 740 + /** 741 741 + * FIXME: May deadlock here when called from the 742 742 + * command parsing code. 743 743 + */ 744 744 + 745 745 + ttm_base_object_unref(&base); 731 746 return ret; 732 747 } 733 748

+3 -2

include/drm/drmP.h

reviewed

··· 296 296 #define DRM_MASTER 0x2 297 297 #define DRM_ROOT_ONLY 0x4 298 298 #define DRM_CONTROL_ALLOW 0x8 299 299 + #define DRM_UNLOCKED 0x10 299 300 300 301 struct drm_ioctl_desc { 301 302 unsigned int cmd; ··· 1129 1128 /* Driver support (drm_drv.h) */ 1130 1129 extern int drm_init(struct drm_driver *driver); 1131 1130 extern void drm_exit(struct drm_driver *driver); 1132 1132 - extern int drm_ioctl(struct inode *inode, struct file *filp, 1133 1133 - unsigned int cmd, unsigned long arg); 1131 1131 + extern long drm_ioctl(struct file *filp, 1132 1132 + unsigned int cmd, unsigned long arg); 1134 1133 extern long drm_compat_ioctl(struct file *filp, 1135 1134 unsigned int cmd, unsigned long arg); 1136 1135 extern int drm_lastclose(struct drm_device *dev);