tjh.dev / kernel
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clk: sunxi-ng: v3s: Fix CSI SCLK clock name

The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for
both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the
documentation.

Fix the name in the driver, header and device-tree.

Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-By: Icenowy Zheng <uwu@icenowy.me>
Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

authored by

Paul Kocialkowski and committed by
Chen-Yu Tsai f45b2949 713d4887

+10 -10
+1 -1
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
··· 110 110 reg = <0x01cb4000 0x1000>; 111 111 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 112 112 clocks = <&ccu CLK_BUS_CSI>, 113 - <&ccu CLK_CSI1_SCLK>, 113 + <&ccu CLK_CSI_SCLK>, 114 114 <&ccu CLK_DRAM_CSI>; 115 115 clock-names = "bus", 116 116 "mod",
+1 -1
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml
··· 79 79 reg = <0x01cb8000 0x1000>; 80 80 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 81 81 clocks = <&ccu CLK_BUS_CSI>, 82 - <&ccu CLK_CSI1_SCLK>, 82 + <&ccu CLK_CSI_SCLK>, 83 83 <&ccu CLK_DRAM_CSI>; 84 84 clock-names = "bus", "mod", "ram"; 85 85 resets = <&ccu RST_BUS_CSI>;
+1 -1
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
··· 103 103 reg = <0x01cb1000 0x1000>; 104 104 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 105 105 clocks = <&ccu CLK_BUS_CSI>, 106 - <&ccu CLK_CSI1_SCLK>; 106 + <&ccu CLK_CSI_SCLK>; 107 107 clock-names = "bus", "mod"; 108 108 resets = <&ccu RST_BUS_CSI>; 109 109
+1 -1
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
··· 652 652 reg = <0x01cb4000 0x3000>; 653 653 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 654 654 clocks = <&ccu CLK_BUS_CSI>, 655 - <&ccu CLK_CSI1_SCLK>, 655 + <&ccu CLK_CSI_SCLK>, 656 656 <&ccu CLK_DRAM_CSI>; 657 657 clock-names = "bus", "mod", "ram"; 658 658 resets = <&ccu RST_BUS_CSI>;
+5 -5
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
··· 362 362 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 363 363 0x130, 0, 5, 8, 3, BIT(15), 0); 364 364 365 - static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" }; 366 - static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents, 365 + static const char * const csi_sclk_parents[] = { "pll-video", "pll-isp" }; 366 + static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 367 367 0x134, 16, 4, 24, 3, BIT(31), 0); 368 368 369 369 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents, ··· 452 452 &tcon_clk.common, 453 453 &csi_misc_clk.common, 454 454 &csi0_mclk_clk.common, 455 - &csi1_sclk_clk.common, 455 + &csi_sclk_clk.common, 456 456 &csi1_mclk_clk.common, 457 457 &ve_clk.common, 458 458 &ac_dig_clk.common, ··· 551 551 [CLK_TCON0] = &tcon_clk.common.hw, 552 552 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 553 553 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 554 - [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, 554 + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 555 555 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 556 556 [CLK_VE] = &ve_clk.common.hw, 557 557 [CLK_AC_DIG] = &ac_dig_clk.common.hw, ··· 633 633 [CLK_TCON0] = &tcon_clk.common.hw, 634 634 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 635 635 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 636 - [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, 636 + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 637 637 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 638 638 [CLK_VE] = &ve_clk.common.hw, 639 639 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
+1 -1
include/dt-bindings/clock/sun8i-v3s-ccu.h
··· 96 96 #define CLK_TCON0 64 97 97 #define CLK_CSI_MISC 65 98 98 #define CLK_CSI0_MCLK 66 99 - #define CLK_CSI1_SCLK 67 99 + #define CLK_CSI_SCLK 67 100 100 #define CLK_CSI1_MCLK 68 101 101 #define CLK_VE 69 102 102 #define CLK_AC_DIG 70