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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
"An unfortunately large collection of arm64 fixes for -rc5.

Some of this is absolutely trivial, but the alternatives, vDSO and CPU
errata workaround fixes are significant. At least people are finding
and fixing these things, I suppose.

- Fix workaround for CPU erratum #1418040 to disable the compat vDSO

- Fix Oops when single-stepping with KGDB

- Fix memory attributes for hypervisor device mappings at EL2

- Fix memory leak in PSCI and remove useless variable assignment

- Fix up some comments and asm labels in our entry code

- Fix broken register table formatting in our generated html docs

- Fix missing NULL sentinel in CPU errata workaround list

- Fix patching of branches in alternative instruction sections"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64/alternatives: don't patch up internal branches
arm64: Add missing sentinel to erratum_1463225
arm64: Documentation: Fix broken table in generated HTML
arm64: kgdb: Fix single-step exception handling oops
arm64: entry: Tidy up block comments and label numbers
arm64: Rework ARM_ERRATUM_1414080 handling
arm64: arch_timer: Disable the compat vdso for cores affected by ARM64_WORKAROUND_1418040
arm64: arch_timer: Allow an workaround descriptor to disable compat vdso
arm64: Introduce a way to disable the 32bit vdso
arm64: entry: Fix the typo in the comment of el1_dbg()
drivers/firmware/psci: Assign @err directly in hotplug_tests()
drivers/firmware/psci: Fix memory leakage in alloc_init_cpu_groups()
KVM: arm64: Fix definition of PAGE_HYP_DEVICE

+68 -44
+2
Documentation/arm64/cpu-feature-registers.rst
··· 171 171 172 172 173 173 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 174 + 174 175 +------------------------------+---------+---------+ 175 176 | Name | bits | visible | 176 177 +------------------------------+---------+---------+ ··· 182 181 183 182 184 183 4) MIDR_EL1 - Main ID Register 184 + 185 185 +------------------------------+---------+---------+ 186 186 | Name | bits | visible | 187 187 +------------------------------+---------+---------+
+1
arch/arm64/include/asm/arch_timer.h
··· 58 58 u64 (*read_cntvct_el0)(void); 59 59 int (*set_next_event_phys)(unsigned long, struct clock_event_device *); 60 60 int (*set_next_event_virt)(unsigned long, struct clock_event_device *); 61 + bool disable_compat_vdso; 61 62 }; 62 63 63 64 DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
+1 -1
arch/arm64/include/asm/pgtable-prot.h
··· 67 67 #define PAGE_HYP __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_HYP_XN) 68 68 #define PAGE_HYP_EXEC __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY) 69 69 #define PAGE_HYP_RO __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY | PTE_HYP_XN) 70 - #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) 70 + #define PAGE_HYP_DEVICE __pgprot(_PROT_DEFAULT | PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_HYP | PTE_HYP_XN) 71 71 72 72 #define PAGE_S2_MEMATTR(attr) \ 73 73 ({ \
+5 -2
arch/arm64/include/asm/vdso/clocksource.h
··· 2 2 #ifndef __ASM_VDSOCLOCKSOURCE_H 3 3 #define __ASM_VDSOCLOCKSOURCE_H 4 4 5 - #define VDSO_ARCH_CLOCKMODES \ 6 - VDSO_CLOCKMODE_ARCHTIMER 5 + #define VDSO_ARCH_CLOCKMODES \ 6 + /* vdso clocksource for both 32 and 64bit tasks */ \ 7 + VDSO_CLOCKMODE_ARCHTIMER, \ 8 + /* vdso clocksource for 64bit tasks only */ \ 9 + VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT 7 10 8 11 #endif
+7 -1
arch/arm64/include/asm/vdso/compat_gettimeofday.h
··· 111 111 * update. Return something. Core will do another round and then 112 112 * see the mode change and fallback to the syscall. 113 113 */ 114 - if (clock_mode == VDSO_CLOCKMODE_NONE) 114 + if (clock_mode != VDSO_CLOCKMODE_ARCHTIMER) 115 115 return 0; 116 116 117 117 /* ··· 151 151 152 152 return ret; 153 153 } 154 + 155 + static inline bool vdso_clocksource_ok(const struct vdso_data *vd) 156 + { 157 + return vd->clock_mode == VDSO_CLOCKMODE_ARCHTIMER; 158 + } 159 + #define vdso_clocksource_ok vdso_clocksource_ok 154 160 155 161 #endif /* !__ASSEMBLY__ */ 156 162
+2 -14
arch/arm64/kernel/alternative.c
··· 43 43 */ 44 44 static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc) 45 45 { 46 - unsigned long replptr; 47 - 48 - if (kernel_text_address(pc)) 49 - return true; 50 - 51 - replptr = (unsigned long)ALT_REPL_PTR(alt); 52 - if (pc >= replptr && pc <= (replptr + alt->alt_len)) 53 - return false; 54 - 55 - /* 56 - * Branching into *another* alternate sequence is doomed, and 57 - * we're not even trying to fix it up. 58 - */ 59 - BUG(); 46 + unsigned long replptr = (unsigned long)ALT_REPL_PTR(alt); 47 + return !(pc >= replptr && pc <= (replptr + alt->alt_len)); 60 48 } 61 49 62 50 #define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1))
+1
arch/arm64/kernel/cpu_errata.c
··· 782 782 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 783 783 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 784 784 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 785 + {}, 785 786 }; 786 787 #endif 787 788
+1 -1
arch/arm64/kernel/entry-common.c
··· 57 57 /* 58 58 * The CPU masked interrupts, and we are leaving them masked during 59 59 * do_debug_exception(). Update PMR as if we had called 60 - * local_mask_daif(). 60 + * local_daif_mask(). 61 61 */ 62 62 if (system_uses_irq_prio_masking()) 63 63 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
+31 -21
arch/arm64/kernel/entry.S
··· 126 126 add \dst, \dst, #(\sym - .entry.tramp.text) 127 127 .endm 128 128 129 - // This macro corrupts x0-x3. It is the caller's duty 130 - // to save/restore them if required. 129 + /* 130 + * This macro corrupts x0-x3. It is the caller's duty to save/restore 131 + * them if required. 132 + */ 131 133 .macro apply_ssbd, state, tmp1, tmp2 132 134 #ifdef CONFIG_ARM64_SSBD 133 135 alternative_cb arm64_enable_wa2_handling ··· 169 167 stp x28, x29, [sp, #16 * 14] 170 168 171 169 .if \el == 0 170 + .if \regsize == 32 171 + /* 172 + * If we're returning from a 32-bit task on a system affected by 173 + * 1418040 then re-enable userspace access to the virtual counter. 174 + */ 175 + #ifdef CONFIG_ARM64_ERRATUM_1418040 176 + alternative_if ARM64_WORKAROUND_1418040 177 + mrs x0, cntkctl_el1 178 + orr x0, x0, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN 179 + msr cntkctl_el1, x0 180 + alternative_else_nop_endif 181 + #endif 182 + .endif 172 183 clear_gp_regs 173 184 mrs x21, sp_el0 174 185 ldr_this_cpu tsk, __entry_task, x20 175 186 msr sp_el0, tsk 176 187 177 - // Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 178 - // when scheduling. 188 + /* 189 + * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 190 + * when scheduling. 191 + */ 179 192 ldr x19, [tsk, #TSK_TI_FLAGS] 180 193 disable_step_tsk x19, x20 181 194 ··· 337 320 tst x22, #PSR_MODE32_BIT // native task? 338 321 b.eq 3f 339 322 323 + #ifdef CONFIG_ARM64_ERRATUM_1418040 324 + alternative_if ARM64_WORKAROUND_1418040 325 + mrs x0, cntkctl_el1 326 + bic x0, x0, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN 327 + msr cntkctl_el1, x0 328 + alternative_else_nop_endif 329 + #endif 330 + 340 331 #ifdef CONFIG_ARM64_ERRATUM_845719 341 332 alternative_if ARM64_WORKAROUND_845719 342 333 #ifdef CONFIG_PID_IN_CONTEXTIDR ··· 356 331 alternative_else_nop_endif 357 332 #endif 358 333 3: 359 - #ifdef CONFIG_ARM64_ERRATUM_1418040 360 - alternative_if_not ARM64_WORKAROUND_1418040 361 - b 4f 362 - alternative_else_nop_endif 363 - /* 364 - * if (x22.mode32 == cntkctl_el1.el0vcten) 365 - * cntkctl_el1.el0vcten = ~cntkctl_el1.el0vcten 366 - */ 367 - mrs x1, cntkctl_el1 368 - eon x0, x1, x22, lsr #3 369 - tbz x0, #1, 4f 370 - eor x1, x1, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN 371 - msr cntkctl_el1, x1 372 - 4: 373 - #endif 374 334 scs_save tsk, x0 375 335 376 336 /* No kernel C function calls after this as user keys are set. */ ··· 387 377 .if \el == 0 388 378 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 389 379 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 390 - bne 5f 380 + bne 4f 391 381 msr far_el1, x30 392 382 tramp_alias x30, tramp_exit_native 393 383 br x30 394 - 5: 384 + 4: 395 385 tramp_alias x30, tramp_exit_compat 396 386 br x30 397 387 #endif
+1 -1
arch/arm64/kernel/kgdb.c
··· 252 252 if (!kgdb_single_step) 253 253 return DBG_HOOK_ERROR; 254 254 255 - kgdb_handle_exception(1, SIGTRAP, 0, regs); 255 + kgdb_handle_exception(0, SIGTRAP, 0, regs); 256 256 return DBG_HOOK_HANDLED; 257 257 } 258 258 NOKPROBE_SYMBOL(kgdb_step_brk_fn);
+11
drivers/clocksource/arm_arch_timer.c
··· 480 480 .set_next_event_virt = erratum_set_next_event_tval_virt, 481 481 }, 482 482 #endif 483 + #ifdef CONFIG_ARM64_ERRATUM_1418040 484 + { 485 + .match_type = ate_match_local_cap_id, 486 + .id = (void *)ARM64_WORKAROUND_1418040, 487 + .desc = "ARM erratum 1418040", 488 + .disable_compat_vdso = true, 489 + }, 490 + #endif 483 491 }; 484 492 485 493 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, ··· 574 566 if (wa->read_cntvct_el0) { 575 567 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE; 576 568 vdso_default = VDSO_CLOCKMODE_NONE; 569 + } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) { 570 + vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT; 571 + clocksource_counter.vdso_clock_mode = vdso_default; 577 572 } 578 573 } 579 574
+5 -3
drivers/firmware/psci/psci_checker.c
··· 157 157 158 158 cpu_groups = kcalloc(nb_available_cpus, sizeof(cpu_groups), 159 159 GFP_KERNEL); 160 - if (!cpu_groups) 160 + if (!cpu_groups) { 161 + free_cpumask_var(tmp); 161 162 return -ENOMEM; 163 + } 162 164 163 165 cpumask_copy(tmp, cpu_online_mask); 164 166 ··· 169 167 topology_core_cpumask(cpumask_any(tmp)); 170 168 171 169 if (!alloc_cpumask_var(&cpu_groups[num_groups], GFP_KERNEL)) { 170 + free_cpumask_var(tmp); 172 171 free_cpu_groups(num_groups, &cpu_groups); 173 172 return -ENOMEM; 174 173 } ··· 199 196 if (!page_buf) 200 197 goto out_free_cpu_groups; 201 198 202 - err = 0; 203 199 /* 204 200 * Of course the last CPU cannot be powered down and cpu_down() should 205 201 * refuse doing that. 206 202 */ 207 203 pr_info("Trying to turn off and on again all CPUs\n"); 208 - err += down_and_up_cpus(cpu_online_mask, offlined_cpus); 204 + err = down_and_up_cpus(cpu_online_mask, offlined_cpus); 209 205 210 206 /* 211 207 * Take down CPUs by cpu group this time. When the last CPU is turned