+4 -6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 900 900 /* protects concurrent MM_INDEX/DATA based register access */ 901 901 spinlock_t mmio_idx_lock; 902 902 struct amdgpu_mmio_remap rmmio_remap; 903 903 - /* protects concurrent SMC based register access */ 904 904 - spinlock_t smc_idx_lock; 905 905 - amdgpu_rreg_t smc_rreg; 906 906 - amdgpu_wreg_t smc_wreg; 903 903 + /* Indirect register access blocks */ 904 904 + struct amdgpu_reg_access reg; 907 905 /* protects concurrent PCIE register access */ 908 906 spinlock_t pcie_idx_lock; 909 907 amdgpu_rreg_t pcie_rreg; ··· 1338 1340 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1339 1341 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1340 1342 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1341 1341 - #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1342 1342 - #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1343 1343 + #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1344 1344 + #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1343 1345 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1344 1346 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1345 1347 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

reviewed

··· 752 752 ssize_t result = 0; 753 753 int r; 754 754 755 755 - if (!adev->smc_rreg) 755 755 + if (!adev->reg.smc.rreg) 756 756 return -EOPNOTSUPP; 757 757 758 758 if (size & 0x3 || *pos & 0x3) ··· 810 810 ssize_t result = 0; 811 811 int r; 812 812 813 813 - if (!adev->smc_wreg) 813 813 + if (!adev->reg.smc.wreg) 814 814 return -EOPNOTSUPP; 815 815 816 816 if (size & 0x3 || *pos & 0x3)

+2 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 3830 3830 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); 3831 3831 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 3832 3832 3833 3833 - adev->smc_rreg = &amdgpu_invalid_rreg; 3834 3834 - adev->smc_wreg = &amdgpu_invalid_wreg; 3833 3833 + amdgpu_reg_access_init(adev); 3834 3834 + 3835 3835 adev->pcie_rreg = &amdgpu_invalid_rreg; 3836 3836 adev->pcie_wreg = &amdgpu_invalid_wreg; 3837 3837 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; ··· 3894 3894 return r; 3895 3895 3896 3896 spin_lock_init(&adev->mmio_idx_lock); 3897 3897 - spin_lock_init(&adev->smc_idx_lock); 3898 3897 spin_lock_init(&adev->pcie_idx_lock); 3899 3898 spin_lock_init(&adev->uvd_ctx_idx_lock); 3900 3899 spin_lock_init(&adev->didt_idx_lock);

+25

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

reviewed

··· 33 33 #define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2) 34 34 #define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2) 35 35 36 36 + void amdgpu_reg_access_init(struct amdgpu_device *adev) 37 37 + { 38 38 + spin_lock_init(&adev->reg.smc.lock); 39 39 + adev->reg.smc.rreg = NULL; 40 40 + adev->reg.smc.wreg = NULL; 41 41 + } 42 42 + 43 43 + uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) 44 44 + { 45 45 + if (!adev->reg.smc.rreg) { 46 46 + dev_err_once(adev->dev, "SMC register read not supported\n"); 47 47 + return 0; 48 48 + } 49 49 + return adev->reg.smc.rreg(adev, reg); 50 50 + } 51 51 + 52 52 + void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 53 53 + { 54 54 + if (!adev->reg.smc.wreg) { 55 55 + dev_err_once(adev->dev, "SMC register write not supported\n"); 56 56 + return; 57 57 + } 58 58 + adev->reg.smc.wreg(adev, reg, v); 59 59 + } 60 60 + 36 61 /* 37 62 * register access helper functions. 38 63 */

+15 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

reviewed

··· 25 25 #define __AMDGPU_REG_ACCESS_H__ 26 26 27 27 #include <linux/types.h> 28 28 + #include <linux/spinlock.h> 28 29 29 30 struct amdgpu_device; 30 31 31 31 - /* 32 32 - * Registers read & write functions. 33 33 - */ 34 32 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); 35 33 typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); 34 34 + 35 35 + struct amdgpu_reg_ind { 36 36 + spinlock_t lock; 37 37 + amdgpu_rreg_t rreg; 38 38 + amdgpu_wreg_t wreg; 39 39 + }; 40 40 + 41 41 + struct amdgpu_reg_access { 42 42 + struct amdgpu_reg_ind smc; 43 43 + }; 44 44 + 45 45 + void amdgpu_reg_access_init(struct amdgpu_device *adev); 46 46 + uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); 47 47 + void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 36 48 37 49 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); 38 50 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);

+8 -8

drivers/gpu/drm/amd/amdgpu/cik.c

reviewed

··· 179 179 unsigned long flags; 180 180 u32 r; 181 181 182 182 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 182 182 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 183 183 WREG32(mmSMC_IND_INDEX_0, (reg)); 184 184 r = RREG32(mmSMC_IND_DATA_0); 185 185 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 185 185 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 186 186 return r; 187 187 } 188 188 ··· 190 190 { 191 191 unsigned long flags; 192 192 193 193 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 193 193 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 194 194 WREG32(mmSMC_IND_INDEX_0, (reg)); 195 195 WREG32(mmSMC_IND_DATA_0, (v)); 196 196 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 196 196 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 197 197 } 198 198 199 199 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) ··· 1027 1027 dw_ptr = (u32 *)bios; 1028 1028 length_dw = ALIGN(length_bytes, 4) / 4; 1029 1029 /* take the smc lock since we are using the smc index */ 1030 1030 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 1030 1030 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 1031 1031 /* set rom index to 0 */ 1032 1032 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); 1033 1033 WREG32(mmSMC_IND_DATA_0, 0); ··· 1035 1035 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); 1036 1036 for (i = 0; i < length_dw; i++) 1037 1037 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); 1038 1038 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 1038 1038 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 1039 1039 1040 1040 return true; 1041 1041 } ··· 1984 1984 { 1985 1985 struct amdgpu_device *adev = ip_block->adev; 1986 1986 1987 1987 - adev->smc_rreg = &cik_smc_rreg; 1988 1988 - adev->smc_wreg = &cik_smc_wreg; 1987 1987 + adev->reg.smc.rreg = cik_smc_rreg; 1988 1988 + adev->reg.smc.wreg = cik_smc_wreg; 1989 1989 adev->pcie_rreg = &cik_pcie_rreg; 1990 1990 adev->pcie_wreg = &cik_pcie_wreg; 1991 1991 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;

-2

drivers/gpu/drm/amd/amdgpu/nv.c

reviewed

··· 635 635 struct amdgpu_device *adev = ip_block->adev; 636 636 637 637 adev->nbio.funcs->set_reg_remap(adev); 638 638 - adev->smc_rreg = NULL; 639 639 - adev->smc_wreg = NULL; 640 638 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 641 639 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 642 640 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;

+6 -6

drivers/gpu/drm/amd/amdgpu/si.c

reviewed

··· 1077 1077 unsigned long flags; 1078 1078 u32 r; 1079 1079 1080 1080 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 1080 1080 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 1081 1081 WREG32(mmSMC_IND_INDEX_0, (reg)); 1082 1082 r = RREG32(mmSMC_IND_DATA_0); 1083 1083 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 1083 1083 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 1084 1084 return r; 1085 1085 } 1086 1086 ··· 1088 1088 { 1089 1089 unsigned long flags; 1090 1090 1091 1091 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 1091 1091 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 1092 1092 WREG32(mmSMC_IND_INDEX_0, (reg)); 1093 1093 WREG32(mmSMC_IND_DATA_0, (v)); 1094 1094 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 1094 1094 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 1095 1095 } 1096 1096 1097 1097 static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) ··· 2037 2037 { 2038 2038 struct amdgpu_device *adev = ip_block->adev; 2039 2039 2040 2040 - adev->smc_rreg = &si_smc_rreg; 2041 2041 - adev->smc_wreg = &si_smc_wreg; 2040 2040 + adev->reg.smc.rreg = si_smc_rreg; 2041 2041 + adev->reg.smc.wreg = si_smc_wreg; 2042 2042 adev->pcie_rreg = &si_pcie_rreg; 2043 2043 adev->pcie_wreg = &si_pcie_wreg; 2044 2044 adev->pciep_rreg = &si_pciep_rreg;

-2

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 961 961 struct amdgpu_device *adev = ip_block->adev; 962 962 963 963 adev->nbio.funcs->set_reg_remap(adev); 964 964 - adev->smc_rreg = NULL; 965 965 - adev->smc_wreg = NULL; 966 964 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 967 965 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 968 966 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;

-2

drivers/gpu/drm/amd/amdgpu/soc21.c

reviewed

··· 589 589 struct amdgpu_device *adev = ip_block->adev; 590 590 591 591 adev->nbio.funcs->set_reg_remap(adev); 592 592 - adev->smc_rreg = NULL; 593 593 - adev->smc_wreg = NULL; 594 592 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 595 593 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 596 594 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;

-2

drivers/gpu/drm/amd/amdgpu/soc24.c

reviewed

··· 362 362 struct amdgpu_device *adev = ip_block->adev; 363 363 364 364 adev->nbio.funcs->set_reg_remap(adev); 365 365 - adev->smc_rreg = NULL; 366 366 - adev->smc_wreg = NULL; 367 365 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 368 366 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 369 367 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;

-2

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

reviewed

··· 250 250 { 251 251 struct amdgpu_device *adev = ip_block->adev; 252 252 253 253 - adev->smc_rreg = NULL; 254 254 - adev->smc_wreg = NULL; 255 253 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 256 254 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 257 255 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;

+14 -14

drivers/gpu/drm/amd/amdgpu/vi.c

reviewed

··· 324 324 unsigned long flags; 325 325 u32 r; 326 326 327 327 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 327 327 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 328 328 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 329 329 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); 330 330 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 330 330 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 331 331 return r; 332 332 } 333 333 ··· 335 335 { 336 336 unsigned long flags; 337 337 338 338 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 338 338 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 339 339 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 340 340 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); 341 341 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 341 341 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 342 342 } 343 343 344 344 /* smu_8_0_d.h */ ··· 350 350 unsigned long flags; 351 351 u32 r; 352 352 353 353 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 353 353 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 354 354 WREG32(mmMP0PUB_IND_INDEX, (reg)); 355 355 r = RREG32(mmMP0PUB_IND_DATA); 356 356 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 356 356 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 357 357 return r; 358 358 } 359 359 ··· 361 361 { 362 362 unsigned long flags; 363 363 364 364 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 364 364 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 365 365 WREG32(mmMP0PUB_IND_INDEX, (reg)); 366 366 WREG32(mmMP0PUB_IND_DATA, (v)); 367 367 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 367 367 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 368 368 } 369 369 370 370 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) ··· 649 649 dw_ptr = (u32 *)bios; 650 650 length_dw = ALIGN(length_bytes, 4) / 4; 651 651 /* take the smc lock since we are using the smc index */ 652 652 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 652 652 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 653 653 /* set rom index to 0 */ 654 654 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); 655 655 WREG32(mmSMC_IND_DATA_11, 0); ··· 657 657 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); 658 658 for (i = 0; i < length_dw; i++) 659 659 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); 660 660 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 660 660 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 661 661 662 662 return true; 663 663 } ··· 1454 1454 struct amdgpu_device *adev = ip_block->adev; 1455 1455 1456 1456 if (adev->flags & AMD_IS_APU) { 1457 1457 - adev->smc_rreg = &cz_smc_rreg; 1458 1458 - adev->smc_wreg = &cz_smc_wreg; 1457 1457 + adev->reg.smc.rreg = cz_smc_rreg; 1458 1458 + adev->reg.smc.wreg = cz_smc_wreg; 1459 1459 } else { 1460 1460 - adev->smc_rreg = &vi_smc_rreg; 1461 1461 - adev->smc_wreg = &vi_smc_wreg; 1460 1460 + adev->reg.smc.rreg = vi_smc_rreg; 1461 1461 + adev->reg.smc.wreg = vi_smc_wreg; 1462 1462 } 1463 1463 adev->pcie_rreg = &vi_pcie_rreg; 1464 1464 adev->pcie_wreg = &vi_pcie_wreg;

+8 -8

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

reviewed

··· 65 65 66 66 addr = smc_start_address; 67 67 68 68 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 68 68 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 69 69 while (byte_count >= 4) { 70 70 /* SMC address space is BE */ 71 71 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; ··· 109 109 } 110 110 111 111 done: 112 112 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 112 112 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 113 113 114 114 return ret; 115 115 } ··· 252 252 if (ucode_size & 3) 253 253 return -EINVAL; 254 254 255 255 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 255 255 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 256 256 WREG32(mmSMC_IND_INDEX_0, ucode_start_address); 257 257 WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); 258 258 while (ucode_size >= 4) { ··· 265 265 ucode_size -= 4; 266 266 } 267 267 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); 268 268 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 268 268 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 269 269 270 270 return 0; 271 271 } ··· 276 276 unsigned long flags; 277 277 int ret; 278 278 279 279 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 279 279 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 280 280 ret = si_set_smc_sram_address(adev, smc_address, limit); 281 281 if (ret == 0) 282 282 *value = RREG32(mmSMC_IND_DATA_0); 283 283 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 283 283 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 284 284 285 285 return ret; 286 286 } ··· 291 291 unsigned long flags; 292 292 int ret; 293 293 294 294 - spin_lock_irqsave(&adev->smc_idx_lock, flags); 294 294 + spin_lock_irqsave(&adev->reg.smc.lock, flags); 295 295 ret = si_set_smc_sram_address(adev, smc_address, limit); 296 296 if (ret == 0) 297 297 WREG32(mmSMC_IND_DATA_0, value); 298 298 - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 298 298 + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 299 299 300 300 return ret; 301 301 }