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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
i3c: mipi-i3c-hci: Extract ring initialization from hci_dma_init()
Split the ring setup logic out of hci_dma_init() into a new helper
hci_dma_init_rings(). This refactoring prepares for Runtime PM support
by allowing DMA rings to be reinitialized independently after resume.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260113072702.16268-11-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
authored by
Adrian Hunter
and committed by
Alexandre Belloni
f5401c97
f180524a
+68
-50
+68
-50
drivers/i3c/master/mipi-i3c-hci/dma.c
+68
-50
drivers/i3c/master/mipi-i3c-hci/dma.c
···
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hci->io_data = NULL;
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}
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+
static void hci_dma_init_rh(struct i3c_hci *hci, struct hci_rh_data *rh, int i)
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+
{
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u32 regval;
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+
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rh_reg_write(CMD_RING_BASE_LO, lower_32_bits(rh->xfer_dma));
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+
rh_reg_write(CMD_RING_BASE_HI, upper_32_bits(rh->xfer_dma));
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rh_reg_write(RESP_RING_BASE_LO, lower_32_bits(rh->resp_dma));
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rh_reg_write(RESP_RING_BASE_HI, upper_32_bits(rh->resp_dma));
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+
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regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries);
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rh_reg_write(CR_SETUP, regval);
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+
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rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
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rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY |
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INTR_TRANSFER_COMPLETION |
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INTR_RING_OP |
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INTR_TRANSFER_ERR |
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INTR_IBI_RING_FULL |
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INTR_TRANSFER_ABORT);
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+
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if (i >= IBI_RINGS)
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goto ring_ready;
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+
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rh_reg_write(IBI_STATUS_RING_BASE_LO, lower_32_bits(rh->ibi_status_dma));
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rh_reg_write(IBI_STATUS_RING_BASE_HI, upper_32_bits(rh->ibi_status_dma));
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rh_reg_write(IBI_DATA_RING_BASE_LO, lower_32_bits(rh->ibi_data_dma));
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rh_reg_write(IBI_DATA_RING_BASE_HI, upper_32_bits(rh->ibi_data_dma));
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+
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regval = FIELD_PREP(IBI_STATUS_RING_SIZE, rh->ibi_status_entries) |
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FIELD_PREP(IBI_DATA_CHUNK_SIZE, ilog2(rh->ibi_chunk_sz) - 2) |
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FIELD_PREP(IBI_DATA_CHUNK_COUNT, rh->ibi_chunks_total);
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rh_reg_write(IBI_SETUP, regval);
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+
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+
regval = rh_reg_read(INTR_SIGNAL_ENABLE);
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+
regval |= INTR_IBI_READY;
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+
rh_reg_write(INTR_SIGNAL_ENABLE, regval);
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+
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+
ring_ready:
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+
/*
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* The MIPI I3C HCI specification does not document reset values for
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+
* RING_OPERATION1 fields and some controllers (e.g. Intel controllers)
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* do not reset the values, so ensure the ring pointers are set to zero
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+
* here.
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+
*/
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rh_reg_write(RING_OPERATION1, 0);
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+
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rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE);
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rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP);
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+
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rh->done_ptr = 0;
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rh->ibi_chunk_ptr = 0;
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+
}
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+
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static void hci_dma_init_rings(struct i3c_hci *hci)
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{
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struct hci_rings_data *rings = hci->io_data;
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u32 regval;
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+
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regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total);
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rhs_reg_write(CONTROL, regval);
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+
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for (int i = 0; i < rings->total; i++)
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hci_dma_init_rh(hci, &rings->headers[i], i);
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}
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+
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static int hci_dma_init(struct i3c_hci *hci)
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{
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struct hci_rings_data *rings;
···
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rings->total = nr_rings;
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rings->sysdev = sysdev;
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-
regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total);
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-
rhs_reg_write(CONTROL, regval);
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-
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for (i = 0; i < rings->total; i++) {
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u32 offset = rhs_reg_read(RHn_OFFSET(i));
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···
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if (!rh->xfer || !rh->resp || !rh->src_xfers)
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goto err_out;
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-
rh_reg_write(CMD_RING_BASE_LO, lower_32_bits(rh->xfer_dma));
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-
rh_reg_write(CMD_RING_BASE_HI, upper_32_bits(rh->xfer_dma));
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-
rh_reg_write(RESP_RING_BASE_LO, lower_32_bits(rh->resp_dma));
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-
rh_reg_write(RESP_RING_BASE_HI, upper_32_bits(rh->resp_dma));
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-
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-
regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries);
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-
rh_reg_write(CR_SETUP, regval);
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-
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rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
358
-
rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY |
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-
INTR_TRANSFER_COMPLETION |
360
-
INTR_RING_OP |
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-
INTR_TRANSFER_ERR |
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INTR_IBI_RING_FULL |
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-
INTR_TRANSFER_ABORT);
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-
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/* IBIs */
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if (i >= IBI_RINGS)
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-
goto ring_ready;
290
+
continue;
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regval = rh_reg_read(IBI_SETUP);
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rh->ibi_status_sz = FIELD_GET(IBI_STATUS_STRUCT_SIZE, regval);
···
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ret = -ENOMEM;
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goto err_out;
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}
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-
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-
rh_reg_write(IBI_STATUS_RING_BASE_LO, lower_32_bits(rh->ibi_status_dma));
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-
rh_reg_write(IBI_STATUS_RING_BASE_HI, upper_32_bits(rh->ibi_status_dma));
394
-
rh_reg_write(IBI_DATA_RING_BASE_LO, lower_32_bits(rh->ibi_data_dma));
395
-
rh_reg_write(IBI_DATA_RING_BASE_HI, upper_32_bits(rh->ibi_data_dma));
396
-
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-
regval = FIELD_PREP(IBI_STATUS_RING_SIZE,
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-
rh->ibi_status_entries) |
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-
FIELD_PREP(IBI_DATA_CHUNK_SIZE,
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ilog2(rh->ibi_chunk_sz) - 2) |
401
-
FIELD_PREP(IBI_DATA_CHUNK_COUNT,
402
-
rh->ibi_chunks_total);
403
-
rh_reg_write(IBI_SETUP, regval);
404
-
405
-
regval = rh_reg_read(INTR_SIGNAL_ENABLE);
406
-
regval |= INTR_IBI_READY;
407
-
rh_reg_write(INTR_SIGNAL_ENABLE, regval);
408
-
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-
ring_ready:
410
-
/*
411
-
* The MIPI I3C HCI specification does not document reset values for
412
-
* RING_OPERATION1 fields and some controllers (e.g. Intel controllers)
413
-
* do not reset the values, so ensure the ring pointers are set to zero
414
-
* here.
415
-
*/
416
-
rh_reg_write(RING_OPERATION1, 0);
417
-
418
-
rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE |
419
-
RING_CTRL_RUN_STOP);
420
345
}
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346
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ret = devm_add_action(hci->master.dev.parent, hci_dma_free, hci);
423
348
if (ret)
424
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goto err_out;
425
350
351
+
hci_dma_init_rings(hci);
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+
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353
return 0;
427
354
428
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err_out:
429
-
hci_dma_cleanup(hci);
430
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hci_dma_free(hci);
431
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return ret;
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358
}