Merge branch 'there-are-some-bugfix-for-the-hns3-ethernet-driver'

-3

drivers/net/ethernet/hisilicon/hns3/hnae3.h

··· 916 916 917 917 u8 netdev_flags; 918 918 struct dentry *hnae3_dbgfs; 919 - /* protects concurrent contention between debugfs commands */ 920 - struct mutex dbgfs_lock; 921 - char **dbgfs_buf; 922 919 923 920 /* Network interface message level enabled bits */ 924 921 u32 msg_enable;

+31 -65

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

··· 1260 1260 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, 1261 1261 size_t count, loff_t *ppos) 1262 1262 { 1263 - struct hns3_dbg_data *dbg_data = filp->private_data; 1263 + char *buf = filp->private_data; 1264 + 1265 + return simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); 1266 + } 1267 + 1268 + static int hns3_dbg_open(struct inode *inode, struct file *filp) 1269 + { 1270 + struct hns3_dbg_data *dbg_data = inode->i_private; 1264 1271 struct hnae3_handle *handle = dbg_data->handle; 1265 1272 struct hns3_nic_priv *priv = handle->priv; 1266 - ssize_t size = 0; 1267 - char **save_buf; 1268 - char *read_buf; 1269 1273 u32 index; 1274 + char *buf; 1270 1275 int ret; 1276 + 1277 + if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 1278 + test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 1279 + return -EBUSY; 1271 1280 1272 1281 ret = hns3_dbg_get_cmd_index(dbg_data, &index); 1273 1282 if (ret) 1274 1283 return ret; 1275 1284 1276 - mutex_lock(&handle->dbgfs_lock); 1277 - save_buf = &handle->dbgfs_buf[index]; 1285 + buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 1286 + if (!buf) 1287 + return -ENOMEM; 1278 1288 1279 - if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 1280 - test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) { 1281 - ret = -EBUSY; 1282 - goto out; 1289 + ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 1290 + buf, hns3_dbg_cmd[index].buf_len); 1291 + if (ret) { 1292 + kvfree(buf); 1293 + return ret; 1283 1294 } 1284 1295 1285 - if (*save_buf) { 1286 - read_buf = *save_buf; 1287 - } else { 1288 - read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 1289 - if (!read_buf) { 1290 - ret = -ENOMEM; 1291 - goto out; 1292 - } 1296 + filp->private_data = buf; 1297 + return 0; 1298 + } 1293 1299 1294 - /* save the buffer addr until the last read operation */ 1295 - *save_buf = read_buf; 1296 - 1297 - /* get data ready for the first time to read */ 1298 - ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 1299 - read_buf, hns3_dbg_cmd[index].buf_len); 1300 - if (ret) 1301 - goto out; 1302 - } 1303 - 1304 - size = simple_read_from_buffer(buffer, count, ppos, read_buf, 1305 - strlen(read_buf)); 1306 - if (size > 0) { 1307 - mutex_unlock(&handle->dbgfs_lock); 1308 - return size; 1309 - } 1310 - 1311 - out: 1312 - /* free the buffer for the last read operation */ 1313 - if (*save_buf) { 1314 - kvfree(*save_buf); 1315 - *save_buf = NULL; 1316 - } 1317 - 1318 - mutex_unlock(&handle->dbgfs_lock); 1319 - return ret; 1300 + static int hns3_dbg_release(struct inode *inode, struct file *filp) 1301 + { 1302 + kvfree(filp->private_data); 1303 + filp->private_data = NULL; 1304 + return 0; 1320 1305 } 1321 1306 1322 1307 static const struct file_operations hns3_dbg_fops = { 1323 1308 .owner = THIS_MODULE, 1324 - .open = simple_open, 1309 + .open = hns3_dbg_open, 1325 1310 .read = hns3_dbg_read, 1311 + .release = hns3_dbg_release, 1326 1312 }; 1327 1313 1328 1314 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) ··· 1365 1379 int ret; 1366 1380 u32 i; 1367 1381 1368 - handle->dbgfs_buf = devm_kcalloc(&handle->pdev->dev, 1369 - ARRAY_SIZE(hns3_dbg_cmd), 1370 - sizeof(*handle->dbgfs_buf), 1371 - GFP_KERNEL); 1372 - if (!handle->dbgfs_buf) 1373 - return -ENOMEM; 1374 - 1375 1382 hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = 1376 1383 debugfs_create_dir(name, hns3_dbgfs_root); 1377 1384 handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; ··· 1373 1394 hns3_dbg_dentry[i].dentry = 1374 1395 debugfs_create_dir(hns3_dbg_dentry[i].name, 1375 1396 handle->hnae3_dbgfs); 1376 - 1377 - mutex_init(&handle->dbgfs_lock); 1378 1397 1379 1398 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1380 1399 if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && ··· 1402 1425 out: 1403 1426 debugfs_remove_recursive(handle->hnae3_dbgfs); 1404 1427 handle->hnae3_dbgfs = NULL; 1405 - mutex_destroy(&handle->dbgfs_lock); 1406 1428 return ret; 1407 1429 } 1408 1430 1409 1431 void hns3_dbg_uninit(struct hnae3_handle *handle) 1410 1432 { 1411 - u32 i; 1412 - 1413 1433 debugfs_remove_recursive(handle->hnae3_dbgfs); 1414 1434 handle->hnae3_dbgfs = NULL; 1415 - 1416 - for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) 1417 - if (handle->dbgfs_buf[i]) { 1418 - kvfree(handle->dbgfs_buf[i]); 1419 - handle->dbgfs_buf[i] = NULL; 1420 - } 1421 - 1422 - mutex_destroy(&handle->dbgfs_lock); 1423 1435 } 1424 1436 1425 1437 void hns3_dbg_register_debugfs(const char *debugfs_dir_name)

-1

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

··· 2452 2452 return ret; 2453 2453 } 2454 2454 2455 - netdev->features = features; 2456 2455 return 0; 2457 2456 } 2458 2457

+36 -9

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

··· 6 6 #include <linux/etherdevice.h> 7 7 #include <linux/init.h> 8 8 #include <linux/interrupt.h> 9 + #include <linux/irq.h> 9 10 #include <linux/kernel.h> 10 11 #include <linux/module.h> 11 12 #include <linux/netdevice.h> ··· 3575 3574 return ret; 3576 3575 } 3577 3576 3577 + static void hclge_set_reset_pending(struct hclge_dev *hdev, 3578 + enum hnae3_reset_type reset_type) 3579 + { 3580 + /* When an incorrect reset type is executed, the get_reset_level 3581 + * function generates the HNAE3_NONE_RESET flag. As a result, this 3582 + * type do not need to pending. 3583 + */ 3584 + if (reset_type != HNAE3_NONE_RESET) 3585 + set_bit(reset_type, &hdev->reset_pending); 3586 + } 3587 + 3578 3588 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3579 3589 { 3580 3590 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; ··· 3606 3594 */ 3607 3595 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3608 3596 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3609 - set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3597 + hclge_set_reset_pending(hdev, HNAE3_IMP_RESET); 3610 3598 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3611 3599 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3612 3600 hdev->rst_stats.imp_rst_cnt++; ··· 3616 3604 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3617 3605 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3618 3606 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3619 - set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3607 + hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET); 3620 3608 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3621 3609 hdev->rst_stats.global_rst_cnt++; 3622 3610 return HCLGE_VECTOR0_EVENT_RST; ··· 3771 3759 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3772 3760 HCLGE_NAME, pci_name(hdev->pdev)); 3773 3761 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3774 - 0, hdev->misc_vector.name, hdev); 3762 + IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); 3775 3763 if (ret) { 3776 3764 hclge_free_vector(hdev, 0); 3777 3765 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", ··· 4064 4052 case HNAE3_FUNC_RESET: 4065 4053 dev_info(&pdev->dev, "PF reset requested\n"); 4066 4054 /* schedule again to check later */ 4067 - set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4055 + hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET); 4068 4056 hclge_reset_task_schedule(hdev); 4069 4057 break; 4070 4058 default: ··· 4097 4085 rst_level = HNAE3_FLR_RESET; 4098 4086 clear_bit(HNAE3_FLR_RESET, addr); 4099 4087 } 4088 + 4089 + clear_bit(HNAE3_NONE_RESET, addr); 4100 4090 4101 4091 if (hdev->reset_type != HNAE3_NONE_RESET && 4102 4092 rst_level < hdev->reset_type) ··· 4241 4227 return false; 4242 4228 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4243 4229 hdev->rst_stats.reset_fail_cnt++; 4244 - set_bit(hdev->reset_type, &hdev->reset_pending); 4230 + hclge_set_reset_pending(hdev, hdev->reset_type); 4245 4231 dev_info(&hdev->pdev->dev, 4246 4232 "re-schedule reset task(%u)\n", 4247 4233 hdev->rst_stats.reset_fail_cnt); ··· 4484 4470 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4485 4471 enum hnae3_reset_type rst_type) 4486 4472 { 4473 + #define HCLGE_SUPPORT_RESET_TYPE \ 4474 + (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \ 4475 + BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET)) 4476 + 4487 4477 struct hclge_dev *hdev = ae_dev->priv; 4478 + 4479 + if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) { 4480 + /* To prevent reset triggered by hclge_reset_event */ 4481 + set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 4482 + dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n", 4483 + rst_type); 4484 + return; 4485 + } 4488 4486 4489 4487 set_bit(rst_type, &hdev->default_reset_request); 4490 4488 } ··· 11907 11881 11908 11882 hclge_init_rxd_adv_layout(hdev); 11909 11883 11910 - /* Enable MISC vector(vector0) */ 11911 - hclge_enable_vector(&hdev->misc_vector, true); 11912 - 11913 11884 ret = hclge_init_wol(hdev); 11914 11885 if (ret) 11915 11886 dev_warn(&pdev->dev, ··· 11918 11895 11919 11896 hclge_state_init(hdev); 11920 11897 hdev->last_reset_time = jiffies; 11898 + 11899 + /* Enable MISC vector(vector0) */ 11900 + enable_irq(hdev->misc_vector.vector_irq); 11901 + hclge_enable_vector(&hdev->misc_vector, true); 11921 11902 11922 11903 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11923 11904 HCLGE_DRIVER_NAME); ··· 12328 12301 12329 12302 /* Disable MISC vector(vector0) */ 12330 12303 hclge_enable_vector(&hdev->misc_vector, false); 12331 - synchronize_irq(hdev->misc_vector.vector_irq); 12304 + disable_irq(hdev->misc_vector.vector_irq); 12332 12305 12333 12306 /* Disable all hw interrupts */ 12334 12307 hclge_config_mac_tnl_int(hdev, false);

+3

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c

··· 58 58 struct hclge_dev *hdev = vport->back; 59 59 struct hclge_ptp *ptp = hdev->ptp; 60 60 61 + if (!ptp) 62 + return false; 63 + 61 64 if (!test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) || 62 65 test_and_set_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) { 63 66 ptp->tx_skipped++;

+5 -4

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

··· 510 510 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, 511 511 struct hnae3_knic_private_info *kinfo) 512 512 { 513 - #define HCLGE_RING_REG_OFFSET 0x200 514 513 #define HCLGE_RING_INT_REG_OFFSET 0x4 515 514 515 + struct hnae3_queue *tqp; 516 516 int i, j, reg_num; 517 517 int data_num_sum; 518 518 u32 *reg = data; ··· 533 533 reg_num = ARRAY_SIZE(ring_reg_addr_list); 534 534 for (j = 0; j < kinfo->num_tqps; j++) { 535 535 reg += hclge_reg_get_tlv(HCLGE_REG_TAG_RING, reg_num, reg); 536 + tqp = kinfo->tqp[j]; 536 537 for (i = 0; i < reg_num; i++) 537 - *reg++ = hclge_read_dev(&hdev->hw, 538 - ring_reg_addr_list[i] + 539 - HCLGE_RING_REG_OFFSET * j); 538 + *reg++ = readl_relaxed(tqp->io_base - 539 + HCLGE_TQP_REG_OFFSET + 540 + ring_reg_addr_list[i]); 540 541 } 541 542 data_num_sum += (reg_num + HCLGE_REG_TLV_SPACE) * kinfo->num_tqps; 542 543

+34 -7

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

··· 1393 1393 return ret; 1394 1394 } 1395 1395 1396 + static void hclgevf_set_reset_pending(struct hclgevf_dev *hdev, 1397 + enum hnae3_reset_type reset_type) 1398 + { 1399 + /* When an incorrect reset type is executed, the get_reset_level 1400 + * function generates the HNAE3_NONE_RESET flag. As a result, this 1401 + * type do not need to pending. 1402 + */ 1403 + if (reset_type != HNAE3_NONE_RESET) 1404 + set_bit(reset_type, &hdev->reset_pending); 1405 + } 1406 + 1396 1407 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1397 1408 { 1398 1409 #define HCLGEVF_RESET_WAIT_US 20000 ··· 1553 1542 hdev->rst_stats.rst_fail_cnt); 1554 1543 1555 1544 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1556 - set_bit(hdev->reset_type, &hdev->reset_pending); 1545 + hclgevf_set_reset_pending(hdev, hdev->reset_type); 1557 1546 1558 1547 if (hclgevf_is_reset_pending(hdev)) { 1559 1548 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); ··· 1673 1662 clear_bit(HNAE3_FLR_RESET, addr); 1674 1663 } 1675 1664 1665 + clear_bit(HNAE3_NONE_RESET, addr); 1666 + 1676 1667 return rst_level; 1677 1668 } 1678 1669 ··· 1684 1671 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1685 1672 struct hclgevf_dev *hdev = ae_dev->priv; 1686 1673 1687 - dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1688 - 1689 1674 if (hdev->default_reset_request) 1690 1675 hdev->reset_level = 1691 1676 hclgevf_get_reset_level(&hdev->default_reset_request); 1692 1677 else 1693 1678 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1679 + 1680 + dev_info(&hdev->pdev->dev, "received reset request from VF enet, reset level is %d\n", 1681 + hdev->reset_level); 1694 1682 1695 1683 /* reset of this VF requested */ 1696 1684 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); ··· 1703 1689 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1704 1690 enum hnae3_reset_type rst_type) 1705 1691 { 1692 + #define HCLGEVF_SUPPORT_RESET_TYPE \ 1693 + (BIT(HNAE3_VF_RESET) | BIT(HNAE3_VF_FUNC_RESET) | \ 1694 + BIT(HNAE3_VF_PF_FUNC_RESET) | BIT(HNAE3_VF_FULL_RESET) | \ 1695 + BIT(HNAE3_FLR_RESET) | BIT(HNAE3_VF_EXP_RESET)) 1696 + 1706 1697 struct hclgevf_dev *hdev = ae_dev->priv; 1707 1698 1699 + if (!(BIT(rst_type) & HCLGEVF_SUPPORT_RESET_TYPE)) { 1700 + /* To prevent reset triggered by hclge_reset_event */ 1701 + set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 1702 + dev_info(&hdev->pdev->dev, "unsupported reset type %d\n", 1703 + rst_type); 1704 + return; 1705 + } 1708 1706 set_bit(rst_type, &hdev->default_reset_request); 1709 1707 } 1710 1708 ··· 1873 1847 */ 1874 1848 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1875 1849 /* prepare for full reset of stack + pcie interface */ 1876 - set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1850 + hclgevf_set_reset_pending(hdev, HNAE3_VF_FULL_RESET); 1877 1851 1878 1852 /* "defer" schedule the reset task again */ 1879 1853 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1880 1854 } else { 1881 1855 hdev->reset_attempts++; 1882 1856 1883 - set_bit(hdev->reset_level, &hdev->reset_pending); 1857 + hclgevf_set_reset_pending(hdev, hdev->reset_level); 1884 1858 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1885 1859 } 1886 1860 hclgevf_reset_task_schedule(hdev); ··· 2003 1977 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2004 1978 dev_info(&hdev->pdev->dev, 2005 1979 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2006 - set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1980 + hclgevf_set_reset_pending(hdev, HNAE3_VF_RESET); 2007 1981 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2008 1982 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 2009 1983 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); ··· 2313 2287 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2314 2288 2315 2289 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2290 + /* timer needs to be initialized before misc irq */ 2291 + timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); 2316 2292 2317 2293 mutex_init(&hdev->mbx_resp.mbx_mutex); 2318 2294 sema_init(&hdev->reset_sem, 1); ··· 3014 2986 HCLGEVF_DRIVER_NAME); 3015 2987 3016 2988 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3017 - timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); 3018 2989 3019 2990 return 0; 3020 2991

+5 -4

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

··· 123 123 void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 124 124 void *data) 125 125 { 126 - #define HCLGEVF_RING_REG_OFFSET 0x200 127 126 #define HCLGEVF_RING_INT_REG_OFFSET 0x4 128 127 129 128 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 129 + struct hnae3_queue *tqp; 130 130 int i, j, reg_um; 131 131 u32 *reg = data; 132 132 ··· 147 147 reg_um = ARRAY_SIZE(ring_reg_addr_list); 148 148 for (j = 0; j < hdev->num_tqps; j++) { 149 149 reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_um, reg); 150 + tqp = &hdev->htqp[j].q; 150 151 for (i = 0; i < reg_um; i++) 151 - *reg++ = hclgevf_read_dev(&hdev->hw, 152 - ring_reg_addr_list[i] + 153 - HCLGEVF_RING_REG_OFFSET * j); 152 + *reg++ = readl_relaxed(tqp->io_base - 153 + HCLGEVF_TQP_REG_OFFSET + 154 + ring_reg_addr_list[i]); 154 155 } 155 156 156 157 reg_um = ARRAY_SIZE(tqp_intr_reg_addr_list);

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