Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: ti: icssg: Add HSR/PRP protocol frame filtering
Add support for HSR and PRP protocol frame filtering in the ICSSG
classifier by configuring filter table 3 (FT3) to detect PTP frames
(EtherType 0x88F7) in HSR/PRP tagged packets.
Also add rx_class_or_base to miig_rt_offsets structure to support
RX_CLASS_OR register access, and fix typos in FT1_N_REG and FT3_N_REG
macros (slize -> slice).
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Link: https://patch.msgid.link/20260227174254.3821443-1-danishanwar@ti.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
authored by
MD Danish Anwar
and committed by
Paolo Abeni
f56438a7
c006396f
+75
-2
+67
-2
drivers/net/ethernet/ti/icssg/icssg_classifier.c
+67
-2
drivers/net/ethernet/ti/icssg/icssg_classifier.c
···
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#define FT1_DA0_MASK 0x8
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#define FT1_DA1_MASK 0xc
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-
#define FT1_N_REG(slize, n, reg) \
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+
#define FT1_N_REG(slice, n, reg) \
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(offs[slice].ft1_slot_base + FT1_SLOT_SIZE * (n) + (reg))
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#define FT1_LEN_MASK GENMASK(19, 16)
···
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#define FT3_T 0x18
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#define FT3_T_MASK 0x1c
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-
#define FT3_N_REG(slize, n, reg) \
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#define FT3_N_REG(slice, n, reg) \
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(offs[slice].ft3_slot_base + FT3_SLOT_SIZE * (n) + (reg))
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/* offsets from rx_class n's base */
···
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#define RX_CLASS_N_REG(slice, n, reg) \
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(offs[slice].rx_class_base + RX_CLASS_EN_SIZE * (n) + (reg))
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+
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#define RX_CLASS_OR_REG(slice, n, reg) \
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(offs[slice].rx_class_or_base + RX_CLASS_EN_SIZE * (n) + (reg))
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/* RX Class Gates */
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#define RX_CLASS_GATES_SIZE 0x4 /* bytes */
···
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#define RX_CLASS_FT_FT1_MATCH(slot) \
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((BIT(slot) << RX_CLASS_FT_FT1_MATCH_SHIFT) & \
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RX_CLASS_FT_FT1_MATCH_MASK)
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/* HSR/PRP protocol frame filtering */
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#define HSR_PTP_ETHERTYPE_OFFSET 0x12
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#define PRP_PTP_ETHERTYPE_OFFSET 0x0C
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#define FT3_PTP_PATTERN 0xF788
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#define FT3_ETHERTYPE_MASK 0xFFFF0000U
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#define FT3_VLAN_MODE_BOTH 0x1
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#define RX_CLASS_OR_DUP_PTP 0x4200
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#define RX_CLASS_OR_HSR_TAG 0x4000
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#define RX_CLASS_GATE_PTP 0x50
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#define RX_CLASS_DISABLE 0x0
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+
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/* HSR/PRP classifier indices */
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#define CLASSIFIER_PTP_DUP 10
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#define CLASSIFIER_HSR_TAG 11
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#define FT3_PTP_SLOT 14
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/* RX class type */
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enum rx_class_sel_type {
···
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u32 ft3_p_base;
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u32 ft_rx_ptr;
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u32 rx_class_base;
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u32 rx_class_or_base;
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u32 rx_class_cfg1;
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u32 rx_class_cfg2;
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u32 rx_class_gates_base;
···
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0x308,
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0x408,
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0x40c,
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+
0x410,
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0x48c,
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0x490,
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0x494,
···
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0x8d4,
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0x9d4,
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0x9d8,
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+
0x9dc,
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0xa58,
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0xa5c,
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0xa60,
···
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rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ);
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}
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EXPORT_SYMBOL_GPL(icssg_ft1_set_mac_addr);
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/**
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* icssg_ft3_hsr_configurations - Configure filter table for HSR/PRP protocol frames
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* @miig_rt: Pointer to the MII-G register map
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* @slice: ICSSG slice number (0 or 1)
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* @prueth: Pointer to prueth structure to determine HSR/PRP mode
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*
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* Configures FT3 to detect PTP frames (EtherType 0x88F7) in HSR/PRP tagged packets.
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* HSR frames have a 6-byte tag, while PRP has no tag offset for EtherType detection.
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*/
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void icssg_ft3_hsr_configurations(struct regmap *miig_rt, int slice,
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struct prueth *prueth)
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{
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u8 offset = (prueth->hsr_prp_version == PRP_V1) ?
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PRP_PTP_ETHERTYPE_OFFSET : HSR_PTP_ETHERTYPE_OFFSET;
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_START), offset);
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_START_AUTO), 0);
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_START_OFFSET), 0);
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_JUMP_OFFSET), 0);
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_LEN), 0);
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_CFG), FT3_VLAN_MODE_BOTH);
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_T), FT3_PTP_PATTERN);
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regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_T_MASK),
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FT3_ETHERTYPE_MASK);
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regmap_write(miig_rt, RX_CLASS_N_REG(slice, CLASSIFIER_PTP_DUP, RX_CLASS_AND_EN),
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RX_CLASS_DISABLE);
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regmap_write(miig_rt, RX_CLASS_OR_REG(slice, CLASSIFIER_PTP_DUP, RX_CLASS_OR_EN),
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RX_CLASS_OR_DUP_PTP);
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regmap_write(miig_rt, RX_CLASS_GATES_N_REG(slice, CLASSIFIER_PTP_DUP),
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RX_CLASS_GATE_PTP);
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if (prueth->hsr_prp_version != PRP_V1) {
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regmap_write(miig_rt, RX_CLASS_N_REG(slice, CLASSIFIER_HSR_TAG, RX_CLASS_AND_EN),
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RX_CLASS_DISABLE);
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regmap_write(miig_rt, RX_CLASS_OR_REG(slice, CLASSIFIER_HSR_TAG, RX_CLASS_OR_EN),
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RX_CLASS_OR_HSR_TAG);
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regmap_write(miig_rt, RX_CLASS_GATES_N_REG(slice, CLASSIFIER_HSR_TAG),
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RX_CLASS_GATE_PTP);
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}
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}
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EXPORT_SYMBOL_GPL(icssg_ft3_hsr_configurations);
+6
drivers/net/ethernet/ti/icssg/icssg_prueth.c
+6
drivers/net/ethernet/ti/icssg/icssg_prueth.c
···
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icssg_class_default(prueth->miig_rt, ICSS_SLICE0, 0, false);
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icssg_class_default(prueth->miig_rt, ICSS_SLICE1, 0, false);
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/* Configure HSR/PRP protocol filtering if in HSR offload mode */
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if (prueth->is_hsr_offload_mode) {
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icssg_ft3_hsr_configurations(prueth->miig_rt, ICSS_SLICE0, prueth);
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icssg_ft3_hsr_configurations(prueth->miig_rt, ICSS_SLICE1, prueth);
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}
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if (prueth->is_switch_mode || prueth->is_hsr_offload_mode)
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icssg_init_fw_offload_mode(prueth);
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else
+2
drivers/net/ethernet/ti/icssg/icssg_prueth.h
+2
drivers/net/ethernet/ti/icssg/icssg_prueth.h
···
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void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,
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struct net_device *ndev);
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void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr);
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void icssg_ft3_hsr_configurations(struct regmap *miig_rt, int slice,
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struct prueth *prueth);
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/* config helpers */
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void icssg_config_ipg(struct prueth_emac *emac);