Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Update FAMS sequence for DCN30 & DCN32
Provide DCN32 specific sequence and update DCN30 sequence
Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Alvin Lee
and committed by
Alex Deucher
f583db81
79f3f1b6
+38
-19
+1
-1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
···
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.pipe_control_lock = dcn20_pipe_control_lock,
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.interdependent_update_lock = dcn10_lock_all_pipes,
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.cursor_lock = dcn10_cursor_lock,
63
-
.prepare_bandwidth = dcn30_prepare_bandwidth,
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+
.prepare_bandwidth = dcn32_prepare_bandwidth,
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.optimize_bandwidth = dcn20_optimize_bandwidth,
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.update_bandwidth = dcn20_update_bandwidth,
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.set_drr = dcn10_set_drr,
+3
-18
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+3
-18
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
···
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993
void dcn30_prepare_bandwidth(struct dc *dc,
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struct dc_state *context)
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{
996
-
bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
997
-
/* Any transition into an FPO config should disable MCLK switching first to avoid
998
-
* driver and FW P-State synchronization issues.
999
-
*/
1000
-
if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
996
+
if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {
1001
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dc->optimized_required = true;
1002
998
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1003
999
}
···
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1008
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1005
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dcn20_prepare_bandwidth(dc, context);
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-
/*
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* enabled -> enabled: do not disable
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-
* enabled -> disabled: disable
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-
* disabled -> enabled: don't care
1011
-
* disabled -> disabled: don't care
1012
-
*/
1013
-
if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1014
-
dc_dmub_srv_p_state_delegate(dc, false, context);
1015
1011
1016
-
if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1017
-
/* After disabling P-State, restore the original value to ensure we get the correct P-State
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-
* on the next optimize. */
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-
context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
1020
-
}
1012
+
if (!dc->clk_mgr->clks.fw_based_mclk_switching)
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+
dc_dmub_srv_p_state_delegate(dc, false, context);
1021
1014
}
1022
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void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+31
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+31
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
···
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#include "dce/dmub_hw_lock_mgr.h"
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#include "dcn32/dcn32_resource.h"
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#include "link.h"
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+
#include "../dcn20/dcn20_hwseq.h"
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#define DC_LOGGER_INIT(logger)
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···
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}
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return is_seamless;
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+
}
1680
+
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+
void dcn32_prepare_bandwidth(struct dc *dc,
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+
struct dc_state *context)
1683
+
{
1684
+
bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1685
+
/* Any transition into an FPO config should disable MCLK switching first to avoid
1686
+
* driver and FW P-State synchronization issues.
1687
+
*/
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+
if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1689
+
dc->optimized_required = true;
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+
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1691
+
}
1692
+
1693
+
if (dc->clk_mgr->dc_mode_softmax_enabled)
1694
+
if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
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+
context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1696
+
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
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+
1698
+
dcn20_prepare_bandwidth(dc, context);
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+
1700
+
if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1701
+
dc_dmub_srv_p_state_delegate(dc, false, context);
1702
+
1703
+
if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1704
+
/* After disabling P-State, restore the original value to ensure we get the correct P-State
1705
+
* on the next optimize.
1706
+
*/
1707
+
context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
1708
+
}
1680
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}