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dt-bindings: display: msm: document DSI controller and phy on QCS8300
Document DSI controller and phy on QCS8300 platform.
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696787/
Link: https://lore.kernel.org/r/20260104134442.732876-4-quic_amakhija@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Ayushi Makhija
and committed by
Dmitry Baryshkov
f5aa414e
c42973f9
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Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
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Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
···
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contains:
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const: qcom,qcs8300-dp
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,qcs8300-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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-
const: qcom,qcs8300-edp-phy
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enum:
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- qcom,qcs8300-dsi-phy-5nm
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- qcom,qcs8300-edp-phy
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required:
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- compatible
···
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
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#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
···
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remote-endpoint = <&mdss_dp0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
···
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required-opps = <&rpmhpd_opp_turbo_l1>;
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,qcs8300-dsi-ctrl",
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"qcom,sa8775p-dsi-ctrl",
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"qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
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phys = <&mdss_dsi0_phy>;
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operating-points-v2 = <&dsi0_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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vdda-supply = <&vreg_l5a>;
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss0_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss0_dsi0_out: endpoint { };
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};
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};
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dsi0_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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mdss_dsi0_phy: phy@ae94400 {
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compatible = "qcom,qcs8300-dsi-phy-5nm",
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"qcom,sa8775p-dsi-phy-5nm";
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reg = <0x0ae94400 0x200>,
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<0x0ae94600 0x280>,
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<0x0ae94900 0x27c>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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vdds-supply = <&vreg_l4a>;
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};
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mdss_dp0_phy: phy@aec2a00 {