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dt-bindings: display: msm: document DSI controller and phy on QCS8300

Document DSI controller and phy on QCS8300 platform.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696787/
Link: https://lore.kernel.org/r/20260104134442.732876-4-quic_amakhija@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Ayushi Makhija and committed by
Dmitry Baryshkov
f5aa414e c42973f9

+101 -1
+101 -1
Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
··· 53 53 contains: 54 54 const: qcom,qcs8300-dp 55 55 56 + "^dsi@[0-9a-f]+$": 57 + type: object 58 + additionalProperties: true 59 + properties: 60 + compatible: 61 + contains: 62 + const: qcom,qcs8300-dsi-ctrl 63 + 56 64 "^phy@[0-9a-f]+$": 57 65 type: object 58 66 additionalProperties: true 59 67 properties: 60 68 compatible: 61 69 contains: 62 - const: qcom,qcs8300-edp-phy 70 + enum: 71 + - qcom,qcs8300-dsi-phy-5nm 72 + - qcom,qcs8300-edp-phy 63 73 64 74 required: 65 75 - compatible ··· 81 71 #include <dt-bindings/interconnect/qcom,icc.h> 82 72 #include <dt-bindings/interrupt-controller/arm-gic.h> 83 73 #include <dt-bindings/clock/qcom,qcs8300-gcc.h> 74 + #include <dt-bindings/clock/qcom,rpmh.h> 84 75 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 85 76 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 86 77 #include <dt-bindings/power/qcom,rpmhpd.h> ··· 153 142 remote-endpoint = <&mdss_dp0_in>; 154 143 }; 155 144 }; 145 + 146 + port@1 { 147 + reg = <1>; 148 + dpu_intf1_out: endpoint { 149 + remote-endpoint = <&mdss_dsi0_in>; 150 + }; 151 + }; 156 152 }; 157 153 158 154 mdp_opp_table: opp-table { ··· 185 167 required-opps = <&rpmhpd_opp_turbo_l1>; 186 168 }; 187 169 }; 170 + }; 171 + 172 + dsi@ae94000 { 173 + compatible = "qcom,qcs8300-dsi-ctrl", 174 + "qcom,sa8775p-dsi-ctrl", 175 + "qcom,mdss-dsi-ctrl"; 176 + reg = <0x0ae94000 0x400>; 177 + reg-names = "dsi_ctrl"; 178 + 179 + interrupt-parent = <&mdss>; 180 + interrupts = <4>; 181 + 182 + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, 183 + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 184 + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, 185 + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, 186 + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 187 + <&gcc GCC_DISP_HF_AXI_CLK>; 188 + clock-names = "byte", 189 + "byte_intf", 190 + "pixel", 191 + "core", 192 + "iface", 193 + "bus"; 194 + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 195 + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 196 + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 197 + phys = <&mdss_dsi0_phy>; 198 + 199 + operating-points-v2 = <&dsi0_opp_table>; 200 + power-domains = <&rpmhpd RPMHPD_MMCX>; 201 + 202 + vdda-supply = <&vreg_l5a>; 203 + 204 + #address-cells = <1>; 205 + #size-cells = <0>; 206 + 207 + ports { 208 + #address-cells = <1>; 209 + #size-cells = <0>; 210 + 211 + port@0 { 212 + reg = <0>; 213 + mdss0_dsi0_in: endpoint { 214 + remote-endpoint = <&dpu_intf1_out>; 215 + }; 216 + }; 217 + 218 + port@1 { 219 + reg = <1>; 220 + mdss0_dsi0_out: endpoint { }; 221 + }; 222 + }; 223 + 224 + dsi0_opp_table: opp-table { 225 + compatible = "operating-points-v2"; 226 + 227 + opp-358000000 { 228 + opp-hz = /bits/ 64 <358000000>; 229 + required-opps = <&rpmhpd_opp_svs_l1>; 230 + }; 231 + }; 232 + }; 233 + 234 + mdss_dsi0_phy: phy@ae94400 { 235 + compatible = "qcom,qcs8300-dsi-phy-5nm", 236 + "qcom,sa8775p-dsi-phy-5nm"; 237 + reg = <0x0ae94400 0x200>, 238 + <0x0ae94600 0x280>, 239 + <0x0ae94900 0x27c>; 240 + reg-names = "dsi_phy", 241 + "dsi_phy_lane", 242 + "dsi_pll"; 243 + 244 + #clock-cells = <1>; 245 + #phy-cells = <0>; 246 + 247 + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 248 + <&rpmhcc RPMH_CXO_CLK>; 249 + clock-names = "iface", "ref"; 250 + 251 + vdds-supply = <&vreg_l4a>; 188 252 }; 189 253 190 254 mdss_dp0_phy: phy@aec2a00 {