tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'for-linus' of git://github.com/realmz/blackfin-linux

Pull blackfin updates from Steven Miao.

* tag 'for-linus' of git://github.com/realmz/blackfin-linux:
bfin cache: dcplb map: add 16M dcplb map for BF60x
blackfin: smp: fix smp build after drop asm/system.h
blackfin: fix bootup core clock and system clock display
Platform Nand: Set the GPIO for NAND read as input
blackfin: rename vmImage to uImage after we move to buildroot
blackfin: twi: Remove bogus #endif
bf609: rsi: Add bf609 rsi MMR macro and board platform data.
blackfin: dmc: Improve DDR2 write through in DMC effict controller.

Linus Torvalds f5b8fcb4 a1f0bccc

+101 -24
+3 -3
arch/blackfin/Makefile
··· 141 141 142 142 INSTALL_PATH ?= /tftpboot 143 143 boot := arch/$(ARCH)/boot 144 - BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip 144 + BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip 145 145 PHONY += $(BOOT_TARGETS) install 146 - KBUILD_IMAGE := $(boot)/vmImage 146 + KBUILD_IMAGE := $(boot)/uImage 147 147 148 - all: vmImage 148 + all: uImage 149 149 150 150 $(BOOT_TARGETS): vmlinux 151 151 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+8 -8
arch/blackfin/boot/Makefile
··· 6 6 # for more details. 7 7 # 8 8 9 - targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip 9 + targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip 10 10 extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip 11 11 12 12 ifeq ($(CONFIG_RAMKERNEL),y) ··· 39 39 $(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE 40 40 $(call if_changed,mk_bin_xip) 41 41 42 - $(obj)/vmImage.bin: $(obj)/vmlinux.bin 42 + $(obj)/uImage.bin: $(obj)/vmlinux.bin 43 43 $(call if_changed,uimage,none) 44 44 45 - $(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2 45 + $(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 46 46 $(call if_changed,uimage,bzip2) 47 47 48 - $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz 48 + $(obj)/uImage.gz: $(obj)/vmlinux.bin.gz 49 49 $(call if_changed,uimage,gzip) 50 50 51 - $(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma 51 + $(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma 52 52 $(call if_changed,uimage,lzma) 53 53 54 - $(obj)/vmImage.lzo: $(obj)/vmlinux.bin.lzo 54 + $(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo 55 55 $(call if_changed,uimage,lzo) 56 56 57 - $(obj)/vmImage.xip: $(obj)/vmlinux.bin.xip 57 + $(obj)/uImage.xip: $(obj)/vmlinux.bin.xip 58 58 $(call if_changed,uimage,none) 59 59 60 60 suffix-y := bin ··· 64 64 suffix-$(CONFIG_KERNEL_LZO) := lzo 65 65 suffix-$(CONFIG_ROMKERNEL) := xip 66 66 67 - $(obj)/vmImage: $(obj)/vmImage.$(suffix-y) 67 + $(obj)/uImage: $(obj)/uImage.$(suffix-y) 68 68 @ln -sf $(notdir $<) $@ 69 69 70 70 install:
+2
arch/blackfin/include/asm/atomic.h
··· 11 11 12 12 #ifdef CONFIG_SMP 13 13 14 + #include <asm/barrier.h> 14 15 #include <linux/linkage.h> 16 + #include <linux/types.h> 15 17 16 18 asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); 17 19 asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value);
+29 -2
arch/blackfin/include/asm/bfin_sdh.h
··· 24 24 #define CMD_INT_E (1 << 8) /* Command Interrupt */ 25 25 #define CMD_PEND_E (1 << 9) /* Command Pending */ 26 26 #define CMD_E (1 << 10) /* Command Enable */ 27 + #ifdef RSI_BLKSZ 28 + #define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */ 29 + #define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */ 30 + #endif 27 31 28 32 /* SDH_PWR_CTL bitmasks */ 33 + #ifndef RSI_BLKSZ 29 34 #define PWR_ON 0x3 /* Power On */ 30 35 #define SD_CMD_OD (1 << 6) /* Open Drain Output */ 31 36 #define ROD_CTL (1 << 7) /* Rod Control */ 37 + #endif 32 38 33 39 /* SDH_CLK_CTL bitmasks */ 34 40 #define CLKDIV 0xff /* MC_CLK Divisor */ 35 41 #define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ 36 42 #define PWR_SV_E (1 << 9) /* Power Save Enable */ 37 43 #define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ 38 - #define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */ 44 + #define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */ 45 + #define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */ 46 + #define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */ 47 + #define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */ 39 48 40 49 /* SDH_RESP_CMD bitmasks */ 41 50 #define RESP_CMD 0x3f /* Response Command */ ··· 54 45 #define DTX_DIR (1 << 1) /* Data Transfer Direction */ 55 46 #define DTX_MODE (1 << 2) /* Data Transfer Mode */ 56 47 #define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */ 48 + #ifndef RSI_BLKSZ 57 49 #define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ 50 + #else 51 + 52 + /* Bit masks for SDH_BLK_SIZE */ 53 + #define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */ 54 + #endif 58 55 59 56 /* SDH_STATUS bitmasks */ 60 57 #define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */ ··· 129 114 /* SDH_E_STATUS bitmasks */ 130 115 #define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ 131 116 #define SD_CARD_DET (1 << 4) /* SD Card Detect */ 117 + #define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */ 118 + #define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */ 119 + #define SD_CARD_READY (1 << 17) /* Card Ready */ 132 120 133 121 /* SDH_E_MASK bitmasks */ 134 122 #define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ 135 - #define SCD_MSK (1 << 6) /* Mask Card Detect */ 123 + #define SCD_MSK (1 << 4) /* Mask Card Detect */ 124 + #define CARD_READY_MSK (1 << 16) /* Mask Card Ready */ 136 125 137 126 /* SDH_CFG bitmasks */ 138 127 #define CLKS_EN (1 << 0) /* Clocks Enable */ ··· 145 126 #define SD_RST (1 << 4) /* SDMMC Reset */ 146 127 #define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ 147 128 #define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ 129 + #ifndef RSI_BLKSZ 148 130 #define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ 131 + #else 132 + #define PWR_ON 0x600 /* Power On */ 133 + #define SD_CMD_OD (1 << 11) /* Open Drain Output */ 134 + #define BOOT_EN (1 << 12) /* Boot Enable */ 135 + #define BOOT_MODE (1 << 13) /* Alternate Boot Mode */ 136 + #define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */ 137 + #endif 149 138 150 139 /* SDH_RD_WAIT_EN bitmasks */ 151 140 #define RWR (1 << 0) /* Read Wait Request */
+1
arch/blackfin/include/asm/bitops.h
··· 41 41 #include <asm-generic/bitops/non-atomic.h> 42 42 #else 43 43 44 + #include <asm/barrier.h> 44 45 #include <asm/byteorder.h> /* swab32 */ 45 46 #include <linux/linkage.h> 46 47
+2
arch/blackfin/include/asm/def_LPBlackfin.h
··· 622 622 #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 623 623 #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 624 624 #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ 625 + #ifdef CONFIG_BF60x 625 626 #define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ 626 627 #define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ 627 628 #define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ 628 629 #define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ 630 + #endif 629 631 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not 630 632 * mapped to L1 631 633 */
+9
arch/blackfin/include/asm/mem_init.h
··· 335 335 struct ddr_config { 336 336 u32 ddr_clk; 337 337 u32 dmc_ddrctl; 338 + u32 dmc_effctl; 338 339 u32 dmc_ddrcfg; 339 340 u32 dmc_ddrtr0; 340 341 u32 dmc_ddrtr1; ··· 349 348 [0] = { 350 349 .ddr_clk = 125, 351 350 .dmc_ddrctl = 0x00000904, 351 + .dmc_effctl = 0x004400C0, 352 352 .dmc_ddrcfg = 0x00000422, 353 353 .dmc_ddrtr0 = 0x20705212, 354 354 .dmc_ddrtr1 = 0x201003CF, ··· 360 358 [1] = { 361 359 .ddr_clk = 133, 362 360 .dmc_ddrctl = 0x00000904, 361 + .dmc_effctl = 0x004400C0, 363 362 .dmc_ddrcfg = 0x00000422, 364 363 .dmc_ddrtr0 = 0x20806313, 365 364 .dmc_ddrtr1 = 0x2013040D, ··· 371 368 [2] = { 372 369 .ddr_clk = 150, 373 370 .dmc_ddrctl = 0x00000904, 371 + .dmc_effctl = 0x004400C0, 374 372 .dmc_ddrcfg = 0x00000422, 375 373 .dmc_ddrtr0 = 0x20A07323, 376 374 .dmc_ddrtr1 = 0x20160492, ··· 382 378 [3] = { 383 379 .ddr_clk = 166, 384 380 .dmc_ddrctl = 0x00000904, 381 + .dmc_effctl = 0x004400C0, 385 382 .dmc_ddrcfg = 0x00000422, 386 383 .dmc_ddrtr0 = 0x20A07323, 387 384 .dmc_ddrtr1 = 0x2016050E, ··· 393 388 [4] = { 394 389 .ddr_clk = 200, 395 390 .dmc_ddrctl = 0x00000904, 391 + .dmc_effctl = 0x004400C0, 396 392 .dmc_ddrcfg = 0x00000422, 397 393 .dmc_ddrtr0 = 0x20a07323, 398 394 .dmc_ddrtr1 = 0x2016050f, ··· 404 398 [5] = { 405 399 .ddr_clk = 225, 406 400 .dmc_ddrctl = 0x00000904, 401 + .dmc_effctl = 0x004400C0, 407 402 .dmc_ddrcfg = 0x00000422, 408 403 .dmc_ddrtr0 = 0x20E0A424, 409 404 .dmc_ddrtr1 = 0x302006DB, ··· 415 408 [6] = { 416 409 .ddr_clk = 250, 417 410 .dmc_ddrctl = 0x00000904, 411 + .dmc_effctl = 0x004400C0, 418 412 .dmc_ddrcfg = 0x00000422, 419 413 .dmc_ddrtr0 = 0x20E0A424, 420 414 .dmc_ddrtr1 = 0x3020079E, ··· 477 469 bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); 478 470 bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); 479 471 bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); 472 + bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl); 480 473 bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); 481 474 break; 482 475 }
+13 -3
arch/blackfin/kernel/cplb-nompu/cplbinit.c
··· 30 30 { 31 31 int i_d, i_i; 32 32 unsigned long addr; 33 + unsigned long cplb_pageflags, cplb_pagesize; 33 34 34 35 struct cplb_entry *d_tbl = dcplb_tbl[cpu]; 35 36 struct cplb_entry *i_tbl = icplb_tbl[cpu]; ··· 50 49 /* Cover kernel memory with 4M pages. */ 51 50 addr = 0; 52 51 53 - for (; addr < memory_start; addr += 4 * 1024 * 1024) { 52 + #ifdef PAGE_SIZE_16MB 53 + cplb_pageflags = PAGE_SIZE_16MB; 54 + cplb_pagesize = SIZE_16M; 55 + #else 56 + cplb_pageflags = PAGE_SIZE_4MB; 57 + cplb_pagesize = SIZE_4M; 58 + #endif 59 + 60 + 61 + for (; addr < memory_start; addr += cplb_pagesize) { 54 62 d_tbl[i_d].addr = addr; 55 - d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; 63 + d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags; 56 64 i_tbl[i_i].addr = addr; 57 - i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; 65 + i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags; 58 66 } 59 67 60 68 #ifdef CONFIG_ROMKERNEL
+23 -4
arch/blackfin/kernel/cplb-nompu/cplbmgr.c
··· 145 145 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); 146 146 int status = bfin_read_DCPLB_STATUS(); 147 147 int idx; 148 - unsigned long d_data, base, addr1, eaddr; 148 + unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags; 149 149 150 150 nr_dcplb_miss[cpu]++; 151 151 if (unlikely(status & FAULT_USERSUPV)) ··· 167 167 if (unlikely(d_data == 0)) 168 168 return CPLB_NO_ADDR_MATCH; 169 169 170 - addr1 = addr & ~(SIZE_4M - 1); 171 170 addr &= ~(SIZE_1M - 1); 172 171 d_data |= PAGE_SIZE_1MB; 173 - if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) { 172 + 173 + /* BF60x support large than 4M CPLB page size */ 174 + #ifdef PAGE_SIZE_16MB 175 + cplb_pageflags = PAGE_SIZE_16MB; 176 + cplb_pagesize = SIZE_16M; 177 + #else 178 + cplb_pageflags = PAGE_SIZE_4MB; 179 + cplb_pagesize = SIZE_4M; 180 + #endif 181 + 182 + find_pagesize: 183 + addr1 = addr & ~(cplb_pagesize - 1); 184 + if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) { 174 185 /* 175 186 * This works because 176 187 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB. 177 188 */ 178 - d_data |= PAGE_SIZE_4MB; 189 + d_data |= cplb_pageflags; 179 190 addr = addr1; 191 + goto found_pagesize; 192 + } else { 193 + if (cplb_pagesize > SIZE_4M) { 194 + cplb_pageflags = PAGE_SIZE_4MB; 195 + cplb_pagesize = SIZE_4M; 196 + goto find_pagesize; 197 + } 180 198 } 181 199 200 + found_pagesize: 182 201 #ifdef CONFIG_BF60x 183 202 if ((addr >= ASYNC_BANK0_BASE) 184 203 && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
+7 -2
arch/blackfin/kernel/cplbinfo.c
··· 17 17 #include <asm/cplbinit.h> 18 18 #include <asm/blackfin.h> 19 19 20 - static char const page_strtbl[][3] = { "1K", "4K", "1M", "4M" }; 21 - #define page(flags) (((flags) & 0x30000) >> 16) 20 + static char const page_strtbl[][4] = { 21 + "1K", "4K", "1M", "4M", 22 + #ifdef CONFIG_BF60x 23 + "16K", "64K", "16M", "64M", 24 + #endif 25 + }; 26 + #define page(flags) (((flags) & 0x70000) >> 16) 22 27 #define strpage(flags) page_strtbl[page(flags)] 23 28 24 29 struct cplbinfo_data {
+1 -1
arch/blackfin/kernel/setup.c
··· 1314 1314 seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid()); 1315 1315 } 1316 1316 1317 - seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", 1317 + seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n", 1318 1318 cclk/1000000, cclk%1000000, 1319 1319 sclk/1000000, sclk%1000000); 1320 1320 seq_printf(m, "bogomips\t: %lu.%02lu\n"
+1
arch/blackfin/mach-bf537/boards/stamp.c
··· 455 455 static void bfin_plat_nand_init(void) 456 456 { 457 457 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); 458 + gpio_direction_input(BFIN_NAND_PLAT_READY); 458 459 } 459 460 #else 460 461 static void bfin_plat_nand_init(void) {}
-1
arch/blackfin/mach-bf538/boards/ezkit.c
··· 764 764 .num_resources = ARRAY_SIZE(bfin_twi1_resource), 765 765 .resource = bfin_twi1_resource, 766 766 }; 767 - #endif /* CONFIG_BF542 */ 768 767 #endif /* CONFIG_I2C_BLACKFIN_TWI */ 769 768 770 769 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+2
arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
··· 312 312 #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) 313 313 #define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) 314 314 #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) 315 + #define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL) 316 + #define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val) 315 317 #define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) 316 318 #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) 317 319 #define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)