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Merge branch 'net-dsa-b53-add-support-for-bcm5389-97-98-and-bcm63xx-arl-formats'

Jonas Gorski says:

====================
net: dsa: b53: add support for BCM5389/97/98 and BCM63XX ARL formats

Currently b53 assumes that all switches apart from BCM5325/5365 use the
same ARL formats, but there are actually multiple formats in use.

Older switches use a format apparently introduced with BCM5387/BCM5389,
while newer chips use a format apparently introduced with BCM5395.

Note that these numbers are not linear, BCM5397/BCM5398 use the older
format.

In addition to that the switches integrated into BCM63XX SoCs use their
own format. While accessing these normal read/write ARL entries are the
same format as BCM5389 one, the search format is different.

So in order to support all these different format, split all code
accessing these entries into chip-family specific functions, and collect
them in appropriate arl ops structs to keep the code cleaner.

Sent as net-next since the ARL accesses have never worked before, and
the extensive refactoring might be too much to warrant a fix.
====================

Link: https://patch.msgid.link/20251107080749.26936-1-jonas.gorski@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski f5d8ec83 7fc2bf8d

+320 -105
+227 -105
drivers/net/dsa/b53/b53_common.c
··· 1850 1850 return b53_arl_op_wait(dev); 1851 1851 } 1852 1852 1853 - static int b53_arl_read(struct b53_device *dev, u64 mac, 1853 + static void b53_arl_read_entry_25(struct b53_device *dev, 1854 + struct b53_arl_entry *ent, u8 idx) 1855 + { 1856 + u64 mac_vid; 1857 + 1858 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1859 + &mac_vid); 1860 + b53_arl_to_entry_25(ent, mac_vid); 1861 + } 1862 + 1863 + static void b53_arl_write_entry_25(struct b53_device *dev, 1864 + const struct b53_arl_entry *ent, u8 idx) 1865 + { 1866 + u64 mac_vid; 1867 + 1868 + b53_arl_from_entry_25(&mac_vid, ent); 1869 + b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1870 + mac_vid); 1871 + } 1872 + 1873 + static void b53_arl_read_entry_89(struct b53_device *dev, 1874 + struct b53_arl_entry *ent, u8 idx) 1875 + { 1876 + u64 mac_vid; 1877 + u16 fwd_entry; 1878 + 1879 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1880 + &mac_vid); 1881 + b53_read16(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry); 1882 + b53_arl_to_entry_89(ent, mac_vid, fwd_entry); 1883 + } 1884 + 1885 + static void b53_arl_write_entry_89(struct b53_device *dev, 1886 + const struct b53_arl_entry *ent, u8 idx) 1887 + { 1888 + u32 fwd_entry; 1889 + u64 mac_vid; 1890 + 1891 + b53_arl_from_entry_89(&mac_vid, &fwd_entry, ent); 1892 + b53_write64(dev, B53_ARLIO_PAGE, 1893 + B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1894 + b53_write16(dev, B53_ARLIO_PAGE, 1895 + B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1896 + } 1897 + 1898 + static void b53_arl_read_entry_95(struct b53_device *dev, 1899 + struct b53_arl_entry *ent, u8 idx) 1900 + { 1901 + u32 fwd_entry; 1902 + u64 mac_vid; 1903 + 1904 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1905 + &mac_vid); 1906 + b53_read32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry); 1907 + b53_arl_to_entry(ent, mac_vid, fwd_entry); 1908 + } 1909 + 1910 + static void b53_arl_write_entry_95(struct b53_device *dev, 1911 + const struct b53_arl_entry *ent, u8 idx) 1912 + { 1913 + u32 fwd_entry; 1914 + u64 mac_vid; 1915 + 1916 + b53_arl_from_entry(&mac_vid, &fwd_entry, ent); 1917 + b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1918 + mac_vid); 1919 + b53_write32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), 1920 + fwd_entry); 1921 + } 1922 + 1923 + static int b53_arl_read(struct b53_device *dev, const u8 *mac, 1854 1924 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1855 1925 { 1856 1926 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); ··· 1935 1865 1936 1866 /* Read the bins */ 1937 1867 for (i = 0; i < dev->num_arl_bins; i++) { 1938 - u64 mac_vid; 1939 - u32 fwd_entry; 1868 + b53_arl_read_entry(dev, ent, i); 1940 1869 1941 - b53_read64(dev, B53_ARLIO_PAGE, 1942 - B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1943 - b53_read32(dev, B53_ARLIO_PAGE, 1944 - B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1945 - b53_arl_to_entry(ent, mac_vid, fwd_entry); 1946 - 1947 - if (!(fwd_entry & ARLTBL_VALID)) { 1870 + if (!ent->is_valid) { 1948 1871 set_bit(i, free_bins); 1949 1872 continue; 1950 1873 } 1951 - if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1874 + if (!ether_addr_equal(ent->mac, mac)) 1952 1875 continue; 1953 - if (dev->vlan_enabled && 1954 - ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1955 - continue; 1956 - *idx = i; 1957 - return 0; 1958 - } 1959 - 1960 - *idx = find_first_bit(free_bins, dev->num_arl_bins); 1961 - return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1962 - } 1963 - 1964 - static int b53_arl_read_25(struct b53_device *dev, u64 mac, 1965 - u16 vid, struct b53_arl_entry *ent, u8 *idx) 1966 - { 1967 - DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1968 - unsigned int i; 1969 - int ret; 1970 - 1971 - ret = b53_arl_op_wait(dev); 1972 - if (ret) 1973 - return ret; 1974 - 1975 - bitmap_zero(free_bins, dev->num_arl_bins); 1976 - 1977 - /* Read the bins */ 1978 - for (i = 0; i < dev->num_arl_bins; i++) { 1979 - u64 mac_vid; 1980 - 1981 - b53_read64(dev, B53_ARLIO_PAGE, 1982 - B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1983 - 1984 - b53_arl_to_entry_25(ent, mac_vid); 1985 - 1986 - if (!(mac_vid & ARLTBL_VALID_25)) { 1987 - set_bit(i, free_bins); 1988 - continue; 1989 - } 1990 - if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1991 - continue; 1992 - if (dev->vlan_enabled && 1993 - ((mac_vid >> ARLTBL_VID_S_65) & ARLTBL_VID_MASK_25) != vid) 1876 + if (dev->vlan_enabled && ent->vid != vid) 1994 1877 continue; 1995 1878 *idx = i; 1996 1879 return 0; ··· 1957 1934 const unsigned char *addr, u16 vid, bool is_valid) 1958 1935 { 1959 1936 struct b53_arl_entry ent; 1960 - u32 fwd_entry; 1961 - u64 mac, mac_vid = 0; 1962 1937 u8 idx = 0; 1938 + u64 mac; 1963 1939 int ret; 1964 1940 1965 1941 /* Convert the array into a 64-bit MAC */ ··· 1974 1952 if (ret) 1975 1953 return ret; 1976 1954 1977 - if (is5325(dev) || is5365(dev)) 1978 - ret = b53_arl_read_25(dev, mac, vid, &ent, &idx); 1979 - else 1980 - ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1955 + ret = b53_arl_read(dev, addr, vid, &ent, &idx); 1981 1956 1982 1957 /* If this is a read, just finish now */ 1983 1958 if (op) ··· 1991 1972 /* We could not find a matching MAC, so reset to a new entry */ 1992 1973 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1993 1974 addr, vid, idx); 1994 - fwd_entry = 0; 1995 1975 break; 1996 1976 default: 1997 1977 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", ··· 2017 1999 ent.is_static = true; 2018 2000 ent.is_age = false; 2019 2001 memcpy(ent.mac, addr, ETH_ALEN); 2020 - if (is5325(dev) || is5365(dev)) 2021 - b53_arl_from_entry_25(&mac_vid, &ent); 2022 - else 2023 - b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 2024 - 2025 - b53_write64(dev, B53_ARLIO_PAGE, 2026 - B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 2027 - 2028 - if (!is5325(dev) && !is5365(dev)) 2029 - b53_write32(dev, B53_ARLIO_PAGE, 2030 - B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 2002 + b53_arl_write_entry(dev, &ent, idx); 2031 2003 2032 2004 return b53_arl_rw_op(dev, 0); 2033 2005 } ··· 2052 2044 } 2053 2045 EXPORT_SYMBOL(b53_fdb_del); 2054 2046 2055 - static int b53_arl_search_wait(struct b53_device *dev) 2047 + static void b53_read_arl_srch_ctl(struct b53_device *dev, u8 *val) 2056 2048 { 2057 - unsigned int timeout = 1000; 2058 - u8 reg, offset; 2049 + u8 offset; 2059 2050 2060 2051 if (is5325(dev) || is5365(dev)) 2061 2052 offset = B53_ARL_SRCH_CTL_25; 2053 + else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) || 2054 + is63xx(dev)) 2055 + offset = B53_ARL_SRCH_CTL_89; 2062 2056 else 2063 2057 offset = B53_ARL_SRCH_CTL; 2064 2058 2059 + if (is63xx(dev)) { 2060 + u16 val16; 2061 + 2062 + b53_read16(dev, B53_ARLIO_PAGE, offset, &val16); 2063 + *val = val16 & 0xff; 2064 + } else { 2065 + b53_read8(dev, B53_ARLIO_PAGE, offset, val); 2066 + } 2067 + } 2068 + 2069 + static void b53_write_arl_srch_ctl(struct b53_device *dev, u8 val) 2070 + { 2071 + u8 offset; 2072 + 2073 + if (is5325(dev) || is5365(dev)) 2074 + offset = B53_ARL_SRCH_CTL_25; 2075 + else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) || 2076 + is63xx(dev)) 2077 + offset = B53_ARL_SRCH_CTL_89; 2078 + else 2079 + offset = B53_ARL_SRCH_CTL; 2080 + 2081 + if (is63xx(dev)) 2082 + b53_write16(dev, B53_ARLIO_PAGE, offset, val); 2083 + else 2084 + b53_write8(dev, B53_ARLIO_PAGE, offset, val); 2085 + } 2086 + 2087 + static int b53_arl_search_wait(struct b53_device *dev) 2088 + { 2089 + unsigned int timeout = 1000; 2090 + u8 reg; 2091 + 2065 2092 do { 2066 - b53_read8(dev, B53_ARLIO_PAGE, offset, &reg); 2093 + b53_read_arl_srch_ctl(dev, &reg); 2067 2094 if (!(reg & ARL_SRCH_STDN)) 2068 2095 return -ENOENT; 2069 2096 ··· 2111 2068 return -ETIMEDOUT; 2112 2069 } 2113 2070 2114 - static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 2115 - struct b53_arl_entry *ent) 2071 + static void b53_arl_search_read_25(struct b53_device *dev, u8 idx, 2072 + struct b53_arl_entry *ent) 2116 2073 { 2117 2074 u64 mac_vid; 2118 2075 2119 - if (is5325(dev)) { 2120 - b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25, 2121 - &mac_vid); 2122 - b53_arl_to_entry_25(ent, mac_vid); 2123 - } else if (is5365(dev)) { 2124 - b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_65, 2125 - &mac_vid); 2126 - b53_arl_to_entry_25(ent, mac_vid); 2127 - } else { 2128 - u32 fwd_entry; 2076 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25, 2077 + &mac_vid); 2078 + b53_arl_to_entry_25(ent, mac_vid); 2079 + } 2129 2080 2130 - b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_MACVID(idx), 2131 - &mac_vid); 2132 - b53_read32(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL(idx), 2133 - &fwd_entry); 2134 - b53_arl_to_entry(ent, mac_vid, fwd_entry); 2135 - } 2081 + static void b53_arl_search_read_65(struct b53_device *dev, u8 idx, 2082 + struct b53_arl_entry *ent) 2083 + { 2084 + u64 mac_vid; 2085 + 2086 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_65, 2087 + &mac_vid); 2088 + b53_arl_to_entry_25(ent, mac_vid); 2089 + } 2090 + 2091 + static void b53_arl_search_read_89(struct b53_device *dev, u8 idx, 2092 + struct b53_arl_entry *ent) 2093 + { 2094 + u16 fwd_entry; 2095 + u64 mac_vid; 2096 + 2097 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_89, 2098 + &mac_vid); 2099 + b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_89, &fwd_entry); 2100 + b53_arl_to_entry_89(ent, mac_vid, fwd_entry); 2101 + } 2102 + 2103 + static void b53_arl_search_read_63xx(struct b53_device *dev, u8 idx, 2104 + struct b53_arl_entry *ent) 2105 + { 2106 + u16 fwd_entry; 2107 + u64 mac_vid; 2108 + 2109 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_63XX, 2110 + &mac_vid); 2111 + b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_63XX, &fwd_entry); 2112 + b53_arl_search_to_entry_63xx(ent, mac_vid, fwd_entry); 2113 + } 2114 + 2115 + static void b53_arl_search_read_95(struct b53_device *dev, u8 idx, 2116 + struct b53_arl_entry *ent) 2117 + { 2118 + u32 fwd_entry; 2119 + u64 mac_vid; 2120 + 2121 + b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_MACVID(idx), 2122 + &mac_vid); 2123 + b53_read32(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL(idx), 2124 + &fwd_entry); 2125 + b53_arl_to_entry(ent, mac_vid, fwd_entry); 2136 2126 } 2137 2127 2138 2128 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, ··· 2186 2110 unsigned int count = 0, results_per_hit = 1; 2187 2111 struct b53_device *priv = ds->priv; 2188 2112 struct b53_arl_entry results[2]; 2189 - u8 offset; 2190 2113 int ret; 2191 - u8 reg; 2192 2114 2193 2115 if (priv->num_arl_bins > 2) 2194 2116 results_per_hit = 2; 2195 2117 2196 2118 mutex_lock(&priv->arl_mutex); 2197 2119 2198 - if (is5325(priv) || is5365(priv)) 2199 - offset = B53_ARL_SRCH_CTL_25; 2200 - else 2201 - offset = B53_ARL_SRCH_CTL; 2202 - 2203 2120 /* Start search operation */ 2204 - reg = ARL_SRCH_STDN; 2205 - b53_write8(priv, B53_ARLIO_PAGE, offset, reg); 2121 + b53_write_arl_srch_ctl(priv, ARL_SRCH_STDN); 2206 2122 2207 2123 do { 2208 2124 ret = b53_arl_search_wait(priv); 2209 2125 if (ret) 2210 2126 break; 2211 2127 2212 - b53_arl_search_rd(priv, 0, &results[0]); 2128 + b53_arl_search_read(priv, 0, &results[0]); 2213 2129 ret = b53_fdb_copy(port, &results[0], cb, data); 2214 2130 if (ret) 2215 2131 break; 2216 2132 2217 2133 if (results_per_hit == 2) { 2218 - b53_arl_search_rd(priv, 1, &results[1]); 2134 + b53_arl_search_read(priv, 1, &results[1]); 2219 2135 ret = b53_fdb_copy(port, &results[1], cb, data); 2220 2136 if (ret) 2221 2137 break; ··· 2736 2668 .port_change_mtu = b53_change_mtu, 2737 2669 }; 2738 2670 2671 + static const struct b53_arl_ops b53_arl_ops_25 = { 2672 + .arl_read_entry = b53_arl_read_entry_25, 2673 + .arl_write_entry = b53_arl_write_entry_25, 2674 + .arl_search_read = b53_arl_search_read_25, 2675 + }; 2676 + 2677 + static const struct b53_arl_ops b53_arl_ops_65 = { 2678 + .arl_read_entry = b53_arl_read_entry_25, 2679 + .arl_write_entry = b53_arl_write_entry_25, 2680 + .arl_search_read = b53_arl_search_read_65, 2681 + }; 2682 + 2683 + static const struct b53_arl_ops b53_arl_ops_89 = { 2684 + .arl_read_entry = b53_arl_read_entry_89, 2685 + .arl_write_entry = b53_arl_write_entry_89, 2686 + .arl_search_read = b53_arl_search_read_89, 2687 + }; 2688 + 2689 + static const struct b53_arl_ops b53_arl_ops_63xx = { 2690 + .arl_read_entry = b53_arl_read_entry_89, 2691 + .arl_write_entry = b53_arl_write_entry_89, 2692 + .arl_search_read = b53_arl_search_read_63xx, 2693 + }; 2694 + 2695 + static const struct b53_arl_ops b53_arl_ops_95 = { 2696 + .arl_read_entry = b53_arl_read_entry_95, 2697 + .arl_write_entry = b53_arl_write_entry_95, 2698 + .arl_search_read = b53_arl_search_read_95, 2699 + }; 2700 + 2739 2701 struct b53_chip_data { 2740 2702 u32 chip_id; 2741 2703 const char *dev_name; ··· 2779 2681 u8 duplex_reg; 2780 2682 u8 jumbo_pm_reg; 2781 2683 u8 jumbo_size_reg; 2684 + const struct b53_arl_ops *arl_ops; 2782 2685 }; 2783 2686 2784 2687 #define B53_VTA_REGS \ ··· 2799 2700 .arl_buckets = 1024, 2800 2701 .imp_port = 5, 2801 2702 .duplex_reg = B53_DUPLEX_STAT_FE, 2703 + .arl_ops = &b53_arl_ops_25, 2802 2704 }, 2803 2705 { 2804 2706 .chip_id = BCM5365_DEVICE_ID, ··· 2810 2710 .arl_buckets = 1024, 2811 2711 .imp_port = 5, 2812 2712 .duplex_reg = B53_DUPLEX_STAT_FE, 2713 + .arl_ops = &b53_arl_ops_65, 2813 2714 }, 2814 2715 { 2815 2716 .chip_id = BCM5389_DEVICE_ID, ··· 2824 2723 .duplex_reg = B53_DUPLEX_STAT_GE, 2825 2724 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2826 2725 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2726 + .arl_ops = &b53_arl_ops_89, 2827 2727 }, 2828 2728 { 2829 2729 .chip_id = BCM5395_DEVICE_ID, ··· 2838 2736 .duplex_reg = B53_DUPLEX_STAT_GE, 2839 2737 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2840 2738 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2739 + .arl_ops = &b53_arl_ops_95, 2841 2740 }, 2842 2741 { 2843 2742 .chip_id = BCM5397_DEVICE_ID, ··· 2852 2749 .duplex_reg = B53_DUPLEX_STAT_GE, 2853 2750 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2854 2751 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2752 + .arl_ops = &b53_arl_ops_89, 2855 2753 }, 2856 2754 { 2857 2755 .chip_id = BCM5398_DEVICE_ID, ··· 2866 2762 .duplex_reg = B53_DUPLEX_STAT_GE, 2867 2763 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2868 2764 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2765 + .arl_ops = &b53_arl_ops_89, 2869 2766 }, 2870 2767 { 2871 2768 .chip_id = BCM53101_DEVICE_ID, ··· 2880 2775 .duplex_reg = B53_DUPLEX_STAT_GE, 2881 2776 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2882 2777 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2778 + .arl_ops = &b53_arl_ops_95, 2883 2779 }, 2884 2780 { 2885 2781 .chip_id = BCM53115_DEVICE_ID, ··· 2894 2788 .duplex_reg = B53_DUPLEX_STAT_GE, 2895 2789 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2896 2790 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2791 + .arl_ops = &b53_arl_ops_95, 2897 2792 }, 2898 2793 { 2899 2794 .chip_id = BCM53125_DEVICE_ID, ··· 2908 2801 .duplex_reg = B53_DUPLEX_STAT_GE, 2909 2802 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2910 2803 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2804 + .arl_ops = &b53_arl_ops_95, 2911 2805 }, 2912 2806 { 2913 2807 .chip_id = BCM53128_DEVICE_ID, ··· 2922 2814 .duplex_reg = B53_DUPLEX_STAT_GE, 2923 2815 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2924 2816 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2817 + .arl_ops = &b53_arl_ops_95, 2925 2818 }, 2926 2819 { 2927 2820 .chip_id = BCM63XX_DEVICE_ID, 2928 2821 .dev_name = "BCM63xx", 2929 2822 .vlans = 4096, 2930 2823 .enabled_ports = 0, /* pdata must provide them */ 2931 - .arl_bins = 4, 2932 - .arl_buckets = 1024, 2824 + .arl_bins = 1, 2825 + .arl_buckets = 4096, 2933 2826 .imp_port = 8, 2934 2827 .vta_regs = B53_VTA_REGS_63XX, 2935 2828 .duplex_reg = B53_DUPLEX_STAT_63XX, 2936 2829 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2937 2830 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2831 + .arl_ops = &b53_arl_ops_63xx, 2938 2832 }, 2939 2833 { 2940 2834 .chip_id = BCM53010_DEVICE_ID, ··· 2950 2840 .duplex_reg = B53_DUPLEX_STAT_GE, 2951 2841 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2952 2842 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2843 + .arl_ops = &b53_arl_ops_95, 2953 2844 }, 2954 2845 { 2955 2846 .chip_id = BCM53011_DEVICE_ID, ··· 2964 2853 .duplex_reg = B53_DUPLEX_STAT_GE, 2965 2854 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2966 2855 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2856 + .arl_ops = &b53_arl_ops_95, 2967 2857 }, 2968 2858 { 2969 2859 .chip_id = BCM53012_DEVICE_ID, ··· 2978 2866 .duplex_reg = B53_DUPLEX_STAT_GE, 2979 2867 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2980 2868 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2869 + .arl_ops = &b53_arl_ops_95, 2981 2870 }, 2982 2871 { 2983 2872 .chip_id = BCM53018_DEVICE_ID, ··· 2992 2879 .duplex_reg = B53_DUPLEX_STAT_GE, 2993 2880 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2994 2881 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2882 + .arl_ops = &b53_arl_ops_95, 2995 2883 }, 2996 2884 { 2997 2885 .chip_id = BCM53019_DEVICE_ID, ··· 3006 2892 .duplex_reg = B53_DUPLEX_STAT_GE, 3007 2893 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3008 2894 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2895 + .arl_ops = &b53_arl_ops_95, 3009 2896 }, 3010 2897 { 3011 2898 .chip_id = BCM58XX_DEVICE_ID, ··· 3020 2905 .duplex_reg = B53_DUPLEX_STAT_GE, 3021 2906 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3022 2907 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2908 + .arl_ops = &b53_arl_ops_95, 3023 2909 }, 3024 2910 { 3025 2911 .chip_id = BCM583XX_DEVICE_ID, ··· 3034 2918 .duplex_reg = B53_DUPLEX_STAT_GE, 3035 2919 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3036 2920 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2921 + .arl_ops = &b53_arl_ops_95, 3037 2922 }, 3038 2923 /* Starfighter 2 */ 3039 2924 { ··· 3049 2932 .duplex_reg = B53_DUPLEX_STAT_GE, 3050 2933 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3051 2934 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2935 + .arl_ops = &b53_arl_ops_95, 3052 2936 }, 3053 2937 { 3054 2938 .chip_id = BCM7445_DEVICE_ID, ··· 3063 2945 .duplex_reg = B53_DUPLEX_STAT_GE, 3064 2946 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3065 2947 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2948 + .arl_ops = &b53_arl_ops_95, 3066 2949 }, 3067 2950 { 3068 2951 .chip_id = BCM7278_DEVICE_ID, ··· 3077 2958 .duplex_reg = B53_DUPLEX_STAT_GE, 3078 2959 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3079 2960 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2961 + .arl_ops = &b53_arl_ops_95, 3080 2962 }, 3081 2963 { 3082 2964 .chip_id = BCM53134_DEVICE_ID, ··· 3092 2972 .duplex_reg = B53_DUPLEX_STAT_GE, 3093 2973 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3094 2974 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2975 + .arl_ops = &b53_arl_ops_95, 3095 2976 }, 3096 2977 }; 3097 2978 ··· 3121 3000 dev->num_vlans = chip->vlans; 3122 3001 dev->num_arl_bins = chip->arl_bins; 3123 3002 dev->num_arl_buckets = chip->arl_buckets; 3003 + dev->arl_ops = chip->arl_ops; 3124 3004 break; 3125 3005 } 3126 3006 }
+71
drivers/net/dsa/b53/b53_priv.h
··· 58 58 bool link_up); 59 59 }; 60 60 61 + struct b53_arl_entry; 62 + 63 + struct b53_arl_ops { 64 + void (*arl_read_entry)(struct b53_device *dev, 65 + struct b53_arl_entry *ent, u8 idx); 66 + void (*arl_write_entry)(struct b53_device *dev, 67 + const struct b53_arl_entry *ent, u8 idx); 68 + void (*arl_search_read)(struct b53_device *dev, u8 idx, 69 + struct b53_arl_entry *ent); 70 + }; 71 + 61 72 #define B53_INVALID_LANE 0xff 62 73 63 74 enum { ··· 138 127 struct mutex stats_mutex; 139 128 struct mutex arl_mutex; 140 129 const struct b53_io_ops *ops; 130 + const struct b53_arl_ops *arl_ops; 141 131 142 132 /* chip specific data */ 143 133 u32 chip_id; ··· 353 341 ent->vid = mac_vid >> ARLTBL_VID_S_65; 354 342 } 355 343 344 + static inline void b53_arl_to_entry_89(struct b53_arl_entry *ent, 345 + u64 mac_vid, u16 fwd_entry) 346 + { 347 + memset(ent, 0, sizeof(*ent)); 348 + ent->port = fwd_entry & ARLTBL_DATA_PORT_ID_MASK_89; 349 + ent->is_valid = !!(fwd_entry & ARLTBL_VALID_89); 350 + ent->is_age = !!(fwd_entry & ARLTBL_AGE_89); 351 + ent->is_static = !!(fwd_entry & ARLTBL_STATIC_89); 352 + u64_to_ether_addr(mac_vid, ent->mac); 353 + ent->vid = mac_vid >> ARLTBL_VID_S; 354 + } 355 + 356 356 static inline void b53_arl_from_entry(u64 *mac_vid, u32 *fwd_entry, 357 357 const struct b53_arl_entry *ent) 358 358 { ··· 393 369 *mac_vid |= ARLTBL_STATIC_25; 394 370 if (ent->is_age) 395 371 *mac_vid |= ARLTBL_AGE_25; 372 + } 373 + 374 + static inline void b53_arl_from_entry_89(u64 *mac_vid, u32 *fwd_entry, 375 + const struct b53_arl_entry *ent) 376 + { 377 + *mac_vid = ether_addr_to_u64(ent->mac); 378 + *mac_vid |= (u64)(ent->vid & ARLTBL_VID_MASK) << ARLTBL_VID_S; 379 + *fwd_entry = ent->port & ARLTBL_DATA_PORT_ID_MASK_89; 380 + if (ent->is_valid) 381 + *fwd_entry |= ARLTBL_VALID_89; 382 + if (ent->is_static) 383 + *fwd_entry |= ARLTBL_STATIC_89; 384 + if (ent->is_age) 385 + *fwd_entry |= ARLTBL_AGE_89; 386 + } 387 + 388 + static inline void b53_arl_search_to_entry_63xx(struct b53_arl_entry *ent, 389 + u64 mac_vid, u16 fwd_entry) 390 + { 391 + memset(ent, 0, sizeof(*ent)); 392 + u64_to_ether_addr(mac_vid, ent->mac); 393 + ent->vid = mac_vid >> ARLTBL_VID_S; 394 + 395 + ent->port = fwd_entry & ARL_SRST_PORT_ID_MASK_63XX; 396 + ent->port >>= 1; 397 + 398 + ent->is_age = !!(fwd_entry & ARL_SRST_AGE_63XX); 399 + ent->is_static = !!(fwd_entry & ARL_SRST_STATIC_63XX); 400 + ent->is_valid = 1; 401 + } 402 + 403 + static inline void b53_arl_read_entry(struct b53_device *dev, 404 + struct b53_arl_entry *ent, u8 idx) 405 + { 406 + dev->arl_ops->arl_read_entry(dev, ent, idx); 407 + } 408 + 409 + static inline void b53_arl_write_entry(struct b53_device *dev, 410 + const struct b53_arl_entry *ent, u8 idx) 411 + { 412 + dev->arl_ops->arl_write_entry(dev, ent, idx); 413 + } 414 + 415 + static inline void b53_arl_search_read(struct b53_device *dev, u8 idx, 416 + struct b53_arl_entry *ent) 417 + { 418 + dev->arl_ops->arl_search_read(dev, idx, ent); 396 419 } 397 420 398 421 #ifdef CONFIG_BCM47XX
+22
drivers/net/dsa/b53/b53_regs.h
··· 346 346 #define ARLTBL_STATIC BIT(15) 347 347 #define ARLTBL_VALID BIT(16) 348 348 349 + /* BCM5389 ARL Table Data Entry N Register format (16 bit) */ 350 + #define ARLTBL_DATA_PORT_ID_MASK_89 GENMASK(8, 0) 351 + #define ARLTBL_TC_MASK_89 GENMASK(12, 10) 352 + #define ARLTBL_AGE_89 BIT(13) 353 + #define ARLTBL_STATIC_89 BIT(14) 354 + #define ARLTBL_VALID_89 BIT(15) 355 + 349 356 /* Maximum number of bin entries in the ARL for all switches */ 350 357 #define B53_ARLTBL_MAX_BIN_ENTRIES 4 351 358 352 359 /* ARL Search Control Register (8 bit) */ 353 360 #define B53_ARL_SRCH_CTL 0x50 354 361 #define B53_ARL_SRCH_CTL_25 0x20 362 + #define B53_ARL_SRCH_CTL_89 0x30 355 363 #define ARL_SRCH_VLID BIT(0) 356 364 #define ARL_SRCH_STDN BIT(7) 357 365 ··· 367 359 #define B53_ARL_SRCH_ADDR 0x51 368 360 #define B53_ARL_SRCH_ADDR_25 0x22 369 361 #define B53_ARL_SRCH_ADDR_65 0x24 362 + #define B53_ARL_SRCH_ADDR_89 0x31 363 + #define B53_ARL_SRCH_ADDR_63XX 0x32 370 364 #define ARL_ADDR_MASK GENMASK(14, 0) 371 365 372 366 /* ARL Search MAC/VID Result (64 bit) */ 373 367 #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 368 + #define B53_ARL_SRCH_RSLT_MACVID_89 0x33 369 + #define B53_ARL_SRCH_RSLT_MACVID_63XX 0x34 374 370 375 371 /* Single register search result on 5325 */ 376 372 #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 ··· 384 372 /* ARL Search Data Result (32 bit) */ 385 373 #define B53_ARL_SRCH_RSTL_0 0x68 386 374 375 + /* BCM5389 ARL Search Data Result (16 bit) */ 376 + #define B53_ARL_SRCH_RSLT_89 0x3b 377 + 387 378 #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) 388 379 #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) 380 + 381 + /* 63XX ARL Search Data Result (16 bit) */ 382 + #define B53_ARL_SRCH_RSLT_63XX 0x3c 383 + #define ARL_SRST_PORT_ID_MASK_63XX GENMASK(9, 1) 384 + #define ARL_SRST_TC_MASK_63XX GENMASK(13, 11) 385 + #define ARL_SRST_AGE_63XX BIT(14) 386 + #define ARL_SRST_STATIC_63XX BIT(15) 389 387 390 388 /************************************************************************* 391 389 * IEEE 802.1X Registers