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Merge branch 'dp83tg720-reduce-link-recovery'
Oleksij Rempel says:
====================
dp83tg720: Reduce link recovery
This patch series improves the link recovery behavior of the TI
DP83TG720 PHY driver.
Previously, we introduced randomized reset delay logic to avoid reset
collisions in multi-PHY setups. While this approach was functional, it
had notable drawbacks: unpredictable behavior, longer and more variable
link recovery times, and overall higher complexity in link handling.
With this new approach, we replace the randomized delay with
deterministic, role-specific delays in the PHY reset logic. This enables
us to:
- Remove the redundant empirical 600 ms delay in read_status()
- Drop the random polling interval logic
- Introduce a clean, adaptive polling strategy with consistent
behavior and improved responsiveness
As a result, the PHY is now able to recover link reliably in under
1000_ms
====================
Link: https://patch.msgid.link/20250612104157.2262058-1-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+124
-57
+124
-57
drivers/net/phy/dp83tg720.c
+124
-57
drivers/net/phy/dp83tg720.c
···
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#include "open_alliance_helpers.h"
14
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/*
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+
* DP83TG720 PHY Limitations and Workarounds
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*
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* The DP83TG720 1000BASE-T1 PHY has several limitations that require
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* software-side mitigations. These workarounds are implemented throughout
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* this driver. This section documents the known issues and their corresponding
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* mitigation strategies.
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*
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* 1. Unreliable Link Detection and Synchronized Reset Deadlock
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* ------------------------------------------------------------
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* After a link loss or during link establishment, the DP83TG720 PHY may fail
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* to detect or report link status correctly. As of June 2025, no public
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* errata sheet for the DP83TG720 PHY documents this behavior.
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* The "DP83TC81x, DP83TG72x Software Implementation Guide" application note
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* (SNLA404, available at https://www.ti.com/lit/an/snla404/snla404.pdf)
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* recommends performing a soft restart if polling for a link fails to establish
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* a connection after 100ms. This procedure is adopted as the workaround for the
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* observed link detection issue.
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*
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* However, in point-to-point setups where both link partners use the same
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* driver (e.g. Linux on both sides), a synchronized reset pattern may emerge.
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* This leads to a deadlock, where both PHYs reset at the same time and
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* continuously miss each other during auto-negotiation.
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*
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* To address this, the reset procedure includes two components:
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*
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* - A **fixed minimum delay of 1ms** after a hardware reset. The datasheet
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* "DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY with SGMII and RGMII"
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* specifies this as the "Post reset stabilization-time prior to MDC preamble
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* for register access" (T6.2), ensuring the PHY is ready for MDIO
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* operations.
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*
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* - An **additional asymmetric delay**, empirically chosen based on
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* master/slave role. This reduces the risk of synchronized resets on both
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* link partners. Values are selected to avoid periodic overlap and ensure
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* the link is re-established within a few cycles.
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*
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* The functions that implement this logic are:
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* - dp83tg720_soft_reset()
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* - dp83tg720_get_next_update_time()
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*
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* 2. Polling-Based Link Detection and IRQ Support
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* -----------------------------------------------
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* Due to the PHY-specific limitation described in section 1, link-up events
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* cannot be reliably detected via interrupts on the DP83TG720. Therefore,
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* polling is required to detect transitions from link-down to link-up.
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*
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* While link-down events *can* be detected via IRQs on this PHY, this driver
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* currently does **not** implement interrupt support. As a result, all link
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* state changes must be detected using polling.
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*
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* Polling behavior:
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* - When the link is up: slow polling (e.g. 1s).
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* - When the link just went down: fast polling for a short time.
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* - When the link stays down: fallback to slow polling.
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*
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* This design balances responsiveness and CPU usage. It sacrifices fast link-up
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* times in cases where the link is expected to remain down for extended periods,
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* assuming that such systems do not require immediate reactivity.
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*/
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+
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/*
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* DP83TG720S_POLL_ACTIVE_LINK - Polling interval in milliseconds when the link
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* is active.
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* DP83TG720S_POLL_NO_LINK_MIN - Minimum polling interval in milliseconds when
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* the link is down.
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* DP83TG720S_POLL_NO_LINK_MAX - Maximum polling interval in milliseconds when
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* the link is down.
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* DP83TG720S_POLL_NO_LINK - Polling interval in milliseconds when the
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* link is down.
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* DP83TG720S_FAST_POLL_DURATION_MS - Timeout in milliseconds for no-link
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* polling after which polling interval is
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* increased.
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* DP83TG720S_POLL_SLOW - Slow polling interval when there is no
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* link for a prolongued period.
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* DP83TG720S_RESET_DELAY_MS_MASTER - Delay after a reset before attempting
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* to establish a link again for master phy.
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* DP83TG720S_RESET_DELAY_MS_SLAVE - Delay after a reset before attempting
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* to establish a link again for slave phy.
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*
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* These values are not documented or officially recommended by the vendor but
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* were determined through empirical testing. They achieve a good balance in
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* minimizing the number of reset retries while ensuring reliable link recovery
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* within a reasonable timeframe.
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*/
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-
#define DP83TG720S_POLL_ACTIVE_LINK 1000
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-
#define DP83TG720S_POLL_NO_LINK_MIN 100
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-
#define DP83TG720S_POLL_NO_LINK_MAX 1000
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#define DP83TG720S_POLL_ACTIVE_LINK 421
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#define DP83TG720S_POLL_NO_LINK 149
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#define DP83TG720S_FAST_POLL_DURATION_MS 6000
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#define DP83TG720S_POLL_SLOW 1117
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#define DP83TG720S_RESET_DELAY_MS_MASTER 97
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#define DP83TG720S_RESET_DELAY_MS_SLAVE 149
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#define DP83TG720S_PHY_ID 0x2000a284
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···
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struct dp83tg720_priv {
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struct dp83tg720_stats stats;
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unsigned long last_link_down_jiffies;
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};
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/**
···
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priv->stats.rx_err_pkt_cnt += ret;
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return 0;
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}
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+
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static int dp83tg720_soft_reset(struct phy_device *phydev)
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{
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int ret;
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+
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ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);
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if (ret)
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return ret;
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+
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/* Include mandatory MDC-access delay (1ms) + extra asymmetric delay to
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* avoid synchronized reset deadlock. See section 1 in the top-of-file
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* comment block.
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*/
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if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE)
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msleep(DP83TG720S_RESET_DELAY_MS_SLAVE);
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else
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msleep(DP83TG720S_RESET_DELAY_MS_MASTER);
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+
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return ret;
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}
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static void dp83tg720_get_link_stats(struct phy_device *phydev,
···
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/* According to the "DP83TC81x, DP83TG72x Software
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* Implementation Guide", the PHY needs to be reset after a
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* link loss or if no link is created after at least 100ms.
477
-
*
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* Currently we are polling with the PHY_STATE_TIME (1000ms)
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* interval, which is still enough for not automotive use cases.
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*/
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ret = phy_init_hw(phydev);
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if (ret)
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return ret;
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-
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/* Sleep 600ms for PHY stabilization post-reset.
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* Empirically chosen value (not documented).
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* Helps reduce reset bounces with link partners having similar
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* issues.
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*/
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msleep(600);
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/* After HW reset we need to restore master/slave configuration.
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* genphy_c45_pma_baset1_read_master_slave() call will be done
···
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477
{
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int ret;
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479
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/* Software Restart is not enough to recover from a link failure.
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* Using Hardware Reset instead.
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*/
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ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);
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/* Reset the PHY to recover from a link failure */
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ret = dp83tg720_soft_reset(phydev);
566
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if (ret)
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return ret;
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/* Wait until MDC can be used again.
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* The wait value of one 1ms is documented in "DP83TG720S-Q1 1000BASE-T1
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* Automotive Ethernet PHY with SGMII and RGMII" datasheet.
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*/
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usleep_range(1000, 2000);
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484
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if (phy_interface_is_rgmii(phydev)) {
576
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ret = dp83tg720_config_rgmii_delay(phydev);
···
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}
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/**
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* dp83tg720_get_next_update_time - Determine the next update time for PHY
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* state
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* dp83tg720_get_next_update_time - Return next polling interval for PHY state
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* @phydev: Pointer to the phy_device structure
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*
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* This function addresses a limitation of the DP83TG720 PHY, which cannot
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* reliably detect or report a stable link state. To recover from such
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* scenarios, the PHY must be periodically reset when the link is down. However,
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* if the link partner also runs Linux with the same driver, synchronized reset
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* intervals can lead to a deadlock where the link never establishes due to
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* simultaneous resets on both sides.
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* Implements adaptive polling interval logic depending on link state and
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* downtime duration. See the "2. Polling-Based Link Detection and IRQ Support"
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* section at the top of this file for details.
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*
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* To avoid this, the function implements randomized polling intervals when the
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* link is down. It ensures that reset intervals are desynchronized by
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* introducing a random delay between a configured minimum and maximum range.
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* When the link is up, a fixed polling interval is used to minimize overhead.
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*
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* This mechanism guarantees that the link will reestablish within 10 seconds
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* in the worst-case scenario.
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*
621
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* Return: Time (in jiffies) until the next update event for the PHY state
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* machine.
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* Return: Time (in jiffies) until the next poll
623
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*/
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static unsigned int dp83tg720_get_next_update_time(struct phy_device *phydev)
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{
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struct dp83tg720_priv *priv = phydev->priv;
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unsigned int next_time_jiffies;
627
541
628
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if (phydev->link) {
629
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/* When the link is up, use a fixed 1000ms interval
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* (in jiffies)
631
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*/
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priv->last_link_down_jiffies = 0;
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+
545
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/* When the link is up, use a slower interval (in jiffies) */
632
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next_time_jiffies =
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msecs_to_jiffies(DP83TG720S_POLL_ACTIVE_LINK);
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} else {
635
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unsigned int min_jiffies, max_jiffies, rand_jiffies;
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+
unsigned long now = jiffies;
636
550
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/* When the link is down, randomize interval between min/max
638
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* (in jiffies)
639
-
*/
640
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min_jiffies = msecs_to_jiffies(DP83TG720S_POLL_NO_LINK_MIN);
641
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max_jiffies = msecs_to_jiffies(DP83TG720S_POLL_NO_LINK_MAX);
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if (!priv->last_link_down_jiffies)
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priv->last_link_down_jiffies = now;
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-
rand_jiffies = min_jiffies +
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get_random_u32_below(max_jiffies - min_jiffies + 1);
645
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next_time_jiffies = rand_jiffies;
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if (time_before(now, priv->last_link_down_jiffies +
555
+
msecs_to_jiffies(DP83TG720S_FAST_POLL_DURATION_MS))) {
556
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/* Link recently went down: fast polling */
557
+
next_time_jiffies =
558
+
msecs_to_jiffies(DP83TG720S_POLL_NO_LINK);
559
+
} else {
560
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/* Link has been down for a while: slow polling */
561
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next_time_jiffies =
562
+
msecs_to_jiffies(DP83TG720S_POLL_SLOW);
563
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}
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}
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/* Ensure the polling time is at least one jiffy */
···
648
582
649
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.flags = PHY_POLL_CABLE_TEST,
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.probe = dp83tg720_probe,
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+
.soft_reset = dp83tg720_soft_reset,
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.config_aneg = dp83tg720_config_aneg,
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.read_status = dp83tg720_read_status,
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.get_features = genphy_c45_pma_read_ext_abilities,