Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+7 -2

drivers/clocksource/arm_global_timer.c

··· 60 60 * different to the 32-bit upper value read previously, go back to step 2. 61 61 * Otherwise the 64-bit timer counter value is correct. 62 62 */ 63 - static u64 gt_counter_read(void) 63 + static u64 notrace _gt_counter_read(void) 64 64 { 65 65 u64 counter; 66 66 u32 lower; ··· 77 77 counter <<= 32; 78 78 counter |= lower; 79 79 return counter; 80 + } 81 + 82 + static u64 gt_counter_read(void) 83 + { 84 + return _gt_counter_read(); 80 85 } 81 86 82 87 /** ··· 206 201 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK 207 202 static u64 notrace gt_sched_clock_read(void) 208 203 { 209 - return gt_counter_read(); 204 + return _gt_counter_read(); 210 205 } 211 206 #endif 212 207

+1 -1

drivers/clocksource/fsl_ftm_timer.c

··· 118 118 ftm_writel(0x00, base + FTM_CNT); 119 119 } 120 120 121 - static u64 ftm_read_sched_clock(void) 121 + static u64 notrace ftm_read_sched_clock(void) 122 122 { 123 123 return ftm_readl(priv->clksrc_base + FTM_CNT); 124 124 }

+1 -1

drivers/clocksource/samsung_pwm_timer.c

··· 307 307 samsung_time_start(pwm.source_id, true); 308 308 } 309 309 310 - static cycle_t samsung_clocksource_read(struct clocksource *c) 310 + static cycle_t notrace samsung_clocksource_read(struct clocksource *c) 311 311 { 312 312 return ~readl_relaxed(pwm.source_reg); 313 313 }

+3 -1

drivers/clocksource/sh_mtu2.c

··· 280 280 { 281 281 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); 282 282 283 - sh_mtu2_disable(ch); 283 + if (clockevent_state_periodic(ced)) 284 + sh_mtu2_disable(ch); 285 + 284 286 return 0; 285 287 } 286 288

+2 -1

drivers/clocksource/time-pistachio.c

··· 67 67 writel(value, base + 0x20 * gpt_id + offset); 68 68 } 69 69 70 - static cycle_t pistachio_clocksource_read_cycles(struct clocksource *cs) 70 + static cycle_t notrace 71 + pistachio_clocksource_read_cycles(struct clocksource *cs) 71 72 { 72 73 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); 73 74 u32 counter, overflw;

+1 -1

drivers/clocksource/timer-digicolor.c

··· 143 143 return IRQ_HANDLED; 144 144 } 145 145 146 - static u64 digicolor_timer_sched_read(void) 146 + static u64 notrace digicolor_timer_sched_read(void) 147 147 { 148 148 return ~readl(dc_timer_dev.base + COUNT(TIMER_B)); 149 149 }

+1 -1

drivers/clocksource/timer-prima2.c

··· 73 73 } 74 74 75 75 /* read 64-bit timer counter */ 76 - static cycle_t sirfsoc_timer_read(struct clocksource *cs) 76 + static cycle_t notrace sirfsoc_timer_read(struct clocksource *cs) 77 77 { 78 78 u64 cycles; 79 79

+1 -1

drivers/clocksource/vf_pit_timer.c

··· 52 52 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); 53 53 } 54 54 55 - static u64 pit_read_sched_clock(void) 55 + static u64 notrace pit_read_sched_clock(void) 56 56 { 57 57 return ~__raw_readl(clksrc_base + PITCVAL); 58 58 }

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