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dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with generic names

The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names.
In addition, fix improper space indent in example.

Fixes: 4ad7b39623ab ("media: dt-binding: mediatek: add bindings for MediaTek MDP3 components")
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

authored by

Moudy Ho and committed by
AngeloGioacchino Del Regno f5f185bf a17cf4c6

+31 -21
+17 -12
Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
··· 69 69 - description: used for 1st data pipe from RDMA 70 70 - description: used for 2nd data pipe from RDMA 71 71 72 + '#dma-cells': 73 + const: 1 74 + 72 75 required: 73 76 - compatible 74 77 - reg ··· 81 78 - clocks 82 79 - iommus 83 80 - mboxes 81 + - '#dma-cells' 84 82 85 83 additionalProperties: false 86 84 ··· 92 88 #include <dt-bindings/power/mt8183-power.h> 93 89 #include <dt-bindings/memory/mt8183-larb-port.h> 94 90 95 - mdp3_rdma0: mdp3-rdma0@14001000 { 96 - compatible = "mediatek,mt8183-mdp3-rdma"; 97 - reg = <0x14001000 0x1000>; 98 - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 99 - mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 100 - <CMDQ_EVENT_MDP_RDMA0_EOF>; 101 - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 102 - clocks = <&mmsys CLK_MM_MDP_RDMA0>, 103 - <&mmsys CLK_MM_MDP_RSZ1>; 104 - iommus = <&iommu>; 105 - mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, 106 - <&gce 21 CMDQ_THR_PRIO_LOWEST>; 91 + dma-controller@14001000 { 92 + compatible = "mediatek,mt8183-mdp3-rdma"; 93 + reg = <0x14001000 0x1000>; 94 + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 95 + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 96 + <CMDQ_EVENT_MDP_RDMA0_EOF>; 97 + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 98 + clocks = <&mmsys CLK_MM_MDP_RDMA0>, 99 + <&mmsys CLK_MM_MDP_RSZ1>; 100 + iommus = <&iommu>; 101 + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, 102 + <&gce 21 CMDQ_THR_PRIO_LOWEST>; 103 + #dma-cells = <1>; 107 104 };
+14 -9
Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
··· 50 50 iommus: 51 51 maxItems: 1 52 52 53 + '#dma-cells': 54 + const: 1 55 + 53 56 required: 54 57 - compatible 55 58 - reg ··· 61 58 - power-domains 62 59 - clocks 63 60 - iommus 61 + - '#dma-cells' 64 62 65 63 additionalProperties: false 66 64 ··· 72 68 #include <dt-bindings/power/mt8183-power.h> 73 69 #include <dt-bindings/memory/mt8183-larb-port.h> 74 70 75 - mdp3_wrot0: mdp3-wrot0@14005000 { 76 - compatible = "mediatek,mt8183-mdp3-wrot"; 77 - reg = <0x14005000 0x1000>; 78 - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 79 - mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, 80 - <CMDQ_EVENT_MDP_WROT0_EOF>; 81 - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 82 - clocks = <&mmsys CLK_MM_MDP_WROT0>; 83 - iommus = <&iommu>; 71 + dma-controller@14005000 { 72 + compatible = "mediatek,mt8183-mdp3-wrot"; 73 + reg = <0x14005000 0x1000>; 74 + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 75 + mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, 76 + <CMDQ_EVENT_MDP_WROT0_EOF>; 77 + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 78 + clocks = <&mmsys CLK_MM_MDP_WROT0>; 79 + iommus = <&iommu>; 80 + #dma-cells = <1>; 84 81 };