Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/radeon/kms/r6xx+: voltage fixes
drm/nouveau: drop leftover debugging
drm/radeon: avoid warnings from r600/eg irq handlers on powered off card.
drm/radeon/kms: add missing param for dce3.2 DP transmitter setup
drm/radeon/kms/atom: fix duallink on some early DCE3.2 cards
drm/nouveau: fix assumption that semaphore dmaobj is valid in x-chan sync
drm/nv50/disp: fix gamma with page flipping overlay turned on
drm/nouveau/pm: Prevent overflow in nouveau_perf_init()
drm/nouveau: fix big-endian switch
+84
-61
-1
drivers/gpu/drm/nouveau/nouveau_acpi.c
-1
drivers/gpu/drm/nouveau/nouveau_acpi.c
+25
-34
drivers/gpu/drm/nouveau/nouveau_fence.c
+25
-34
drivers/gpu/drm/nouveau/nouveau_fence.c
···
339
339
int ret;
340
340
341
341
if (dev_priv->chipset < 0x84) {
342
-
ret = RING_SPACE(chan, 3);
342
+
ret = RING_SPACE(chan, 4);
343
343
if (ret)
344
344
return ret;
345
345
346
-
BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 2);
346
+
BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 3);
347
+
OUT_RING (chan, NvSema);
347
348
OUT_RING (chan, sema->mem->start);
348
349
OUT_RING (chan, 1);
349
350
} else
···
352
351
struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
353
352
u64 offset = vma->offset + sema->mem->start;
354
353
355
-
ret = RING_SPACE(chan, 5);
354
+
ret = RING_SPACE(chan, 7);
356
355
if (ret)
357
356
return ret;
358
357
358
+
BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
359
+
OUT_RING (chan, chan->vram_handle);
359
360
BEGIN_RING(chan, NvSubSw, 0x0010, 4);
360
361
OUT_RING (chan, upper_32_bits(offset));
361
362
OUT_RING (chan, lower_32_bits(offset));
···
397
394
int ret;
398
395
399
396
if (dev_priv->chipset < 0x84) {
400
-
ret = RING_SPACE(chan, 4);
397
+
ret = RING_SPACE(chan, 5);
401
398
if (ret)
402
399
return ret;
403
400
404
-
BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 1);
401
+
BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 2);
402
+
OUT_RING (chan, NvSema);
405
403
OUT_RING (chan, sema->mem->start);
406
404
BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1);
407
405
OUT_RING (chan, 1);
···
411
407
struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
412
408
u64 offset = vma->offset + sema->mem->start;
413
409
414
-
ret = RING_SPACE(chan, 5);
410
+
ret = RING_SPACE(chan, 7);
415
411
if (ret)
416
412
return ret;
417
413
414
+
BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
415
+
OUT_RING (chan, chan->vram_handle);
418
416
BEGIN_RING(chan, NvSubSw, 0x0010, 4);
419
417
OUT_RING (chan, upper_32_bits(offset));
420
418
OUT_RING (chan, lower_32_bits(offset));
···
510
504
struct nouveau_gpuobj *obj = NULL;
511
505
int ret;
512
506
513
-
if (dev_priv->card_type >= NV_C0)
514
-
goto out_initialised;
507
+
if (dev_priv->card_type < NV_C0) {
508
+
/* Create an NV_SW object for various sync purposes */
509
+
ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
510
+
if (ret)
511
+
return ret;
515
512
516
-
/* Create an NV_SW object for various sync purposes */
517
-
ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
518
-
if (ret)
519
-
return ret;
513
+
ret = RING_SPACE(chan, 2);
514
+
if (ret)
515
+
return ret;
520
516
521
-
/* we leave subchannel empty for nvc0 */
522
-
ret = RING_SPACE(chan, 2);
523
-
if (ret)
524
-
return ret;
525
-
BEGIN_RING(chan, NvSubSw, 0, 1);
526
-
OUT_RING(chan, NvSw);
517
+
BEGIN_RING(chan, NvSubSw, 0, 1);
518
+
OUT_RING (chan, NvSw);
519
+
FIRE_RING (chan);
520
+
}
527
521
528
-
/* Create a DMA object for the shared cross-channel sync area. */
522
+
/* Setup area of memory shared between all channels for x-chan sync */
529
523
if (USE_SEMA(dev) && dev_priv->chipset < 0x84) {
530
524
struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem;
531
525
···
540
534
nouveau_gpuobj_ref(NULL, &obj);
541
535
if (ret)
542
536
return ret;
543
-
544
-
ret = RING_SPACE(chan, 2);
545
-
if (ret)
546
-
return ret;
547
-
BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
548
-
OUT_RING(chan, NvSema);
549
-
} else {
550
-
ret = RING_SPACE(chan, 2);
551
-
if (ret)
552
-
return ret;
553
-
BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
554
-
OUT_RING (chan, chan->vram_handle); /* whole VM */
555
537
}
556
538
557
-
FIRE_RING(chan);
558
-
559
-
out_initialised:
560
539
INIT_LIST_HEAD(&chan->fence.pending);
561
540
spin_lock_init(&chan->fence.lock);
562
541
atomic_set(&chan->fence.last_sequence_irq, 0);
+5
drivers/gpu/drm/nouveau/nouveau_perf.c
+5
drivers/gpu/drm/nouveau/nouveau_perf.c
···
182
182
entries = perf[2];
183
183
}
184
184
185
+
if (entries > NOUVEAU_PM_MAX_LEVEL) {
186
+
NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n");
187
+
entries = NOUVEAU_PM_MAX_LEVEL;
188
+
}
189
+
185
190
entry = perf + headerlen;
186
191
for (i = 0; i < entries; i++) {
187
192
struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
+2
-2
drivers/gpu/drm/nouveau/nouveau_state.c
+2
-2
drivers/gpu/drm/nouveau/nouveau_state.c
···
881
881
882
882
#ifdef __BIG_ENDIAN
883
883
/* Put the card in BE mode if it's not */
884
-
if (nv_rd32(dev, NV03_PMC_BOOT_1))
885
-
nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
884
+
if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
885
+
nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
886
886
887
887
DRM_MEMORYBARRIER();
888
888
#endif
+14
-3
drivers/gpu/drm/nouveau/nv50_display.c
+14
-3
drivers/gpu/drm/nouveau/nv50_display.c
···
409
409
struct nouveau_channel *evo = dispc->sync;
410
410
int ret;
411
411
412
-
ret = RING_SPACE(evo, 24);
412
+
ret = RING_SPACE(evo, chan ? 25 : 27);
413
413
if (unlikely(ret))
414
414
return ret;
415
415
···
458
458
/* queue the flip on the crtc's "display sync" channel */
459
459
BEGIN_RING(evo, 0, 0x0100, 1);
460
460
OUT_RING (evo, 0xfffe0000);
461
-
BEGIN_RING(evo, 0, 0x0084, 5);
462
-
OUT_RING (evo, chan ? 0x00000100 : 0x00000010);
461
+
if (chan) {
462
+
BEGIN_RING(evo, 0, 0x0084, 1);
463
+
OUT_RING (evo, 0x00000100);
464
+
} else {
465
+
BEGIN_RING(evo, 0, 0x0084, 1);
466
+
OUT_RING (evo, 0x00000010);
467
+
/* allows gamma somehow, PDISP will bitch at you if
468
+
* you don't wait for vblank before changing this..
469
+
*/
470
+
BEGIN_RING(evo, 0, 0x00e0, 1);
471
+
OUT_RING (evo, 0x40000000);
472
+
}
473
+
BEGIN_RING(evo, 0, 0x0088, 4);
463
474
OUT_RING (evo, dispc->sem.offset);
464
475
OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
465
476
OUT_RING (evo, 0x74b1e000);
+13
-10
drivers/gpu/drm/radeon/evergreen.c
+13
-10
drivers/gpu/drm/radeon/evergreen.c
···
140
140
struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
141
141
142
142
if (voltage->type == VOLTAGE_SW) {
143
+
/* 0xff01 is a flag rather then an actual voltage */
144
+
if (voltage->voltage == 0xff01)
145
+
return;
143
146
if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
144
147
radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
145
148
rdev->pm.current_vddc = voltage->voltage;
146
149
DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
147
150
}
151
+
/* 0xff01 is a flag rather then an actual voltage */
152
+
if (voltage->vddci == 0xff01)
153
+
return;
148
154
if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
149
155
radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
150
156
rdev->pm.current_vddci = voltage->vddci;
···
2701
2695
2702
2696
int evergreen_irq_process(struct radeon_device *rdev)
2703
2697
{
2704
-
u32 wptr = evergreen_get_ih_wptr(rdev);
2705
-
u32 rptr = rdev->ih.rptr;
2698
+
u32 wptr;
2699
+
u32 rptr;
2706
2700
u32 src_id, src_data;
2707
2701
u32 ring_index;
2708
2702
unsigned long flags;
2709
2703
bool queue_hotplug = false;
2710
2704
2711
-
DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2712
-
if (!rdev->ih.enabled)
2705
+
if (!rdev->ih.enabled || rdev->shutdown)
2713
2706
return IRQ_NONE;
2714
2707
2715
-
spin_lock_irqsave(&rdev->ih.lock, flags);
2708
+
wptr = evergreen_get_ih_wptr(rdev);
2709
+
rptr = rdev->ih.rptr;
2710
+
DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2716
2711
2712
+
spin_lock_irqsave(&rdev->ih.lock, flags);
2717
2713
if (rptr == wptr) {
2718
2714
spin_unlock_irqrestore(&rdev->ih.lock, flags);
2719
2715
return IRQ_NONE;
2720
2716
}
2721
-
if (rdev->shutdown) {
2722
-
spin_unlock_irqrestore(&rdev->ih.lock, flags);
2723
-
return IRQ_NONE;
2724
-
}
2725
-
2726
2717
restart_ih:
2727
2718
/* display interrupts */
2728
2719
evergreen_irq_ack(rdev);
+10
-8
drivers/gpu/drm/radeon/r600.c
+10
-8
drivers/gpu/drm/radeon/r600.c
···
590
590
struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
591
591
592
592
if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
593
+
/* 0xff01 is a flag rather then an actual voltage */
594
+
if (voltage->voltage == 0xff01)
595
+
return;
593
596
if (voltage->voltage != rdev->pm.current_vddc) {
594
597
radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
595
598
rdev->pm.current_vddc = voltage->voltage;
···
3297
3294
3298
3295
int r600_irq_process(struct radeon_device *rdev)
3299
3296
{
3300
-
u32 wptr = r600_get_ih_wptr(rdev);
3301
-
u32 rptr = rdev->ih.rptr;
3297
+
u32 wptr;
3298
+
u32 rptr;
3302
3299
u32 src_id, src_data;
3303
3300
u32 ring_index;
3304
3301
unsigned long flags;
3305
3302
bool queue_hotplug = false;
3306
3303
3307
-
DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3308
-
if (!rdev->ih.enabled)
3304
+
if (!rdev->ih.enabled || rdev->shutdown)
3309
3305
return IRQ_NONE;
3306
+
3307
+
wptr = r600_get_ih_wptr(rdev);
3308
+
rptr = rdev->ih.rptr;
3309
+
DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3310
3310
3311
3311
spin_lock_irqsave(&rdev->ih.lock, flags);
3312
3312
3313
3313
if (rptr == wptr) {
3314
-
spin_unlock_irqrestore(&rdev->ih.lock, flags);
3315
-
return IRQ_NONE;
3316
-
}
3317
-
if (rdev->shutdown) {
3318
3314
spin_unlock_irqrestore(&rdev->ih.lock, flags);
3319
3315
return IRQ_NONE;
3320
3316
}
+4
drivers/gpu/drm/radeon/radeon_atombios.c
+4
drivers/gpu/drm/radeon/radeon_atombios.c
···
2607
2607
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2608
2608
return;
2609
2609
2610
+
/* 0xff01 is a flag rather then an actual voltage */
2611
+
if (voltage_level == 0xff01)
2612
+
return;
2613
+
2610
2614
switch (crev) {
2611
2615
case 1:
2612
2616
args.v1.ucVoltageType = voltage_type;
+8
-3
drivers/gpu/drm/radeon/radeon_encoders.c
+8
-3
drivers/gpu/drm/radeon/radeon_encoders.c
···
1090
1090
break;
1091
1091
}
1092
1092
1093
-
if (is_dp)
1093
+
if (is_dp) {
1094
1094
args.v2.acConfig.fCoherentMode = 1;
1095
-
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1095
+
args.v2.acConfig.fDPConnector = 1;
1096
+
} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1096
1097
if (dig->coherent_mode)
1097
1098
args.v2.acConfig.fCoherentMode = 1;
1098
1099
if (radeon_encoder->pixel_clock > 165000)
···
1432
1431
if (is_dig) {
1433
1432
switch (mode) {
1434
1433
case DRM_MODE_DPMS_ON:
1435
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1434
+
/* some early dce3.2 boards have a bug in their transmitter control table */
1435
+
if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1436
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1437
+
else
1438
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1436
1439
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1437
1440
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1438
1441
+3
drivers/gpu/drm/radeon/rv770.c
+3
drivers/gpu/drm/radeon/rv770.c
···
105
105
struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
106
106
107
107
if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108
+
/* 0xff01 is a flag rather then an actual voltage */
109
+
if (voltage->voltage == 0xff01)
110
+
return;
108
111
if (voltage->voltage != rdev->pm.current_vddc) {
109
112
radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
110
113
rdev->pm.current_vddc = voltage->voltage;