tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'mtd/fixes-for-6.6-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD fixes from Miquel Raynal:
"In the raw NAND subsystem, the major fix prevents using cached reads
with devices not supporting it. There was two bug reports about this.

Apart from that, three drivers (pl353, arasan and marvell) could
sometimes hide page program failures due to their their own program
page helper not being fully compliant with the specification (many
drivers use the default helpers shared by the core). Adding a missing
check prevents these situation.

Finally, the Qualcomm driver had a broken error path.

In the SPI-NAND subsystem one Micron device used a wrong bitmak
reporting possibly corrupted ECC status.

Finally, the physmap-core got stripped from its map_rom fallback by
mistake, this feature is added back"

* tag 'mtd/fixes-for-6.6-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: rawnand: Ensure the nand chip supports cached reads
mtd: rawnand: qcom: Unmap the right resource upon probe failure
mtd: rawnand: pl353: Ensure program page operations are successful
mtd: rawnand: arasan: Ensure program page operations are successful
mtd: spinand: micron: correct bitmask for ecc status
mtd: physmap-core: Restore map_rom fallback
mtd: rawnand: marvell: Ensure program page operations are successful

Linus Torvalds f6176471 7da6c042

+73 -5
+11
drivers/mtd/maps/physmap-core.c
··· 551 551 if (info->probe_type) { 552 552 info->mtds[i] = do_map_probe(info->probe_type, 553 553 &info->maps[i]); 554 + 555 + /* Fall back to mapping region as ROM */ 556 + if (!info->mtds[i] && IS_ENABLED(CONFIG_MTD_ROM) && 557 + strcmp(info->probe_type, "map_rom")) { 558 + dev_warn(&dev->dev, 559 + "map_probe() failed for type %s\n", 560 + info->probe_type); 561 + 562 + info->mtds[i] = do_map_probe("map_rom", 563 + &info->maps[i]); 564 + } 554 565 } else { 555 566 int j; 556 567
+14 -2
drivers/mtd/nand/raw/arasan-nand-controller.c
··· 515 515 struct mtd_info *mtd = nand_to_mtd(chip); 516 516 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); 517 517 dma_addr_t dma_addr; 518 + u8 status; 518 519 int ret; 519 520 struct anfc_op nfc_op = { 520 521 .pkt_reg = ··· 562 561 } 563 562 564 563 /* Spare data is not protected */ 565 - if (oob_required) 564 + if (oob_required) { 566 565 ret = nand_write_oob_std(chip, page); 566 + if (ret) 567 + return ret; 568 + } 567 569 568 - return ret; 570 + /* Check write status on the chip side */ 571 + ret = nand_status_op(chip, &status); 572 + if (ret) 573 + return ret; 574 + 575 + if (status & NAND_STATUS_FAIL) 576 + return -EIO; 577 + 578 + return 0; 569 579 } 570 580 571 581 static int anfc_sel_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,
+22 -1
drivers/mtd/nand/raw/marvell_nand.c
··· 1165 1165 .ndcb[2] = NDCB2_ADDR5_PAGE(page), 1166 1166 }; 1167 1167 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 1168 + u8 status; 1168 1169 int ret; 1169 1170 1170 1171 /* NFCv2 needs more information about the operation being executed */ ··· 1199 1198 1200 1199 ret = marvell_nfc_wait_op(chip, 1201 1200 PSEC_TO_MSEC(sdr->tPROG_max)); 1202 - return ret; 1201 + if (ret) 1202 + return ret; 1203 + 1204 + /* Check write status on the chip side */ 1205 + ret = nand_status_op(chip, &status); 1206 + if (ret) 1207 + return ret; 1208 + 1209 + if (status & NAND_STATUS_FAIL) 1210 + return -EIO; 1211 + 1212 + return 0; 1203 1213 } 1204 1214 1205 1215 static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip, ··· 1639 1627 int data_len = lt->data_bytes; 1640 1628 int spare_len = lt->spare_bytes; 1641 1629 int chunk, ret; 1630 + u8 status; 1642 1631 1643 1632 marvell_nfc_select_target(chip, chip->cur_cs); 1644 1633 ··· 1675 1662 1676 1663 if (ret) 1677 1664 return ret; 1665 + 1666 + /* Check write status on the chip side */ 1667 + ret = nand_status_op(chip, &status); 1668 + if (ret) 1669 + return ret; 1670 + 1671 + if (status & NAND_STATUS_FAIL) 1672 + return -EIO; 1678 1673 1679 1674 return 0; 1680 1675 }
+3
drivers/mtd/nand/raw/nand_base.c
··· 5110 5110 { 5111 5111 struct mtd_info *mtd = nand_to_mtd(chip); 5112 5112 5113 + if (!chip->parameters.supports_read_cache) 5114 + return; 5115 + 5113 5116 if (chip->read_retries) 5114 5117 return; 5115 5118
+3
drivers/mtd/nand/raw/nand_jedec.c
··· 94 94 goto free_jedec_param_page; 95 95 } 96 96 97 + if (p->opt_cmd[0] & JEDEC_OPT_CMD_READ_CACHE) 98 + chip->parameters.supports_read_cache = true; 99 + 97 100 memorg->pagesize = le32_to_cpu(p->byte_per_page); 98 101 mtd->writesize = memorg->pagesize; 99 102
+3
drivers/mtd/nand/raw/nand_onfi.c
··· 303 303 ONFI_FEATURE_ADDR_TIMING_MODE, 1); 304 304 } 305 305 306 + if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_READ_CACHE) 307 + chip->parameters.supports_read_cache = true; 308 + 306 309 onfi = kzalloc(sizeof(*onfi), GFP_KERNEL); 307 310 if (!onfi) { 308 311 ret = -ENOMEM;
+9
drivers/mtd/nand/raw/pl35x-nand-controller.c
··· 511 511 u32 addr1 = 0, addr2 = 0, row; 512 512 u32 cmd_addr; 513 513 int i, ret; 514 + u8 status; 514 515 515 516 ret = pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_APB); 516 517 if (ret) ··· 563 562 ret = pl35x_smc_wait_for_irq(nfc); 564 563 if (ret) 565 564 goto disable_ecc_engine; 565 + 566 + /* Check write status on the chip side */ 567 + ret = nand_status_op(chip, &status); 568 + if (ret) 569 + goto disable_ecc_engine; 570 + 571 + if (status & NAND_STATUS_FAIL) 572 + ret = -EIO; 566 573 567 574 disable_ecc_engine: 568 575 pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_BYPASS);
+1 -1
drivers/mtd/nand/raw/qcom_nandc.c
··· 3444 3444 err_aon_clk: 3445 3445 clk_disable_unprepare(nandc->core_clk); 3446 3446 err_core_clk: 3447 - dma_unmap_resource(dev, res->start, resource_size(res), 3447 + dma_unmap_resource(dev, nandc->base_dma, resource_size(res), 3448 3448 DMA_BIDIRECTIONAL, 0); 3449 3449 return ret; 3450 3450 }
+1 -1
drivers/mtd/nand/spi/micron.c
··· 12 12 13 13 #define SPINAND_MFR_MICRON 0x2c 14 14 15 - #define MICRON_STATUS_ECC_MASK GENMASK(7, 4) 15 + #define MICRON_STATUS_ECC_MASK GENMASK(6, 4) 16 16 #define MICRON_STATUS_ECC_NO_BITFLIPS (0 << 4) 17 17 #define MICRON_STATUS_ECC_1TO3_BITFLIPS (1 << 4) 18 18 #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
+3
include/linux/mtd/jedec.h
··· 21 21 /* JEDEC features */ 22 22 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 23 23 24 + /* JEDEC Optional Commands */ 25 + #define JEDEC_OPT_CMD_READ_CACHE BIT(1) 26 + 24 27 struct nand_jedec_params { 25 28 /* rev info and features block */ 26 29 /* 'J' 'E' 'S' 'D' */
+1
include/linux/mtd/onfi.h
··· 55 55 #define ONFI_SUBFEATURE_PARAM_LEN 4 56 56 57 57 /* ONFI optional commands SET/GET FEATURES supported? */ 58 + #define ONFI_OPT_CMD_READ_CACHE BIT(1) 58 59 #define ONFI_OPT_CMD_SET_GET_FEATURES BIT(2) 59 60 60 61 struct nand_onfi_params {
+2
include/linux/mtd/rawnand.h
··· 225 225 * struct nand_parameters - NAND generic parameters from the parameter page 226 226 * @model: Model name 227 227 * @supports_set_get_features: The NAND chip supports setting/getting features 228 + * @supports_read_cache: The NAND chip supports read cache operations 228 229 * @set_feature_list: Bitmap of features that can be set 229 230 * @get_feature_list: Bitmap of features that can be get 230 231 * @onfi: ONFI specific parameters ··· 234 233 /* Generic parameters */ 235 234 const char *model; 236 235 bool supports_set_get_features; 236 + bool supports_read_cache; 237 237 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 238 238 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 239 239