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dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY

Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in
the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual
in that only the combo PHY can perform a calibration step needed to
determine settings used by the other two PCIe PHYs.

Calibration must be done with the combo PHY in PCIe mode, and to allow
this to occur independent of the eventual use for the PHY (PCIe or USB)
some PCIe-related properties must be supplied: clocks; resets; and a
syscon phandle.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20251218151235.454997-2-elder@riscstar.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Alex Elder and committed by
Vinod Koul f6194de7 ff89cea2

+114
+114
Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: SpacemiT K1 PCIe/USB3 Combo PHY 8 + 9 + maintainers: 10 + - Alex Elder <elder@riscstar.com> 11 + 12 + description: > 13 + Of the three PHYs on the SpacemiT K1 SoC capable of being used for 14 + PCIe, one is a combo PHY that can also be configured for use by a 15 + USB 3 controller. Using PCIe or USB 3 is a board design decision. 16 + 17 + The combo PHY is also the only PCIe PHY that is able to determine 18 + PCIe calibration values to use, and this must be determined before 19 + the other two PCIe PHYs can be used. This calibration must be 20 + performed with the combo PHY in PCIe mode, and is this is done 21 + when the combo PHY is probed. 22 + 23 + The combo PHY uses an external oscillator as a reference clock. 24 + During normal operation, the PCIe or USB port driver is responsible 25 + for ensuring all other clocks needed by a PHY are enabled, and all 26 + resets affecting the PHY are deasserted. However, for the combo 27 + PHY to perform calibration independent of whether it's later used 28 + for PCIe or USB, all PCIe mode clocks and resets must be defined. 29 + 30 + properties: 31 + compatible: 32 + const: spacemit,k1-combo-phy 33 + 34 + reg: 35 + items: 36 + - description: PHY control registers 37 + 38 + clocks: 39 + items: 40 + - description: External oscillator used by the PHY PLL 41 + - description: DWC PCIe Data Bus Interface (DBI) clock 42 + - description: DWC PCIe application AXI-bus Master interface clock 43 + - description: DWC PCIe application AXI-bus slave interface clock 44 + 45 + clock-names: 46 + items: 47 + - const: refclk 48 + - const: dbi 49 + - const: mstr 50 + - const: slv 51 + 52 + resets: 53 + items: 54 + - description: PHY reset; remains deasserted after initialization 55 + - description: DWC PCIe Data Bus Interface (DBI) reset 56 + - description: DWC PCIe application AXI-bus Master interface reset 57 + - description: DWC PCIe application AXI-bus slave interface reset 58 + 59 + reset-names: 60 + items: 61 + - const: phy 62 + - const: dbi 63 + - const: mstr 64 + - const: slv 65 + 66 + spacemit,apmu: 67 + description: 68 + A phandle that refers to the APMU system controller, whose 69 + regmap is used in setting the mode 70 + $ref: /schemas/types.yaml#/definitions/phandle 71 + 72 + "#phy-cells": 73 + const: 1 74 + description: 75 + The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines 76 + whether the PHY operates in PCIe or USB3 mode. 77 + 78 + required: 79 + - compatible 80 + - reg 81 + - clocks 82 + - clock-names 83 + - resets 84 + - reset-names 85 + - spacemit,apmu 86 + - "#phy-cells" 87 + 88 + additionalProperties: false 89 + 90 + examples: 91 + - | 92 + #include <dt-bindings/clock/spacemit,k1-syscon.h> 93 + phy@c0b10000 { 94 + compatible = "spacemit,k1-combo-phy"; 95 + reg = <0xc0b10000 0x1000>; 96 + clocks = <&vctcxo_24m>, 97 + <&syscon_apmu CLK_PCIE0_DBI>, 98 + <&syscon_apmu CLK_PCIE0_MASTER>, 99 + <&syscon_apmu CLK_PCIE0_SLAVE>; 100 + clock-names = "refclk", 101 + "dbi", 102 + "mstr", 103 + "slv"; 104 + resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, 105 + <&syscon_apmu RESET_PCIE0_DBI>, 106 + <&syscon_apmu RESET_PCIE0_MASTER>, 107 + <&syscon_apmu RESET_PCIE0_SLAVE>; 108 + reset-names = "phy", 109 + "dbi", 110 + "mstr", 111 + "slv"; 112 + spacemit,apmu = <&syscon_apmu>; 113 + #phy-cells = <1>; 114 + };