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clk: qcom: gcc-sc8180x: Refactor to use qcom_cc_driver_data

Use a qcom_cc_driver_data struct instead of a long custom probe
callback to align with modern qcom/gcc-*.c style.

No functional change intended.

Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-7-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Val Packett and committed by
Bjorn Andersson f641773e 73322066

+31 -30
+31 -30
drivers/clk/qcom/gcc-sc8180x.c
··· 4605 4605 [GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 }, 4606 4606 }; 4607 4607 4608 - static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 4608 + static const struct clk_rcg_dfs_data gcc_sc8180x_dfs_clocks[] = { 4609 4609 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 4610 4610 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 4611 4611 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), ··· 4647 4647 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 4648 4648 }; 4649 4649 4650 + static u32 gcc_sc8180x_critical_cbcrs[] = { 4651 + 0xb004, /* GCC_VIDEO_AHB_CLK */ 4652 + 0xb008, /* GCC_CAMERA_AHB_CLK */ 4653 + 0xb00c, /* GCC_DISP_AHB_CLK */ 4654 + 0xb040, /* GCC_VIDEO_XO_CLK */ 4655 + 0xb044, /* GCC_CAMERA_XO_CLK */ 4656 + 0xb048, /* GCC_DISP_XO_CLK */ 4657 + 0x48004, /* GCC_CPUSS_GNOC_CLK */ 4658 + 0x48190, /* GCC_CPUSS_DVM_BUS_CLK */ 4659 + 0x4d004, /* GCC_NPU_CFG_AHB_CLK */ 4660 + 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 4661 + }; 4662 + 4650 4663 static const struct regmap_config gcc_sc8180x_regmap_config = { 4651 4664 .reg_bits = 32, 4652 4665 .reg_stride = 4, 4653 4666 .val_bits = 32, 4654 4667 .max_register = 0xc0004, 4655 4668 .fast_io = true, 4669 + }; 4670 + 4671 + static void clk_sc8180x_regs_configure(struct device *dev, struct regmap *regmap) 4672 + { 4673 + /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 4674 + regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 4675 + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 4676 + } 4677 + 4678 + static struct qcom_cc_driver_data gcc_sc8180x_driver_data = { 4679 + .clk_cbcrs = gcc_sc8180x_critical_cbcrs, 4680 + .num_clk_cbcrs = ARRAY_SIZE(gcc_sc8180x_critical_cbcrs), 4681 + .dfs_rcgs = gcc_sc8180x_dfs_clocks, 4682 + .num_dfs_rcgs = ARRAY_SIZE(gcc_sc8180x_dfs_clocks), 4683 + .clk_regs_configure = clk_sc8180x_regs_configure, 4656 4684 }; 4657 4685 4658 4686 static const struct qcom_cc_desc gcc_sc8180x_desc = { ··· 4692 4664 .gdscs = gcc_sc8180x_gdscs, 4693 4665 .num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs), 4694 4666 .use_rpm = true, 4667 + .driver_data = &gcc_sc8180x_driver_data, 4695 4668 }; 4696 4669 4697 4670 static const struct of_device_id gcc_sc8180x_match_table[] = { ··· 4703 4674 4704 4675 static int gcc_sc8180x_probe(struct platform_device *pdev) 4705 4676 { 4706 - struct regmap *regmap; 4707 - int ret; 4708 - 4709 - regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc); 4710 - if (IS_ERR(regmap)) 4711 - return PTR_ERR(regmap); 4712 - 4713 - /* Keep some clocks always-on */ 4714 - qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ 4715 - qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ 4716 - qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ 4717 - qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ 4718 - qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ 4719 - qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ 4720 - qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ 4721 - qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ 4722 - qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ 4723 - qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 4724 - 4725 - /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 4726 - regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 4727 - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 4728 - 4729 - ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 4730 - ARRAY_SIZE(gcc_dfs_clocks)); 4731 - if (ret) 4732 - return ret; 4733 - 4734 - return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap); 4677 + return qcom_cc_probe(pdev, &gcc_sc8180x_desc); 4735 4678 } 4736 4679 4737 4680 static struct platform_driver gcc_sc8180x_driver = {