tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
"A new drivers/cache/ subsystem is added to contain drivers for
abstracting cache flush methods on riscv and potentially others, as
this is needed for handling non-coherent DMA but several SoCs require
nonstandard hardware methods for it.

op-tee gains support for asynchronous notification with FF-A, as well
as support for a system thread for executing in secure world.

The tee, reset, bus, memory and scmi subsystems have a couple of minor
updates.

Platform specific soc driver changes include:

- Samsung Exynos gains driver support for Google GS101 (Tensor G1)
across multiple subsystems

- Qualcomm Snapdragon gains support for SM8650 and X1E along with
added features for some other SoCs

- Mediatek adds support for "Smart Voltage Scaling" on MT8186 and
MT8195, and driver support for MT8188 along with some code
refactoring.

- Microchip Polarfire FPGA support for "Auto Update" of the FPGA
bitstream

- Apple M1 mailbox driver is rewritten into a SoC driver

- minor updates on amlogic, mvebu, ti, zynq, imx, renesas and
hisilicon"

* tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits)
memory: ti-emif-pm: Convert to platform remove callback returning void
memory: ti-aemif: Convert to platform remove callback returning void
memory: tegra210-emc: Convert to platform remove callback returning void
memory: tegra186-emc: Convert to platform remove callback returning void
memory: stm32-fmc2-ebi: Convert to platform remove callback returning void
memory: exynos5422-dmc: Convert to platform remove callback returning void
memory: renesas-rpc-if: Convert to platform remove callback returning void
memory: omap-gpmc: Convert to platform remove callback returning void
memory: mtk-smi: Convert to platform remove callback returning void
memory: jz4780-nemc: Convert to platform remove callback returning void
memory: fsl_ifc: Convert to platform remove callback returning void
memory: fsl-corenet-cf: Convert to platform remove callback returning void
memory: emif: Convert to platform remove callback returning void
memory: brcmstb_memc: Convert to platform remove callback returning void
memory: brcmstb_dpfe: Convert to platform remove callback returning void
soc: qcom: llcc: Fix LLCC_TRP_ATTR2_CFGn offset
firmware: qcom: qseecom: fix memory leaks in error paths
dt-bindings: clock: google,gs101: rename CMU_TOP gate defines
soc: qcom: llcc: Fix typo in kernel-doc
dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel
...

Linus Torvalds f6597d17 c4101e55

+7238 -2123
+4
CREDITS
··· 1424 1424 S: Stellenbosch, Western Cape 1425 1425 S: South Africa 1426 1426 1427 + N: Andy Gross 1428 + E: agross@kernel.org 1429 + D: Qualcomm SoC subsystem and drivers 1430 + 1427 1431 N: Grant Grundler 1428 1432 E: grantgrundler@gmail.com 1429 1433 W: http://obmouse.sourceforge.net/
+3 -3
Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs
··· 3 3 What: /sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt 4 4 Date: November 2023 5 5 KernelVersion: 6.6 6 - Contact: Huisong Li <lihuisong@huawei.org> 6 + Contact: Huisong Li <lihuisong@huawei.com> 7 7 Description: 8 8 The /sys/devices/platform/HISI04Bx:00/chipX/ directory 9 9 contains read-only attributes exposing some summarization ··· 26 26 What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt 27 27 Date: November 2023 28 28 KernelVersion: 6.6 29 - Contact: Huisong Li <lihuisong@huawei.org> 29 + Contact: Huisong Li <lihuisong@huawei.com> 30 30 Description: 31 31 The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory 32 32 contains read-only attributes exposing some summarization ··· 54 54 What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt 55 55 Date: November 2023 56 56 KernelVersion: 6.6 57 - Contact: Huisong Li <lihuisong@huawei.org> 57 + Contact: Huisong Li <lihuisong@huawei.com> 58 58 Description: 59 59 The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory 60 60 contains read-only attributes exposing information about
+3
Documentation/devicetree/bindings/cache/qcom,llcc.yaml
··· 33 33 - qcom,sm8350-llcc 34 34 - qcom,sm8450-llcc 35 35 - qcom,sm8550-llcc 36 + - qcom,sm8650-llcc 37 + - qcom,x1e80100-llcc 36 38 37 39 reg: 38 40 minItems: 2 ··· 106 104 - qcom,qdu1000-llcc 107 105 - qcom,sc8180x-llcc 108 106 - qcom,sc8280xp-llcc 107 + - qcom,x1e80100-llcc 109 108 then: 110 109 properties: 111 110 reg:
+5 -1
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
··· 38 38 - sifive,fu740-c000-ccache 39 39 - const: cache 40 40 - items: 41 - - const: starfive,jh7110-ccache 41 + - enum: 42 + - starfive,jh7100-ccache 43 + - starfive,jh7110-ccache 42 44 - const: sifive,ccache0 43 45 - const: cache 44 46 - items: ··· 90 88 contains: 91 89 enum: 92 90 - sifive,fu740-c000-ccache 91 + - starfive,jh7100-ccache 93 92 - starfive,jh7110-ccache 94 93 - microchip,mpfs-ccache 95 94 ··· 114 111 contains: 115 112 enum: 116 113 - sifive,fu740-c000-ccache 114 + - starfive,jh7100-ccache 117 115 - starfive,jh7110-ccache 118 116 119 117 then:
+3 -15
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
··· 63 63 - qcom,scm-sm8350 64 64 - qcom,scm-sm8450 65 65 - qcom,scm-sm8550 66 + - qcom,scm-sm8650 66 67 - qcom,scm-qcs404 68 + - qcom,scm-x1e80100 67 69 - const: qcom,scm 68 70 69 71 clocks: ··· 180 178 minItems: 3 181 179 maxItems: 3 182 180 183 - # Interconnects 184 - - if: 185 - not: 186 - properties: 187 - compatible: 188 - contains: 189 - enum: 190 - - qcom,scm-qdu1000 191 - - qcom,scm-sc8280xp 192 - - qcom,scm-sm8450 193 - - qcom,scm-sm8550 194 - then: 195 - properties: 196 - interconnects: false 197 - 198 181 # Interrupts 199 182 - if: 200 183 not: ··· 189 202 enum: 190 203 - qcom,scm-sm8450 191 204 - qcom,scm-sm8550 205 + - qcom,scm-sm8650 192 206 then: 193 207 properties: 194 208 interrupts: false
+1
Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
··· 18 18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs 19 19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs 20 20 - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs 21 + - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs 21 22 22 23 reg: 23 24 maxItems: 1
+10 -21
Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
··· 28 28 properties: 29 29 compatible: 30 30 oneOf: 31 - - const: "fsl,imx51-src" 31 + - const: fsl,imx51-src 32 32 - items: 33 - - const: "fsl,imx50-src" 34 - - const: "fsl,imx51-src" 35 - - items: 36 - - const: "fsl,imx53-src" 37 - - const: "fsl,imx51-src" 38 - - items: 39 - - const: "fsl,imx6q-src" 40 - - const: "fsl,imx51-src" 41 - - items: 42 - - const: "fsl,imx6sx-src" 43 - - const: "fsl,imx51-src" 44 - - items: 45 - - const: "fsl,imx6sl-src" 46 - - const: "fsl,imx51-src" 47 - - items: 48 - - const: "fsl,imx6ul-src" 49 - - const: "fsl,imx51-src" 50 - - items: 51 - - const: "fsl,imx6sll-src" 52 - - const: "fsl,imx51-src" 33 + - enum: 34 + - fsl,imx50-src 35 + - fsl,imx53-src 36 + - fsl,imx6q-src 37 + - fsl,imx6sx-src 38 + - fsl,imx6sl-src 39 + - fsl,imx6ul-src 40 + - fsl,imx6sll-src 41 + - const: fsl,imx51-src 53 42 54 43 reg: 55 44 maxItems: 1
+1 -24
Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml
··· 50 50 51 51 examples: 52 52 - | 53 - #include <dt-bindings/interrupt-controller/irq.h> 54 - #include <dt-bindings/interrupt-controller/arm-gic.h> 55 - #include <dt-bindings/clock/hi3660-clock.h> 56 - 57 - iomcu: iomcu@ffd7e000 { 58 - compatible = "hisilicon,hi3660-iomcu", "syscon"; 59 - reg = <0xffd7e000 0x1000>; 60 - }; 61 - 62 - iomcu_rst: iomcu_rst_controller { 53 + iomcu_rst_controller { 63 54 compatible = "hisilicon,hi3660-reset"; 64 55 hisilicon,rst-syscon = <&iomcu>; 65 56 #reset-cells = <2>; 66 - }; 67 - 68 - /* Specifying reset lines connected to IP modules */ 69 - i2c@ffd71000 { 70 - compatible = "snps,designware-i2c"; 71 - reg = <0xffd71000 0x1000>; 72 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 73 - #address-cells = <1>; 74 - #size-cells = <0>; 75 - clock-frequency = <400000>; 76 - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 77 - resets = <&iomcu_rst 0x20 3>; 78 - pinctrl-names = "default"; 79 - pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 80 57 }; 81 58 ...
+5 -5
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
··· 18 18 oneOf: 19 19 - description: on SC7180 SoCs the following compatibles must be specified 20 20 items: 21 - - const: "qcom,sc7180-aoss-cc" 22 - - const: "qcom,sdm845-aoss-cc" 21 + - const: qcom,sc7180-aoss-cc 22 + - const: qcom,sdm845-aoss-cc 23 23 24 24 - description: on SC7280 SoCs the following compatibles must be specified 25 25 items: 26 - - const: "qcom,sc7280-aoss-cc" 27 - - const: "qcom,sdm845-aoss-cc" 26 + - const: qcom,sc7280-aoss-cc 27 + - const: qcom,sdm845-aoss-cc 28 28 29 29 - description: on SDM845 SoCs the following compatibles must be specified 30 30 items: 31 - - const: "qcom,sdm845-aoss-cc" 31 + - const: qcom,sdm845-aoss-cc 32 32 33 33 reg: 34 34 maxItems: 1
+4 -4
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
··· 18 18 oneOf: 19 19 - description: on SC7180 SoCs the following compatibles must be specified 20 20 items: 21 - - const: "qcom,sc7180-pdc-global" 22 - - const: "qcom,sdm845-pdc-global" 21 + - const: qcom,sc7180-pdc-global 22 + - const: qcom,sdm845-pdc-global 23 23 24 24 - description: on SC7280 SoCs the following compatibles must be specified 25 25 items: 26 - - const: "qcom,sc7280-pdc-global" 26 + - const: qcom,sc7280-pdc-global 27 27 28 28 - description: on SDM845 SoCs the following compatibles must be specified 29 29 items: 30 - - const: "qcom,sdm845-pdc-global" 30 + - const: qcom,sdm845-pdc-global 31 31 32 32 reg: 33 33 maxItems: 1
+1 -1
Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
··· 17 17 compatible: 18 18 items: 19 19 - enum: 20 - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL 20 + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five 21 21 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 22 22 - renesas,r9a07g054-usbphy-ctrl # RZ/V2L 23 23 - const: renesas,rzg2l-usbphy-ctrl
+11
Documentation/devicetree/bindings/serial/samsung_uart.yaml
··· 21 21 - enum: 22 22 - apple,s5l-uart 23 23 - axis,artpec8-uart 24 + - google,gs101-uart 24 25 - samsung,s3c6400-uart 25 26 - samsung,s5pv210-uart 26 27 - samsung,exynos4210-uart ··· 133 132 items: 134 133 - const: uart 135 134 - const: clk_uart_baud0 135 + 136 + - if: 137 + properties: 138 + compatible: 139 + contains: 140 + enum: 141 + - google,gs101-uart 142 + then: 143 + required: 144 + - samsung,uart-fifosize 136 145 137 146 unevaluatedProperties: false 138 147
+10
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
··· 26 26 compatible: 27 27 const: microchip,mpfs-sys-controller 28 28 29 + microchip,bitstream-flash: 30 + $ref: /schemas/types.yaml#/definitions/phandle 31 + description: 32 + The SPI flash connected to the system controller's QSPI controller. 33 + The system controller may retrieve FPGA bitstreams from this flash to 34 + perform In-Application Programming (IAP) or during device initialisation 35 + for Auto Update. The MSS and system controller have separate QSPI 36 + controllers and this flash is connected to both. Software running in the 37 + MSS can write bitstreams to the flash. 38 + 29 39 required: 30 40 - compatible 31 41 - mboxes
+2
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
··· 38 38 - qcom,sm8350-aoss-qmp 39 39 - qcom,sm8450-aoss-qmp 40 40 - qcom,sm8550-aoss-qmp 41 + - qcom,sm8650-aoss-qmp 42 + - qcom,x1e80100-aoss-qmp 41 43 - const: qcom,aoss-qmp 42 44 43 45 reg:
+14 -8
Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml
··· 20 20 21 21 properties: 22 22 compatible: 23 - items: 24 - - enum: 25 - - qcom,sc8180x-pmic-glink 26 - - qcom,sc8280xp-pmic-glink 27 - - qcom,sm8350-pmic-glink 28 - - qcom,sm8450-pmic-glink 29 - - qcom,sm8550-pmic-glink 30 - - const: qcom,pmic-glink 23 + oneOf: 24 + - items: 25 + - enum: 26 + - qcom,sc8180x-pmic-glink 27 + - qcom,sc8280xp-pmic-glink 28 + - qcom,sm8350-pmic-glink 29 + - qcom,sm8450-pmic-glink 30 + - qcom,sm8550-pmic-glink 31 + - const: qcom,pmic-glink 32 + - items: 33 + - enum: 34 + - qcom,sm8650-pmic-glink 35 + - const: qcom,sm8550-pmic-glink 36 + - const: qcom,pmic-glink 31 37 32 38 '#address-cells': 33 39 const: 1
+14
Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml
··· 31 31 reg: 32 32 maxItems: 1 33 33 34 + qcom,qmp: 35 + $ref: /schemas/types.yaml#/definitions/phandle 36 + description: Reference to the AOSS side-channel message RAM 37 + 34 38 required: 35 39 - compatible 36 40 - reg 41 + 42 + allOf: 43 + - if: 44 + not: 45 + properties: 46 + compatible: 47 + const: qcom,rpmh-stats 48 + then: 49 + properties: 50 + qcom,qmp: false 37 51 38 52 additionalProperties: false 39 53
+1
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
··· 25 25 oneOf: 26 26 - items: 27 27 - enum: 28 + - google,gs101-usi 28 29 - samsung,exynosautov9-usi 29 30 - samsung,exynosautov920-usi 30 31 - const: samsung,exynos850-usi
+6 -2
Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
··· 18 18 compatible: 19 19 oneOf: 20 20 - enum: 21 + - google,gs101-wdt # for Google gs101 21 22 - samsung,s3c2410-wdt # for S3C2410 22 23 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4 23 24 - samsung,exynos5250-wdt # for Exynos5250 ··· 48 47 samsung,cluster-index: 49 48 $ref: /schemas/types.yaml#/definitions/uint32 50 49 description: 51 - Index of CPU cluster on which watchdog is running (in case of Exynos850) 50 + Index of CPU cluster on which watchdog is running (in case of Exynos850 51 + or Google gs101). 52 52 53 53 samsung,syscon-phandle: 54 54 $ref: /schemas/types.yaml#/definitions/phandle 55 55 description: 56 56 Phandle to the PMU system controller node (in case of Exynos5250, 57 - Exynos5420, Exynos7 and Exynos850). 57 + Exynos5420, Exynos7, Exynos850 and gs101). 58 58 59 59 required: 60 60 - compatible ··· 71 69 compatible: 72 70 contains: 73 71 enum: 72 + - google,gs101-wdt 74 73 - samsung,exynos5250-wdt 75 74 - samsung,exynos5420-wdt 76 75 - samsung,exynos7-wdt ··· 85 82 compatible: 86 83 contains: 87 84 enum: 85 + - google,gs101-wdt 88 86 - samsung,exynos850-wdt 89 87 - samsung,exynosautov9-wdt 90 88 then:
+8 -10
MAINTAINERS
··· 1931 1931 F: drivers/iommu/apple-dart.c 1932 1932 F: drivers/iommu/io-pgtable-dart.c 1933 1933 F: drivers/irqchip/irq-apple-aic.c 1934 - F: drivers/mailbox/apple-mailbox.c 1935 1934 F: drivers/nvme/host/apple.c 1936 1935 F: drivers/nvmem/apple-efuses.c 1937 1936 F: drivers/pinctrl/pinctrl-apple-gpio.c ··· 1939 1940 F: drivers/watchdog/apple_wdt.c 1940 1941 F: include/dt-bindings/interrupt-controller/apple-aic.h 1941 1942 F: include/dt-bindings/pinctrl/apple.h 1942 - F: include/linux/apple-mailbox.h 1943 1943 F: include/linux/soc/apple/* 1944 1944 1945 1945 ARM/ARTPEC MACHINE SUPPORT ··· 2542 2544 F: arch/arm64/boot/dts/qcom/sdm845-cheza* 2543 2545 2544 2546 ARM/QUALCOMM SUPPORT 2545 - M: Andy Gross <agross@kernel.org> 2546 2547 M: Bjorn Andersson <andersson@kernel.org> 2547 2548 M: Konrad Dybcio <konrad.dybcio@linaro.org> 2548 2549 L: linux-arm-msm@vger.kernel.org ··· 18641 18644 F: arch/riscv/boot/dts/microchip/ 18642 18645 F: drivers/char/hw_random/mpfs-rng.c 18643 18646 F: drivers/clk/microchip/clk-mpfs*.c 18647 + F: drivers/firmware/microchip/mpfs-auto-update.c 18644 18648 F: drivers/i2c/busses/i2c-microchip-corei2c.c 18645 18649 F: drivers/mailbox/mailbox-mpfs.c 18646 18650 F: drivers/pci/controller/pcie-microchip-host.c ··· 19777 19779 N: sifive 19778 19780 K: [^@]sifive 19779 19781 19782 + SIFIVE CACHE DRIVER 19783 + M: Conor Dooley <conor@kernel.org> 19784 + L: linux-riscv@lists.infradead.org 19785 + S: Maintained 19786 + F: Documentation/devicetree/bindings/cache/sifive,ccache0.yaml 19787 + F: drivers/cache/sifive_ccache.c 19788 + 19780 19789 SIFIVE FU540 SYSTEM-ON-CHIP 19781 19790 M: Paul Walmsley <paul.walmsley@sifive.com> 19782 19791 M: Palmer Dabbelt <palmer@dabbelt.com> ··· 19799 19794 F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml 19800 19795 F: drivers/dma/sf-pdma/ 19801 19796 19802 - SIFIVE SOC DRIVERS 19803 - M: Conor Dooley <conor@kernel.org> 19804 - L: linux-riscv@lists.infradead.org 19805 - S: Maintained 19806 - T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ 19807 - F: Documentation/devicetree/bindings/cache/sifive,ccache0.yaml 19808 - F: drivers/soc/sifive/ 19809 19797 19810 19798 SILEAD TOUCHSCREEN DRIVER 19811 19799 M: Hans de Goede <hdegoede@redhat.com>
+19
arch/riscv/Kconfig.errata
··· 53 53 54 54 If you don't know what to do here, say "Y". 55 55 56 + config ERRATA_STARFIVE_JH7100 57 + bool "StarFive JH7100 support" 58 + depends on ARCH_STARFIVE 59 + depends on !DMA_DIRECT_REMAP 60 + depends on NONPORTABLE 61 + select DMA_GLOBAL_POOL 62 + select RISCV_DMA_NONCOHERENT 63 + select RISCV_NONSTANDARD_CACHE_OPS 64 + select SIFIVE_CCACHE 65 + default n 66 + help 67 + The StarFive JH7100 was a test chip for the JH7110 and has 68 + caches that are non-coherent with respect to peripheral DMAs. 69 + It was designed before the Zicbom extension so needs non-standard 70 + cache operations through the SiFive cache controller. 71 + 72 + Say "Y" if you want to support the BeagleV Starlight and/or 73 + StarFive VisionFive V1 boards. 74 + 56 75 config ERRATA_THEAD 57 76 bool "T-HEAD errata" 58 77 depends on RISCV_ALTERNATIVE
+3 -13
drivers/bus/fsl-mc/fsl-mc-bus.c
··· 1167 1167 * fsl_mc_bus_remove - callback invoked when the root MC bus is being 1168 1168 * removed 1169 1169 */ 1170 - static int fsl_mc_bus_remove(struct platform_device *pdev) 1170 + static void fsl_mc_bus_remove(struct platform_device *pdev) 1171 1171 { 1172 1172 struct fsl_mc *mc = platform_get_drvdata(pdev); 1173 1173 struct fsl_mc_io *mc_io; 1174 - 1175 - if (!fsl_mc_is_root_dprc(&mc->root_mc_bus_dev->dev)) 1176 - return -EINVAL; 1177 1174 1178 1175 mc_io = mc->root_mc_bus_dev->mc_io; 1179 1176 fsl_mc_device_remove(mc->root_mc_bus_dev); ··· 1187 1190 (GCR1_P1_STOP | GCR1_P2_STOP), 1188 1191 mc->fsl_mc_regs + FSL_MC_GCR1); 1189 1192 } 1190 - 1191 - return 0; 1192 - } 1193 - 1194 - static void fsl_mc_bus_shutdown(struct platform_device *pdev) 1195 - { 1196 - fsl_mc_bus_remove(pdev); 1197 1193 } 1198 1194 1199 1195 static const struct of_device_id fsl_mc_bus_match_table[] = { ··· 1210 1220 .acpi_match_table = fsl_mc_bus_acpi_match_table, 1211 1221 }, 1212 1222 .probe = fsl_mc_bus_probe, 1213 - .remove = fsl_mc_bus_remove, 1214 - .shutdown = fsl_mc_bus_shutdown, 1223 + .remove_new = fsl_mc_bus_remove, 1224 + .shutdown = fsl_mc_bus_remove, 1215 1225 }; 1216 1226 1217 1227 static int fsl_mc_bus_notifier(struct notifier_block *nb,
+2 -4
drivers/bus/hisi_lpc.c
··· 657 657 return ret; 658 658 } 659 659 660 - static int hisi_lpc_remove(struct platform_device *pdev) 660 + static void hisi_lpc_remove(struct platform_device *pdev) 661 661 { 662 662 struct device *dev = &pdev->dev; 663 663 struct hisi_lpc_dev *lpcdev = dev_get_drvdata(dev); ··· 669 669 of_platform_depopulate(dev); 670 670 671 671 logic_pio_unregister_range(range); 672 - 673 - return 0; 674 672 } 675 673 676 674 static const struct of_device_id hisi_lpc_of_match[] = { ··· 689 691 .acpi_match_table = hisi_lpc_acpi_match, 690 692 }, 691 693 .probe = hisi_lpc_probe, 692 - .remove = hisi_lpc_remove, 694 + .remove_new = hisi_lpc_remove, 693 695 }; 694 696 builtin_platform_driver(hisi_lpc_driver);
+5 -4
drivers/bus/imx-weim.c
··· 11 11 #include <linux/clk.h> 12 12 #include <linux/io.h> 13 13 #include <linux/of_address.h> 14 - #include <linux/of_device.h> 14 + #include <linux/of.h> 15 + #include <linux/of_platform.h> 16 + #include <linux/platform_device.h> 17 + #include <linux/property.h> 15 18 #include <linux/mfd/syscon.h> 16 19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 17 20 #include <linux/regmap.h> ··· 205 202 206 203 static int weim_parse_dt(struct platform_device *pdev) 207 204 { 208 - const struct of_device_id *of_id = of_match_device(weim_id_table, 209 - &pdev->dev); 210 - const struct imx_weim_devtype *devtype = of_id->data; 205 + const struct imx_weim_devtype *devtype = device_get_match_data(&pdev->dev); 211 206 int ret = 0, have_child = 0; 212 207 struct device_node *child; 213 208 struct weim_priv *priv;
+8 -1
drivers/bus/moxtet.c
··· 755 755 moxtet->irq.masked = ~0; 756 756 757 757 ret = request_threaded_irq(moxtet->dev_irq, NULL, moxtet_irq_thread_fn, 758 - IRQF_ONESHOT, "moxtet", moxtet); 758 + IRQF_SHARED | IRQF_ONESHOT, "moxtet", moxtet); 759 759 if (ret < 0) 760 760 goto err_free; 761 761 ··· 830 830 mutex_destroy(&moxtet->lock); 831 831 } 832 832 833 + static const struct spi_device_id moxtet_spi_ids[] = { 834 + { "moxtet" }, 835 + { }, 836 + }; 837 + MODULE_DEVICE_TABLE(spi, moxtet_spi_ids); 838 + 833 839 static const struct of_device_id moxtet_dt_ids[] = { 834 840 { .compatible = "cznic,moxtet" }, 835 841 {}, ··· 847 841 .name = "moxtet", 848 842 .of_match_table = moxtet_dt_ids, 849 843 }, 844 + .id_table = moxtet_spi_ids, 850 845 .probe = moxtet_probe, 851 846 .remove = moxtet_remove, 852 847 };
+2 -4
drivers/bus/omap-ocp2scp.c
··· 84 84 return ret; 85 85 } 86 86 87 - static int omap_ocp2scp_remove(struct platform_device *pdev) 87 + static void omap_ocp2scp_remove(struct platform_device *pdev) 88 88 { 89 89 pm_runtime_disable(&pdev->dev); 90 90 device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices); 91 - 92 - return 0; 93 91 } 94 92 95 93 #ifdef CONFIG_OF ··· 101 103 102 104 static struct platform_driver omap_ocp2scp_driver = { 103 105 .probe = omap_ocp2scp_probe, 104 - .remove = omap_ocp2scp_remove, 106 + .remove_new = omap_ocp2scp_remove, 105 107 .driver = { 106 108 .name = "omap-ocp2scp", 107 109 .of_match_table = of_match_ptr(omap_ocp2scp_id_table),
+2 -4
drivers/bus/omap_l3_smx.c
··· 261 261 return ret; 262 262 } 263 263 264 - static int omap3_l3_remove(struct platform_device *pdev) 264 + static void omap3_l3_remove(struct platform_device *pdev) 265 265 { 266 266 struct omap3_l3 *l3 = platform_get_drvdata(pdev); 267 267 ··· 269 269 free_irq(l3->debug_irq, l3); 270 270 iounmap(l3->rt); 271 271 kfree(l3); 272 - 273 - return 0; 274 272 } 275 273 276 274 static struct platform_driver omap3_l3_driver = { 277 275 .probe = omap3_l3_probe, 278 - .remove = omap3_l3_remove, 276 + .remove_new = omap3_l3_remove, 279 277 .driver = { 280 278 .name = "omap_l3_smx", 281 279 .of_match_table = of_match_ptr(omap3_l3_match),
+2 -4
drivers/bus/qcom-ssc-block-bus.c
··· 350 350 return 0; 351 351 } 352 352 353 - static int qcom_ssc_block_bus_remove(struct platform_device *pdev) 353 + static void qcom_ssc_block_bus_remove(struct platform_device *pdev) 354 354 { 355 355 struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev); 356 356 ··· 363 363 qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds); 364 364 pm_runtime_disable(&pdev->dev); 365 365 pm_clk_destroy(&pdev->dev); 366 - 367 - return 0; 368 366 } 369 367 370 368 static const struct of_device_id qcom_ssc_block_bus_of_match[] = { ··· 373 375 374 376 static struct platform_driver qcom_ssc_block_bus_driver = { 375 377 .probe = qcom_ssc_block_bus_probe, 376 - .remove = qcom_ssc_block_bus_remove, 378 + .remove_new = qcom_ssc_block_bus_remove, 377 379 .driver = { 378 380 .name = "qcom-ssc-block-bus", 379 381 .of_match_table = qcom_ssc_block_bus_of_match,
+3 -4
drivers/bus/simple-pm-bus.c
··· 74 74 return 0; 75 75 } 76 76 77 - static int simple_pm_bus_remove(struct platform_device *pdev) 77 + static void simple_pm_bus_remove(struct platform_device *pdev) 78 78 { 79 79 const void *data = of_device_get_match_data(&pdev->dev); 80 80 81 81 if (pdev->driver_override || data) 82 - return 0; 82 + return; 83 83 84 84 dev_dbg(&pdev->dev, "%s\n", __func__); 85 85 86 86 pm_runtime_disable(&pdev->dev); 87 - return 0; 88 87 } 89 88 90 89 static int simple_pm_bus_runtime_suspend(struct device *dev) ··· 128 129 129 130 static struct platform_driver simple_pm_bus_driver = { 130 131 .probe = simple_pm_bus_probe, 131 - .remove = simple_pm_bus_remove, 132 + .remove_new = simple_pm_bus_remove, 132 133 .driver = { 133 134 .name = "simple-pm-bus", 134 135 .of_match_table = simple_pm_bus_of_match,
+2 -3
drivers/bus/sun50i-de2.c
··· 24 24 return 0; 25 25 } 26 26 27 - static int sun50i_de2_bus_remove(struct platform_device *pdev) 27 + static void sun50i_de2_bus_remove(struct platform_device *pdev) 28 28 { 29 29 sunxi_sram_release(&pdev->dev); 30 - return 0; 31 30 } 32 31 33 32 static const struct of_device_id sun50i_de2_bus_of_match[] = { ··· 36 37 37 38 static struct platform_driver sun50i_de2_bus_driver = { 38 39 .probe = sun50i_de2_bus_probe, 39 - .remove = sun50i_de2_bus_remove, 40 + .remove_new = sun50i_de2_bus_remove, 40 41 .driver = { 41 42 .name = "sun50i-de2-bus", 42 43 .of_match_table = sun50i_de2_bus_of_match,
+2 -4
drivers/bus/sunxi-rsb.c
··· 817 817 return 0; 818 818 } 819 819 820 - static int sunxi_rsb_remove(struct platform_device *pdev) 820 + static void sunxi_rsb_remove(struct platform_device *pdev) 821 821 { 822 822 struct sunxi_rsb *rsb = platform_get_drvdata(pdev); 823 823 824 824 device_for_each_child(rsb->dev, NULL, sunxi_rsb_remove_devices); 825 825 pm_runtime_disable(&pdev->dev); 826 826 sunxi_rsb_hw_exit(rsb); 827 - 828 - return 0; 829 827 } 830 828 831 829 static const struct dev_pm_ops sunxi_rsb_dev_pm_ops = { ··· 840 842 841 843 static struct platform_driver sunxi_rsb_driver = { 842 844 .probe = sunxi_rsb_probe, 843 - .remove = sunxi_rsb_remove, 845 + .remove_new = sunxi_rsb_remove, 844 846 .driver = { 845 847 .name = RSB_CTRL_NAME, 846 848 .of_match_table = sunxi_rsb_of_match_table,
+2 -4
drivers/bus/tegra-aconnect.c
··· 53 53 return 0; 54 54 } 55 55 56 - static int tegra_aconnect_remove(struct platform_device *pdev) 56 + static void tegra_aconnect_remove(struct platform_device *pdev) 57 57 { 58 58 pm_runtime_disable(&pdev->dev); 59 - 60 - return 0; 61 59 } 62 60 63 61 static int tegra_aconnect_runtime_resume(struct device *dev) ··· 104 106 105 107 static struct platform_driver tegra_aconnect_driver = { 106 108 .probe = tegra_aconnect_probe, 107 - .remove = tegra_aconnect_remove, 109 + .remove_new = tegra_aconnect_remove, 108 110 .driver = { 109 111 .name = "tegra-aconnect", 110 112 .of_match_table = tegra_aconnect_of_match,
+2 -4
drivers/bus/tegra-gmi.c
··· 258 258 return 0; 259 259 } 260 260 261 - static int tegra_gmi_remove(struct platform_device *pdev) 261 + static void tegra_gmi_remove(struct platform_device *pdev) 262 262 { 263 263 struct tegra_gmi *gmi = platform_get_drvdata(pdev); 264 264 265 265 of_platform_depopulate(gmi->dev); 266 266 tegra_gmi_disable(gmi); 267 - 268 - return 0; 269 267 } 270 268 271 269 static int __maybe_unused tegra_gmi_runtime_resume(struct device *dev) ··· 303 305 304 306 static struct platform_driver tegra_gmi_driver = { 305 307 .probe = tegra_gmi_probe, 306 - .remove = tegra_gmi_remove, 308 + .remove_new = tegra_gmi_remove, 307 309 .driver = { 308 310 .name = "tegra-gmi", 309 311 .of_match_table = tegra_gmi_id_table,
+2 -3
drivers/bus/ti-pwmss.c
··· 33 33 return ret; 34 34 } 35 35 36 - static int pwmss_remove(struct platform_device *pdev) 36 + static void pwmss_remove(struct platform_device *pdev) 37 37 { 38 38 pm_runtime_disable(&pdev->dev); 39 - return 0; 40 39 } 41 40 42 41 static struct platform_driver pwmss_driver = { ··· 44 45 .of_match_table = pwmss_of_match, 45 46 }, 46 47 .probe = pwmss_probe, 47 - .remove = pwmss_remove, 48 + .remove_new = pwmss_remove, 48 49 }; 49 50 50 51 module_platform_driver(pwmss_driver);
+2 -4
drivers/bus/ti-sysc.c
··· 3397 3397 return error; 3398 3398 } 3399 3399 3400 - static int sysc_remove(struct platform_device *pdev) 3400 + static void sysc_remove(struct platform_device *pdev) 3401 3401 { 3402 3402 struct sysc *ddata = platform_get_drvdata(pdev); 3403 3403 int error; ··· 3422 3422 3423 3423 unprepare: 3424 3424 sysc_unprepare(ddata); 3425 - 3426 - return 0; 3427 3425 } 3428 3426 3429 3427 static const struct of_device_id sysc_match[] = { ··· 3447 3449 3448 3450 static struct platform_driver sysc_driver = { 3449 3451 .probe = sysc_probe, 3450 - .remove = sysc_remove, 3452 + .remove_new = sysc_remove, 3451 3453 .driver = { 3452 3454 .name = "ti-sysc", 3453 3455 .of_match_table = sysc_match,
+2 -4
drivers/bus/ts-nbus.c
··· 331 331 return 0; 332 332 } 333 333 334 - static int ts_nbus_remove(struct platform_device *pdev) 334 + static void ts_nbus_remove(struct platform_device *pdev) 335 335 { 336 336 struct ts_nbus *ts_nbus = dev_get_drvdata(&pdev->dev); 337 337 ··· 339 339 mutex_lock(&ts_nbus->lock); 340 340 pwm_disable(ts_nbus->pwm); 341 341 mutex_unlock(&ts_nbus->lock); 342 - 343 - return 0; 344 342 } 345 343 346 344 static const struct of_device_id ts_nbus_of_match[] = { ··· 349 351 350 352 static struct platform_driver ts_nbus_driver = { 351 353 .probe = ts_nbus_probe, 352 - .remove = ts_nbus_remove, 354 + .remove_new = ts_nbus_remove, 353 355 .driver = { 354 356 .name = "ts_nbus", 355 357 .of_match_table = ts_nbus_of_match,
+6
drivers/cache/Kconfig
··· 8 8 help 9 9 Support for the L2 cache controller on Andes Technology AX45MP platforms. 10 10 11 + config SIFIVE_CCACHE 12 + bool "Sifive Composable Cache controller" 13 + depends on ARCH_SIFIVE || ARCH_STARFIVE 14 + help 15 + Support for the composable cache controller on SiFive platforms. 16 + 11 17 endmenu
+2 -1
drivers/cache/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 3 - obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o 3 + obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o 4 + obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
+1
drivers/clk/samsung/Makefile
··· 21 21 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o 22 22 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o 23 23 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o 24 + obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o 24 25 obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o 25 26 obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o 26 27 obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
+2518
drivers/clk/samsung/clk-gs101.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (C) 2023 Linaro Ltd. 4 + * Author: Peter Griffin <peter.griffin@linaro.org> 5 + * 6 + * Common Clock Framework support for GS101. 7 + */ 8 + 9 + #include <linux/clk.h> 10 + #include <linux/clk-provider.h> 11 + #include <linux/of.h> 12 + #include <linux/platform_device.h> 13 + 14 + #include <dt-bindings/clock/google,gs101.h> 15 + 16 + #include "clk.h" 17 + #include "clk-exynos-arm64.h" 18 + 19 + /* NOTE: Must be equal to the last clock ID increased by one */ 20 + #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) 21 + #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) 22 + #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) 23 + 24 + /* ---- CMU_TOP ------------------------------------------------------------- */ 25 + 26 + /* Register Offset definitions for CMU_TOP (0x1e080000) */ 27 + 28 + #define PLL_LOCKTIME_PLL_SHARED0 0x0000 29 + #define PLL_LOCKTIME_PLL_SHARED1 0x0004 30 + #define PLL_LOCKTIME_PLL_SHARED2 0x0008 31 + #define PLL_LOCKTIME_PLL_SHARED3 0x000c 32 + #define PLL_LOCKTIME_PLL_SPARE 0x0010 33 + #define PLL_CON0_PLL_SHARED0 0x0100 34 + #define PLL_CON1_PLL_SHARED0 0x0104 35 + #define PLL_CON2_PLL_SHARED0 0x0108 36 + #define PLL_CON3_PLL_SHARED0 0x010c 37 + #define PLL_CON4_PLL_SHARED0 0x0110 38 + #define PLL_CON0_PLL_SHARED1 0x0140 39 + #define PLL_CON1_PLL_SHARED1 0x0144 40 + #define PLL_CON2_PLL_SHARED1 0x0148 41 + #define PLL_CON3_PLL_SHARED1 0x014c 42 + #define PLL_CON4_PLL_SHARED1 0x0150 43 + #define PLL_CON0_PLL_SHARED2 0x0180 44 + #define PLL_CON1_PLL_SHARED2 0x0184 45 + #define PLL_CON2_PLL_SHARED2 0x0188 46 + #define PLL_CON3_PLL_SHARED2 0x018c 47 + #define PLL_CON4_PLL_SHARED2 0x0190 48 + #define PLL_CON0_PLL_SHARED3 0x01c0 49 + #define PLL_CON1_PLL_SHARED3 0x01c4 50 + #define PLL_CON2_PLL_SHARED3 0x01c8 51 + #define PLL_CON3_PLL_SHARED3 0x01cc 52 + #define PLL_CON4_PLL_SHARED3 0x01d0 53 + #define PLL_CON0_PLL_SPARE 0x0200 54 + #define PLL_CON1_PLL_SPARE 0x0204 55 + #define PLL_CON2_PLL_SPARE 0x0208 56 + #define PLL_CON3_PLL_SPARE 0x020c 57 + #define PLL_CON4_PLL_SPARE 0x0210 58 + #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 59 + #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 60 + #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 61 + #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 62 + #define CMU_HCHGEN_CLKMUX 0x0850 63 + #define POWER_FAIL_DETECT_PLL 0x0864 64 + #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 65 + #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 66 + #define EARLY_WAKEUP_APM_CTRL 0x0878 67 + #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c 68 + #define EARLY_WAKEUP_DPU_CTRL 0x0880 69 + #define EARLY_WAKEUP_CSIS_CTRL 0x0884 70 + #define EARLY_WAKEUP_APM_DEST 0x0890 71 + #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 72 + #define EARLY_WAKEUP_DPU_DEST 0x0898 73 + #define EARLY_WAKEUP_CSIS_DEST 0x089c 74 + #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 75 + #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 76 + #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 77 + #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 78 + #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 79 + #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 80 + #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 81 + #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 82 + #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 83 + #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 84 + #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 85 + #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 86 + #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 87 + #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 88 + #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 89 + #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c 90 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 91 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 92 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 93 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c 94 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 95 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 96 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 97 + #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c 98 + #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 99 + #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 100 + #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 101 + #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c 102 + #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 103 + #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 104 + #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 105 + #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c 106 + #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 107 + #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 108 + #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 109 + #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c 110 + #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 111 + #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 112 + #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 113 + #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c 114 + #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 115 + #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 116 + #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 117 + #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c 118 + #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 119 + #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 120 + #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 121 + #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c 122 + #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 123 + #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 124 + #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 125 + #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c 126 + #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 127 + #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 128 + #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 129 + #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac 130 + #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 131 + #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 132 + #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 133 + #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc 134 + #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 135 + #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 136 + #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 137 + #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc 138 + #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 139 + #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 140 + #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 141 + #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc 142 + #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 143 + #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 144 + #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 145 + #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec 146 + #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 147 + #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 148 + #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 149 + #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc 150 + #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 151 + #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 152 + #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 153 + #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 154 + #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 155 + #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 156 + #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c 157 + #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 158 + #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 159 + #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 160 + #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c 161 + #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 162 + #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 163 + #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 164 + #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c 165 + #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 166 + #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 167 + #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 168 + #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c 169 + #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 170 + #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 171 + #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 172 + #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c 173 + #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 174 + #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 175 + #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 176 + #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c 177 + #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 178 + #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 179 + #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 180 + #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c 181 + #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 182 + #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 183 + #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 184 + #define CLK_CON_DIV_CLKCMU_HPM 0x187c 185 + #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 186 + #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 187 + #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 188 + #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c 189 + #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 190 + #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 191 + #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 192 + #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c 193 + #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 194 + #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 195 + #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 196 + #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac 197 + #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 198 + #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 199 + #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 200 + #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc 201 + #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 202 + #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 203 + #define CLK_CON_DIV_CLKCMU_OTP 0x18c8 204 + #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc 205 + #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 206 + #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 207 + #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 208 + #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc 209 + #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 210 + #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 211 + #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 212 + #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec 213 + #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 214 + #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 215 + #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 216 + #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc 217 + #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 218 + #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 219 + #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 220 + #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c 221 + #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 222 + #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 223 + #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 224 + #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c 225 + #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 226 + #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 227 + #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 228 + #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 229 + #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c 230 + #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 231 + #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 232 + #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 233 + #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c 234 + #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 235 + #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 236 + #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 237 + #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c 238 + #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 239 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 240 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 241 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c 242 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 243 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 244 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 245 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c 246 + #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 247 + #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 248 + #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 249 + #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c 250 + #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 251 + #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 252 + #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 253 + #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c 254 + #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 255 + #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 256 + #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 257 + #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c 258 + #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 259 + #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 260 + #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 261 + #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c 262 + #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 263 + #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 264 + #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 265 + #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c 266 + #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 267 + #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 268 + #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 269 + #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac 270 + #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 271 + #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 272 + #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 273 + #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc 274 + #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 275 + #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 276 + #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 277 + #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc 278 + #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 279 + #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 280 + #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 281 + #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc 282 + #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 283 + #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 284 + #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 285 + #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec 286 + #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 287 + #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 288 + #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 289 + #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc 290 + #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 291 + #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 292 + #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 293 + #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c 294 + #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 295 + #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 296 + #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 297 + #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c 298 + #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 299 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 300 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 301 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c 302 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 303 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 304 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 305 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c 306 + #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 307 + #define DMYQCH_CON_OTP_QCH 0x3024 308 + #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 309 + #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 310 + #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 311 + #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 312 + #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c 313 + #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 314 + #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 315 + #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 316 + #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c 317 + #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 318 + #define MIFMIRROR_QUEUE_ENTRY0 0x3e10 319 + #define MIFMIRROR_QUEUE_ENTRY1 0x3e14 320 + #define MIFMIRROR_QUEUE_ENTRY2 0x3e18 321 + #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c 322 + #define MIFMIRROR_QUEUE_ENTRY4 0x3e20 323 + #define MIFMIRROR_QUEUE_ENTRY5 0x3e24 324 + #define MIFMIRROR_QUEUE_ENTRY6 0x3e28 325 + #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c 326 + #define MIFMIRROR_QUEUE_BUSY 0x3e30 327 + #define GENERALIO_ACD_CHANNEL_0 0x3f00 328 + #define GENERALIO_ACD_CHANNEL_1 0x3f04 329 + #define GENERALIO_ACD_CHANNEL_2 0x3f08 330 + #define GENERALIO_ACD_CHANNEL_3 0x3f0c 331 + #define GENERALIO_ACD_MASK 0x3f14 332 + 333 + static const unsigned long cmu_top_clk_regs[] __initconst = { 334 + PLL_LOCKTIME_PLL_SHARED0, 335 + PLL_LOCKTIME_PLL_SHARED1, 336 + PLL_LOCKTIME_PLL_SHARED2, 337 + PLL_LOCKTIME_PLL_SHARED3, 338 + PLL_LOCKTIME_PLL_SPARE, 339 + PLL_CON0_PLL_SHARED0, 340 + PLL_CON1_PLL_SHARED0, 341 + PLL_CON2_PLL_SHARED0, 342 + PLL_CON3_PLL_SHARED0, 343 + PLL_CON4_PLL_SHARED0, 344 + PLL_CON0_PLL_SHARED1, 345 + PLL_CON1_PLL_SHARED1, 346 + PLL_CON2_PLL_SHARED1, 347 + PLL_CON3_PLL_SHARED1, 348 + PLL_CON4_PLL_SHARED1, 349 + PLL_CON0_PLL_SHARED2, 350 + PLL_CON1_PLL_SHARED2, 351 + PLL_CON2_PLL_SHARED2, 352 + PLL_CON3_PLL_SHARED2, 353 + PLL_CON4_PLL_SHARED2, 354 + PLL_CON0_PLL_SHARED3, 355 + PLL_CON1_PLL_SHARED3, 356 + PLL_CON2_PLL_SHARED3, 357 + PLL_CON3_PLL_SHARED3, 358 + PLL_CON4_PLL_SHARED3, 359 + PLL_CON0_PLL_SPARE, 360 + PLL_CON1_PLL_SPARE, 361 + PLL_CON2_PLL_SPARE, 362 + PLL_CON3_PLL_SPARE, 363 + PLL_CON4_PLL_SPARE, 364 + CMU_CMU_TOP_CONTROLLER_OPTION, 365 + CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, 366 + CMU_HCHGEN_CLKMUX_CMU_BOOST, 367 + CMU_HCHGEN_CLKMUX_TOP_BOOST, 368 + CMU_HCHGEN_CLKMUX, 369 + POWER_FAIL_DETECT_PLL, 370 + EARLY_WAKEUP_FORCED_0_ENABLE, 371 + EARLY_WAKEUP_FORCED_1_ENABLE, 372 + EARLY_WAKEUP_APM_CTRL, 373 + EARLY_WAKEUP_CLUSTER0_CTRL, 374 + EARLY_WAKEUP_DPU_CTRL, 375 + EARLY_WAKEUP_CSIS_CTRL, 376 + EARLY_WAKEUP_APM_DEST, 377 + EARLY_WAKEUP_CLUSTER0_DEST, 378 + EARLY_WAKEUP_DPU_DEST, 379 + EARLY_WAKEUP_CSIS_DEST, 380 + EARLY_WAKEUP_SW_TRIG_APM, 381 + EARLY_WAKEUP_SW_TRIG_APM_SET, 382 + EARLY_WAKEUP_SW_TRIG_APM_CLEAR, 383 + EARLY_WAKEUP_SW_TRIG_CLUSTER0, 384 + EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET, 385 + EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR, 386 + EARLY_WAKEUP_SW_TRIG_DPU, 387 + EARLY_WAKEUP_SW_TRIG_DPU_SET, 388 + EARLY_WAKEUP_SW_TRIG_DPU_CLEAR, 389 + EARLY_WAKEUP_SW_TRIG_CSIS, 390 + EARLY_WAKEUP_SW_TRIG_CSIS_SET, 391 + EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR, 392 + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 393 + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 394 + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 395 + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 396 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 397 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 398 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 399 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 400 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 401 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 402 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 403 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 404 + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 405 + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 406 + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 407 + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 408 + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 409 + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 410 + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 411 + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 412 + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 413 + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 414 + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 415 + CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 416 + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 417 + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 418 + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 419 + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 420 + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 421 + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 422 + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 423 + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 424 + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 425 + CLK_CON_MUX_MUX_CLKCMU_HPM, 426 + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 427 + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 428 + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 429 + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 430 + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 431 + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 432 + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 433 + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 434 + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 435 + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 436 + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 437 + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 438 + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 439 + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 440 + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 441 + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 442 + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 443 + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 444 + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 445 + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 446 + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 447 + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 448 + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 449 + CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 450 + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 451 + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 452 + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 453 + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 454 + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 455 + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 456 + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 457 + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 458 + CLK_CON_MUX_MUX_CMU_CMUREF, 459 + CLK_CON_DIV_CLKCMU_BO_BUS, 460 + CLK_CON_DIV_CLKCMU_BUS0_BUS, 461 + CLK_CON_DIV_CLKCMU_BUS1_BUS, 462 + CLK_CON_DIV_CLKCMU_BUS2_BUS, 463 + CLK_CON_DIV_CLKCMU_CIS_CLK0, 464 + CLK_CON_DIV_CLKCMU_CIS_CLK1, 465 + CLK_CON_DIV_CLKCMU_CIS_CLK2, 466 + CLK_CON_DIV_CLKCMU_CIS_CLK3, 467 + CLK_CON_DIV_CLKCMU_CIS_CLK4, 468 + CLK_CON_DIV_CLKCMU_CIS_CLK5, 469 + CLK_CON_DIV_CLKCMU_CIS_CLK6, 470 + CLK_CON_DIV_CLKCMU_CIS_CLK7, 471 + CLK_CON_DIV_CLKCMU_CORE_BUS, 472 + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 473 + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 474 + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 475 + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 476 + CLK_CON_DIV_CLKCMU_CSIS_BUS, 477 + CLK_CON_DIV_CLKCMU_DISP_BUS, 478 + CLK_CON_DIV_CLKCMU_DNS_BUS, 479 + CLK_CON_DIV_CLKCMU_DPU_BUS, 480 + CLK_CON_DIV_CLKCMU_EH_BUS, 481 + CLK_CON_DIV_CLKCMU_G2D_G2D, 482 + CLK_CON_DIV_CLKCMU_G2D_MSCL, 483 + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 484 + CLK_CON_DIV_CLKCMU_G3D_BUSD, 485 + CLK_CON_DIV_CLKCMU_G3D_GLB, 486 + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 487 + CLK_CON_DIV_CLKCMU_GDC_GDC0, 488 + CLK_CON_DIV_CLKCMU_GDC_GDC1, 489 + CLK_CON_DIV_CLKCMU_GDC_SCSC, 490 + CLK_CON_DIV_CLKCMU_HPM, 491 + CLK_CON_DIV_CLKCMU_HSI0_BUS, 492 + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 493 + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 494 + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 495 + CLK_CON_DIV_CLKCMU_HSI1_BUS, 496 + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 497 + CLK_CON_DIV_CLKCMU_HSI2_BUS, 498 + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 499 + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 500 + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 501 + CLK_CON_DIV_CLKCMU_IPP_BUS, 502 + CLK_CON_DIV_CLKCMU_ITP_BUS, 503 + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 504 + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 505 + CLK_CON_DIV_CLKCMU_MFC_MFC, 506 + CLK_CON_DIV_CLKCMU_MIF_BUSP, 507 + CLK_CON_DIV_CLKCMU_MISC_BUS, 508 + CLK_CON_DIV_CLKCMU_MISC_SSS, 509 + CLK_CON_DIV_CLKCMU_OTP, 510 + CLK_CON_DIV_CLKCMU_PDP_BUS, 511 + CLK_CON_DIV_CLKCMU_PDP_VRA, 512 + CLK_CON_DIV_CLKCMU_PERIC0_BUS, 513 + CLK_CON_DIV_CLKCMU_PERIC0_IP, 514 + CLK_CON_DIV_CLKCMU_PERIC1_BUS, 515 + CLK_CON_DIV_CLKCMU_PERIC1_IP, 516 + CLK_CON_DIV_CLKCMU_TNR_BUS, 517 + CLK_CON_DIV_CLKCMU_TPU_BUS, 518 + CLK_CON_DIV_CLKCMU_TPU_TPU, 519 + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 520 + CLK_CON_DIV_CLKCMU_TPU_UART, 521 + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 522 + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 523 + CLK_CON_DIV_PLL_SHARED0_DIV2, 524 + CLK_CON_DIV_PLL_SHARED0_DIV3, 525 + CLK_CON_DIV_PLL_SHARED0_DIV4, 526 + CLK_CON_DIV_PLL_SHARED0_DIV5, 527 + CLK_CON_DIV_PLL_SHARED1_DIV2, 528 + CLK_CON_DIV_PLL_SHARED1_DIV3, 529 + CLK_CON_DIV_PLL_SHARED1_DIV4, 530 + CLK_CON_DIV_PLL_SHARED2_DIV2, 531 + CLK_CON_DIV_PLL_SHARED3_DIV2, 532 + CLK_CON_GAT_CLKCMU_BUS0_BOOST, 533 + CLK_CON_GAT_CLKCMU_BUS1_BOOST, 534 + CLK_CON_GAT_CLKCMU_BUS2_BOOST, 535 + CLK_CON_GAT_CLKCMU_CORE_BOOST, 536 + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 537 + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 538 + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 539 + CLK_CON_GAT_CLKCMU_MIF_BOOST, 540 + CLK_CON_GAT_CLKCMU_MIF_SWITCH, 541 + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 542 + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 543 + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 544 + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 545 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 546 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 547 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 548 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 549 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 550 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 551 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 552 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 553 + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 554 + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 555 + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 556 + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 557 + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 558 + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 559 + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 560 + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 561 + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 562 + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 563 + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 564 + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 565 + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 566 + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, 567 + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 568 + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 569 + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 570 + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 571 + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 572 + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 573 + CLK_CON_GAT_GATE_CLKCMU_HPM, 574 + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 575 + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 576 + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 577 + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 578 + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 579 + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 580 + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 581 + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 582 + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 583 + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 584 + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 585 + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 586 + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 587 + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 588 + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 589 + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 590 + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 591 + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 592 + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 593 + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, 594 + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 595 + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 596 + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 597 + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 598 + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 599 + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 600 + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 601 + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 602 + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 603 + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 604 + DMYQCH_CON_CMU_TOP_CMUREF_QCH, 605 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 606 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 607 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 608 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 609 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 610 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 611 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, 612 + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, 613 + DMYQCH_CON_OTP_QCH, 614 + QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, 615 + QUEUE_ENTRY0_BLK_CMU_CMU_TOP, 616 + QUEUE_ENTRY1_BLK_CMU_CMU_TOP, 617 + QUEUE_ENTRY2_BLK_CMU_CMU_TOP, 618 + QUEUE_ENTRY3_BLK_CMU_CMU_TOP, 619 + QUEUE_ENTRY4_BLK_CMU_CMU_TOP, 620 + QUEUE_ENTRY5_BLK_CMU_CMU_TOP, 621 + QUEUE_ENTRY6_BLK_CMU_CMU_TOP, 622 + QUEUE_ENTRY7_BLK_CMU_CMU_TOP, 623 + MIFMIRROR_QUEUE_CTRL_REG, 624 + MIFMIRROR_QUEUE_ENTRY0, 625 + MIFMIRROR_QUEUE_ENTRY1, 626 + MIFMIRROR_QUEUE_ENTRY2, 627 + MIFMIRROR_QUEUE_ENTRY3, 628 + MIFMIRROR_QUEUE_ENTRY4, 629 + MIFMIRROR_QUEUE_ENTRY5, 630 + MIFMIRROR_QUEUE_ENTRY6, 631 + MIFMIRROR_QUEUE_ENTRY7, 632 + MIFMIRROR_QUEUE_BUSY, 633 + GENERALIO_ACD_CHANNEL_0, 634 + GENERALIO_ACD_CHANNEL_1, 635 + GENERALIO_ACD_CHANNEL_2, 636 + GENERALIO_ACD_CHANNEL_3, 637 + GENERALIO_ACD_MASK, 638 + }; 639 + 640 + static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { 641 + /* CMU_TOP_PURECLKCOMP */ 642 + PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 643 + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 644 + NULL), 645 + PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 646 + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 647 + NULL), 648 + PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", 649 + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, 650 + NULL), 651 + PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", 652 + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, 653 + NULL), 654 + PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", 655 + PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, 656 + NULL), 657 + }; 658 + 659 + /* List of parent clocks for Muxes in CMU_TOP */ 660 + PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" }; 661 + PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" }; 662 + PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" }; 663 + PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" }; 664 + PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" }; 665 + PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 666 + "fout_shared3_pll", "dout_cmu_shared1_div3", 667 + "dout_cmu_shared0_div4", 668 + "dout_cmu_shared1_div4", 669 + "fout_spare_pll", "oscclk" }; 670 + PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4", 671 + "dout_cmu_shared1_div4", 672 + "dout_cmu_shared2_div2", 673 + "dout_cmu_shared3_div2", 674 + "fout_spare_pll", "oscclk", 675 + "oscclk", "oscclk" }; 676 + PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 677 + "dout_cmu_shared1_div3", 678 + "dout_cmu_shared0_div4", 679 + "dout_cmu_shared1_div4", 680 + "dout_cmu_shared2_div2", 681 + "fout_spare_pll", "oscclk" }; 682 + PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2", 683 + "dout_cmu_shared1_div2", 684 + "fout_shared2_pll", "fout_shared3_pll", 685 + "dout_cmu_shared0_div3", 686 + "dout_cmu_shared1_div3", 687 + "dout_cmu_shared0_div5", "fout_spare_pll" }; 688 + PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3", 689 + "dout_cmu_shared1_div3", 690 + "dout_cmu_shared2_div2", 691 + "dout_cmu_shared3_div2", "fout_spare_pll", 692 + "oscclk", "oscclk" }; 693 + PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4", 694 + "dout_cmu_shared1_div4", 695 + "dout_cmu_shared2_div2", 696 + "dout_cmu_shared3_div2" }; 697 + PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost", 698 + "gout_cmu_boost_option1" }; 699 + PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2", 700 + "dout_cmu_shared1_div2", 701 + "fout_shared2_pll", "fout_shared3_pll", 702 + "dout_cmu_shared0_div3", 703 + "dout_cmu_shared1_div3", 704 + "dout_cmu_shared0_div5", "fout_spare_pll" }; 705 + PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", 706 + "dout_cmu_shared0_div4", 707 + "dout_cmu_shared1_div4", 708 + "dout_cmu_shared2_div2", "fout_spare_pll", 709 + "oscclk", "oscclk" }; 710 + PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 711 + "dout_cmu_shared1_div2", "fout_shared2_pll", 712 + "fout_shared3_pll", "dout_cmu_shared0_div3", 713 + "dout_cmu_shared1_div3", "fout_spare_pll" }; 714 + PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 715 + "dout_cmu_shared1_div2", "fout_shared2_pll", 716 + "fout_shared3_pll", "dout_cmu_shared0_div3", 717 + "dout_cmu_shared1_div3", "fout_spare_pll" }; 718 + PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 719 + "dout_cmu_shared1_div2", "fout_shared2_pll", 720 + "fout_shared3_pll", "dout_cmu_shared0_div3", 721 + "dout_cmu_shared1_div3", "fout_spare_pll" }; 722 + PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 723 + "dout_cmu_shared1_div3", 724 + "dout_cmu_shared0_div4", 725 + "dout_cmu_shared1_div4", 726 + "dout_cmu_shared2_div2", 727 + "fout_spare_pll", "oscclk" }; 728 + PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 729 + "dout_cmu_shared1_div3", 730 + "dout_cmu_shared0_div4", 731 + "dout_cmu_shared1_div4", 732 + "dout_cmu_shared2_div2", 733 + "fout_spare_pll", "oscclk" }; 734 + PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 735 + "dout_cmu_shared1_div3", 736 + "dout_cmu_shared0_div4", 737 + "dout_cmu_shared1_div4", 738 + "dout_cmu_shared2_div2", 739 + "fout_spare_pll", "oscclk" }; 740 + PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3", 741 + "fout_shared3_pll", 742 + "dout_cmu_shared1_div3", 743 + "dout_cmu_shared0_div4", 744 + "dout_cmu_shared1_div4", 745 + "dout_cmu_shared2_div2", 746 + "fout_spare_pll", "oscclk" }; 747 + PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2", 748 + "dout_cmu_shared1_div2", 749 + "fout_shared2_pll", "fout_shared3_pll", 750 + "dout_cmu_shared0_div3", 751 + "dout_cmu_shared1_div3", 752 + "dout_cmu_shared0_div5", "fout_spare_pll" }; 753 + PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 754 + "dout_cmu_shared1_div3", 755 + "dout_cmu_shared0_div4", 756 + "dout_cmu_shared1_div4", 757 + "dout_cmu_shared2_div2", 758 + "fout_spare_pll", "oscclk" }; 759 + PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4", 760 + "dout_cmu_shared1_div4", 761 + "dout_cmu_shared2_div2", 762 + "dout_cmu_shared3_div2", 763 + "fout_spare_pll", "oscclk", 764 + "oscclk", "oscclk" }; 765 + PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 766 + "dout_cmu_shared1_div3", 767 + "dout_cmu_shared0_div4", 768 + "dout_cmu_shared1_div4", 769 + "dout_cmu_shared2_div2", 770 + "fout_spare_pll", "oscclk" }; 771 + PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2", 772 + "dout_cmu_shared1_div2", 773 + "fout_shared2_pll", "fout_shared3_pll", 774 + "dout_cmu_shared0_div3", 775 + "dout_cmu_shared1_div3", 776 + "dout_cmu_shared0_div4", "fout_spare_pll" }; 777 + PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2", 778 + "dout_cmu_shared1_div2", 779 + "fout_shared2_pll", "fout_shared3_pll", 780 + "dout_cmu_shared0_div3", 781 + "dout_cmu_shared1_div3", 782 + "dout_cmu_shared0_div4", "fout_spare_pll" }; 783 + PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 784 + "fout_shared3_pll", "dout_cmu_shared1_div3", 785 + "dout_cmu_shared0_div4", 786 + "dout_cmu_shared1_div4", 787 + "fout_spare_pll", "fout_spare_pll"}; 788 + PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 789 + "dout_cmu_shared1_div3", 790 + "dout_cmu_shared0_div4", 791 + "dout_cmu_shared1_div4", 792 + "dout_cmu_shared2_div2", 793 + "fout_spare_pll", "oscclk" }; 794 + PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 795 + "dout_cmu_shared1_div3", 796 + "dout_cmu_shared0_div4", 797 + "dout_cmu_shared1_div4", 798 + "dout_cmu_shared2_div2", 799 + "fout_spare_pll", "oscclk" }; 800 + PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 801 + "dout_cmu_shared1_div3", 802 + "dout_cmu_shared0_div4", 803 + "dout_cmu_shared1_div4", 804 + "dout_cmu_shared2_div2", 805 + "fout_spare_pll", "oscclk" }; 806 + PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3", 807 + "dout_cmu_shared0_div4", 808 + "dout_cmu_shared2_div2" }; 809 + PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4", 810 + "dout_cmu_shared1_div4", 811 + "dout_cmu_shared2_div2", 812 + "dout_cmu_shared3_div2", 813 + "fout_spare_pll", "oscclk", 814 + "oscclk", "oscclk" }; 815 + PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4", 816 + "dout_cmu_shared2_div2", "fout_spare_pll" }; 817 + PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" }; 818 + PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" }; 819 + PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4", 820 + "dout_cmu_shared1_div4", 821 + "dout_cmu_shared2_div2", 822 + "dout_cmu_shared3_div2", 823 + "fout_spare_pll" }; 824 + PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" }; 825 + PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4", 826 + "dout_cmu_shared1_div4", 827 + "dout_cmu_shared2_div2", 828 + "dout_cmu_shared3_div2", 829 + "fout_spare_pll", "oscclk", 830 + "oscclk", "oscclk" }; 831 + PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", 832 + "dout_cmu_shared0_div4", "fout_spare_pll" }; 833 + PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" }; 834 + PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4", 835 + "dout_cmu_shared2_div2", "fout_spare_pll" }; 836 + PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 837 + "dout_cmu_shared1_div3", 838 + "dout_cmu_shared0_div4", 839 + "dout_cmu_shared1_div4", 840 + "dout_cmu_shared2_div2", 841 + "fout_spare_pll", "oscclk" }; 842 + PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 843 + "dout_cmu_shared1_div3", 844 + "dout_cmu_shared0_div4", 845 + "dout_cmu_shared1_div4", 846 + "dout_cmu_shared2_div2", 847 + "fout_spare_pll", "oscclk" }; 848 + PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 849 + "dout_cmu_shared1_div3", 850 + "dout_cmu_shared0_div4", 851 + "dout_cmu_shared1_div4", 852 + "dout_cmu_shared2_div2", 853 + "fout_spare_pll", "oscclk" }; 854 + PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 855 + "dout_cmu_shared1_div3", 856 + "dout_cmu_shared0_div4", 857 + "dout_cmu_shared1_div4", 858 + "dout_cmu_shared2_div2", 859 + "fout_spare_pll", "oscclk" }; 860 + PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 861 + "dout_cmu_shared0_div4", 862 + "dout_cmu_shared1_div4", 863 + "dout_cmu_shared2_div2", "fout_spare_pll", 864 + "oscclk", "oscclk" }; 865 + PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4", 866 + "dout_cmu_shared1_div4", 867 + "dout_cmu_shared0_div5", "fout_spare_pll" }; 868 + PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", 869 + "dout_cmu_shared0_div2", 870 + "dout_cmu_shared1_div2", 871 + "fout_shared2_pll", "dout_cmu_shared0_div3", 872 + "fout_shared3_pll", "fout_spare_pll" }; 873 + PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4", 874 + "dout_cmu_shared2_div2", 875 + "dout_cmu_shared3_div2", "fout_spare_pll" }; 876 + PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4", 877 + "dout_cmu_shared2_div2", 878 + "dout_cmu_shared3_div2", "fout_spare_pll" }; 879 + PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 880 + "dout_cmu_shared1_div3", 881 + "dout_cmu_shared0_div4", 882 + "dout_cmu_shared1_div4", 883 + "dout_cmu_shared2_div2", 884 + "fout_spare_pll", "oscclk" }; 885 + PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 886 + "fout_shared3_pll", "dout_cmu_shared1_div3", 887 + "dout_cmu_shared0_div4", 888 + "dout_cmu_shared1_div4", 889 + "fout_spare_pll", "oscclk" }; 890 + PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4", 891 + "dout_cmu_shared2_div2", 892 + "dout_cmu_shared3_div2", "fout_spare_pll" }; 893 + PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4", 894 + "dout_cmu_shared2_div2", 895 + "dout_cmu_shared3_div2", "fout_spare_pll" }; 896 + PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4", 897 + "dout_cmu_shared2_div2", 898 + "dout_cmu_shared3_div2", "fout_spare_pll" }; 899 + PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4", 900 + "dout_cmu_shared2_div2", 901 + "dout_cmu_shared3_div2", "fout_spare_pll" }; 902 + PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 903 + "dout_cmu_shared1_div3", 904 + "dout_cmu_shared0_div4", 905 + "dout_cmu_shared1_div4", 906 + "dout_cmu_shared2_div2", 907 + "fout_spare_pll", "oscclk" }; 908 + PNAME(mout_cmu_top_boost_option1_p) = { "oscclk", 909 + "gout_cmu_boost_option1" }; 910 + PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4", 911 + "dout_cmu_shared1_div4", 912 + "dout_cmu_shared2_div2", 913 + "dout_cmu_shared3_div2" }; 914 + PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2", 915 + "dout_cmu_shared1_div2", 916 + "fout_shared2_pll", 917 + "fout_shared3_pll", 918 + "dout_cmu_shared0_div3", 919 + "dout_cmu_shared1_div3", 920 + "dout_cmu_shared0_div4", 921 + "fout_spare_pll" }; 922 + PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2", 923 + "dout_cmu_shared1_div2", 924 + "fout_shared2_pll", 925 + "fout_shared3_pll", 926 + "dout_cmu_shared0_div3", 927 + "dout_cmu_shared1_div3", 928 + "dout_cmu_shared0_div4", "fout_spare_pll" }; 929 + PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2", 930 + "dout_cmu_shared1_div2", 931 + "fout_shared2_pll", "fout_shared3_pll", 932 + "dout_cmu_shared0_div3", 933 + "dout_cmu_shared1_div3", 934 + "dout_cmu_shared0_div4", "fout_spare_pll" }; 935 + PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4", 936 + "dout_cmu_shared2_div2", 937 + "dout_cmu_shared3_div2", "fout_spare_pll" }; 938 + PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", 939 + "dout_cmu_cmuref" }; 940 + 941 + /* 942 + * Register name to clock name mangling strategy used in this file 943 + * 944 + * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll 945 + * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu 946 + * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 947 + * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 948 + * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu 949 + * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu 950 + * 951 + * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC 952 + */ 953 + 954 + static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { 955 + MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, 956 + PLL_CON0_PLL_SHARED0, 4, 1), 957 + MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, 958 + PLL_CON0_PLL_SHARED1, 4, 1), 959 + MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, 960 + PLL_CON0_PLL_SHARED2, 4, 1), 961 + MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, 962 + PLL_CON0_PLL_SHARED3, 4, 1), 963 + MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p, 964 + PLL_CON0_PLL_SPARE, 4, 1), 965 + MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, 966 + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3), 967 + MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, 968 + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3), 969 + MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, 970 + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3), 971 + MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, 972 + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3), 973 + MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p, 974 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3), 975 + MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p, 976 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3), 977 + MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p, 978 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3), 979 + MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p, 980 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3), 981 + MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p, 982 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3), 983 + MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p, 984 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3), 985 + MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p, 986 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3), 987 + MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p, 988 + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3), 989 + MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p, 990 + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), 991 + MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1", 992 + mout_cmu_cmu_boost_option1_p, 993 + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1), 994 + MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, 995 + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), 996 + MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", 997 + mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), 998 + MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", 999 + mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 1000 + 0, 3), 1001 + MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", 1002 + mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 1003 + 0, 3), 1004 + MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", 1005 + mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 1006 + 0, 3), 1007 + MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, 1008 + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3), 1009 + MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, 1010 + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3), 1011 + MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, 1012 + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3), 1013 + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, 1014 + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3), 1015 + MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, 1016 + CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3), 1017 + MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, 1018 + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), 1019 + MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, 1020 + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3), 1021 + MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p, 1022 + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3), 1023 + MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, 1024 + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3), 1025 + MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, 1026 + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3), 1027 + MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch", 1028 + mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3), 1029 + MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, 1030 + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3), 1031 + MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, 1032 + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3), 1033 + MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, 1034 + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3), 1035 + MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, 1036 + CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), 1037 + MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, 1038 + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), 1039 + MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", 1040 + mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), 1041 + MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", 1042 + mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 1043 + 0, 1), 1044 + MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg", 1045 + mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 1046 + 0, 1), 1047 + MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, 1048 + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), 1049 + MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, 1050 + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), 1051 + MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, 1052 + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3), 1053 + MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", 1054 + mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 1055 + 0, 2), 1056 + MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, 1057 + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1), 1058 + MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", 1059 + mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 1060 + 0, 2), 1061 + MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, 1062 + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3), 1063 + MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, 1064 + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3), 1065 + MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, 1066 + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3), 1067 + MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, 1068 + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), 1069 + MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, 1070 + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3), 1071 + MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, 1072 + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), 1073 + MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", 1074 + mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), 1075 + MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, 1076 + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), 1077 + MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, 1078 + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), 1079 + MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, 1080 + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3), 1081 + MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p, 1082 + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3), 1083 + MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus", 1084 + mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), 1085 + MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, 1086 + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), 1087 + MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus", 1088 + mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2), 1089 + MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, 1090 + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2), 1091 + MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, 1092 + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), 1093 + MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1", 1094 + mout_cmu_top_boost_option1_p, 1095 + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1), 1096 + MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref", 1097 + mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2), 1098 + MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, 1099 + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3), 1100 + MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, 1101 + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3), 1102 + MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", 1103 + mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3), 1104 + MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, 1105 + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), 1106 + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, 1107 + CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 1108 + }; 1109 + 1110 + static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { 1111 + DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", 1112 + CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), 1113 + DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", 1114 + CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), 1115 + DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", 1116 + CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), 1117 + DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", 1118 + CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), 1119 + DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", 1120 + CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), 1121 + DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", 1122 + CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), 1123 + DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", 1124 + CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), 1125 + DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", 1126 + CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), 1127 + DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4", 1128 + CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), 1129 + DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5", 1130 + CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5), 1131 + DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6", 1132 + CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5), 1133 + DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7", 1134 + CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5), 1135 + DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", 1136 + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 1137 + DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", 1138 + "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), 1139 + DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", 1140 + "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), 1141 + DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", 1142 + "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), 1143 + DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", 1144 + "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), 1145 + DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", 1146 + CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), 1147 + DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", 1148 + CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), 1149 + DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", 1150 + CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), 1151 + DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", 1152 + CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), 1153 + DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", 1154 + CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), 1155 + DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", 1156 + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), 1157 + DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", 1158 + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), 1159 + DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa", 1160 + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), 1161 + DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", 1162 + CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), 1163 + DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", 1164 + CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), 1165 + DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", 1166 + "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 1167 + DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", 1168 + CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), 1169 + DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", 1170 + CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), 1171 + DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", 1172 + CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), 1173 + DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", 1174 + CLK_CON_DIV_CLKCMU_HPM, 0, 2), 1175 + DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", 1176 + CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), 1177 + DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", 1178 + "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), 1179 + DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", 1180 + "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), 1181 + DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", 1182 + CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), 1183 + DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", 1184 + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), 1185 + DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", 1186 + CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), 1187 + DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", 1188 + "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), 1189 + DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", 1190 + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), 1191 + DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", 1192 + "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), 1193 + DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", 1194 + CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), 1195 + DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", 1196 + CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), 1197 + DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", 1198 + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), 1199 + DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", 1200 + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), 1201 + DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", 1202 + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), 1203 + DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", 1204 + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), 1205 + DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", 1206 + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), 1207 + DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", 1208 + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), 1209 + DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", 1210 + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), 1211 + DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", 1212 + CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), 1213 + DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", 1214 + "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), 1215 + DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", 1216 + CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), 1217 + DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", 1218 + "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), 1219 + DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", 1220 + CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), 1221 + DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", 1222 + CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), 1223 + DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", 1224 + CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), 1225 + DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", 1226 + CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), 1227 + DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", 1228 + "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), 1229 + DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", 1230 + CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), 1231 + DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost", 1232 + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), 1233 + DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref", 1234 + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), 1235 + DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", 1236 + "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 1237 + DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", 1238 + "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 1239 + DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", 1240 + "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 1241 + DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5", 1242 + "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), 1243 + DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", 1244 + "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 1245 + DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", 1246 + "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 1247 + DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", 1248 + "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 1249 + DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", 1250 + "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), 1251 + DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2", 1252 + "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), 1253 + }; 1254 + 1255 + static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { 1256 + FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", 1257 + "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), 1258 + FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), 1259 + }; 1260 + 1261 + static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { 1262 + GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", 1263 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), 1264 + GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", 1265 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), 1266 + GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost", 1267 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), 1268 + GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost", 1269 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), 1270 + GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", 1271 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 1272 + 21, 0, 0), 1273 + GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", 1274 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 1275 + 21, 0, 0), 1276 + GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", 1277 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 1278 + 21, 0, 0), 1279 + GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost", 1280 + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, 1281 + 21, 0, 0), 1282 + GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch", 1283 + "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), 1284 + GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", 1285 + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), 1286 + GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", 1287 + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), 1288 + GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", 1289 + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), 1290 + GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", 1291 + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), 1292 + GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", 1293 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), 1294 + GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", 1295 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), 1296 + GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", 1297 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), 1298 + GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", 1299 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), 1300 + GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", 1301 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), 1302 + GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", 1303 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), 1304 + GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", 1305 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), 1306 + GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", 1307 + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), 1308 + GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", 1309 + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), 1310 + GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", 1311 + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 1312 + GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", 1313 + "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 1314 + 21, 0, 0), 1315 + GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", 1316 + "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 1317 + 21, 0, 0), 1318 + GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", 1319 + "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 1320 + 21, 0, 0), 1321 + GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", 1322 + "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 1323 + 21, 0, 0), 1324 + GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", 1325 + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), 1326 + GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", 1327 + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), 1328 + GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", 1329 + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), 1330 + GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", 1331 + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), 1332 + GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", 1333 + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), 1334 + GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", 1335 + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), 1336 + GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", 1337 + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), 1338 + GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", 1339 + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), 1340 + GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", 1341 + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), 1342 + GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", 1343 + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), 1344 + GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", 1345 + "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 1346 + 21, 0, 0), 1347 + GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", 1348 + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), 1349 + GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", 1350 + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), 1351 + GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", 1352 + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), 1353 + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", 1354 + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), 1355 + GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", 1356 + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), 1357 + GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", 1358 + "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 1359 + 21, 0, 0), 1360 + GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", 1361 + "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 1362 + 21, 0, 0), 1363 + GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", 1364 + "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 1365 + 21, 0, 0), 1366 + GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", 1367 + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), 1368 + GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", 1369 + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), 1370 + GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", 1371 + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), 1372 + GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", 1373 + "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 1374 + 21, 0, 0), 1375 + GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", 1376 + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), 1377 + GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", 1378 + "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 1379 + 21, 0, 0), 1380 + GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", 1381 + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), 1382 + GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", 1383 + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), 1384 + GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", 1385 + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), 1386 + GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", 1387 + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), 1388 + GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", 1389 + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), 1390 + GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", 1391 + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), 1392 + GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", 1393 + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), 1394 + GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", 1395 + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), 1396 + GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", 1397 + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1398 + GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", 1399 + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1400 + GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus", 1401 + "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 1402 + 21, 0, 0), 1403 + GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", 1404 + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), 1405 + GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus", 1406 + "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 1407 + 21, 0, 0), 1408 + GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", 1409 + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), 1410 + GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", 1411 + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), 1412 + GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref", 1413 + "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 1414 + 21, 0, 0), 1415 + GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", 1416 + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), 1417 + GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", 1418 + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), 1419 + GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", 1420 + "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 1421 + 21, 0, 0), 1422 + GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", 1423 + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), 1424 + }; 1425 + 1426 + static const struct samsung_cmu_info top_cmu_info __initconst = { 1427 + .pll_clks = cmu_top_pll_clks, 1428 + .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), 1429 + .mux_clks = cmu_top_mux_clks, 1430 + .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), 1431 + .div_clks = cmu_top_div_clks, 1432 + .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), 1433 + .fixed_factor_clks = cmu_top_ffactor, 1434 + .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor), 1435 + .gate_clks = cmu_top_gate_clks, 1436 + .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), 1437 + .nr_clk_ids = CLKS_NR_TOP, 1438 + .clk_regs = cmu_top_clk_regs, 1439 + .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), 1440 + }; 1441 + 1442 + static void __init gs101_cmu_top_init(struct device_node *np) 1443 + { 1444 + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 1445 + } 1446 + 1447 + /* Register CMU_TOP early, as it's a dependency for other early domains */ 1448 + CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", 1449 + gs101_cmu_top_init); 1450 + 1451 + /* ---- CMU_APM ------------------------------------------------------------- */ 1452 + 1453 + /* Register Offset definitions for CMU_APM (0x17400000) */ 1454 + #define APM_CMU_APM_CONTROLLER_OPTION 0x0800 1455 + #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 1456 + #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 1457 + #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 1458 + #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 1459 + #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 1460 + #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 1461 + #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c 1462 + #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 1463 + #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 1464 + #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 1465 + #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c 1466 + #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 1467 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 1468 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 1469 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c 1470 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 1471 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 1472 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 1473 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c 1474 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 1475 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 1476 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 1477 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c 1478 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 1479 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 1480 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 1481 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c 1482 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 1483 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 1484 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 1485 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c 1486 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 1487 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 1488 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 1489 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c 1490 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 1491 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 1492 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c 1493 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 1494 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 1495 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 1496 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c 1497 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 1498 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 1499 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 1500 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c 1501 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 1502 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 1503 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 1504 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac 1505 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 1506 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 1507 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 1508 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc 1509 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 1510 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 1511 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc 1512 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 1513 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 1514 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 1515 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc 1516 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 1517 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 1518 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 1519 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec 1520 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 1521 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 1522 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 1523 + #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc 1524 + #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 1525 + #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 1526 + #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 1527 + #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c 1528 + #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 1529 + #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 1530 + #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 1531 + #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c 1532 + #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 1533 + #define QCH_CON_APBIF_RTC_QCH 0x3024 1534 + #define QCH_CON_APBIF_TRTC_QCH 0x3028 1535 + #define QCH_CON_APM_CMU_APM_QCH 0x302c 1536 + #define QCH_CON_APM_USI0_UART_QCH 0x3030 1537 + #define QCH_CON_APM_USI0_USI_QCH 0x3034 1538 + #define QCH_CON_APM_USI1_UART_QCH 0x3038 1539 + #define QCH_CON_D_TZPC_APM_QCH 0x303c 1540 + #define QCH_CON_GPC_APM_QCH 0x3040 1541 + #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 1542 + #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 1543 + #define QCH_CON_INTMEM_QCH 0x304c 1544 + #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 1545 + #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 1546 + #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 1547 + #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c 1548 + #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 1549 + #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 1550 + #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 1551 + #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c 1552 + #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 1553 + #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 1554 + #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c 1555 + #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 1556 + #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 1557 + #define QCH_CON_PMU_INTR_GEN_QCH 0x3088 1558 + #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c 1559 + #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 1560 + #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 1561 + #define QCH_CON_SPEEDY_APM_QCH 0x3098 1562 + #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c 1563 + #define QCH_CON_SSMT_D_APM_QCH 0x30a0 1564 + #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 1565 + #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 1566 + #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac 1567 + #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 1568 + #define QCH_CON_SYSREG_APM_QCH 0x30b8 1569 + #define QCH_CON_UASC_APM_QCH 0x30bc 1570 + #define QCH_CON_UASC_DBGCORE_QCH 0x30c0 1571 + #define QCH_CON_UASC_G_SWD_QCH 0x30c4 1572 + #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 1573 + #define QCH_CON_UASC_P_APM_QCH 0x30cc 1574 + #define QCH_CON_WDT_APM_QCH 0x30d0 1575 + #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 1576 + 1577 + static const unsigned long apm_clk_regs[] __initconst = { 1578 + APM_CMU_APM_CONTROLLER_OPTION, 1579 + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, 1580 + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 1581 + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 1582 + CLK_CON_DIV_DIV_CLK_APM_BOOST, 1583 + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 1584 + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 1585 + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 1586 + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 1587 + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 1588 + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 1589 + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 1590 + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 1591 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1592 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1593 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1594 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 1595 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 1596 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1597 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1598 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1599 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1600 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1601 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1602 + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 1603 + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 1604 + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1605 + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 1606 + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 1607 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1608 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1609 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 1610 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1611 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1612 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1613 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1614 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1615 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1616 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1617 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1618 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1619 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1620 + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1621 + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1622 + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1623 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1624 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1625 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, 1626 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1627 + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 1628 + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1629 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 1630 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 1631 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1632 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1633 + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1634 + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1635 + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 1636 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 1637 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 1638 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1639 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1640 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 1641 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 1642 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1643 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, 1644 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 1645 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 1646 + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 1647 + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 1648 + }; 1649 + 1650 + PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc", 1651 + "pad_clk_apm", "oscclk" }; 1652 + PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", 1653 + "pll_alv_div16_apm" }; 1654 + 1655 + static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 1656 + FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000), 1657 + FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000), 1658 + FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000), 1659 + }; 1660 + 1661 + static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 1662 + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, 1663 + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), 1664 + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, 1665 + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), 1666 + }; 1667 + 1668 + static const struct samsung_div_clock apm_div_clks[] __initconst = { 1669 + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", 1670 + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), 1671 + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", 1672 + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), 1673 + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", 1674 + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), 1675 + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", 1676 + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), 1677 + }; 1678 + 1679 + static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 1680 + GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK, 1681 + "gout_apm_apm_cmu_apm_pclk", "mout_apm_func", 1682 + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0), 1683 + GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1", 1684 + "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0), 1685 + GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1", 1686 + "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0), 1687 + GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1", 1688 + "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0), 1689 + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", 1690 + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), 1691 + GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 1692 + "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func", 1693 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1694 + 21, 0, 0), 1695 + GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK, 1696 + "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func", 1697 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1698 + 21, 0, 0), 1699 + GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 1700 + "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func", 1701 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1702 + 21, 0, 0), 1703 + GATE(CLK_GOUT_APM_APBIF_RTC_PCLK, 1704 + "gout_apm_apbif_rtc_pclk", "gout_apm_func", 1705 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), 1706 + GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK, 1707 + "gout_apm_apbif_trtc_pclk", "gout_apm_func", 1708 + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), 1709 + GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK, 1710 + "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart", 1711 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1712 + 21, 0, 0), 1713 + GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK, 1714 + "gout_apm_apm_usi0_uart_pclk", "gout_apm_func", 1715 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1716 + 21, 0, 0), 1717 + GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK, 1718 + "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi", 1719 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1720 + 21, 0, 0), 1721 + GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK, 1722 + "gout_apm_apm_usi0_usi_pclk", "gout_apm_func", 1723 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1724 + 21, 0, 0), 1725 + GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK, 1726 + "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart", 1727 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1728 + 21, 0, 0), 1729 + GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK, 1730 + "gout_apm_apm_usi1_uart_pclk", "gout_apm_func", 1731 + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1732 + 21, 0, 0), 1733 + GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK, 1734 + "gout_apm_d_tzpc_apm_pclk", "gout_apm_func", 1735 + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1736 + GATE(CLK_GOUT_APM_GPC_APM_PCLK, 1737 + "gout_apm_gpc_apm_pclk", "gout_apm_func", 1738 + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1739 + GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, 1740 + "gout_apm_grebeintegration_hclk", "gout_apm_func", 1741 + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1742 + 21, 0, 0), 1743 + GATE(CLK_GOUT_APM_INTMEM_ACLK, 1744 + "gout_apm_intmem_aclk", "gout_apm_func", 1745 + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0), 1746 + GATE(CLK_GOUT_APM_INTMEM_PCLK, 1747 + "gout_apm_intmem_pclk", "gout_apm_func", 1748 + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0), 1749 + GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK, 1750 + "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func", 1751 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1752 + 21, 0, 0), 1753 + GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK, 1754 + "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func", 1755 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1756 + 21, 0, 0), 1757 + GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK, 1758 + "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func", 1759 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1760 + 21, 0, 0), 1761 + GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK, 1762 + "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func", 1763 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1764 + 21, 0, 0), 1765 + GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK, 1766 + "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func", 1767 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1768 + 21, 0, 0), 1769 + GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK, 1770 + "gout_apm_lhs_axi_g_scan2dram_i_clk", 1771 + "gout_apm_func", 1772 + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1773 + 21, 0, 0), 1774 + GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK, 1775 + "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func", 1776 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1777 + 21, 0, 0), 1778 + GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK, 1779 + "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func", 1780 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1781 + 21, 0, 0), 1782 + GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK, 1783 + "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func", 1784 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1785 + 21, 0, 0), 1786 + GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK, 1787 + "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func", 1788 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1789 + 21, 0, 0), 1790 + GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK, 1791 + "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func", 1792 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1793 + 21, 0, 0), 1794 + GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK, 1795 + "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func", 1796 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1797 + 21, 0, 0), 1798 + GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK, 1799 + "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func", 1800 + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1801 + 21, 0, 0), 1802 + GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, 1803 + "gout_apm_pmu_intr_gen_pclk", "gout_apm_func", 1804 + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1805 + 21, 0, 0), 1806 + GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK, 1807 + "gout_apm_rom_crc32_host_aclk", "gout_apm_func", 1808 + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1809 + 21, 0, 0), 1810 + GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK, 1811 + "gout_apm_rom_crc32_host_pclk", "gout_apm_func", 1812 + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1813 + 21, 0, 0), 1814 + GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK, 1815 + "gout_apm_clk_apm_bus_clk", "gout_apm_func", 1816 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1817 + 21, 0, 0), 1818 + GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK, 1819 + "gout_apm_clk_apm_usi0_uart_clk", 1820 + "dout_apm_usi0_uart", 1821 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1822 + 21, 0, 0), 1823 + GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK, 1824 + "gout_apm_clk_apm_usi0_usi_clk", 1825 + "dout_apm_usi0_usi", 1826 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1827 + 21, 0, 0), 1828 + GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK, 1829 + "gout_apm_clk_apm_usi1_uart_clk", 1830 + "dout_apm_usi1_uart", 1831 + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1832 + 21, 0, 0), 1833 + GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK, 1834 + "gout_apm_speedy_apm_pclk", "gout_apm_func", 1835 + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0), 1836 + GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK, 1837 + "gout_apm_speedy_sub_apm_pclk", "gout_apm_func", 1838 + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1839 + 21, 0, 0), 1840 + GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK, 1841 + "gout_apm_ssmt_d_apm_aclk", "gout_apm_func", 1842 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0), 1843 + GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK, 1844 + "gout_apm_ssmt_d_apm_pclk", "gout_apm_func", 1845 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0), 1846 + GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK, 1847 + "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func", 1848 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1849 + 21, 0, 0), 1850 + GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK, 1851 + "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func", 1852 + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1853 + 21, 0, 0), 1854 + GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK, 1855 + "gout_apm_ss_dbgcore_ss_dbgcore_hclk", 1856 + "gout_apm_func", 1857 + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1858 + 21, 0, 0), 1859 + GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2, 1860 + "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func", 1861 + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1862 + 21, 0, 0), 1863 + GATE(CLK_GOUT_APM_SYSREG_APM_PCLK, 1864 + "gout_apm_sysreg_apm_pclk", "gout_apm_func", 1865 + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0), 1866 + GATE(CLK_GOUT_APM_UASC_APM_ACLK, 1867 + "gout_apm_uasc_apm_aclk", "gout_apm_func", 1868 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0), 1869 + GATE(CLK_GOUT_APM_UASC_APM_PCLK, 1870 + "gout_apm_uasc_apm_pclk", "gout_apm_func", 1871 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1872 + GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK, 1873 + "gout_apm_uasc_dbgcore_aclk", "gout_apm_func", 1874 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1875 + 21, 0, 0), 1876 + GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK, 1877 + "gout_apm_uasc_dbgcore_pclk", "gout_apm_func", 1878 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1879 + 21, 0, 0), 1880 + GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK, 1881 + "gout_apm_uasc_g_swd_aclk", "gout_apm_func", 1882 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0), 1883 + GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK, 1884 + "gout_apm_uasc_g_swd_pclk", "gout_apm_func", 1885 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1886 + GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK, 1887 + "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func", 1888 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1889 + 21, 0, 0), 1890 + GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK, 1891 + "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func", 1892 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1893 + GATE(CLK_GOUT_APM_UASC_P_APM_ACLK, 1894 + "gout_apm_uasc_p_apm_aclk", "gout_apm_func", 1895 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0), 1896 + GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, 1897 + "gout_apm_uasc_p_apm_pclk", "gout_apm_func", 1898 + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), 1899 + GATE(CLK_GOUT_APM_WDT_APM_PCLK, 1900 + "gout_apm_wdt_apm_pclk", "gout_apm_func", 1901 + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), 1902 + GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, 1903 + "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", 1904 + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), 1905 + }; 1906 + 1907 + static const struct samsung_cmu_info apm_cmu_info __initconst = { 1908 + .mux_clks = apm_mux_clks, 1909 + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 1910 + .div_clks = apm_div_clks, 1911 + .nr_div_clks = ARRAY_SIZE(apm_div_clks), 1912 + .gate_clks = apm_gate_clks, 1913 + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 1914 + .fixed_clks = apm_fixed_clks, 1915 + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 1916 + .nr_clk_ids = CLKS_NR_APM, 1917 + .clk_regs = apm_clk_regs, 1918 + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 1919 + }; 1920 + 1921 + /* ---- CMU_MISC ------------------------------------------------------------ */ 1922 + 1923 + /* Register Offset definitions for CMU_MISC (0x10010000) */ 1924 + #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 1925 + #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 1926 + #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 1927 + #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 1928 + #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 1929 + #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 1930 + #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 1931 + #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 1932 + #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 1933 + #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 1934 + #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 1935 + #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 1936 + #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c 1937 + #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 1938 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 1939 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 1940 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c 1941 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 1942 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 1943 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 1944 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c 1945 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030 1946 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034 1947 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038 1948 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c 1949 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040 1950 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044 1951 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048 1952 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c 1953 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050 1954 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054 1955 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058 1956 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c 1957 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060 1958 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064 1959 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068 1960 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c 1961 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070 1962 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074 1963 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078 1964 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c 1965 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080 1966 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084 1967 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088 1968 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c 1969 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090 1970 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094 1971 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098 1972 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c 1973 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0 1974 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4 1975 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8 1976 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac 1977 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0 1978 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4 1979 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8 1980 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc 1981 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0 1982 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4 1983 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8 1984 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc 1985 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0 1986 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4 1987 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8 1988 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc 1989 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0 1990 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4 1991 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8 1992 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec 1993 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0 1994 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4 1995 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8 1996 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc 1997 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100 1998 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104 1999 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108 2000 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c 2001 + #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110 2002 + #define DMYQCH_CON_PPMU_DMA_QCH 0x3000 2003 + #define DMYQCH_CON_PUF_QCH 0x3004 2004 + #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c 2005 + #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010 2006 + #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014 2007 + #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018 2008 + #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c 2009 + #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020 2010 + #define QCH_CON_ADM_AHB_SSS_QCH 0x3024 2011 + #define QCH_CON_DIT_QCH 0x3028 2012 + #define QCH_CON_GIC_QCH 0x3030 2013 + #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038 2014 + #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c 2015 + #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040 2016 + #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044 2017 + #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048 2018 + #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c 2019 + #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050 2020 + #define QCH_CON_MCT_QCH 0x3054 2021 + #define QCH_CON_MISC_CMU_MISC_QCH 0x3058 2022 + #define QCH_CON_OTP_CON_BIRA_QCH 0x305c 2023 + #define QCH_CON_OTP_CON_BISR_QCH 0x3060 2024 + #define QCH_CON_OTP_CON_TOP_QCH 0x3064 2025 + #define QCH_CON_PDMA_QCH 0x3068 2026 + #define QCH_CON_PPMU_MISC_QCH 0x306c 2027 + #define QCH_CON_QE_DIT_QCH 0x3070 2028 + #define QCH_CON_QE_PDMA_QCH 0x3074 2029 + #define QCH_CON_QE_PPMU_DMA_QCH 0x3078 2030 + #define QCH_CON_QE_RTIC_QCH 0x307c 2031 + #define QCH_CON_QE_SPDMA_QCH 0x3080 2032 + #define QCH_CON_QE_SSS_QCH 0x3084 2033 + #define QCH_CON_RTIC_QCH 0x3088 2034 + #define QCH_CON_SPDMA_QCH 0x308c 2035 + #define QCH_CON_SSMT_DIT_QCH 0x3090 2036 + #define QCH_CON_SSMT_PDMA_QCH 0x3094 2037 + #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098 2038 + #define QCH_CON_SSMT_RTIC_QCH 0x309c 2039 + #define QCH_CON_SSMT_SPDMA_QCH 0x30a0 2040 + #define QCH_CON_SSMT_SSS_QCH 0x30a4 2041 + #define QCH_CON_SSS_QCH 0x30a8 2042 + #define QCH_CON_SYSMMU_MISC_QCH 0x30ac 2043 + #define QCH_CON_SYSMMU_SSS_QCH 0x30b0 2044 + #define QCH_CON_SYSREG_MISC_QCH 0x30b4 2045 + #define QCH_CON_TMU_SUB_QCH 0x30b8 2046 + #define QCH_CON_TMU_TOP_QCH 0x30bc 2047 + #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0 2048 + #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4 2049 + #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00 2050 + 2051 + static const unsigned long misc_clk_regs[] __initconst = { 2052 + PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 2053 + PLL_CON1_MUX_CLKCMU_MISC_BUS_USER, 2054 + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 2055 + PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, 2056 + MISC_CMU_MISC_CONTROLLER_OPTION, 2057 + CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0, 2058 + CLK_CON_MUX_MUX_CLK_MISC_GIC, 2059 + CLK_CON_DIV_DIV_CLK_MISC_BUSP, 2060 + CLK_CON_DIV_DIV_CLK_MISC_GIC, 2061 + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 2062 + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 2063 + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 2064 + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 2065 + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 2066 + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 2067 + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 2068 + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 2069 + CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, 2070 + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 2071 + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 2072 + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 2073 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 2074 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 2075 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 2076 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 2077 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 2078 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 2079 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 2080 + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 2081 + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 2082 + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 2083 + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 2084 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 2085 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK, 2086 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 2087 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 2088 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 2089 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 2090 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 2091 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 2092 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 2093 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 2094 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 2095 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 2096 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 2097 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 2098 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 2099 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 2100 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 2101 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 2102 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 2103 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 2104 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 2105 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 2106 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 2107 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 2108 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 2109 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 2110 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 2111 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 2112 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 2113 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 2114 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 2115 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 2116 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 2117 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 2118 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 2119 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 2120 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 2121 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 2122 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 2123 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 2124 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 2125 + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 2126 + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 2127 + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 2128 + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 2129 + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 2130 + DMYQCH_CON_PPMU_DMA_QCH, 2131 + DMYQCH_CON_PUF_QCH, 2132 + PCH_CON_LHM_AXI_D_SSS_PCH, 2133 + PCH_CON_LHM_AXI_P_GIC_PCH, 2134 + PCH_CON_LHM_AXI_P_MISC_PCH, 2135 + PCH_CON_LHS_ACEL_D_MISC_PCH, 2136 + PCH_CON_LHS_AST_IRI_GICCPU_PCH, 2137 + PCH_CON_LHS_AXI_D_SSS_PCH, 2138 + QCH_CON_ADM_AHB_SSS_QCH, 2139 + QCH_CON_DIT_QCH, 2140 + QCH_CON_GIC_QCH, 2141 + QCH_CON_LHM_AST_ICC_CPUGIC_QCH, 2142 + QCH_CON_LHM_AXI_D_SSS_QCH, 2143 + QCH_CON_LHM_AXI_P_GIC_QCH, 2144 + QCH_CON_LHM_AXI_P_MISC_QCH, 2145 + QCH_CON_LHS_ACEL_D_MISC_QCH, 2146 + QCH_CON_LHS_AST_IRI_GICCPU_QCH, 2147 + QCH_CON_LHS_AXI_D_SSS_QCH, 2148 + QCH_CON_MCT_QCH, 2149 + QCH_CON_MISC_CMU_MISC_QCH, 2150 + QCH_CON_OTP_CON_BIRA_QCH, 2151 + QCH_CON_OTP_CON_BISR_QCH, 2152 + QCH_CON_OTP_CON_TOP_QCH, 2153 + QCH_CON_PDMA_QCH, 2154 + QCH_CON_PPMU_MISC_QCH, 2155 + QCH_CON_QE_DIT_QCH, 2156 + QCH_CON_QE_PDMA_QCH, 2157 + QCH_CON_QE_PPMU_DMA_QCH, 2158 + QCH_CON_QE_RTIC_QCH, 2159 + QCH_CON_QE_SPDMA_QCH, 2160 + QCH_CON_QE_SSS_QCH, 2161 + QCH_CON_RTIC_QCH, 2162 + QCH_CON_SPDMA_QCH, 2163 + QCH_CON_SSMT_DIT_QCH, 2164 + QCH_CON_SSMT_PDMA_QCH, 2165 + QCH_CON_SSMT_PPMU_DMA_QCH, 2166 + QCH_CON_SSMT_RTIC_QCH, 2167 + QCH_CON_SSMT_SPDMA_QCH, 2168 + QCH_CON_SSMT_SSS_QCH, 2169 + QCH_CON_SSS_QCH, 2170 + QCH_CON_SYSMMU_MISC_QCH, 2171 + QCH_CON_SYSMMU_SSS_QCH, 2172 + QCH_CON_SYSREG_MISC_QCH, 2173 + QCH_CON_TMU_SUB_QCH, 2174 + QCH_CON_TMU_TOP_QCH, 2175 + QCH_CON_WDT_CLUSTER0_QCH, 2176 + QCH_CON_WDT_CLUSTER1_QCH, 2177 + QUEUE_CTRL_REG_BLK_MISC_CMU_MISC, 2178 + }; 2179 + 2180 + /* List of parent clocks for Muxes in CMU_MISC */ 2181 + PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" }; 2182 + PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" }; 2183 + PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" }; 2184 + 2185 + static const struct samsung_mux_clock misc_mux_clks[] __initconst = { 2186 + MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p, 2187 + PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1), 2188 + MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p, 2189 + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1), 2190 + MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p, 2191 + CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0), 2192 + }; 2193 + 2194 + static const struct samsung_div_clock misc_div_clks[] __initconst = { 2195 + DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", 2196 + CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), 2197 + DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", 2198 + CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), 2199 + }; 2200 + 2201 + static const struct samsung_gate_clock misc_gate_clks[] __initconst = { 2202 + GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK, 2203 + "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp", 2204 + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 2205 + 21, 0, 0), 2206 + GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK, 2207 + "gout_misc_otp_con_bira_i_oscclk", "oscclk", 2208 + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 2209 + 21, 0, 0), 2210 + GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK, 2211 + "gout_misc_otp_con_bisr_i_oscclk", "oscclk", 2212 + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 2213 + 21, 0, 0), 2214 + GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK, 2215 + "gout_misc_otp_con_top_i_oscclk", "oscclk", 2216 + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 2217 + 21, 0, 0), 2218 + GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK, 2219 + "gout_misc_clk_misc_oscclk_clk", "oscclk", 2220 + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 2221 + 21, 0, 0), 2222 + GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM, 2223 + "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user", 2224 + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 2225 + 21, 0, 0), 2226 + GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM, 2227 + "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user", 2228 + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 2229 + 21, 0, 0), 2230 + GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK, 2231 + "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp", 2232 + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 2233 + 21, 0, 0), 2234 + GATE(CLK_GOUT_MISC_GIC_GICCLK, 2235 + "gout_misc_gic_gicclk", "mout_misc_gic", 2236 + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 2237 + 21, 0, 0), 2238 + GATE(CLK_GOUT_MISC_GPC_MISC_PCLK, 2239 + "gout_misc_gpc_misc_pclk", "dout_misc_busp", 2240 + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 2241 + 21, 0, 0), 2242 + GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK, 2243 + "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic", 2244 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 2245 + 21, 0, 0), 2246 + GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK, 2247 + "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user", 2248 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 2249 + 21, 0, 0), 2250 + GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK, 2251 + "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic", 2252 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 2253 + 21, 0, 0), 2254 + GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK, 2255 + "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp", 2256 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 2257 + 21, 0, 0), 2258 + GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK, 2259 + "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user", 2260 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 2261 + 21, 0, 0), 2262 + GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK, 2263 + "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic", 2264 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 2265 + 21, 0, 0), 2266 + GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK, 2267 + "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user", 2268 + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 2269 + 21, 0, 0), 2270 + GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk", 2271 + "dout_misc_busp", 2272 + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 2273 + 21, 0, 0), 2274 + GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK, 2275 + "gout_misc_otp_con_bira_pclk", "dout_misc_busp", 2276 + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 2277 + 21, 0, 0), 2278 + GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK, 2279 + "gout_misc_otp_con_bisr_pclk", "dout_misc_busp", 2280 + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 2281 + 21, 0, 0), 2282 + GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK, 2283 + "gout_misc_otp_con_top_pclk", "dout_misc_busp", 2284 + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 2285 + 21, 0, 0), 2286 + GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk", 2287 + "mout_misc_bus_user", 2288 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 2289 + 21, 0, 0), 2290 + GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK, 2291 + "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user", 2292 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 2293 + 21, 0, 0), 2294 + GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK, 2295 + "gout_misc_ppmu_misc_pclk", "dout_misc_busp", 2296 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 2297 + 21, 0, 0), 2298 + GATE(CLK_GOUT_MISC_PUF_I_CLK, 2299 + "gout_misc_puf_i_clk", "mout_misc_sss_user", 2300 + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 2301 + 21, 0, 0), 2302 + GATE(CLK_GOUT_MISC_QE_DIT_ACLK, 2303 + "gout_misc_qe_dit_aclk", "mout_misc_bus_user", 2304 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 2305 + 21, 0, 0), 2306 + GATE(CLK_GOUT_MISC_QE_DIT_PCLK, 2307 + "gout_misc_qe_dit_pclk", "dout_misc_busp", 2308 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 2309 + 21, 0, 0), 2310 + GATE(CLK_GOUT_MISC_QE_PDMA_ACLK, 2311 + "gout_misc_qe_pdma_aclk", "mout_misc_bus_user", 2312 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 2313 + 21, 0, 0), 2314 + GATE(CLK_GOUT_MISC_QE_PDMA_PCLK, 2315 + "gout_misc_qe_pdma_pclk", "dout_misc_busp", 2316 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 2317 + 21, 0, 0), 2318 + GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK, 2319 + "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user", 2320 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 2321 + 21, 0, 0), 2322 + GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK, 2323 + "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp", 2324 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 2325 + 21, 0, 0), 2326 + GATE(CLK_GOUT_MISC_QE_RTIC_ACLK, 2327 + "gout_misc_qe_rtic_aclk", "mout_misc_bus_user", 2328 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 2329 + 21, 0, 0), 2330 + GATE(CLK_GOUT_MISC_QE_RTIC_PCLK, 2331 + "gout_misc_qe_rtic_pclk", "dout_misc_busp", 2332 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 2333 + 21, 0, 0), 2334 + GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK, 2335 + "gout_misc_qe_spdma_aclk", "mout_misc_bus_user", 2336 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 2337 + 21, 0, 0), 2338 + GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK, 2339 + "gout_misc_qe_spdma_pclk", "dout_misc_busp", 2340 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 2341 + 21, 0, 0), 2342 + GATE(CLK_GOUT_MISC_QE_SSS_ACLK, 2343 + "gout_misc_qe_sss_aclk", "mout_misc_sss_user", 2344 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 2345 + 21, 0, 0), 2346 + GATE(CLK_GOUT_MISC_QE_SSS_PCLK, 2347 + "gout_misc_qe_sss_pclk", "dout_misc_busp", 2348 + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 2349 + 21, 0, 0), 2350 + GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK, 2351 + "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user", 2352 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 2353 + 21, 0, 0), 2354 + GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK, 2355 + "gout_misc_clk_misc_busp_clk", "dout_misc_busp", 2356 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 2357 + 21, 0, 0), 2358 + GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK, 2359 + "gout_misc_clk_misc_gic_clk", "mout_misc_gic", 2360 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 2361 + 21, 0, 0), 2362 + GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK, 2363 + "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user", 2364 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 2365 + 21, 0, 0), 2366 + GATE(CLK_GOUT_MISC_RTIC_I_ACLK, 2367 + "gout_misc_rtic_i_aclk", "mout_misc_bus_user", 2368 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 2369 + 21, 0, 0), 2370 + GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk", 2371 + "dout_misc_busp", 2372 + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 2373 + 21, 0, 0), 2374 + GATE(CLK_GOUT_MISC_SPDMA_ACLK, 2375 + "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user", 2376 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 2377 + 21, 0, 0), 2378 + GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK, 2379 + "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user", 2380 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 2381 + 21, 0, 0), 2382 + GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK, 2383 + "gout_misc_ssmt_dit_pclk", "dout_misc_busp", 2384 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 2385 + 21, 0, 0), 2386 + GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK, 2387 + "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user", 2388 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 2389 + 21, 0, 0), 2390 + GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK, 2391 + "gout_misc_ssmt_pdma_pclk", "dout_misc_busp", 2392 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 2393 + 21, 0, 0), 2394 + GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK, 2395 + "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user", 2396 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 2397 + 21, 0, 0), 2398 + GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK, 2399 + "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp", 2400 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 2401 + 21, 0, 0), 2402 + GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK, 2403 + "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user", 2404 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 2405 + 21, 0, 0), 2406 + GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK, 2407 + "gout_misc_ssmt_rtic_pclk", "dout_misc_busp", 2408 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 2409 + 21, 0, 0), 2410 + GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK, 2411 + "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user", 2412 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 2413 + 21, 0, 0), 2414 + GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK, 2415 + "gout_misc_ssmt_spdma_pclk", "dout_misc_busp", 2416 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 2417 + 21, 0, 0), 2418 + GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK, 2419 + "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user", 2420 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 2421 + 21, 0, 0), 2422 + GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK, 2423 + "gout_misc_ssmt_sss_pclk", "dout_misc_busp", 2424 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 2425 + 21, 0, 0), 2426 + GATE(CLK_GOUT_MISC_SSS_I_ACLK, 2427 + "gout_misc_sss_i_aclk", "mout_misc_bus_user", 2428 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 2429 + 21, 0, 0), 2430 + GATE(CLK_GOUT_MISC_SSS_I_PCLK, 2431 + "gout_misc_sss_i_pclk", "dout_misc_busp", 2432 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 2433 + 21, 0, 0), 2434 + GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2, 2435 + "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user", 2436 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 2437 + 21, 0, 0), 2438 + GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1, 2439 + "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user", 2440 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 2441 + 21, 0, 0), 2442 + GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK, 2443 + "gout_misc_sysreg_misc_pclk", "dout_misc_busp", 2444 + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 2445 + 21, 0, 0), 2446 + GATE(CLK_GOUT_MISC_TMU_SUB_PCLK, 2447 + "gout_misc_tmu_sub_pclk", "dout_misc_busp", 2448 + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 2449 + 21, 0, 0), 2450 + GATE(CLK_GOUT_MISC_TMU_TOP_PCLK, 2451 + "gout_misc_tmu_top_pclk", "dout_misc_busp", 2452 + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 2453 + 21, 0, 0), 2454 + GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK, 2455 + "gout_misc_wdt_cluster0_pclk", "dout_misc_busp", 2456 + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 2457 + 21, 0, 0), 2458 + GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK, 2459 + "gout_misc_wdt_cluster1_pclk", "dout_misc_busp", 2460 + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 2461 + 21, 0, 0), 2462 + GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK, 2463 + "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user", 2464 + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 2465 + 21, 0, 0), 2466 + }; 2467 + 2468 + static const struct samsung_cmu_info misc_cmu_info __initconst = { 2469 + .mux_clks = misc_mux_clks, 2470 + .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), 2471 + .div_clks = misc_div_clks, 2472 + .nr_div_clks = ARRAY_SIZE(misc_div_clks), 2473 + .gate_clks = misc_gate_clks, 2474 + .nr_gate_clks = ARRAY_SIZE(misc_gate_clks), 2475 + .nr_clk_ids = CLKS_NR_MISC, 2476 + .clk_regs = misc_clk_regs, 2477 + .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), 2478 + .clk_name = "dout_cmu_misc_bus", 2479 + }; 2480 + 2481 + /* ---- platform_driver ----------------------------------------------------- */ 2482 + 2483 + static int __init gs101_cmu_probe(struct platform_device *pdev) 2484 + { 2485 + const struct samsung_cmu_info *info; 2486 + struct device *dev = &pdev->dev; 2487 + 2488 + info = of_device_get_match_data(dev); 2489 + exynos_arm64_register_cmu(dev, dev->of_node, info); 2490 + 2491 + return 0; 2492 + } 2493 + 2494 + static const struct of_device_id gs101_cmu_of_match[] = { 2495 + { 2496 + .compatible = "google,gs101-cmu-apm", 2497 + .data = &apm_cmu_info, 2498 + }, { 2499 + .compatible = "google,gs101-cmu-misc", 2500 + .data = &misc_cmu_info, 2501 + }, { 2502 + }, 2503 + }; 2504 + 2505 + static struct platform_driver gs101_cmu_driver __refdata = { 2506 + .driver = { 2507 + .name = "gs101-cmu", 2508 + .of_match_table = gs101_cmu_of_match, 2509 + .suppress_bind_attrs = true, 2510 + }, 2511 + .probe = gs101_cmu_probe, 2512 + }; 2513 + 2514 + static int __init gs101_cmu_init(void) 2515 + { 2516 + return platform_driver_register(&gs101_cmu_driver); 2517 + } 2518 + core_initcall(gs101_cmu_init);
+6
drivers/clk/samsung/clk-pll.c
··· 443 443 sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; 444 444 445 445 fvco *= mdiv; 446 + if (pll->type == pll_0516x) 447 + fvco *= 2; 448 + 446 449 do_div(fvco, (pdiv << sdiv)); 447 450 448 451 return (unsigned long)fvco; ··· 1319 1316 case pll_1417x: 1320 1317 case pll_0818x: 1321 1318 case pll_0822x: 1319 + case pll_0516x: 1320 + case pll_0517x: 1321 + case pll_0518x: 1322 1322 pll->enable_offs = PLL0822X_ENABLE_SHIFT; 1323 1323 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; 1324 1324 if (!pll->rate_table)
+3
drivers/clk/samsung/clk-pll.h
··· 38 38 pll_0822x, 39 39 pll_0831x, 40 40 pll_142xx, 41 + pll_0516x, 42 + pll_0517x, 43 + pll_0518x, 41 44 }; 42 45 43 46 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
+1
drivers/firmware/Kconfig
··· 272 272 source "drivers/firmware/efi/Kconfig" 273 273 source "drivers/firmware/imx/Kconfig" 274 274 source "drivers/firmware/meson/Kconfig" 275 + source "drivers/firmware/microchip/Kconfig" 275 276 source "drivers/firmware/psci/Kconfig" 276 277 source "drivers/firmware/qcom/Kconfig" 277 278 source "drivers/firmware/smccc/Kconfig"
+1
drivers/firmware/Makefile
··· 28 28 obj-y += broadcom/ 29 29 obj-y += cirrus/ 30 30 obj-y += meson/ 31 + obj-y += microchip/ 31 32 obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ 32 33 obj-y += efi/ 33 34 obj-y += imx/
+5 -1
drivers/firmware/arm_scmi/base.c
··· 13 13 #include "common.h" 14 14 #include "notify.h" 15 15 16 + /* Updated only after ALL the mandatory features for that version are merged */ 17 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x20000 18 + 16 19 #define SCMI_BASE_NUM_SOURCES 1 17 20 #define SCMI_BASE_MAX_CMD_ERR_COUNT 1024 18 21 ··· 388 385 389 386 rev->major_ver = PROTOCOL_REV_MAJOR(version), 390 387 rev->minor_ver = PROTOCOL_REV_MINOR(version); 391 - ph->set_priv(ph, rev); 388 + ph->set_priv(ph, rev, version); 392 389 393 390 ret = scmi_base_attributes_get(ph); 394 391 if (ret) ··· 426 423 .instance_init = &scmi_base_protocol_init, 427 424 .ops = NULL, 428 425 .events = &base_protocol_events, 426 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 429 427 }; 430 428 431 429 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(base, scmi_base)
+6 -2
drivers/firmware/arm_scmi/clock.c
··· 12 12 #include "protocols.h" 13 13 #include "notify.h" 14 14 15 + /* Updated only after ALL the mandatory features for that version are merged */ 16 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x20001 17 + 15 18 enum scmi_clock_protocol_cmd { 16 19 CLOCK_ATTRIBUTES = 0x3, 17 20 CLOCK_DESCRIBE_RATES = 0x4, ··· 321 318 if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x2) { 322 319 if (SUPPORTS_EXTENDED_NAMES(attributes)) 323 320 ph->hops->extended_name_get(ph, CLOCK_NAME_GET, clk_id, 324 - clk->name, 321 + NULL, clk->name, 325 322 SCMI_MAX_STR_SIZE); 326 323 327 324 if (SUPPORTS_RATE_CHANGED_NOTIF(attributes)) ··· 964 961 } 965 962 966 963 cinfo->version = version; 967 - return ph->set_priv(ph, cinfo); 964 + return ph->set_priv(ph, cinfo, version); 968 965 } 969 966 970 967 static const struct scmi_protocol scmi_clock = { ··· 973 970 .instance_init = &scmi_clock_protocol_init, 974 971 .ops = &clk_proto_ops, 975 972 .events = &clk_protocol_events, 973 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 976 974 }; 977 975 978 976 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(clock, scmi_clock)
+19 -5
drivers/firmware/arm_scmi/driver.c
··· 85 85 * @gid: A reference for per-protocol devres management. 86 86 * @users: A refcount to track effective users of this protocol. 87 87 * @priv: Reference for optional protocol private data. 88 + * @version: Protocol version supported by the platform as detected at runtime. 88 89 * @ph: An embedded protocol handle that will be passed down to protocol 89 90 * initialization code to identify this instance. 90 91 * ··· 98 97 void *gid; 99 98 refcount_t users; 100 99 void *priv; 100 + unsigned int version; 101 101 struct scmi_protocol_handle ph; 102 102 }; 103 103 ··· 1394 1392 * 1395 1393 * @ph: A reference to the protocol handle. 1396 1394 * @priv: The private data to set. 1395 + * @version: The detected protocol version for the core to register. 1397 1396 * 1398 1397 * Return: 0 on Success 1399 1398 */ 1400 1399 static int scmi_set_protocol_priv(const struct scmi_protocol_handle *ph, 1401 - void *priv) 1400 + void *priv, u32 version) 1402 1401 { 1403 1402 struct scmi_protocol_instance *pi = ph_to_pi(ph); 1404 1403 1405 1404 pi->priv = priv; 1405 + pi->version = version; 1406 1406 1407 1407 return 0; 1408 1408 } ··· 1442 1438 * @ph: A protocol handle reference. 1443 1439 * @cmd_id: The specific command ID to use. 1444 1440 * @res_id: The specific resource ID to use. 1441 + * @flags: A pointer to specific flags to use, if any. 1445 1442 * @name: A pointer to the preallocated area where the retrieved name will be 1446 1443 * stored as a NULL terminated string. 1447 1444 * @len: The len in bytes of the @name char array. ··· 1450 1445 * Return: 0 on Succcess 1451 1446 */ 1452 1447 static int scmi_common_extended_name_get(const struct scmi_protocol_handle *ph, 1453 - u8 cmd_id, u32 res_id, char *name, 1454 - size_t len) 1448 + u8 cmd_id, u32 res_id, u32 *flags, 1449 + char *name, size_t len) 1455 1450 { 1456 1451 int ret; 1452 + size_t txlen; 1457 1453 struct scmi_xfer *t; 1458 1454 struct scmi_msg_resp_domain_name_get *resp; 1459 1455 1460 - ret = ph->xops->xfer_get_init(ph, cmd_id, sizeof(res_id), 1461 - sizeof(*resp), &t); 1456 + txlen = !flags ? sizeof(res_id) : sizeof(res_id) + sizeof(*flags); 1457 + ret = ph->xops->xfer_get_init(ph, cmd_id, txlen, sizeof(*resp), &t); 1462 1458 if (ret) 1463 1459 goto out; 1464 1460 1465 1461 put_unaligned_le32(res_id, t->tx.buf); 1462 + if (flags) 1463 + put_unaligned_le32(*flags, t->tx.buf + sizeof(res_id)); 1466 1464 resp = t->rx.buf; 1467 1465 1468 1466 ret = ph->xops->do_xfer(ph, t); ··· 1852 1844 1853 1845 devres_close_group(handle->dev, pi->gid); 1854 1846 dev_dbg(handle->dev, "Initialized protocol: 0x%X\n", pi->proto->id); 1847 + 1848 + if (pi->version > proto->supported_version) 1849 + dev_warn(handle->dev, 1850 + "Detected UNSUPPORTED higher version 0x%X for protocol 0x%X." 1851 + "Backward compatibility is NOT assured.\n", 1852 + pi->version, pi->proto->id); 1855 1853 1856 1854 return pi; 1857 1855
+4
drivers/firmware/arm_scmi/optee.c
··· 440 440 if (ret) 441 441 goto err_free_shm; 442 442 443 + ret = tee_client_system_session(scmi_optee_private->tee_ctx, channel->tee_session); 444 + if (ret) 445 + dev_warn(dev, "Could not switch to system session, do best effort\n"); 446 + 443 447 ret = get_channel(channel); 444 448 if (ret) 445 449 goto err_close_sess;
+30 -18
drivers/firmware/arm_scmi/perf.c
··· 24 24 #include "protocols.h" 25 25 #include "notify.h" 26 26 27 - #define MAX_OPPS 16 27 + /* Updated only after ALL the mandatory features for that version are merged */ 28 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x40000 29 + 30 + #define MAX_OPPS 32 28 31 29 32 enum scmi_performance_protocol_cmd { 30 33 PERF_DOMAIN_ATTRIBUTES = 0x3, ··· 292 289 if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x3 && 293 290 SUPPORTS_EXTENDED_NAMES(flags)) 294 291 ph->hops->extended_name_get(ph, PERF_DOMAIN_NAME_GET, 295 - dom_info->id, dom_info->info.name, 292 + dom_info->id, NULL, dom_info->info.name, 296 293 SCMI_MAX_STR_SIZE); 297 294 298 295 if (dom_info->level_indexing_mode) { ··· 508 505 if (IS_ERR(dom)) 509 506 return PTR_ERR(dom); 510 507 508 + if (!dom->set_limits) 509 + return -EOPNOTSUPP; 510 + 511 511 if (PROTOCOL_REV_MAJOR(pi->version) >= 0x3 && !max_perf && !min_perf) 512 512 return -EINVAL; 513 513 ··· 661 655 if (IS_ERR(dom)) 662 656 return PTR_ERR(dom); 663 657 658 + if (!dom->info.set_perf) 659 + return -EOPNOTSUPP; 660 + 664 661 if (dom->level_indexing_mode) { 665 662 struct scmi_opp *opp; 666 663 ··· 763 754 } 764 755 765 756 static void scmi_perf_domain_init_fc(const struct scmi_protocol_handle *ph, 766 - u32 domain, struct scmi_fc_info **p_fc) 757 + struct perf_dom_info *dom) 767 758 { 768 759 struct scmi_fc_info *fc; 769 760 ··· 772 763 return; 773 764 774 765 ph->hops->fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL, 775 - PERF_LEVEL_SET, 4, domain, 776 - &fc[PERF_FC_LEVEL].set_addr, 777 - &fc[PERF_FC_LEVEL].set_db); 778 - 779 - ph->hops->fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL, 780 - PERF_LEVEL_GET, 4, domain, 766 + PERF_LEVEL_GET, 4, dom->id, 781 767 &fc[PERF_FC_LEVEL].get_addr, NULL); 782 768 783 769 ph->hops->fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL, 784 - PERF_LIMITS_SET, 8, domain, 785 - &fc[PERF_FC_LIMIT].set_addr, 786 - &fc[PERF_FC_LIMIT].set_db); 787 - 788 - ph->hops->fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL, 789 - PERF_LIMITS_GET, 8, domain, 770 + PERF_LIMITS_GET, 8, dom->id, 790 771 &fc[PERF_FC_LIMIT].get_addr, NULL); 791 772 792 - *p_fc = fc; 773 + if (dom->info.set_perf) 774 + ph->hops->fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL, 775 + PERF_LEVEL_SET, 4, dom->id, 776 + &fc[PERF_FC_LEVEL].set_addr, 777 + &fc[PERF_FC_LEVEL].set_db); 778 + 779 + if (dom->set_limits) 780 + ph->hops->fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL, 781 + PERF_LIMITS_SET, 8, dom->id, 782 + &fc[PERF_FC_LIMIT].set_addr, 783 + &fc[PERF_FC_LIMIT].set_db); 784 + 785 + dom->fc_info = fc; 793 786 } 794 787 795 788 static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph, ··· 1102 1091 scmi_perf_describe_levels_get(ph, dom, version); 1103 1092 1104 1093 if (dom->perf_fastchannels) 1105 - scmi_perf_domain_init_fc(ph, dom->id, &dom->fc_info); 1094 + scmi_perf_domain_init_fc(ph, dom); 1106 1095 } 1107 1096 1108 1097 ret = devm_add_action_or_reset(ph->dev, scmi_perf_xa_destroy, pinfo); 1109 1098 if (ret) 1110 1099 return ret; 1111 1100 1112 - return ph->set_priv(ph, pinfo); 1101 + return ph->set_priv(ph, pinfo, version); 1113 1102 } 1114 1103 1115 1104 static const struct scmi_protocol scmi_perf = { ··· 1118 1107 .instance_init = &scmi_perf_protocol_init, 1119 1108 .ops = &perf_proto_ops, 1120 1109 .events = &perf_protocol_events, 1110 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 1121 1111 }; 1122 1112 1123 1113 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(perf, scmi_perf)
+6 -2
drivers/firmware/arm_scmi/power.c
··· 13 13 #include "protocols.h" 14 14 #include "notify.h" 15 15 16 + /* Updated only after ALL the mandatory features for that version are merged */ 17 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x30000 18 + 16 19 enum scmi_power_protocol_cmd { 17 20 POWER_DOMAIN_ATTRIBUTES = 0x3, 18 21 POWER_STATE_SET = 0x4, ··· 136 133 if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x3 && 137 134 SUPPORTS_EXTENDED_NAMES(flags)) { 138 135 ph->hops->extended_name_get(ph, POWER_DOMAIN_NAME_GET, 139 - domain, dom_info->name, 136 + domain, NULL, dom_info->name, 140 137 SCMI_MAX_STR_SIZE); 141 138 } 142 139 ··· 331 328 332 329 pinfo->version = version; 333 330 334 - return ph->set_priv(ph, pinfo); 331 + return ph->set_priv(ph, pinfo, version); 335 332 } 336 333 337 334 static const struct scmi_protocol scmi_power = { ··· 340 337 .instance_init = &scmi_power_protocol_init, 341 338 .ops = &power_proto_ops, 342 339 .events = &power_protocol_events, 340 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 343 341 }; 344 342 345 343 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(power, scmi_power)
+6 -2
drivers/firmware/arm_scmi/powercap.c
··· 17 17 #include "protocols.h" 18 18 #include "notify.h" 19 19 20 + /* Updated only after ALL the mandatory features for that version are merged */ 21 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x20000 22 + 20 23 enum scmi_powercap_protocol_cmd { 21 24 POWERCAP_DOMAIN_ATTRIBUTES = 0x3, 22 25 POWERCAP_CAP_GET = 0x4, ··· 273 270 */ 274 271 if (!ret && SUPPORTS_EXTENDED_NAMES(flags)) 275 272 ph->hops->extended_name_get(ph, POWERCAP_DOMAIN_NAME_GET, 276 - domain, dom_info->name, 273 + domain, NULL, dom_info->name, 277 274 SCMI_MAX_STR_SIZE); 278 275 279 276 return ret; ··· 978 975 } 979 976 980 977 pinfo->version = version; 981 - return ph->set_priv(ph, pinfo); 978 + return ph->set_priv(ph, pinfo, version); 982 979 } 983 980 984 981 static const struct scmi_protocol scmi_powercap = { ··· 987 984 .instance_init = &scmi_powercap_protocol_init, 988 985 .ops = &powercap_proto_ops, 989 986 .events = &powercap_protocol_events, 987 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 990 988 }; 991 989 992 990 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(powercap, scmi_powercap)
+9 -2
drivers/firmware/arm_scmi/protocols.h
··· 174 174 struct device *dev; 175 175 const struct scmi_xfer_ops *xops; 176 176 const struct scmi_proto_helpers_ops *hops; 177 - int (*set_priv)(const struct scmi_protocol_handle *ph, void *priv); 177 + int (*set_priv)(const struct scmi_protocol_handle *ph, void *priv, 178 + u32 version); 178 179 void *(*get_priv)(const struct scmi_protocol_handle *ph); 179 180 }; 180 181 ··· 257 256 */ 258 257 struct scmi_proto_helpers_ops { 259 258 int (*extended_name_get)(const struct scmi_protocol_handle *ph, 260 - u8 cmd_id, u32 res_id, char *name, size_t len); 259 + u8 cmd_id, u32 res_id, u32 *flags, char *name, 260 + size_t len); 261 261 void *(*iter_response_init)(const struct scmi_protocol_handle *ph, 262 262 struct scmi_iterator_ops *ops, 263 263 unsigned int max_resources, u8 msg_id, ··· 312 310 * @ops: Optional reference to the operations provided by the protocol and 313 311 * exposed in scmi_protocol.h. 314 312 * @events: An optional reference to the events supported by this protocol. 313 + * @supported_version: The highest version currently supported for this 314 + * protocol by the agent. Each protocol implementation 315 + * in the agent is supposed to downgrade to match the 316 + * protocol version supported by the platform. 315 317 */ 316 318 struct scmi_protocol { 317 319 const u8 id; ··· 324 318 const scmi_prot_init_ph_fn_t instance_deinit; 325 319 const void *ops; 326 320 const struct scmi_protocol_events *events; 321 + unsigned int supported_version; 327 322 }; 328 323 329 324 #define DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(name, proto) \
+7 -2
drivers/firmware/arm_scmi/reset.c
··· 13 13 #include "protocols.h" 14 14 #include "notify.h" 15 15 16 + /* Updated only after ALL the mandatory features for that version are merged */ 17 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x30000 18 + 16 19 enum scmi_reset_protocol_cmd { 17 20 RESET_DOMAIN_ATTRIBUTES = 0x3, 18 21 RESET = 0x4, ··· 131 128 if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x3 && 132 129 SUPPORTS_EXTENDED_NAMES(attributes)) 133 130 ph->hops->extended_name_get(ph, RESET_DOMAIN_NAME_GET, domain, 134 - dom_info->name, SCMI_MAX_STR_SIZE); 131 + NULL, dom_info->name, 132 + SCMI_MAX_STR_SIZE); 135 133 136 134 return ret; 137 135 } ··· 346 342 } 347 343 348 344 pinfo->version = version; 349 - return ph->set_priv(ph, pinfo); 345 + return ph->set_priv(ph, pinfo, version); 350 346 } 351 347 352 348 static const struct scmi_protocol scmi_reset = { ··· 355 351 .instance_init = &scmi_reset_protocol_init, 356 352 .ops = &reset_proto_ops, 357 353 .events = &reset_protocol_events, 354 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 358 355 }; 359 356 360 357 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(reset, scmi_reset)
+6 -2
drivers/firmware/arm_scmi/sensors.c
··· 14 14 #include "protocols.h" 15 15 #include "notify.h" 16 16 17 + /* Updated only after ALL the mandatory features for that version are merged */ 18 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x30000 19 + 17 20 #define SCMI_MAX_NUM_SENSOR_AXIS 63 18 21 #define SCMIv2_SENSOR_PROTOCOL 0x10000 19 22 ··· 647 644 if (PROTOCOL_REV_MAJOR(si->version) >= 0x3 && 648 645 SUPPORTS_EXTENDED_NAMES(attrl)) 649 646 ph->hops->extended_name_get(ph, SENSOR_NAME_GET, s->id, 650 - s->name, SCMI_MAX_STR_SIZE); 647 + NULL, s->name, SCMI_MAX_STR_SIZE); 651 648 652 649 if (s->extended_scalar_attrs) { 653 650 s->sensor_power = le32_to_cpu(sdesc->power); ··· 1141 1138 if (ret) 1142 1139 return ret; 1143 1140 1144 - return ph->set_priv(ph, sinfo); 1141 + return ph->set_priv(ph, sinfo, version); 1145 1142 } 1146 1143 1147 1144 static const struct scmi_protocol scmi_sensors = { ··· 1150 1147 .instance_init = &scmi_sensors_protocol_init, 1151 1148 .ops = &sensor_proto_ops, 1152 1149 .events = &sensor_protocol_events, 1150 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 1153 1151 }; 1154 1152 1155 1153 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(sensors, scmi_sensors)
+5 -1
drivers/firmware/arm_scmi/system.c
··· 13 13 #include "protocols.h" 14 14 #include "notify.h" 15 15 16 + /* Updated only after ALL the mandatory features for that version are merged */ 17 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x20000 18 + 16 19 #define SCMI_SYSTEM_NUM_SOURCES 1 17 20 18 21 enum scmi_system_protocol_cmd { ··· 147 144 if (PROTOCOL_REV_MAJOR(pinfo->version) >= 0x2) 148 145 pinfo->graceful_timeout_supported = true; 149 146 150 - return ph->set_priv(ph, pinfo); 147 + return ph->set_priv(ph, pinfo, version); 151 148 } 152 149 153 150 static const struct scmi_protocol scmi_system = { ··· 156 153 .instance_init = &scmi_system_protocol_init, 157 154 .ops = NULL, 158 155 .events = &system_protocol_events, 156 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 159 157 }; 160 158 161 159 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(system, scmi_system)
+6 -2
drivers/firmware/arm_scmi/voltage.c
··· 10 10 11 11 #include "protocols.h" 12 12 13 + /* Updated only after ALL the mandatory features for that version are merged */ 14 + #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x20000 15 + 13 16 #define VOLTAGE_DOMS_NUM_MASK GENMASK(15, 0) 14 17 #define REMAINING_LEVELS_MASK GENMASK(31, 16) 15 18 #define RETURNED_LEVELS_MASK GENMASK(11, 0) ··· 245 242 if (SUPPORTS_EXTENDED_NAMES(attributes)) 246 243 ph->hops->extended_name_get(ph, 247 244 VOLTAGE_DOMAIN_NAME_GET, 248 - v->id, v->name, 245 + v->id, NULL, v->name, 249 246 SCMI_MAX_STR_SIZE); 250 247 if (SUPPORTS_ASYNC_LEVEL_SET(attributes)) 251 248 v->async_level_set = true; ··· 435 432 dev_warn(ph->dev, "No Voltage domains found.\n"); 436 433 } 437 434 438 - return ph->set_priv(ph, vinfo); 435 + return ph->set_priv(ph, vinfo, version); 439 436 } 440 437 441 438 static const struct scmi_protocol scmi_voltage = { ··· 443 440 .owner = THIS_MODULE, 444 441 .instance_init = &scmi_voltage_protocol_init, 445 442 .ops = &voltage_proto_ops, 443 + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, 446 444 }; 447 445 448 446 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(voltage, scmi_voltage)
+8 -11
drivers/firmware/meson/meson_sm.c
··· 274 274 275 275 static DEVICE_ATTR_RO(serial); 276 276 277 - static struct attribute *meson_sm_sysfs_attributes[] = { 277 + static struct attribute *meson_sm_sysfs_attrs[] = { 278 278 &dev_attr_serial.attr, 279 279 NULL, 280 280 }; 281 - 282 - static const struct attribute_group meson_sm_sysfs_attr_group = { 283 - .attrs = meson_sm_sysfs_attributes, 284 - }; 281 + ATTRIBUTE_GROUPS(meson_sm_sysfs); 285 282 286 283 static const struct of_device_id meson_sm_ids[] = { 287 284 { .compatible = "amlogic,meson-gxbb-sm", .data = &gxbb_chip }, ··· 310 313 fw->sm_shmem_out_base = meson_sm_map_shmem(chip->cmd_shmem_out_base, 311 314 chip->shmem_size); 312 315 if (WARN_ON(!fw->sm_shmem_out_base)) 313 - goto out_in_base; 316 + goto unmap_in_base; 314 317 } 315 318 316 319 fw->chip = chip; ··· 318 321 platform_set_drvdata(pdev, fw); 319 322 320 323 if (devm_of_platform_populate(dev)) 321 - goto out_in_base; 322 - 323 - if (sysfs_create_group(&pdev->dev.kobj, &meson_sm_sysfs_attr_group)) 324 - goto out_in_base; 324 + goto unmap_out_base; 325 325 326 326 pr_info("secure-monitor enabled\n"); 327 327 328 328 return 0; 329 329 330 - out_in_base: 330 + unmap_out_base: 331 + iounmap(fw->sm_shmem_out_base); 332 + unmap_in_base: 331 333 iounmap(fw->sm_shmem_in_base); 332 334 out: 333 335 return -EINVAL; ··· 336 340 .driver = { 337 341 .name = "meson-sm", 338 342 .of_match_table = of_match_ptr(meson_sm_ids), 343 + .dev_groups = meson_sm_sysfs_groups, 339 344 }, 340 345 }; 341 346 module_platform_driver_probe(meson_sm_driver, meson_sm_probe);
+12
drivers/firmware/microchip/Kconfig
··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + 3 + config POLARFIRE_SOC_AUTO_UPDATE 4 + tristate "Microchip PolarFire SoC AUTO UPDATE" 5 + depends on POLARFIRE_SOC_SYS_CTRL 6 + select FW_LOADER 7 + select FW_UPLOAD 8 + help 9 + Support for reprogramming PolarFire SoC from within Linux, using the 10 + Auto Upgrade feature of the system controller. 11 + 12 + If built as a module, it will be called mpfs-auto-update.
+3
drivers/firmware/microchip/Makefile
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + 3 + obj-$(CONFIG_POLARFIRE_SOC_AUTO_UPDATE) += mpfs-auto-update.o
+494
drivers/firmware/microchip/mpfs-auto-update.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Microchip Polarfire SoC "Auto Update" FPGA reprogramming. 4 + * 5 + * Documentation of this functionality is available in the "PolarFire® FPGA and 6 + * PolarFire SoC FPGA Programming" User Guide. 7 + * 8 + * Copyright (c) 2022-2023 Microchip Corporation. All rights reserved. 9 + * 10 + * Author: Conor Dooley <conor.dooley@microchip.com> 11 + */ 12 + #include <linux/debugfs.h> 13 + #include <linux/firmware.h> 14 + #include <linux/math.h> 15 + #include <linux/module.h> 16 + #include <linux/mtd/mtd.h> 17 + #include <linux/platform_device.h> 18 + #include <linux/sizes.h> 19 + 20 + #include <soc/microchip/mpfs.h> 21 + 22 + #define AUTO_UPDATE_DEFAULT_MBOX_OFFSET 0u 23 + #define AUTO_UPDATE_DEFAULT_RESP_OFFSET 0u 24 + 25 + #define AUTO_UPDATE_FEATURE_CMD_OPCODE 0x05u 26 + #define AUTO_UPDATE_FEATURE_CMD_DATA_SIZE 0u 27 + #define AUTO_UPDATE_FEATURE_RESP_SIZE 33u 28 + #define AUTO_UPDATE_FEATURE_CMD_DATA NULL 29 + #define AUTO_UPDATE_FEATURE_ENABLED BIT(5) 30 + 31 + #define AUTO_UPDATE_AUTHENTICATE_CMD_OPCODE 0x22u 32 + #define AUTO_UPDATE_AUTHENTICATE_CMD_DATA_SIZE 0u 33 + #define AUTO_UPDATE_AUTHENTICATE_RESP_SIZE 1u 34 + #define AUTO_UPDATE_AUTHENTICATE_CMD_DATA NULL 35 + 36 + #define AUTO_UPDATE_PROGRAM_CMD_OPCODE 0x46u 37 + #define AUTO_UPDATE_PROGRAM_CMD_DATA_SIZE 0u 38 + #define AUTO_UPDATE_PROGRAM_RESP_SIZE 1u 39 + #define AUTO_UPDATE_PROGRAM_CMD_DATA NULL 40 + 41 + /* 42 + * SPI Flash layout example: 43 + * |------------------------------| 0x0000000 44 + * | 1 KiB | 45 + * | SPI "directories" | 46 + * |------------------------------| 0x0000400 47 + * | 1 MiB | 48 + * | Reserved area | 49 + * | Used for bitstream info | 50 + * |------------------------------| 0x0100400 51 + * | 20 MiB | 52 + * | Golden Image | 53 + * |------------------------------| 0x1500400 54 + * | 20 MiB | 55 + * | Auto Upgrade Image | 56 + * |------------------------------| 0x2900400 57 + * | 20 MiB | 58 + * | Reserved for multi-image IAP | 59 + * | Unused for Auto Upgrade | 60 + * |------------------------------| 0x3D00400 61 + * | ? B | 62 + * | Unused | 63 + * |------------------------------| 0x? 64 + */ 65 + #define AUTO_UPDATE_DIRECTORY_BASE 0u 66 + #define AUTO_UPDATE_DIRECTORY_WIDTH 4u 67 + #define AUTO_UPDATE_GOLDEN_INDEX 0u 68 + #define AUTO_UPDATE_UPGRADE_INDEX 1u 69 + #define AUTO_UPDATE_BLANK_INDEX 2u 70 + #define AUTO_UPDATE_GOLDEN_DIRECTORY (AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_GOLDEN_INDEX) 71 + #define AUTO_UPDATE_UPGRADE_DIRECTORY (AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_UPGRADE_INDEX) 72 + #define AUTO_UPDATE_BLANK_DIRECTORY (AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_BLANK_INDEX) 73 + #define AUTO_UPDATE_DIRECTORY_SIZE SZ_1K 74 + #define AUTO_UPDATE_RESERVED_SIZE SZ_1M 75 + #define AUTO_UPDATE_BITSTREAM_BASE (AUTO_UPDATE_DIRECTORY_SIZE + AUTO_UPDATE_RESERVED_SIZE) 76 + 77 + #define AUTO_UPDATE_TIMEOUT_MS 60000 78 + 79 + struct mpfs_auto_update_priv { 80 + struct mpfs_sys_controller *sys_controller; 81 + struct device *dev; 82 + struct mtd_info *flash; 83 + struct fw_upload *fw_uploader; 84 + struct completion programming_complete; 85 + size_t size_per_bitstream; 86 + bool cancel_request; 87 + }; 88 + 89 + static enum fw_upload_err mpfs_auto_update_prepare(struct fw_upload *fw_uploader, const u8 *data, 90 + u32 size) 91 + { 92 + struct mpfs_auto_update_priv *priv = fw_uploader->dd_handle; 93 + size_t erase_size = AUTO_UPDATE_DIRECTORY_SIZE; 94 + 95 + /* 96 + * Verifying the Golden Image is idealistic. It will be evaluated 97 + * against the currently programmed image and thus may fail - due to 98 + * either rollback protection (if its an older version than that in use) 99 + * or if the version is the same as that of the in-use image. 100 + * Extracting the information as to why a failure occurred is not 101 + * currently possible due to limitations of the system controller 102 + * driver. If those are fixed, verification of the Golden Image should 103 + * be added here. 104 + */ 105 + 106 + priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller); 107 + if (!priv->flash) 108 + return FW_UPLOAD_ERR_HW_ERROR; 109 + 110 + erase_size = round_up(erase_size, (u64)priv->flash->erasesize); 111 + 112 + /* 113 + * We need to calculate if we have enough space in the flash for the 114 + * new image. 115 + * First, chop off the first 1 KiB as it's reserved for the directory. 116 + * The 1 MiB reserved for design info needs to be ignored also. 117 + * All that remains is carved into 3 & rounded down to the erasesize. 118 + * If this is smaller than the image size, we abort. 119 + * There's also no need to consume more than 20 MiB per image. 120 + */ 121 + priv->size_per_bitstream = priv->flash->size - SZ_1K - SZ_1M; 122 + priv->size_per_bitstream = round_down(priv->size_per_bitstream / 3, erase_size); 123 + if (priv->size_per_bitstream > 20 * SZ_1M) 124 + priv->size_per_bitstream = 20 * SZ_1M; 125 + 126 + if (priv->size_per_bitstream < size) { 127 + dev_err(priv->dev, 128 + "flash device has insufficient capacity to store this bitstream\n"); 129 + return FW_UPLOAD_ERR_INVALID_SIZE; 130 + } 131 + 132 + priv->cancel_request = false; 133 + 134 + return FW_UPLOAD_ERR_NONE; 135 + } 136 + 137 + static void mpfs_auto_update_cancel(struct fw_upload *fw_uploader) 138 + { 139 + struct mpfs_auto_update_priv *priv = fw_uploader->dd_handle; 140 + 141 + priv->cancel_request = true; 142 + } 143 + 144 + static enum fw_upload_err mpfs_auto_update_poll_complete(struct fw_upload *fw_uploader) 145 + { 146 + struct mpfs_auto_update_priv *priv = fw_uploader->dd_handle; 147 + int ret; 148 + 149 + /* 150 + * There is no meaningful way to get the status of the programming while 151 + * it is in progress, so attempting anything other than waiting for it 152 + * to complete would be misplaced. 153 + */ 154 + ret = wait_for_completion_timeout(&priv->programming_complete, 155 + msecs_to_jiffies(AUTO_UPDATE_TIMEOUT_MS)); 156 + if (ret) 157 + return FW_UPLOAD_ERR_TIMEOUT; 158 + 159 + return FW_UPLOAD_ERR_NONE; 160 + } 161 + 162 + static int mpfs_auto_update_verify_image(struct fw_upload *fw_uploader) 163 + { 164 + struct mpfs_auto_update_priv *priv = fw_uploader->dd_handle; 165 + struct mpfs_mss_response *response; 166 + struct mpfs_mss_msg *message; 167 + u32 *response_msg; 168 + int ret; 169 + 170 + response_msg = devm_kzalloc(priv->dev, AUTO_UPDATE_FEATURE_RESP_SIZE * sizeof(response_msg), 171 + GFP_KERNEL); 172 + if (!response_msg) 173 + return -ENOMEM; 174 + 175 + response = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_response), GFP_KERNEL); 176 + if (!response) { 177 + ret = -ENOMEM; 178 + goto free_response_msg; 179 + } 180 + 181 + message = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_msg), GFP_KERNEL); 182 + if (!message) { 183 + ret = -ENOMEM; 184 + goto free_response; 185 + } 186 + 187 + /* 188 + * The system controller can verify that an image in the flash is valid. 189 + * Rather than duplicate the check in this driver, call the relevant 190 + * service from the system controller instead. 191 + * This service has no command data and no response data. It overloads 192 + * mbox_offset with the image index in the flash's SPI directory where 193 + * the bitstream is located. 194 + */ 195 + response->resp_msg = response_msg; 196 + response->resp_size = AUTO_UPDATE_AUTHENTICATE_RESP_SIZE; 197 + message->cmd_opcode = AUTO_UPDATE_AUTHENTICATE_CMD_OPCODE; 198 + message->cmd_data_size = AUTO_UPDATE_AUTHENTICATE_CMD_DATA_SIZE; 199 + message->response = response; 200 + message->cmd_data = AUTO_UPDATE_AUTHENTICATE_CMD_DATA; 201 + message->mbox_offset = AUTO_UPDATE_UPGRADE_INDEX; 202 + message->resp_offset = AUTO_UPDATE_DEFAULT_RESP_OFFSET; 203 + 204 + dev_info(priv->dev, "Running verification of Upgrade Image\n"); 205 + ret = mpfs_blocking_transaction(priv->sys_controller, message); 206 + if (ret | response->resp_status) { 207 + dev_warn(priv->dev, "Verification of Upgrade Image failed!\n"); 208 + ret = ret ? ret : -EBADMSG; 209 + } 210 + 211 + dev_info(priv->dev, "Verification of Upgrade Image passed!\n"); 212 + 213 + devm_kfree(priv->dev, message); 214 + free_response: 215 + devm_kfree(priv->dev, response); 216 + free_response_msg: 217 + devm_kfree(priv->dev, response_msg); 218 + 219 + return ret; 220 + } 221 + 222 + static int mpfs_auto_update_set_image_address(struct mpfs_auto_update_priv *priv, char *buffer, 223 + u32 image_address, loff_t directory_address) 224 + { 225 + struct erase_info erase; 226 + size_t erase_size = AUTO_UPDATE_DIRECTORY_SIZE; 227 + size_t bytes_written = 0, bytes_read = 0; 228 + int ret; 229 + 230 + erase_size = round_up(erase_size, (u64)priv->flash->erasesize); 231 + 232 + erase.addr = AUTO_UPDATE_DIRECTORY_BASE; 233 + erase.len = erase_size; 234 + 235 + /* 236 + * We need to write the "SPI DIRECTORY" to the first 1 KiB, telling 237 + * the system controller where to find the actual bitstream. Since 238 + * this is spi-nor, we have to read the first eraseblock, erase that 239 + * portion of the flash, modify the data and then write it back. 240 + * There's no need to do this though if things are already the way they 241 + * should be, so check and save the write in that case. 242 + */ 243 + ret = mtd_read(priv->flash, AUTO_UPDATE_DIRECTORY_BASE, erase_size, &bytes_read, 244 + (u_char *)buffer); 245 + if (ret) 246 + return ret; 247 + 248 + if (bytes_read != erase_size) 249 + return -EIO; 250 + 251 + if ((*(u32 *)(buffer + AUTO_UPDATE_UPGRADE_DIRECTORY) == image_address) && 252 + !(*(u32 *)(buffer + AUTO_UPDATE_BLANK_DIRECTORY))) 253 + return 0; 254 + 255 + ret = mtd_erase(priv->flash, &erase); 256 + if (ret) 257 + return ret; 258 + 259 + /* 260 + * Populate the image address and then zero out the next directory so 261 + * that the system controller doesn't complain if in "Single Image" 262 + * mode. 263 + */ 264 + memcpy(buffer + AUTO_UPDATE_UPGRADE_DIRECTORY, &image_address, 265 + AUTO_UPDATE_DIRECTORY_WIDTH); 266 + memset(buffer + AUTO_UPDATE_BLANK_DIRECTORY, 0x0, AUTO_UPDATE_DIRECTORY_WIDTH); 267 + 268 + dev_info(priv->dev, "Writing the image address (%x) to the flash directory (%llx)\n", 269 + image_address, directory_address); 270 + 271 + ret = mtd_write(priv->flash, 0x0, erase_size, &bytes_written, (u_char *)buffer); 272 + if (ret) 273 + return ret; 274 + 275 + if (bytes_written != erase_size) 276 + return ret; 277 + 278 + return 0; 279 + } 280 + 281 + static int mpfs_auto_update_write_bitstream(struct fw_upload *fw_uploader, const u8 *data, 282 + u32 offset, u32 size, u32 *written) 283 + { 284 + struct mpfs_auto_update_priv *priv = fw_uploader->dd_handle; 285 + struct erase_info erase; 286 + char *buffer; 287 + loff_t directory_address = AUTO_UPDATE_UPGRADE_DIRECTORY; 288 + size_t erase_size = AUTO_UPDATE_DIRECTORY_SIZE; 289 + size_t bytes_written = 0; 290 + u32 image_address; 291 + int ret; 292 + 293 + erase_size = round_up(erase_size, (u64)priv->flash->erasesize); 294 + 295 + image_address = AUTO_UPDATE_BITSTREAM_BASE + 296 + AUTO_UPDATE_UPGRADE_INDEX * priv->size_per_bitstream; 297 + 298 + buffer = devm_kzalloc(priv->dev, erase_size, GFP_KERNEL); 299 + if (!buffer) 300 + return -ENOMEM; 301 + 302 + ret = mpfs_auto_update_set_image_address(priv, buffer, image_address, directory_address); 303 + if (ret) { 304 + dev_err(priv->dev, "failed to set image address in the SPI directory: %d\n", ret); 305 + goto out; 306 + } 307 + 308 + /* 309 + * Now the .spi image itself can be written to the flash. Preservation 310 + * of contents here is not important here, unlike the spi "directory" 311 + * which must be RMWed. 312 + */ 313 + erase.len = round_up(size, (size_t)priv->flash->erasesize); 314 + erase.addr = image_address; 315 + 316 + dev_info(priv->dev, "Erasing the flash at address (%x)\n", image_address); 317 + ret = mtd_erase(priv->flash, &erase); 318 + if (ret) 319 + goto out; 320 + 321 + /* 322 + * No parsing etc of the bitstream is required. The system controller 323 + * will do all of that itself - including verifying that the bitstream 324 + * is valid. 325 + */ 326 + dev_info(priv->dev, "Writing the image to the flash at address (%x)\n", image_address); 327 + ret = mtd_write(priv->flash, (loff_t)image_address, size, &bytes_written, data); 328 + if (ret) 329 + goto out; 330 + 331 + if (bytes_written != size) { 332 + ret = -EIO; 333 + goto out; 334 + } 335 + 336 + *written = bytes_written; 337 + 338 + out: 339 + devm_kfree(priv->dev, buffer); 340 + return ret; 341 + } 342 + 343 + static enum fw_upload_err mpfs_auto_update_write(struct fw_upload *fw_uploader, const u8 *data, 344 + u32 offset, u32 size, u32 *written) 345 + { 346 + struct mpfs_auto_update_priv *priv = fw_uploader->dd_handle; 347 + enum fw_upload_err err = FW_UPLOAD_ERR_NONE; 348 + int ret; 349 + 350 + reinit_completion(&priv->programming_complete); 351 + 352 + ret = mpfs_auto_update_write_bitstream(fw_uploader, data, offset, size, written); 353 + if (ret) { 354 + err = FW_UPLOAD_ERR_RW_ERROR; 355 + goto out; 356 + } 357 + 358 + if (priv->cancel_request) { 359 + err = FW_UPLOAD_ERR_CANCELED; 360 + goto out; 361 + } 362 + 363 + ret = mpfs_auto_update_verify_image(fw_uploader); 364 + if (ret) 365 + err = FW_UPLOAD_ERR_FW_INVALID; 366 + 367 + out: 368 + complete(&priv->programming_complete); 369 + 370 + return err; 371 + } 372 + 373 + static const struct fw_upload_ops mpfs_auto_update_ops = { 374 + .prepare = mpfs_auto_update_prepare, 375 + .write = mpfs_auto_update_write, 376 + .poll_complete = mpfs_auto_update_poll_complete, 377 + .cancel = mpfs_auto_update_cancel, 378 + }; 379 + 380 + static int mpfs_auto_update_available(struct mpfs_auto_update_priv *priv) 381 + { 382 + struct mpfs_mss_response *response; 383 + struct mpfs_mss_msg *message; 384 + u32 *response_msg; 385 + int ret; 386 + 387 + response_msg = devm_kzalloc(priv->dev, AUTO_UPDATE_FEATURE_RESP_SIZE * sizeof(response_msg), 388 + GFP_KERNEL); 389 + if (!response_msg) 390 + return -ENOMEM; 391 + 392 + response = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_response), GFP_KERNEL); 393 + if (!response) 394 + return -ENOMEM; 395 + 396 + message = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_msg), GFP_KERNEL); 397 + if (!message) 398 + return -ENOMEM; 399 + 400 + /* 401 + * To verify that Auto Update is possible, the "Query Security Service 402 + * Request" is performed. 403 + * This service has no command data & does not overload mbox_offset. 404 + */ 405 + response->resp_msg = response_msg; 406 + response->resp_size = AUTO_UPDATE_FEATURE_RESP_SIZE; 407 + message->cmd_opcode = AUTO_UPDATE_FEATURE_CMD_OPCODE; 408 + message->cmd_data_size = AUTO_UPDATE_FEATURE_CMD_DATA_SIZE; 409 + message->response = response; 410 + message->cmd_data = AUTO_UPDATE_FEATURE_CMD_DATA; 411 + message->mbox_offset = AUTO_UPDATE_DEFAULT_MBOX_OFFSET; 412 + message->resp_offset = AUTO_UPDATE_DEFAULT_RESP_OFFSET; 413 + 414 + ret = mpfs_blocking_transaction(priv->sys_controller, message); 415 + if (ret) 416 + return ret; 417 + 418 + /* 419 + * Currently, the system controller's firmware does not generate any 420 + * interrupts for failed services, so mpfs_blocking_transaction() should 421 + * time out & therefore return an error. 422 + * Hitting this check is highly unlikely at present, but if the system 423 + * controller's behaviour changes so that it does generate interrupts 424 + * for failed services, it will be required. 425 + */ 426 + if (response->resp_status) 427 + return -EIO; 428 + 429 + /* 430 + * Bit 5 of byte 1 is "UL_Auto Update" & if it is set, Auto Update is 431 + * not possible. 432 + */ 433 + if (response_msg[1] & AUTO_UPDATE_FEATURE_ENABLED) 434 + return -EPERM; 435 + 436 + return 0; 437 + } 438 + 439 + static int mpfs_auto_update_probe(struct platform_device *pdev) 440 + { 441 + struct device *dev = &pdev->dev; 442 + struct mpfs_auto_update_priv *priv; 443 + struct fw_upload *fw_uploader; 444 + int ret; 445 + 446 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 447 + if (!priv) 448 + return -ENOMEM; 449 + 450 + priv->sys_controller = mpfs_sys_controller_get(dev); 451 + if (IS_ERR(priv->sys_controller)) 452 + return dev_err_probe(dev, PTR_ERR(priv->sys_controller), 453 + "Could not register as a sub device of the system controller\n"); 454 + 455 + priv->dev = dev; 456 + platform_set_drvdata(pdev, priv); 457 + 458 + ret = mpfs_auto_update_available(priv); 459 + if (ret) 460 + return dev_err_probe(dev, ret, 461 + "The current bitstream does not support auto-update\n"); 462 + 463 + init_completion(&priv->programming_complete); 464 + 465 + fw_uploader = firmware_upload_register(THIS_MODULE, dev, "mpfs-auto-update", 466 + &mpfs_auto_update_ops, priv); 467 + if (IS_ERR(fw_uploader)) 468 + return dev_err_probe(dev, PTR_ERR(fw_uploader), 469 + "Failed to register the bitstream uploader\n"); 470 + 471 + priv->fw_uploader = fw_uploader; 472 + 473 + return 0; 474 + } 475 + 476 + static void mpfs_auto_update_remove(struct platform_device *pdev) 477 + { 478 + struct mpfs_auto_update_priv *priv = platform_get_drvdata(pdev); 479 + 480 + firmware_upload_unregister(priv->fw_uploader); 481 + } 482 + 483 + static struct platform_driver mpfs_auto_update_driver = { 484 + .driver = { 485 + .name = "mpfs-auto-update", 486 + }, 487 + .probe = mpfs_auto_update_probe, 488 + .remove_new = mpfs_auto_update_remove, 489 + }; 490 + module_platform_driver(mpfs_auto_update_driver); 491 + 492 + MODULE_LICENSE("GPL"); 493 + MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); 494 + MODULE_DESCRIPTION("PolarFire SoC Auto Update FPGA reprogramming");
+13 -7
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
··· 325 325 req_data->length = req_size; 326 326 327 327 status = ucs2_strscpy(((void *)req_data) + req_data->name_offset, name, name_length); 328 - if (status < 0) 329 - return EFI_INVALID_PARAMETER; 328 + if (status < 0) { 329 + efi_status = EFI_INVALID_PARAMETER; 330 + goto out_free; 331 + } 330 332 331 333 memcpy(((void *)req_data) + req_data->guid_offset, guid, req_data->guid_size); 332 334 ··· 473 471 req_data->length = req_size; 474 472 475 473 status = ucs2_strscpy(((void *)req_data) + req_data->name_offset, name, name_length); 476 - if (status < 0) 477 - return EFI_INVALID_PARAMETER; 474 + if (status < 0) { 475 + efi_status = EFI_INVALID_PARAMETER; 476 + goto out_free; 477 + } 478 478 479 479 memcpy(((void *)req_data) + req_data->guid_offset, guid, req_data->guid_size); 480 480 ··· 567 563 memcpy(((void *)req_data) + req_data->guid_offset, guid, req_data->guid_size); 568 564 status = ucs2_strscpy(((void *)req_data) + req_data->name_offset, name, 569 565 *name_size / sizeof(*name)); 570 - if (status < 0) 571 - return EFI_INVALID_PARAMETER; 566 + if (status < 0) { 567 + efi_status = EFI_INVALID_PARAMETER; 568 + goto out_free; 569 + } 572 570 573 571 status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, rsp_size); 574 572 if (status) { ··· 641 635 * have already been validated above, causing this function to 642 636 * bail with EFI_BUFFER_TOO_SMALL. 643 637 */ 644 - return EFI_DEVICE_ERROR; 638 + efi_status = EFI_DEVICE_ERROR; 645 639 } 646 640 647 641 out_free:
+5 -5
drivers/firmware/ti_sci.c
··· 164 164 { 165 165 struct device *dev = &pdev->dev; 166 166 struct resource *res; 167 - char debug_name[50] = "ti_sci_debug@"; 167 + char debug_name[50]; 168 168 169 169 /* Debug region is optional */ 170 170 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, ··· 181 181 /* Setup NULL termination */ 182 182 info->debug_buffer[info->debug_region_size] = 0; 183 183 184 - info->d = debugfs_create_file(strncat(debug_name, dev_name(dev), 185 - sizeof(debug_name) - 186 - sizeof("ti_sci_debug@")), 187 - 0444, NULL, info, &ti_sci_debug_fops); 184 + snprintf(debug_name, sizeof(debug_name), "ti_sci_debug@%s", 185 + dev_name(dev)); 186 + info->d = debugfs_create_file(debug_name, 0444, NULL, info, 187 + &ti_sci_debug_fops); 188 188 if (IS_ERR(info->d)) 189 189 return PTR_ERR(info->d); 190 190
-12
drivers/mailbox/Kconfig
··· 8 8 9 9 if MAILBOX 10 10 11 - config APPLE_MAILBOX 12 - tristate "Apple Mailbox driver" 13 - depends on ARCH_APPLE || (ARM64 && COMPILE_TEST) 14 - default ARCH_APPLE 15 - help 16 - Apple SoCs have various co-processors required for certain 17 - peripherals to work (NVMe, display controller, etc.). This 18 - driver adds support for the mailbox controller used to 19 - communicate with those. 20 - 21 - Say Y here if you have a Apple SoC. 22 - 23 11 config ARM_MHU 24 12 tristate "ARM MHU Mailbox" 25 13 depends on ARM_AMBA
-2
drivers/mailbox/Makefile
··· 60 60 obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o 61 61 62 62 obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o 63 - 64 - obj-$(CONFIG_APPLE_MAILBOX) += apple-mailbox.o
-441
drivers/mailbox/apple-mailbox.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only OR MIT 2 - /* 3 - * Apple mailbox driver 4 - * 5 - * Copyright (C) 2021 The Asahi Linux Contributors 6 - * 7 - * This driver adds support for two mailbox variants (called ASC and M3 by 8 - * Apple) found in Apple SoCs such as the M1. It consists of two FIFOs used to 9 - * exchange 64+32 bit messages between the main CPU and a co-processor. 10 - * Various coprocessors implement different IPC protocols based on these simple 11 - * messages and shared memory buffers. 12 - * 13 - * Both the main CPU and the co-processor see the same set of registers but 14 - * the first FIFO (A2I) is always used to transfer messages from the application 15 - * processor (us) to the I/O processor and the second one (I2A) for the 16 - * other direction. 17 - */ 18 - 19 - #include <linux/apple-mailbox.h> 20 - #include <linux/delay.h> 21 - #include <linux/device.h> 22 - #include <linux/gfp.h> 23 - #include <linux/interrupt.h> 24 - #include <linux/io.h> 25 - #include <linux/mailbox_controller.h> 26 - #include <linux/module.h> 27 - #include <linux/of.h> 28 - #include <linux/platform_device.h> 29 - #include <linux/spinlock.h> 30 - #include <linux/types.h> 31 - 32 - #define APPLE_ASC_MBOX_CONTROL_FULL BIT(16) 33 - #define APPLE_ASC_MBOX_CONTROL_EMPTY BIT(17) 34 - 35 - #define APPLE_ASC_MBOX_A2I_CONTROL 0x110 36 - #define APPLE_ASC_MBOX_A2I_SEND0 0x800 37 - #define APPLE_ASC_MBOX_A2I_SEND1 0x808 38 - #define APPLE_ASC_MBOX_A2I_RECV0 0x810 39 - #define APPLE_ASC_MBOX_A2I_RECV1 0x818 40 - 41 - #define APPLE_ASC_MBOX_I2A_CONTROL 0x114 42 - #define APPLE_ASC_MBOX_I2A_SEND0 0x820 43 - #define APPLE_ASC_MBOX_I2A_SEND1 0x828 44 - #define APPLE_ASC_MBOX_I2A_RECV0 0x830 45 - #define APPLE_ASC_MBOX_I2A_RECV1 0x838 46 - 47 - #define APPLE_M3_MBOX_CONTROL_FULL BIT(16) 48 - #define APPLE_M3_MBOX_CONTROL_EMPTY BIT(17) 49 - 50 - #define APPLE_M3_MBOX_A2I_CONTROL 0x50 51 - #define APPLE_M3_MBOX_A2I_SEND0 0x60 52 - #define APPLE_M3_MBOX_A2I_SEND1 0x68 53 - #define APPLE_M3_MBOX_A2I_RECV0 0x70 54 - #define APPLE_M3_MBOX_A2I_RECV1 0x78 55 - 56 - #define APPLE_M3_MBOX_I2A_CONTROL 0x80 57 - #define APPLE_M3_MBOX_I2A_SEND0 0x90 58 - #define APPLE_M3_MBOX_I2A_SEND1 0x98 59 - #define APPLE_M3_MBOX_I2A_RECV0 0xa0 60 - #define APPLE_M3_MBOX_I2A_RECV1 0xa8 61 - 62 - #define APPLE_M3_MBOX_IRQ_ENABLE 0x48 63 - #define APPLE_M3_MBOX_IRQ_ACK 0x4c 64 - #define APPLE_M3_MBOX_IRQ_A2I_EMPTY BIT(0) 65 - #define APPLE_M3_MBOX_IRQ_A2I_NOT_EMPTY BIT(1) 66 - #define APPLE_M3_MBOX_IRQ_I2A_EMPTY BIT(2) 67 - #define APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY BIT(3) 68 - 69 - #define APPLE_MBOX_MSG1_OUTCNT GENMASK(56, 52) 70 - #define APPLE_MBOX_MSG1_INCNT GENMASK(51, 48) 71 - #define APPLE_MBOX_MSG1_OUTPTR GENMASK(47, 44) 72 - #define APPLE_MBOX_MSG1_INPTR GENMASK(43, 40) 73 - #define APPLE_MBOX_MSG1_MSG GENMASK(31, 0) 74 - 75 - struct apple_mbox_hw { 76 - unsigned int control_full; 77 - unsigned int control_empty; 78 - 79 - unsigned int a2i_control; 80 - unsigned int a2i_send0; 81 - unsigned int a2i_send1; 82 - 83 - unsigned int i2a_control; 84 - unsigned int i2a_recv0; 85 - unsigned int i2a_recv1; 86 - 87 - bool has_irq_controls; 88 - unsigned int irq_enable; 89 - unsigned int irq_ack; 90 - unsigned int irq_bit_recv_not_empty; 91 - unsigned int irq_bit_send_empty; 92 - }; 93 - 94 - struct apple_mbox { 95 - void __iomem *regs; 96 - const struct apple_mbox_hw *hw; 97 - 98 - int irq_recv_not_empty; 99 - int irq_send_empty; 100 - 101 - struct mbox_chan chan; 102 - 103 - struct device *dev; 104 - struct mbox_controller controller; 105 - spinlock_t rx_lock; 106 - }; 107 - 108 - static const struct of_device_id apple_mbox_of_match[]; 109 - 110 - static bool apple_mbox_hw_can_send(struct apple_mbox *apple_mbox) 111 - { 112 - u32 mbox_ctrl = 113 - readl_relaxed(apple_mbox->regs + apple_mbox->hw->a2i_control); 114 - 115 - return !(mbox_ctrl & apple_mbox->hw->control_full); 116 - } 117 - 118 - static bool apple_mbox_hw_send_empty(struct apple_mbox *apple_mbox) 119 - { 120 - u32 mbox_ctrl = 121 - readl_relaxed(apple_mbox->regs + apple_mbox->hw->a2i_control); 122 - 123 - return mbox_ctrl & apple_mbox->hw->control_empty; 124 - } 125 - 126 - static int apple_mbox_hw_send(struct apple_mbox *apple_mbox, 127 - struct apple_mbox_msg *msg) 128 - { 129 - if (!apple_mbox_hw_can_send(apple_mbox)) 130 - return -EBUSY; 131 - 132 - dev_dbg(apple_mbox->dev, "> TX %016llx %08x\n", msg->msg0, msg->msg1); 133 - 134 - writeq_relaxed(msg->msg0, apple_mbox->regs + apple_mbox->hw->a2i_send0); 135 - writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg->msg1), 136 - apple_mbox->regs + apple_mbox->hw->a2i_send1); 137 - 138 - return 0; 139 - } 140 - 141 - static bool apple_mbox_hw_can_recv(struct apple_mbox *apple_mbox) 142 - { 143 - u32 mbox_ctrl = 144 - readl_relaxed(apple_mbox->regs + apple_mbox->hw->i2a_control); 145 - 146 - return !(mbox_ctrl & apple_mbox->hw->control_empty); 147 - } 148 - 149 - static int apple_mbox_hw_recv(struct apple_mbox *apple_mbox, 150 - struct apple_mbox_msg *msg) 151 - { 152 - if (!apple_mbox_hw_can_recv(apple_mbox)) 153 - return -ENOMSG; 154 - 155 - msg->msg0 = readq_relaxed(apple_mbox->regs + apple_mbox->hw->i2a_recv0); 156 - msg->msg1 = FIELD_GET( 157 - APPLE_MBOX_MSG1_MSG, 158 - readq_relaxed(apple_mbox->regs + apple_mbox->hw->i2a_recv1)); 159 - 160 - dev_dbg(apple_mbox->dev, "< RX %016llx %08x\n", msg->msg0, msg->msg1); 161 - 162 - return 0; 163 - } 164 - 165 - static int apple_mbox_chan_send_data(struct mbox_chan *chan, void *data) 166 - { 167 - struct apple_mbox *apple_mbox = chan->con_priv; 168 - struct apple_mbox_msg *msg = data; 169 - int ret; 170 - 171 - ret = apple_mbox_hw_send(apple_mbox, msg); 172 - if (ret) 173 - return ret; 174 - 175 - /* 176 - * The interrupt is level triggered and will keep firing as long as the 177 - * FIFO is empty. It will also keep firing if the FIFO was empty 178 - * at any point in the past until it has been acknowledged at the 179 - * mailbox level. By acknowledging it here we can ensure that we will 180 - * only get the interrupt once the FIFO has been cleared again. 181 - * If the FIFO is already empty before the ack it will fire again 182 - * immediately after the ack. 183 - */ 184 - if (apple_mbox->hw->has_irq_controls) { 185 - writel_relaxed(apple_mbox->hw->irq_bit_send_empty, 186 - apple_mbox->regs + apple_mbox->hw->irq_ack); 187 - } 188 - enable_irq(apple_mbox->irq_send_empty); 189 - 190 - return 0; 191 - } 192 - 193 - static irqreturn_t apple_mbox_send_empty_irq(int irq, void *data) 194 - { 195 - struct apple_mbox *apple_mbox = data; 196 - 197 - /* 198 - * We don't need to acknowledge the interrupt at the mailbox level 199 - * here even if supported by the hardware. It will keep firing but that 200 - * doesn't matter since it's disabled at the main interrupt controller. 201 - * apple_mbox_chan_send_data will acknowledge it before enabling 202 - * it at the main controller again. 203 - */ 204 - disable_irq_nosync(apple_mbox->irq_send_empty); 205 - mbox_chan_txdone(&apple_mbox->chan, 0); 206 - return IRQ_HANDLED; 207 - } 208 - 209 - static int apple_mbox_poll(struct apple_mbox *apple_mbox) 210 - { 211 - struct apple_mbox_msg msg; 212 - int ret = 0; 213 - 214 - while (apple_mbox_hw_recv(apple_mbox, &msg) == 0) { 215 - mbox_chan_received_data(&apple_mbox->chan, (void *)&msg); 216 - ret++; 217 - } 218 - 219 - /* 220 - * The interrupt will keep firing even if there are no more messages 221 - * unless we also acknowledge it at the mailbox level here. 222 - * There's no race if a message comes in between the check in the while 223 - * loop above and the ack below: If a new messages arrives inbetween 224 - * those two the interrupt will just fire again immediately after the 225 - * ack since it's level triggered. 226 - */ 227 - if (apple_mbox->hw->has_irq_controls) { 228 - writel_relaxed(apple_mbox->hw->irq_bit_recv_not_empty, 229 - apple_mbox->regs + apple_mbox->hw->irq_ack); 230 - } 231 - 232 - return ret; 233 - } 234 - 235 - static irqreturn_t apple_mbox_recv_irq(int irq, void *data) 236 - { 237 - struct apple_mbox *apple_mbox = data; 238 - 239 - spin_lock(&apple_mbox->rx_lock); 240 - apple_mbox_poll(apple_mbox); 241 - spin_unlock(&apple_mbox->rx_lock); 242 - 243 - return IRQ_HANDLED; 244 - } 245 - 246 - static bool apple_mbox_chan_peek_data(struct mbox_chan *chan) 247 - { 248 - struct apple_mbox *apple_mbox = chan->con_priv; 249 - unsigned long flags; 250 - int ret; 251 - 252 - spin_lock_irqsave(&apple_mbox->rx_lock, flags); 253 - ret = apple_mbox_poll(apple_mbox); 254 - spin_unlock_irqrestore(&apple_mbox->rx_lock, flags); 255 - 256 - return ret > 0; 257 - } 258 - 259 - static int apple_mbox_chan_flush(struct mbox_chan *chan, unsigned long timeout) 260 - { 261 - struct apple_mbox *apple_mbox = chan->con_priv; 262 - unsigned long deadline = jiffies + msecs_to_jiffies(timeout); 263 - 264 - while (time_before(jiffies, deadline)) { 265 - if (apple_mbox_hw_send_empty(apple_mbox)) { 266 - mbox_chan_txdone(&apple_mbox->chan, 0); 267 - return 0; 268 - } 269 - 270 - udelay(1); 271 - } 272 - 273 - return -ETIME; 274 - } 275 - 276 - static int apple_mbox_chan_startup(struct mbox_chan *chan) 277 - { 278 - struct apple_mbox *apple_mbox = chan->con_priv; 279 - 280 - /* 281 - * Only some variants of this mailbox HW provide interrupt control 282 - * at the mailbox level. We therefore need to handle enabling/disabling 283 - * interrupts at the main interrupt controller anyway for hardware that 284 - * doesn't. Just always keep the interrupts we care about enabled at 285 - * the mailbox level so that both hardware revisions behave almost 286 - * the same. 287 - */ 288 - if (apple_mbox->hw->has_irq_controls) { 289 - writel_relaxed(apple_mbox->hw->irq_bit_recv_not_empty | 290 - apple_mbox->hw->irq_bit_send_empty, 291 - apple_mbox->regs + apple_mbox->hw->irq_enable); 292 - } 293 - 294 - enable_irq(apple_mbox->irq_recv_not_empty); 295 - return 0; 296 - } 297 - 298 - static void apple_mbox_chan_shutdown(struct mbox_chan *chan) 299 - { 300 - struct apple_mbox *apple_mbox = chan->con_priv; 301 - 302 - disable_irq(apple_mbox->irq_recv_not_empty); 303 - } 304 - 305 - static const struct mbox_chan_ops apple_mbox_ops = { 306 - .send_data = apple_mbox_chan_send_data, 307 - .peek_data = apple_mbox_chan_peek_data, 308 - .flush = apple_mbox_chan_flush, 309 - .startup = apple_mbox_chan_startup, 310 - .shutdown = apple_mbox_chan_shutdown, 311 - }; 312 - 313 - static struct mbox_chan *apple_mbox_of_xlate(struct mbox_controller *mbox, 314 - const struct of_phandle_args *args) 315 - { 316 - if (args->args_count != 0) 317 - return ERR_PTR(-EINVAL); 318 - 319 - return &mbox->chans[0]; 320 - } 321 - 322 - static int apple_mbox_probe(struct platform_device *pdev) 323 - { 324 - int ret; 325 - const struct of_device_id *match; 326 - char *irqname; 327 - struct apple_mbox *mbox; 328 - struct device *dev = &pdev->dev; 329 - 330 - match = of_match_node(apple_mbox_of_match, pdev->dev.of_node); 331 - if (!match) 332 - return -EINVAL; 333 - if (!match->data) 334 - return -EINVAL; 335 - 336 - mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); 337 - if (!mbox) 338 - return -ENOMEM; 339 - platform_set_drvdata(pdev, mbox); 340 - 341 - mbox->dev = dev; 342 - mbox->regs = devm_platform_ioremap_resource(pdev, 0); 343 - if (IS_ERR(mbox->regs)) 344 - return PTR_ERR(mbox->regs); 345 - 346 - mbox->hw = match->data; 347 - mbox->irq_recv_not_empty = 348 - platform_get_irq_byname(pdev, "recv-not-empty"); 349 - if (mbox->irq_recv_not_empty < 0) 350 - return -ENODEV; 351 - 352 - mbox->irq_send_empty = platform_get_irq_byname(pdev, "send-empty"); 353 - if (mbox->irq_send_empty < 0) 354 - return -ENODEV; 355 - 356 - mbox->controller.dev = mbox->dev; 357 - mbox->controller.num_chans = 1; 358 - mbox->controller.chans = &mbox->chan; 359 - mbox->controller.ops = &apple_mbox_ops; 360 - mbox->controller.txdone_irq = true; 361 - mbox->controller.of_xlate = apple_mbox_of_xlate; 362 - mbox->chan.con_priv = mbox; 363 - spin_lock_init(&mbox->rx_lock); 364 - 365 - irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-recv", dev_name(dev)); 366 - if (!irqname) 367 - return -ENOMEM; 368 - 369 - ret = devm_request_threaded_irq(dev, mbox->irq_recv_not_empty, NULL, 370 - apple_mbox_recv_irq, 371 - IRQF_NO_AUTOEN | IRQF_ONESHOT, irqname, 372 - mbox); 373 - if (ret) 374 - return ret; 375 - 376 - irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-send", dev_name(dev)); 377 - if (!irqname) 378 - return -ENOMEM; 379 - 380 - ret = devm_request_irq(dev, mbox->irq_send_empty, 381 - apple_mbox_send_empty_irq, IRQF_NO_AUTOEN, 382 - irqname, mbox); 383 - if (ret) 384 - return ret; 385 - 386 - return devm_mbox_controller_register(dev, &mbox->controller); 387 - } 388 - 389 - static const struct apple_mbox_hw apple_mbox_asc_hw = { 390 - .control_full = APPLE_ASC_MBOX_CONTROL_FULL, 391 - .control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY, 392 - 393 - .a2i_control = APPLE_ASC_MBOX_A2I_CONTROL, 394 - .a2i_send0 = APPLE_ASC_MBOX_A2I_SEND0, 395 - .a2i_send1 = APPLE_ASC_MBOX_A2I_SEND1, 396 - 397 - .i2a_control = APPLE_ASC_MBOX_I2A_CONTROL, 398 - .i2a_recv0 = APPLE_ASC_MBOX_I2A_RECV0, 399 - .i2a_recv1 = APPLE_ASC_MBOX_I2A_RECV1, 400 - 401 - .has_irq_controls = false, 402 - }; 403 - 404 - static const struct apple_mbox_hw apple_mbox_m3_hw = { 405 - .control_full = APPLE_M3_MBOX_CONTROL_FULL, 406 - .control_empty = APPLE_M3_MBOX_CONTROL_EMPTY, 407 - 408 - .a2i_control = APPLE_M3_MBOX_A2I_CONTROL, 409 - .a2i_send0 = APPLE_M3_MBOX_A2I_SEND0, 410 - .a2i_send1 = APPLE_M3_MBOX_A2I_SEND1, 411 - 412 - .i2a_control = APPLE_M3_MBOX_I2A_CONTROL, 413 - .i2a_recv0 = APPLE_M3_MBOX_I2A_RECV0, 414 - .i2a_recv1 = APPLE_M3_MBOX_I2A_RECV1, 415 - 416 - .has_irq_controls = true, 417 - .irq_enable = APPLE_M3_MBOX_IRQ_ENABLE, 418 - .irq_ack = APPLE_M3_MBOX_IRQ_ACK, 419 - .irq_bit_recv_not_empty = APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY, 420 - .irq_bit_send_empty = APPLE_M3_MBOX_IRQ_A2I_EMPTY, 421 - }; 422 - 423 - static const struct of_device_id apple_mbox_of_match[] = { 424 - { .compatible = "apple,asc-mailbox-v4", .data = &apple_mbox_asc_hw }, 425 - { .compatible = "apple,m3-mailbox-v2", .data = &apple_mbox_m3_hw }, 426 - {} 427 - }; 428 - MODULE_DEVICE_TABLE(of, apple_mbox_of_match); 429 - 430 - static struct platform_driver apple_mbox_driver = { 431 - .driver = { 432 - .name = "apple-mailbox", 433 - .of_match_table = apple_mbox_of_match, 434 - }, 435 - .probe = apple_mbox_probe, 436 - }; 437 - module_platform_driver(apple_mbox_driver); 438 - 439 - MODULE_LICENSE("Dual MIT/GPL"); 440 - MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>"); 441 - MODULE_DESCRIPTION("Apple Mailbox driver");
+2 -4
drivers/memory/brcmstb_dpfe.c
··· 909 909 return ret; 910 910 } 911 911 912 - static int brcmstb_dpfe_remove(struct platform_device *pdev) 912 + static void brcmstb_dpfe_remove(struct platform_device *pdev) 913 913 { 914 914 struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev); 915 915 916 916 sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs); 917 - 918 - return 0; 919 917 } 920 918 921 919 static const struct of_device_id brcmstb_dpfe_of_match[] = { ··· 934 936 .of_match_table = brcmstb_dpfe_of_match, 935 937 }, 936 938 .probe = brcmstb_dpfe_probe, 937 - .remove = brcmstb_dpfe_remove, 939 + .remove_new = brcmstb_dpfe_remove, 938 940 .resume = brcmstb_dpfe_resume, 939 941 }; 940 942
+2 -4
drivers/memory/brcmstb_memc.c
··· 152 152 return 0; 153 153 } 154 154 155 - static int brcmstb_memc_remove(struct platform_device *pdev) 155 + static void brcmstb_memc_remove(struct platform_device *pdev) 156 156 { 157 157 struct device *dev = &pdev->dev; 158 158 159 159 sysfs_remove_group(&dev->kobj, &dev_attr_group); 160 - 161 - return 0; 162 160 } 163 161 164 162 enum brcmstb_memc_hwtype { ··· 282 284 283 285 static struct platform_driver brcmstb_memc_driver = { 284 286 .probe = brcmstb_memc_probe, 285 - .remove = brcmstb_memc_remove, 287 + .remove_new = brcmstb_memc_remove, 286 288 .driver = { 287 289 .name = "brcmstb_memc", 288 290 .of_match_table = brcmstb_memc_of_match,
+2 -4
drivers/memory/emif.c
··· 1159 1159 return -ENODEV; 1160 1160 } 1161 1161 1162 - static int __exit emif_remove(struct platform_device *pdev) 1162 + static void __exit emif_remove(struct platform_device *pdev) 1163 1163 { 1164 1164 struct emif_data *emif = platform_get_drvdata(pdev); 1165 1165 1166 1166 emif_debugfs_exit(emif); 1167 - 1168 - return 0; 1169 1167 } 1170 1168 1171 1169 static void emif_shutdown(struct platform_device *pdev) ··· 1183 1185 #endif 1184 1186 1185 1187 static struct platform_driver emif_driver = { 1186 - .remove = __exit_p(emif_remove), 1188 + .remove_new = __exit_p(emif_remove), 1187 1189 .shutdown = emif_shutdown, 1188 1190 .driver = { 1189 1191 .name = "emif",
+2 -4
drivers/memory/fsl-corenet-cf.c
··· 223 223 return 0; 224 224 } 225 225 226 - static int ccf_remove(struct platform_device *pdev) 226 + static void ccf_remove(struct platform_device *pdev) 227 227 { 228 228 struct ccf_private *ccf = dev_get_drvdata(&pdev->dev); 229 229 ··· 241 241 iowrite32be(0, &ccf->err_regs->errinten); 242 242 break; 243 243 } 244 - 245 - return 0; 246 244 } 247 245 248 246 static struct platform_driver ccf_driver = { ··· 249 251 .of_match_table = ccf_matches, 250 252 }, 251 253 .probe = ccf_probe, 252 - .remove = ccf_remove, 254 + .remove_new = ccf_remove, 253 255 }; 254 256 255 257 module_platform_driver(ccf_driver);
+2 -4
drivers/memory/fsl_ifc.c
··· 84 84 return 0; 85 85 } 86 86 87 - static int fsl_ifc_ctrl_remove(struct platform_device *dev) 87 + static void fsl_ifc_ctrl_remove(struct platform_device *dev) 88 88 { 89 89 struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev); 90 90 ··· 98 98 iounmap(ctrl->gregs); 99 99 100 100 dev_set_drvdata(&dev->dev, NULL); 101 - 102 - return 0; 103 101 } 104 102 105 103 /* ··· 316 318 .of_match_table = fsl_ifc_match, 317 319 }, 318 320 .probe = fsl_ifc_ctrl_probe, 319 - .remove = fsl_ifc_ctrl_remove, 321 + .remove_new = fsl_ifc_ctrl_remove, 320 322 }; 321 323 322 324 static int __init fsl_ifc_init(void)
+2 -3
drivers/memory/jz4780-nemc.c
··· 384 384 return 0; 385 385 } 386 386 387 - static int jz4780_nemc_remove(struct platform_device *pdev) 387 + static void jz4780_nemc_remove(struct platform_device *pdev) 388 388 { 389 389 struct jz4780_nemc *nemc = platform_get_drvdata(pdev); 390 390 391 391 clk_disable_unprepare(nemc->clk); 392 - return 0; 393 392 } 394 393 395 394 static const struct jz_soc_info jz4740_soc_info = { ··· 407 408 408 409 static struct platform_driver jz4780_nemc_driver = { 409 410 .probe = jz4780_nemc_probe, 410 - .remove = jz4780_nemc_remove, 411 + .remove_new = jz4780_nemc_remove, 411 412 .driver = { 412 413 .name = "jz4780-nemc", 413 414 .of_match_table = of_match_ptr(jz4780_nemc_dt_match),
+4 -6
drivers/memory/mtk-smi.c
··· 566 566 return ret; 567 567 } 568 568 569 - static int mtk_smi_larb_remove(struct platform_device *pdev) 569 + static void mtk_smi_larb_remove(struct platform_device *pdev) 570 570 { 571 571 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 572 572 573 573 device_link_remove(&pdev->dev, larb->smi_common_dev); 574 574 pm_runtime_disable(&pdev->dev); 575 575 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 576 - return 0; 577 576 } 578 577 579 578 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) ··· 615 616 616 617 static struct platform_driver mtk_smi_larb_driver = { 617 618 .probe = mtk_smi_larb_probe, 618 - .remove = mtk_smi_larb_remove, 619 + .remove_new = mtk_smi_larb_remove, 619 620 .driver = { 620 621 .name = "mtk-smi-larb", 621 622 .of_match_table = mtk_smi_larb_of_ids, ··· 794 795 return 0; 795 796 } 796 797 797 - static int mtk_smi_common_remove(struct platform_device *pdev) 798 + static void mtk_smi_common_remove(struct platform_device *pdev) 798 799 { 799 800 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 800 801 801 802 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 802 803 device_link_remove(&pdev->dev, common->smi_common_dev); 803 804 pm_runtime_disable(&pdev->dev); 804 - return 0; 805 805 } 806 806 807 807 static int __maybe_unused mtk_smi_common_resume(struct device *dev) ··· 840 842 841 843 static struct platform_driver mtk_smi_common_driver = { 842 844 .probe = mtk_smi_common_probe, 843 - .remove = mtk_smi_common_remove, 845 + .remove_new = mtk_smi_common_remove, 844 846 .driver = { 845 847 .name = "mtk-smi-common", 846 848 .of_match_table = mtk_smi_common_of_ids,
+2 -4
drivers/memory/omap-gpmc.c
··· 2690 2690 return rc; 2691 2691 } 2692 2692 2693 - static int gpmc_remove(struct platform_device *pdev) 2693 + static void gpmc_remove(struct platform_device *pdev) 2694 2694 { 2695 2695 int i; 2696 2696 struct gpmc_device *gpmc = platform_get_drvdata(pdev); ··· 2702 2702 gpmc_mem_exit(); 2703 2703 pm_runtime_put_sync(&pdev->dev); 2704 2704 pm_runtime_disable(&pdev->dev); 2705 - 2706 - return 0; 2707 2705 } 2708 2706 2709 2707 #ifdef CONFIG_PM_SLEEP ··· 2745 2747 2746 2748 static struct platform_driver gpmc_driver = { 2747 2749 .probe = gpmc_probe, 2748 - .remove = gpmc_remove, 2750 + .remove_new = gpmc_remove, 2749 2751 .driver = { 2750 2752 .name = DEVICE_NAME, 2751 2753 .of_match_table = of_match_ptr(gpmc_dt_ids),
+2 -4
drivers/memory/renesas-rpc-if.c
··· 777 777 return 0; 778 778 } 779 779 780 - static int rpcif_remove(struct platform_device *pdev) 780 + static void rpcif_remove(struct platform_device *pdev) 781 781 { 782 782 struct rpcif_priv *rpc = platform_get_drvdata(pdev); 783 783 784 784 platform_device_unregister(rpc->vdev); 785 - 786 - return 0; 787 785 } 788 786 789 787 static const struct of_device_id rpcif_of_match[] = { ··· 795 797 796 798 static struct platform_driver rpcif_driver = { 797 799 .probe = rpcif_probe, 798 - .remove = rpcif_remove, 800 + .remove_new = rpcif_remove, 799 801 .driver = { 800 802 .name = "rpc-if", 801 803 .of_match_table = rpcif_of_match,
+2 -4
drivers/memory/samsung/exynos5422-dmc.c
··· 1558 1558 * clean the device's resources. It just calls explicitly disable function for 1559 1559 * the performance counters. 1560 1560 */ 1561 - static int exynos5_dmc_remove(struct platform_device *pdev) 1561 + static void exynos5_dmc_remove(struct platform_device *pdev) 1562 1562 { 1563 1563 struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); 1564 1564 ··· 1569 1569 1570 1570 clk_disable_unprepare(dmc->mout_bpll); 1571 1571 clk_disable_unprepare(dmc->fout_bpll); 1572 - 1573 - return 0; 1574 1572 } 1575 1573 1576 1574 static const struct of_device_id exynos5_dmc_of_match[] = { ··· 1579 1581 1580 1582 static struct platform_driver exynos5_dmc_platdrv = { 1581 1583 .probe = exynos5_dmc_probe, 1582 - .remove = exynos5_dmc_remove, 1584 + .remove_new = exynos5_dmc_remove, 1583 1585 .driver = { 1584 1586 .name = "exynos5-dmc", 1585 1587 .of_match_table = exynos5_dmc_of_match,
+2 -4
drivers/memory/stm32-fmc2-ebi.c
··· 1146 1146 return ret; 1147 1147 } 1148 1148 1149 - static int stm32_fmc2_ebi_remove(struct platform_device *pdev) 1149 + static void stm32_fmc2_ebi_remove(struct platform_device *pdev) 1150 1150 { 1151 1151 struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev); 1152 1152 ··· 1154 1154 stm32_fmc2_ebi_disable_banks(ebi); 1155 1155 stm32_fmc2_ebi_disable(ebi); 1156 1156 clk_disable_unprepare(ebi->clk); 1157 - 1158 - return 0; 1159 1157 } 1160 1158 1161 1159 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) ··· 1195 1197 1196 1198 static struct platform_driver stm32_fmc2_ebi_driver = { 1197 1199 .probe = stm32_fmc2_ebi_probe, 1198 - .remove = stm32_fmc2_ebi_remove, 1200 + .remove_new = stm32_fmc2_ebi_remove, 1199 1201 .driver = { 1200 1202 .name = "stm32_fmc2_ebi", 1201 1203 .of_match_table = stm32_fmc2_ebi_match,
+2 -4
drivers/memory/tegra/tegra186-emc.c
··· 378 378 return err; 379 379 } 380 380 381 - static int tegra186_emc_remove(struct platform_device *pdev) 381 + static void tegra186_emc_remove(struct platform_device *pdev) 382 382 { 383 383 struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); 384 384 struct tegra186_emc *emc = platform_get_drvdata(pdev); ··· 387 387 388 388 mc->bpmp = NULL; 389 389 tegra_bpmp_put(emc->bpmp); 390 - 391 - return 0; 392 390 } 393 391 394 392 static const struct of_device_id tegra186_emc_of_match[] = { ··· 411 413 .sync_state = icc_sync_state, 412 414 }, 413 415 .probe = tegra186_emc_probe, 414 - .remove = tegra186_emc_remove, 416 + .remove_new = tegra186_emc_remove, 415 417 }; 416 418 module_platform_driver(tegra186_emc_driver); 417 419
+19
drivers/memory/tegra/tegra186.c
··· 75 75 { 76 76 u32 value, old; 77 77 78 + if (client->regs.sid.security == 0 && client->regs.sid.override == 0) 79 + return; 80 + 78 81 value = readl(mc->regs + client->regs.sid.security); 79 82 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { 80 83 /* ··· 139 136 return 0; 140 137 } 141 138 139 + static int tegra186_mc_resume(struct tegra_mc *mc) 140 + { 141 + #if IS_ENABLED(CONFIG_IOMMU_API) 142 + unsigned int i; 143 + 144 + for (i = 0; i < mc->soc->num_clients; i++) { 145 + const struct tegra_mc_client *client = &mc->soc->clients[i]; 146 + 147 + tegra186_mc_client_sid_override(mc, client, client->sid); 148 + } 149 + #endif 150 + 151 + return 0; 152 + } 153 + 142 154 const struct tegra_mc_ops tegra186_mc_ops = { 143 155 .probe = tegra186_mc_probe, 144 156 .remove = tegra186_mc_remove, 157 + .resume = tegra186_mc_resume, 145 158 .probe_device = tegra186_mc_probe_device, 146 159 .handle_irq = tegra30_mc_handle_irq, 147 160 };
+2 -4
drivers/memory/tegra/tegra210-emc-core.c
··· 1985 1985 return err; 1986 1986 } 1987 1987 1988 - static int tegra210_emc_remove(struct platform_device *pdev) 1988 + static void tegra210_emc_remove(struct platform_device *pdev) 1989 1989 { 1990 1990 struct tegra210_emc *emc = platform_get_drvdata(pdev); 1991 1991 1992 1992 debugfs_remove_recursive(emc->debugfs.root); 1993 1993 tegra210_clk_emc_detach(emc->clk); 1994 1994 of_reserved_mem_device_release(emc->dev); 1995 - 1996 - return 0; 1997 1995 } 1998 1996 1999 1997 static int __maybe_unused tegra210_emc_suspend(struct device *dev) ··· 2051 2053 .pm = &tegra210_emc_pm_ops, 2052 2054 }, 2053 2055 .probe = tegra210_emc_probe, 2054 - .remove = tegra210_emc_remove, 2056 + .remove_new = tegra210_emc_remove, 2055 2057 }; 2056 2058 2057 2059 module_platform_driver(tegra210_emc_driver);
+2 -3
drivers/memory/ti-aemif.c
··· 427 427 return ret; 428 428 } 429 429 430 - static int aemif_remove(struct platform_device *pdev) 430 + static void aemif_remove(struct platform_device *pdev) 431 431 { 432 432 struct aemif_device *aemif = platform_get_drvdata(pdev); 433 433 434 434 clk_disable_unprepare(aemif->clk); 435 - return 0; 436 435 } 437 436 438 437 static struct platform_driver aemif_driver = { 439 438 .probe = aemif_probe, 440 - .remove = aemif_remove, 439 + .remove_new = aemif_remove, 441 440 .driver = { 442 441 .name = "ti-aemif", 443 442 .of_match_table = of_match_ptr(aemif_of_match),
+2 -4
drivers/memory/ti-emif-pm.c
··· 315 315 return ret; 316 316 } 317 317 318 - static int ti_emif_remove(struct platform_device *pdev) 318 + static void ti_emif_remove(struct platform_device *pdev) 319 319 { 320 320 struct ti_emif_data *emif_data = emif_instance; 321 321 322 322 emif_instance = NULL; 323 323 324 324 ti_emif_free_sram(emif_data); 325 - 326 - return 0; 327 325 } 328 326 329 327 static const struct dev_pm_ops ti_emif_pm_ops = { ··· 330 332 331 333 static struct platform_driver ti_emif_driver = { 332 334 .probe = ti_emif_probe, 333 - .remove = ti_emif_remove, 335 + .remove_new = ti_emif_remove, 334 336 .driver = { 335 337 .name = KBUILD_MODNAME, 336 338 .of_match_table = ti_emif_of_match,
+1 -2
drivers/reset/reset-brcmstb.c
··· 90 90 if (!priv) 91 91 return -ENOMEM; 92 92 93 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 94 - priv->base = devm_ioremap_resource(kdev, res); 93 + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 95 94 if (IS_ERR(priv->base)) 96 95 return PTR_ERR(priv->base); 97 96
+1 -3
drivers/reset/reset-meson-audio-arb.c
··· 139 139 struct device *dev = &pdev->dev; 140 140 const struct meson_audio_arb_match_data *data; 141 141 struct meson_audio_arb_data *arb; 142 - struct resource *res; 143 142 int ret; 144 143 145 144 data = of_device_get_match_data(dev); ··· 154 155 if (IS_ERR(arb->clk)) 155 156 return dev_err_probe(dev, PTR_ERR(arb->clk), "failed to get clock\n"); 156 157 157 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 158 - arb->regs = devm_ioremap_resource(dev, res); 158 + arb->regs = devm_platform_ioremap_resource(pdev, 0); 159 159 if (IS_ERR(arb->regs)) 160 160 return PTR_ERR(arb->regs); 161 161
+1
drivers/reset/reset-meson.c
··· 108 108 { .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param}, 109 109 { .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param}, 110 110 { .compatible = "amlogic,meson-s4-reset", .data = &meson_s4_param}, 111 + { .compatible = "amlogic,c3-reset", .data = &meson_s4_param}, 111 112 { /* sentinel */ }, 112 113 }; 113 114 MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
+2 -3
drivers/reset/reset-npcm.c
··· 6 6 #include <linux/io.h> 7 7 #include <linux/init.h> 8 8 #include <linux/of.h> 9 - #include <linux/of_device.h> 10 9 #include <linux/platform_device.h> 10 + #include <linux/property.h> 11 11 #include <linux/reboot.h> 12 12 #include <linux/reset-controller.h> 13 13 #include <linux/spinlock.h> ··· 351 351 } 352 352 } 353 353 354 - rc->info = (const struct npcm_reset_info *) 355 - of_match_device(dev->driver->of_match_table, dev)->data; 354 + rc->info = device_get_match_data(dev); 356 355 switch (rc->info->bmc_id) { 357 356 case BMC_NPCM7XX: 358 357 npcm_usb_reset_npcm7xx(rc);
+1 -3
drivers/reset/reset-qcom-aoss.c
··· 90 90 struct qcom_aoss_reset_data *data; 91 91 struct device *dev = &pdev->dev; 92 92 const struct qcom_aoss_desc *desc; 93 - struct resource *res; 94 93 95 94 desc = of_device_get_match_data(dev); 96 95 if (!desc) ··· 100 101 return -ENOMEM; 101 102 102 103 data->desc = desc; 103 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 104 - data->base = devm_ioremap_resource(dev, res); 104 + data->base = devm_platform_ioremap_resource(pdev, 0); 105 105 if (IS_ERR(data->base)) 106 106 return PTR_ERR(data->base); 107 107
+1 -3
drivers/reset/reset-qcom-pdc.c
··· 114 114 struct qcom_pdc_reset_data *data; 115 115 struct device *dev = &pdev->dev; 116 116 void __iomem *base; 117 - struct resource *res; 118 117 119 118 desc = device_get_match_data(&pdev->dev); 120 119 if (!desc) ··· 124 125 return -ENOMEM; 125 126 126 127 data->desc = desc; 127 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 128 - base = devm_ioremap_resource(dev, res); 128 + base = devm_platform_ioremap_resource(pdev, 0); 129 129 if (IS_ERR(base)) 130 130 return PTR_ERR(base); 131 131
+1 -2
drivers/reset/reset-simple.c
··· 169 169 if (!data) 170 170 return -ENOMEM; 171 171 172 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 173 - membase = devm_ioremap_resource(dev, res); 172 + membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 174 173 if (IS_ERR(membase)) 175 174 return PTR_ERR(membase); 176 175
+1 -2
drivers/reset/reset-sunplus.c
··· 176 176 if (!reset) 177 177 return -ENOMEM; 178 178 179 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 180 - reset->base = devm_ioremap_resource(dev, res); 179 + reset->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 181 180 if (IS_ERR(reset->base)) 182 181 return PTR_ERR(reset->base); 183 182
+1 -2
drivers/reset/reset-uniphier-glue.c
··· 58 58 priv->data->nrsts > MAX_RSTS)) 59 59 return -EINVAL; 60 60 61 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 62 - priv->rdata.membase = devm_ioremap_resource(dev, res); 61 + priv->rdata.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 63 62 if (IS_ERR(priv->rdata.membase)) 64 63 return PTR_ERR(priv->rdata.membase); 65 64
+6 -5
drivers/reset/sti/reset-syscfg.c
··· 7 7 */ 8 8 #include <linux/kernel.h> 9 9 #include <linux/platform_device.h> 10 + #include <linux/property.h> 10 11 #include <linux/module.h> 11 12 #include <linux/err.h> 12 13 #include <linux/types.h> 13 - #include <linux/of_device.h> 14 + #include <linux/of.h> 14 15 #include <linux/regmap.h> 15 16 #include <linux/mfd/syscon.h> 16 17 ··· 184 183 int syscfg_reset_probe(struct platform_device *pdev) 185 184 { 186 185 struct device *dev = pdev ? &pdev->dev : NULL; 187 - const struct of_device_id *match; 186 + const void *data; 188 187 189 188 if (!dev || !dev->driver) 190 189 return -ENODEV; 191 190 192 - match = of_match_device(dev->driver->of_match_table, dev); 193 - if (!match || !match->data) 191 + data = device_get_match_data(&pdev->dev); 192 + if (!data) 194 193 return -EINVAL; 195 194 196 - return syscfg_reset_controller_register(dev, match->data); 195 + return syscfg_reset_controller_register(dev, data); 197 196 }
-1
drivers/soc/Kconfig
··· 22 22 source "drivers/soc/renesas/Kconfig" 23 23 source "drivers/soc/rockchip/Kconfig" 24 24 source "drivers/soc/samsung/Kconfig" 25 - source "drivers/soc/sifive/Kconfig" 26 25 source "drivers/soc/sunxi/Kconfig" 27 26 source "drivers/soc/tegra/Kconfig" 28 27 source "drivers/soc/ti/Kconfig"
-1
drivers/soc/Makefile
··· 28 28 obj-y += renesas/ 29 29 obj-y += rockchip/ 30 30 obj-$(CONFIG_SOC_SAMSUNG) += samsung/ 31 - obj-y += sifive/ 32 31 obj-y += sunxi/ 33 32 obj-$(CONFIG_ARCH_TEGRA) += tegra/ 34 33 obj-y += ti/
+14 -1
drivers/soc/apple/Kconfig
··· 4 4 5 5 menu "Apple SoC drivers" 6 6 7 + config APPLE_MAILBOX 8 + tristate "Apple SoC mailboxes" 9 + depends on PM 10 + depends on ARCH_APPLE || (64BIT && COMPILE_TEST) 11 + default ARCH_APPLE 12 + help 13 + Apple SoCs have various co-processors required for certain 14 + peripherals to work (NVMe, display controller, etc.). This 15 + driver adds support for the mailbox controller used to 16 + communicate with those. 17 + 18 + Say Y here if you have an Apple SoC. 19 + 7 20 config APPLE_RTKIT 8 21 tristate "Apple RTKit co-processor IPC protocol" 9 - depends on MAILBOX 22 + depends on APPLE_MAILBOX 10 23 depends on ARCH_APPLE || COMPILE_TEST 11 24 default ARCH_APPLE 12 25 help
+4
drivers/soc/apple/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 + 3 + obj-$(CONFIG_APPLE_MAILBOX) += apple-mailbox.o 4 + apple-mailbox-y = mailbox.o 5 + 2 6 obj-$(CONFIG_APPLE_RTKIT) += apple-rtkit.o 3 7 apple-rtkit-y = rtkit.o rtkit-crashlog.o 4 8
+437
drivers/soc/apple/mailbox.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only OR MIT 2 + /* 3 + * Apple mailbox driver 4 + * 5 + * Copyright The Asahi Linux Contributors 6 + * 7 + * This driver adds support for two mailbox variants (called ASC and M3 by 8 + * Apple) found in Apple SoCs such as the M1. It consists of two FIFOs used to 9 + * exchange 64+32 bit messages between the main CPU and a co-processor. 10 + * Various coprocessors implement different IPC protocols based on these simple 11 + * messages and shared memory buffers. 12 + * 13 + * Both the main CPU and the co-processor see the same set of registers but 14 + * the first FIFO (A2I) is always used to transfer messages from the application 15 + * processor (us) to the I/O processor and the second one (I2A) for the 16 + * other direction. 17 + */ 18 + 19 + #include <linux/bitfield.h> 20 + #include <linux/bits.h> 21 + #include <linux/delay.h> 22 + #include <linux/device.h> 23 + #include <linux/interrupt.h> 24 + #include <linux/io.h> 25 + #include <linux/iopoll.h> 26 + #include <linux/module.h> 27 + #include <linux/of.h> 28 + #include <linux/of_platform.h> 29 + #include <linux/platform_device.h> 30 + #include <linux/pm_runtime.h> 31 + #include <linux/spinlock.h> 32 + #include <linux/types.h> 33 + #include "mailbox.h" 34 + 35 + #define APPLE_ASC_MBOX_CONTROL_FULL BIT(16) 36 + #define APPLE_ASC_MBOX_CONTROL_EMPTY BIT(17) 37 + 38 + #define APPLE_ASC_MBOX_A2I_CONTROL 0x110 39 + #define APPLE_ASC_MBOX_A2I_SEND0 0x800 40 + #define APPLE_ASC_MBOX_A2I_SEND1 0x808 41 + #define APPLE_ASC_MBOX_A2I_RECV0 0x810 42 + #define APPLE_ASC_MBOX_A2I_RECV1 0x818 43 + 44 + #define APPLE_ASC_MBOX_I2A_CONTROL 0x114 45 + #define APPLE_ASC_MBOX_I2A_SEND0 0x820 46 + #define APPLE_ASC_MBOX_I2A_SEND1 0x828 47 + #define APPLE_ASC_MBOX_I2A_RECV0 0x830 48 + #define APPLE_ASC_MBOX_I2A_RECV1 0x838 49 + 50 + #define APPLE_M3_MBOX_CONTROL_FULL BIT(16) 51 + #define APPLE_M3_MBOX_CONTROL_EMPTY BIT(17) 52 + 53 + #define APPLE_M3_MBOX_A2I_CONTROL 0x50 54 + #define APPLE_M3_MBOX_A2I_SEND0 0x60 55 + #define APPLE_M3_MBOX_A2I_SEND1 0x68 56 + #define APPLE_M3_MBOX_A2I_RECV0 0x70 57 + #define APPLE_M3_MBOX_A2I_RECV1 0x78 58 + 59 + #define APPLE_M3_MBOX_I2A_CONTROL 0x80 60 + #define APPLE_M3_MBOX_I2A_SEND0 0x90 61 + #define APPLE_M3_MBOX_I2A_SEND1 0x98 62 + #define APPLE_M3_MBOX_I2A_RECV0 0xa0 63 + #define APPLE_M3_MBOX_I2A_RECV1 0xa8 64 + 65 + #define APPLE_M3_MBOX_IRQ_ENABLE 0x48 66 + #define APPLE_M3_MBOX_IRQ_ACK 0x4c 67 + #define APPLE_M3_MBOX_IRQ_A2I_EMPTY BIT(0) 68 + #define APPLE_M3_MBOX_IRQ_A2I_NOT_EMPTY BIT(1) 69 + #define APPLE_M3_MBOX_IRQ_I2A_EMPTY BIT(2) 70 + #define APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY BIT(3) 71 + 72 + #define APPLE_MBOX_MSG1_OUTCNT GENMASK(56, 52) 73 + #define APPLE_MBOX_MSG1_INCNT GENMASK(51, 48) 74 + #define APPLE_MBOX_MSG1_OUTPTR GENMASK(47, 44) 75 + #define APPLE_MBOX_MSG1_INPTR GENMASK(43, 40) 76 + #define APPLE_MBOX_MSG1_MSG GENMASK(31, 0) 77 + 78 + #define APPLE_MBOX_TX_TIMEOUT 500 79 + 80 + struct apple_mbox_hw { 81 + unsigned int control_full; 82 + unsigned int control_empty; 83 + 84 + unsigned int a2i_control; 85 + unsigned int a2i_send0; 86 + unsigned int a2i_send1; 87 + 88 + unsigned int i2a_control; 89 + unsigned int i2a_recv0; 90 + unsigned int i2a_recv1; 91 + 92 + bool has_irq_controls; 93 + unsigned int irq_enable; 94 + unsigned int irq_ack; 95 + unsigned int irq_bit_recv_not_empty; 96 + unsigned int irq_bit_send_empty; 97 + }; 98 + 99 + int apple_mbox_send(struct apple_mbox *mbox, const struct apple_mbox_msg msg, 100 + bool atomic) 101 + { 102 + unsigned long flags; 103 + int ret; 104 + u32 mbox_ctrl; 105 + long t; 106 + 107 + spin_lock_irqsave(&mbox->tx_lock, flags); 108 + mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->a2i_control); 109 + 110 + while (mbox_ctrl & mbox->hw->control_full) { 111 + if (atomic) { 112 + ret = readl_poll_timeout_atomic( 113 + mbox->regs + mbox->hw->a2i_control, mbox_ctrl, 114 + !(mbox_ctrl & mbox->hw->control_full), 100, 115 + APPLE_MBOX_TX_TIMEOUT * 1000); 116 + 117 + if (ret) { 118 + spin_unlock_irqrestore(&mbox->tx_lock, flags); 119 + return ret; 120 + } 121 + 122 + break; 123 + } 124 + /* 125 + * The interrupt is level triggered and will keep firing as long as the 126 + * FIFO is empty. It will also keep firing if the FIFO was empty 127 + * at any point in the past until it has been acknowledged at the 128 + * mailbox level. By acknowledging it here we can ensure that we will 129 + * only get the interrupt once the FIFO has been cleared again. 130 + * If the FIFO is already empty before the ack it will fire again 131 + * immediately after the ack. 132 + */ 133 + if (mbox->hw->has_irq_controls) { 134 + writel_relaxed(mbox->hw->irq_bit_send_empty, 135 + mbox->regs + mbox->hw->irq_ack); 136 + } 137 + enable_irq(mbox->irq_send_empty); 138 + reinit_completion(&mbox->tx_empty); 139 + spin_unlock_irqrestore(&mbox->tx_lock, flags); 140 + 141 + t = wait_for_completion_interruptible_timeout( 142 + &mbox->tx_empty, 143 + msecs_to_jiffies(APPLE_MBOX_TX_TIMEOUT)); 144 + if (t < 0) 145 + return t; 146 + else if (t == 0) 147 + return -ETIMEDOUT; 148 + 149 + spin_lock_irqsave(&mbox->tx_lock, flags); 150 + mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->a2i_control); 151 + } 152 + 153 + writeq_relaxed(msg.msg0, mbox->regs + mbox->hw->a2i_send0); 154 + writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg.msg1), 155 + mbox->regs + mbox->hw->a2i_send1); 156 + 157 + spin_unlock_irqrestore(&mbox->tx_lock, flags); 158 + 159 + return 0; 160 + } 161 + EXPORT_SYMBOL(apple_mbox_send); 162 + 163 + static irqreturn_t apple_mbox_send_empty_irq(int irq, void *data) 164 + { 165 + struct apple_mbox *mbox = data; 166 + 167 + /* 168 + * We don't need to acknowledge the interrupt at the mailbox level 169 + * here even if supported by the hardware. It will keep firing but that 170 + * doesn't matter since it's disabled at the main interrupt controller. 171 + * apple_mbox_send will acknowledge it before enabling 172 + * it at the main controller again. 173 + */ 174 + spin_lock(&mbox->tx_lock); 175 + disable_irq_nosync(mbox->irq_send_empty); 176 + complete(&mbox->tx_empty); 177 + spin_unlock(&mbox->tx_lock); 178 + 179 + return IRQ_HANDLED; 180 + } 181 + 182 + static int apple_mbox_poll_locked(struct apple_mbox *mbox) 183 + { 184 + struct apple_mbox_msg msg; 185 + int ret = 0; 186 + 187 + u32 mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->i2a_control); 188 + 189 + while (!(mbox_ctrl & mbox->hw->control_empty)) { 190 + msg.msg0 = readq_relaxed(mbox->regs + mbox->hw->i2a_recv0); 191 + msg.msg1 = FIELD_GET( 192 + APPLE_MBOX_MSG1_MSG, 193 + readq_relaxed(mbox->regs + mbox->hw->i2a_recv1)); 194 + 195 + mbox->rx(mbox, msg, mbox->cookie); 196 + ret++; 197 + mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->i2a_control); 198 + } 199 + 200 + /* 201 + * The interrupt will keep firing even if there are no more messages 202 + * unless we also acknowledge it at the mailbox level here. 203 + * There's no race if a message comes in between the check in the while 204 + * loop above and the ack below: If a new messages arrives inbetween 205 + * those two the interrupt will just fire again immediately after the 206 + * ack since it's level triggered. 207 + */ 208 + if (mbox->hw->has_irq_controls) { 209 + writel_relaxed(mbox->hw->irq_bit_recv_not_empty, 210 + mbox->regs + mbox->hw->irq_ack); 211 + } 212 + 213 + return ret; 214 + } 215 + 216 + static irqreturn_t apple_mbox_recv_irq(int irq, void *data) 217 + { 218 + struct apple_mbox *mbox = data; 219 + 220 + spin_lock(&mbox->rx_lock); 221 + apple_mbox_poll_locked(mbox); 222 + spin_unlock(&mbox->rx_lock); 223 + 224 + return IRQ_HANDLED; 225 + } 226 + 227 + int apple_mbox_poll(struct apple_mbox *mbox) 228 + { 229 + unsigned long flags; 230 + int ret; 231 + 232 + spin_lock_irqsave(&mbox->rx_lock, flags); 233 + ret = apple_mbox_poll_locked(mbox); 234 + spin_unlock_irqrestore(&mbox->rx_lock, flags); 235 + 236 + return ret; 237 + } 238 + EXPORT_SYMBOL(apple_mbox_poll); 239 + 240 + int apple_mbox_start(struct apple_mbox *mbox) 241 + { 242 + int ret; 243 + 244 + if (mbox->active) 245 + return 0; 246 + 247 + ret = pm_runtime_resume_and_get(mbox->dev); 248 + if (ret) 249 + return ret; 250 + 251 + /* 252 + * Only some variants of this mailbox HW provide interrupt control 253 + * at the mailbox level. We therefore need to handle enabling/disabling 254 + * interrupts at the main interrupt controller anyway for hardware that 255 + * doesn't. Just always keep the interrupts we care about enabled at 256 + * the mailbox level so that both hardware revisions behave almost 257 + * the same. 258 + */ 259 + if (mbox->hw->has_irq_controls) { 260 + writel_relaxed(mbox->hw->irq_bit_recv_not_empty | 261 + mbox->hw->irq_bit_send_empty, 262 + mbox->regs + mbox->hw->irq_enable); 263 + } 264 + 265 + enable_irq(mbox->irq_recv_not_empty); 266 + mbox->active = true; 267 + return 0; 268 + } 269 + EXPORT_SYMBOL(apple_mbox_start); 270 + 271 + void apple_mbox_stop(struct apple_mbox *mbox) 272 + { 273 + if (!mbox->active) 274 + return; 275 + 276 + mbox->active = false; 277 + disable_irq(mbox->irq_recv_not_empty); 278 + pm_runtime_mark_last_busy(mbox->dev); 279 + pm_runtime_put_autosuspend(mbox->dev); 280 + } 281 + EXPORT_SYMBOL(apple_mbox_stop); 282 + 283 + struct apple_mbox *apple_mbox_get(struct device *dev, int index) 284 + { 285 + struct of_phandle_args args; 286 + struct platform_device *pdev; 287 + struct apple_mbox *mbox; 288 + int ret; 289 + 290 + ret = of_parse_phandle_with_args(dev->of_node, "mboxes", "#mbox-cells", 291 + index, &args); 292 + if (ret || !args.np) 293 + return ERR_PTR(ret); 294 + 295 + pdev = of_find_device_by_node(args.np); 296 + of_node_put(args.np); 297 + 298 + if (!pdev) 299 + return ERR_PTR(EPROBE_DEFER); 300 + 301 + mbox = platform_get_drvdata(pdev); 302 + if (!mbox) 303 + return ERR_PTR(EPROBE_DEFER); 304 + 305 + if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_CONSUMER)) 306 + return ERR_PTR(ENODEV); 307 + 308 + return mbox; 309 + } 310 + EXPORT_SYMBOL(apple_mbox_get); 311 + 312 + struct apple_mbox *apple_mbox_get_byname(struct device *dev, const char *name) 313 + { 314 + int index; 315 + 316 + index = of_property_match_string(dev->of_node, "mbox-names", name); 317 + if (index < 0) 318 + return ERR_PTR(index); 319 + 320 + return apple_mbox_get(dev, index); 321 + } 322 + EXPORT_SYMBOL(apple_mbox_get_byname); 323 + 324 + static int apple_mbox_probe(struct platform_device *pdev) 325 + { 326 + int ret; 327 + char *irqname; 328 + struct apple_mbox *mbox; 329 + struct device *dev = &pdev->dev; 330 + 331 + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); 332 + if (!mbox) 333 + return -ENOMEM; 334 + 335 + mbox->dev = &pdev->dev; 336 + mbox->hw = of_device_get_match_data(dev); 337 + if (!mbox->hw) 338 + return -EINVAL; 339 + 340 + mbox->regs = devm_platform_ioremap_resource(pdev, 0); 341 + if (IS_ERR(mbox->regs)) 342 + return PTR_ERR(mbox->regs); 343 + 344 + mbox->irq_recv_not_empty = 345 + platform_get_irq_byname(pdev, "recv-not-empty"); 346 + if (mbox->irq_recv_not_empty < 0) 347 + return -ENODEV; 348 + 349 + mbox->irq_send_empty = platform_get_irq_byname(pdev, "send-empty"); 350 + if (mbox->irq_send_empty < 0) 351 + return -ENODEV; 352 + 353 + spin_lock_init(&mbox->rx_lock); 354 + spin_lock_init(&mbox->tx_lock); 355 + init_completion(&mbox->tx_empty); 356 + 357 + irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-recv", dev_name(dev)); 358 + if (!irqname) 359 + return -ENOMEM; 360 + 361 + ret = devm_request_irq(dev, mbox->irq_recv_not_empty, 362 + apple_mbox_recv_irq, 363 + IRQF_NO_AUTOEN | IRQF_NO_SUSPEND, irqname, mbox); 364 + if (ret) 365 + return ret; 366 + 367 + irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-send", dev_name(dev)); 368 + if (!irqname) 369 + return -ENOMEM; 370 + 371 + ret = devm_request_irq(dev, mbox->irq_send_empty, 372 + apple_mbox_send_empty_irq, 373 + IRQF_NO_AUTOEN | IRQF_NO_SUSPEND, irqname, mbox); 374 + if (ret) 375 + return ret; 376 + 377 + ret = devm_pm_runtime_enable(dev); 378 + if (ret) 379 + return ret; 380 + 381 + platform_set_drvdata(pdev, mbox); 382 + return 0; 383 + } 384 + 385 + static const struct apple_mbox_hw apple_mbox_asc_hw = { 386 + .control_full = APPLE_ASC_MBOX_CONTROL_FULL, 387 + .control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY, 388 + 389 + .a2i_control = APPLE_ASC_MBOX_A2I_CONTROL, 390 + .a2i_send0 = APPLE_ASC_MBOX_A2I_SEND0, 391 + .a2i_send1 = APPLE_ASC_MBOX_A2I_SEND1, 392 + 393 + .i2a_control = APPLE_ASC_MBOX_I2A_CONTROL, 394 + .i2a_recv0 = APPLE_ASC_MBOX_I2A_RECV0, 395 + .i2a_recv1 = APPLE_ASC_MBOX_I2A_RECV1, 396 + 397 + .has_irq_controls = false, 398 + }; 399 + 400 + static const struct apple_mbox_hw apple_mbox_m3_hw = { 401 + .control_full = APPLE_M3_MBOX_CONTROL_FULL, 402 + .control_empty = APPLE_M3_MBOX_CONTROL_EMPTY, 403 + 404 + .a2i_control = APPLE_M3_MBOX_A2I_CONTROL, 405 + .a2i_send0 = APPLE_M3_MBOX_A2I_SEND0, 406 + .a2i_send1 = APPLE_M3_MBOX_A2I_SEND1, 407 + 408 + .i2a_control = APPLE_M3_MBOX_I2A_CONTROL, 409 + .i2a_recv0 = APPLE_M3_MBOX_I2A_RECV0, 410 + .i2a_recv1 = APPLE_M3_MBOX_I2A_RECV1, 411 + 412 + .has_irq_controls = true, 413 + .irq_enable = APPLE_M3_MBOX_IRQ_ENABLE, 414 + .irq_ack = APPLE_M3_MBOX_IRQ_ACK, 415 + .irq_bit_recv_not_empty = APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY, 416 + .irq_bit_send_empty = APPLE_M3_MBOX_IRQ_A2I_EMPTY, 417 + }; 418 + 419 + static const struct of_device_id apple_mbox_of_match[] = { 420 + { .compatible = "apple,asc-mailbox-v4", .data = &apple_mbox_asc_hw }, 421 + { .compatible = "apple,m3-mailbox-v2", .data = &apple_mbox_m3_hw }, 422 + {} 423 + }; 424 + MODULE_DEVICE_TABLE(of, apple_mbox_of_match); 425 + 426 + static struct platform_driver apple_mbox_driver = { 427 + .driver = { 428 + .name = "apple-mailbox", 429 + .of_match_table = apple_mbox_of_match, 430 + }, 431 + .probe = apple_mbox_probe, 432 + }; 433 + module_platform_driver(apple_mbox_driver); 434 + 435 + MODULE_LICENSE("Dual MIT/GPL"); 436 + MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>"); 437 + MODULE_DESCRIPTION("Apple Mailbox driver");
+48
drivers/soc/apple/mailbox.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 + /* 3 + * Apple mailbox message format 4 + * 5 + * Copyright The Asahi Linux Contributors 6 + */ 7 + 8 + #ifndef _APPLE_MAILBOX_H_ 9 + #define _APPLE_MAILBOX_H_ 10 + 11 + #include <linux/device.h> 12 + #include <linux/types.h> 13 + 14 + /* encodes a single 96bit message sent over the single channel */ 15 + struct apple_mbox_msg { 16 + u64 msg0; 17 + u32 msg1; 18 + }; 19 + 20 + struct apple_mbox { 21 + struct device *dev; 22 + void __iomem *regs; 23 + const struct apple_mbox_hw *hw; 24 + bool active; 25 + 26 + int irq_recv_not_empty; 27 + int irq_send_empty; 28 + 29 + spinlock_t rx_lock; 30 + spinlock_t tx_lock; 31 + 32 + struct completion tx_empty; 33 + 34 + /** Receive callback for incoming messages */ 35 + void (*rx)(struct apple_mbox *mbox, struct apple_mbox_msg msg, void *cookie); 36 + void *cookie; 37 + }; 38 + 39 + struct apple_mbox *apple_mbox_get(struct device *dev, int index); 40 + struct apple_mbox *apple_mbox_get_byname(struct device *dev, const char *name); 41 + 42 + int apple_mbox_start(struct apple_mbox *mbox); 43 + void apple_mbox_stop(struct apple_mbox *mbox); 44 + int apple_mbox_poll(struct apple_mbox *mbox); 45 + int apple_mbox_send(struct apple_mbox *mbox, struct apple_mbox_msg msg, 46 + bool atomic); 47 + 48 + #endif
+2 -6
drivers/soc/apple/rtkit-internal.h
··· 7 7 #ifndef _APPLE_RTKIT_INTERAL_H 8 8 #define _APPLE_RTKIT_INTERAL_H 9 9 10 - #include <linux/apple-mailbox.h> 11 10 #include <linux/bitfield.h> 12 11 #include <linux/bitmap.h> 13 12 #include <linux/completion.h> 14 13 #include <linux/dma-mapping.h> 15 14 #include <linux/io.h> 16 15 #include <linux/kernel.h> 17 - #include <linux/mailbox_client.h> 18 16 #include <linux/module.h> 19 17 #include <linux/slab.h> 20 18 #include <linux/soc/apple/rtkit.h> 21 19 #include <linux/workqueue.h> 20 + #include "mailbox.h" 22 21 23 22 #define APPLE_RTKIT_APP_ENDPOINT_START 0x20 24 23 #define APPLE_RTKIT_MAX_ENDPOINTS 0x100 ··· 27 28 const struct apple_rtkit_ops *ops; 28 29 struct device *dev; 29 30 30 - const char *mbox_name; 31 - int mbox_idx; 32 - struct mbox_client mbox_cl; 33 - struct mbox_chan *mbox_chan; 31 + struct apple_mbox *mbox; 34 32 35 33 struct completion epmap_completion; 36 34 struct completion iop_pwr_ack_completion;
+28 -105
drivers/soc/apple/rtkit.c
··· 72 72 #define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11 73 73 #define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12 74 74 75 - struct apple_rtkit_msg { 76 - struct completion *completion; 77 - struct apple_mbox_msg mbox_msg; 78 - }; 79 - 80 75 struct apple_rtkit_rx_work { 81 76 struct apple_rtkit *rtk; 82 77 u8 ep; ··· 545 550 kfree(rtk_work); 546 551 } 547 552 548 - static void apple_rtkit_rx(struct mbox_client *cl, void *mssg) 553 + static void apple_rtkit_rx(struct apple_mbox *mbox, struct apple_mbox_msg msg, 554 + void *cookie) 549 555 { 550 - struct apple_rtkit *rtk = container_of(cl, struct apple_rtkit, mbox_cl); 551 - struct apple_mbox_msg *msg = mssg; 556 + struct apple_rtkit *rtk = cookie; 552 557 struct apple_rtkit_rx_work *work; 553 - u8 ep = msg->msg1; 558 + u8 ep = msg.msg1; 554 559 555 560 /* 556 561 * The message was read from a MMIO FIFO and we have to make ··· 566 571 567 572 if (ep >= APPLE_RTKIT_APP_ENDPOINT_START && 568 573 rtk->ops->recv_message_early && 569 - rtk->ops->recv_message_early(rtk->cookie, ep, msg->msg0)) 574 + rtk->ops->recv_message_early(rtk->cookie, ep, msg.msg0)) 570 575 return; 571 576 572 577 work = kzalloc(sizeof(*work), GFP_ATOMIC); ··· 575 580 576 581 work->rtk = rtk; 577 582 work->ep = ep; 578 - work->msg = msg->msg0; 583 + work->msg = msg.msg0; 579 584 INIT_WORK(&work->work, apple_rtkit_rx_work); 580 585 queue_work(rtk->wq, &work->work); 581 - } 582 - 583 - static void apple_rtkit_tx_done(struct mbox_client *cl, void *mssg, int r) 584 - { 585 - struct apple_rtkit_msg *msg = 586 - container_of(mssg, struct apple_rtkit_msg, mbox_msg); 587 - 588 - if (r == -ETIME) 589 - return; 590 - 591 - if (msg->completion) 592 - complete(msg->completion); 593 - kfree(msg); 594 586 } 595 587 596 588 int apple_rtkit_send_message(struct apple_rtkit *rtk, u8 ep, u64 message, 597 589 struct completion *completion, bool atomic) 598 590 { 599 - struct apple_rtkit_msg *msg; 600 - int ret; 601 - gfp_t flags; 591 + struct apple_mbox_msg msg = { 592 + .msg0 = message, 593 + .msg1 = ep, 594 + }; 602 595 603 596 if (rtk->crashed) 604 597 return -EINVAL; 605 598 if (ep >= APPLE_RTKIT_APP_ENDPOINT_START && 606 599 !apple_rtkit_is_running(rtk)) 607 600 return -EINVAL; 608 - 609 - if (atomic) 610 - flags = GFP_ATOMIC; 611 - else 612 - flags = GFP_KERNEL; 613 - 614 - msg = kzalloc(sizeof(*msg), flags); 615 - if (!msg) 616 - return -ENOMEM; 617 - 618 - msg->mbox_msg.msg0 = message; 619 - msg->mbox_msg.msg1 = ep; 620 - msg->completion = completion; 621 601 622 602 /* 623 603 * The message will be sent with a MMIO write. We need the barrier ··· 601 631 */ 602 632 dma_wmb(); 603 633 604 - ret = mbox_send_message(rtk->mbox_chan, &msg->mbox_msg); 605 - if (ret < 0) { 606 - kfree(msg); 607 - return ret; 608 - } 609 - 610 - return 0; 634 + return apple_mbox_send(rtk->mbox, msg, atomic); 611 635 } 612 636 EXPORT_SYMBOL_GPL(apple_rtkit_send_message); 613 637 614 - int apple_rtkit_send_message_wait(struct apple_rtkit *rtk, u8 ep, u64 message, 615 - unsigned long timeout, bool atomic) 616 - { 617 - DECLARE_COMPLETION_ONSTACK(completion); 618 - int ret; 619 - long t; 620 - 621 - ret = apple_rtkit_send_message(rtk, ep, message, &completion, atomic); 622 - if (ret < 0) 623 - return ret; 624 - 625 - if (atomic) { 626 - ret = mbox_flush(rtk->mbox_chan, timeout); 627 - if (ret < 0) 628 - return ret; 629 - 630 - if (try_wait_for_completion(&completion)) 631 - return 0; 632 - 633 - return -ETIME; 634 - } else { 635 - t = wait_for_completion_interruptible_timeout( 636 - &completion, msecs_to_jiffies(timeout)); 637 - if (t < 0) 638 - return t; 639 - else if (t == 0) 640 - return -ETIME; 641 - return 0; 642 - } 643 - } 644 - EXPORT_SYMBOL_GPL(apple_rtkit_send_message_wait); 645 - 646 638 int apple_rtkit_poll(struct apple_rtkit *rtk) 647 639 { 648 - return mbox_client_peek_data(rtk->mbox_chan); 640 + return apple_mbox_poll(rtk->mbox); 649 641 } 650 642 EXPORT_SYMBOL_GPL(apple_rtkit_poll); 651 643 ··· 628 696 return 0; 629 697 } 630 698 EXPORT_SYMBOL_GPL(apple_rtkit_start_ep); 631 - 632 - static int apple_rtkit_request_mbox_chan(struct apple_rtkit *rtk) 633 - { 634 - if (rtk->mbox_name) 635 - rtk->mbox_chan = mbox_request_channel_byname(&rtk->mbox_cl, 636 - rtk->mbox_name); 637 - else 638 - rtk->mbox_chan = 639 - mbox_request_channel(&rtk->mbox_cl, rtk->mbox_idx); 640 - 641 - if (IS_ERR(rtk->mbox_chan)) 642 - return PTR_ERR(rtk->mbox_chan); 643 - return 0; 644 - } 645 699 646 700 struct apple_rtkit *apple_rtkit_init(struct device *dev, void *cookie, 647 701 const char *mbox_name, int mbox_idx, ··· 654 736 bitmap_zero(rtk->endpoints, APPLE_RTKIT_MAX_ENDPOINTS); 655 737 set_bit(APPLE_RTKIT_EP_MGMT, rtk->endpoints); 656 738 657 - rtk->mbox_name = mbox_name; 658 - rtk->mbox_idx = mbox_idx; 659 - rtk->mbox_cl.dev = dev; 660 - rtk->mbox_cl.tx_block = false; 661 - rtk->mbox_cl.knows_txdone = false; 662 - rtk->mbox_cl.rx_callback = &apple_rtkit_rx; 663 - rtk->mbox_cl.tx_done = &apple_rtkit_tx_done; 739 + if (mbox_name) 740 + rtk->mbox = apple_mbox_get_byname(dev, mbox_name); 741 + else 742 + rtk->mbox = apple_mbox_get(dev, mbox_idx); 743 + 744 + if (IS_ERR(rtk->mbox)) { 745 + ret = PTR_ERR(rtk->mbox); 746 + goto free_rtk; 747 + } 748 + 749 + rtk->mbox->rx = apple_rtkit_rx; 750 + rtk->mbox->cookie = rtk; 664 751 665 752 rtk->wq = alloc_ordered_workqueue("rtkit-%s", WQ_MEM_RECLAIM, 666 753 dev_name(rtk->dev)); ··· 674 751 goto free_rtk; 675 752 } 676 753 677 - ret = apple_rtkit_request_mbox_chan(rtk); 754 + ret = apple_mbox_start(rtk->mbox); 678 755 if (ret) 679 756 goto destroy_wq; 680 757 ··· 705 782 int apple_rtkit_reinit(struct apple_rtkit *rtk) 706 783 { 707 784 /* make sure we don't handle any messages while reinitializing */ 708 - mbox_free_channel(rtk->mbox_chan); 785 + apple_mbox_stop(rtk->mbox); 709 786 flush_workqueue(rtk->wq); 710 787 711 788 apple_rtkit_free_buffer(rtk, &rtk->ioreport_buffer); ··· 729 806 rtk->iop_power_state = APPLE_RTKIT_PWR_STATE_OFF; 730 807 rtk->ap_power_state = APPLE_RTKIT_PWR_STATE_OFF; 731 808 732 - return apple_rtkit_request_mbox_chan(rtk); 809 + return apple_mbox_start(rtk->mbox); 733 810 } 734 811 EXPORT_SYMBOL_GPL(apple_rtkit_reinit); 735 812 ··· 885 962 886 963 void apple_rtkit_free(struct apple_rtkit *rtk) 887 964 { 888 - mbox_free_channel(rtk->mbox_chan); 965 + apple_mbox_stop(rtk->mbox); 889 966 destroy_workqueue(rtk->wq); 890 967 891 968 apple_rtkit_free_buffer(rtk, &rtk->ioreport_buffer);
+500 -158
drivers/soc/fsl/qe/qmc.c
··· 166 166 struct qmc_xfer_desc { 167 167 union { 168 168 void (*tx_complete)(void *context); 169 - void (*rx_complete)(void *context, size_t length); 169 + void (*rx_complete)(void *context, size_t length, unsigned int flags); 170 170 }; 171 171 void *context; 172 172 }; ··· 175 175 struct list_head list; 176 176 unsigned int id; 177 177 struct qmc *qmc; 178 - void *__iomem s_param; 178 + void __iomem *s_param; 179 179 enum qmc_mode mode; 180 + spinlock_t ts_lock; /* Protect timeslots */ 181 + u64 tx_ts_mask_avail; 180 182 u64 tx_ts_mask; 183 + u64 rx_ts_mask_avail; 181 184 u64 rx_ts_mask; 182 185 bool is_reverse_data; 183 186 ··· 206 203 struct qmc { 207 204 struct device *dev; 208 205 struct tsa_serial *tsa_serial; 209 - void *__iomem scc_regs; 210 - void *__iomem scc_pram; 211 - void *__iomem dpram; 206 + void __iomem *scc_regs; 207 + void __iomem *scc_pram; 208 + void __iomem *dpram; 212 209 u16 scc_pram_offset; 213 210 cbd_t __iomem *bd_table; 214 211 dma_addr_t bd_dma_addr; ··· 217 214 u16 __iomem *int_curr; 218 215 dma_addr_t int_dma_addr; 219 216 size_t int_size; 217 + bool is_tsa_64rxtx; 220 218 struct list_head chan_head; 221 219 struct qmc_chan *chans[64]; 222 220 }; 223 221 224 - static inline void qmc_write16(void *__iomem addr, u16 val) 222 + static void qmc_write16(void __iomem *addr, u16 val) 225 223 { 226 224 iowrite16be(val, addr); 227 225 } 228 226 229 - static inline u16 qmc_read16(void *__iomem addr) 227 + static u16 qmc_read16(void __iomem *addr) 230 228 { 231 229 return ioread16be(addr); 232 230 } 233 231 234 - static inline void qmc_setbits16(void *__iomem addr, u16 set) 232 + static void qmc_setbits16(void __iomem *addr, u16 set) 235 233 { 236 234 qmc_write16(addr, qmc_read16(addr) | set); 237 235 } 238 236 239 - static inline void qmc_clrbits16(void *__iomem addr, u16 clr) 237 + static void qmc_clrbits16(void __iomem *addr, u16 clr) 240 238 { 241 239 qmc_write16(addr, qmc_read16(addr) & ~clr); 242 240 } 243 241 244 - static inline void qmc_write32(void *__iomem addr, u32 val) 242 + static void qmc_clrsetbits16(void __iomem *addr, u16 clr, u16 set) 243 + { 244 + qmc_write16(addr, (qmc_read16(addr) & ~clr) | set); 245 + } 246 + 247 + static void qmc_write32(void __iomem *addr, u32 val) 245 248 { 246 249 iowrite32be(val, addr); 247 250 } 248 251 249 - static inline u32 qmc_read32(void *__iomem addr) 252 + static u32 qmc_read32(void __iomem *addr) 250 253 { 251 254 return ioread32be(addr); 252 255 } 253 256 254 - static inline void qmc_setbits32(void *__iomem addr, u32 set) 257 + static void qmc_setbits32(void __iomem *addr, u32 set) 255 258 { 256 259 qmc_write32(addr, qmc_read32(addr) | set); 257 260 } ··· 266 257 int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info) 267 258 { 268 259 struct tsa_serial_info tsa_info; 260 + unsigned long flags; 269 261 int ret; 270 262 271 263 /* Retrieve info from the TSA related serial */ 272 264 ret = tsa_serial_get_info(chan->qmc->tsa_serial, &tsa_info); 273 265 if (ret) 274 266 return ret; 267 + 268 + spin_lock_irqsave(&chan->ts_lock, flags); 275 269 276 270 info->mode = chan->mode; 277 271 info->rx_fs_rate = tsa_info.rx_fs_rate; ··· 284 272 info->tx_bit_rate = tsa_info.tx_bit_rate; 285 273 info->nb_rx_ts = hweight64(chan->rx_ts_mask); 286 274 275 + spin_unlock_irqrestore(&chan->ts_lock, flags); 276 + 287 277 return 0; 288 278 } 289 279 EXPORT_SYMBOL(qmc_chan_get_info); 280 + 281 + int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info) 282 + { 283 + unsigned long flags; 284 + 285 + spin_lock_irqsave(&chan->ts_lock, flags); 286 + 287 + ts_info->rx_ts_mask_avail = chan->rx_ts_mask_avail; 288 + ts_info->tx_ts_mask_avail = chan->tx_ts_mask_avail; 289 + ts_info->rx_ts_mask = chan->rx_ts_mask; 290 + ts_info->tx_ts_mask = chan->tx_ts_mask; 291 + 292 + spin_unlock_irqrestore(&chan->ts_lock, flags); 293 + 294 + return 0; 295 + } 296 + EXPORT_SYMBOL(qmc_chan_get_ts_info); 297 + 298 + int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info) 299 + { 300 + unsigned long flags; 301 + int ret; 302 + 303 + /* Only a subset of available timeslots is allowed */ 304 + if ((ts_info->rx_ts_mask & chan->rx_ts_mask_avail) != ts_info->rx_ts_mask) 305 + return -EINVAL; 306 + if ((ts_info->tx_ts_mask & chan->tx_ts_mask_avail) != ts_info->tx_ts_mask) 307 + return -EINVAL; 308 + 309 + /* In case of common rx/tx table, rx/tx masks must be identical */ 310 + if (chan->qmc->is_tsa_64rxtx) { 311 + if (ts_info->rx_ts_mask != ts_info->tx_ts_mask) 312 + return -EINVAL; 313 + } 314 + 315 + spin_lock_irqsave(&chan->ts_lock, flags); 316 + 317 + if ((chan->tx_ts_mask != ts_info->tx_ts_mask && !chan->is_tx_stopped) || 318 + (chan->rx_ts_mask != ts_info->rx_ts_mask && !chan->is_rx_stopped)) { 319 + dev_err(chan->qmc->dev, "Channel rx and/or tx not stopped\n"); 320 + ret = -EBUSY; 321 + } else { 322 + chan->tx_ts_mask = ts_info->tx_ts_mask; 323 + chan->rx_ts_mask = ts_info->rx_ts_mask; 324 + ret = 0; 325 + } 326 + spin_unlock_irqrestore(&chan->ts_lock, flags); 327 + 328 + return ret; 329 + } 330 + EXPORT_SYMBOL(qmc_chan_set_ts_info); 290 331 291 332 int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param) 292 333 { ··· 383 318 { 384 319 struct qmc_xfer_desc *xfer_desc; 385 320 unsigned long flags; 386 - cbd_t *__iomem bd; 321 + cbd_t __iomem *bd; 387 322 u16 ctrl; 388 323 int ret; 389 324 ··· 439 374 void (*complete)(void *context); 440 375 unsigned long flags; 441 376 void *context; 442 - cbd_t *__iomem bd; 377 + cbd_t __iomem *bd; 443 378 u16 ctrl; 444 379 445 380 /* ··· 486 421 } 487 422 488 423 int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, 489 - void (*complete)(void *context, size_t length), void *context) 424 + void (*complete)(void *context, size_t length, unsigned int flags), 425 + void *context) 490 426 { 491 427 struct qmc_xfer_desc *xfer_desc; 492 428 unsigned long flags; 493 - cbd_t *__iomem bd; 429 + cbd_t __iomem *bd; 494 430 u16 ctrl; 495 431 int ret; 496 432 ··· 519 453 xfer_desc = &chan->rx_desc[bd - chan->rxbds]; 520 454 xfer_desc->rx_complete = complete; 521 455 xfer_desc->context = context; 456 + 457 + /* Clear previous status flags */ 458 + ctrl &= ~(QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | QMC_BD_RX_NO | 459 + QMC_BD_RX_AB | QMC_BD_RX_CR); 522 460 523 461 /* Activate the descriptor */ 524 462 ctrl |= (QMC_BD_RX_E | QMC_BD_RX_UB); ··· 555 485 556 486 static void qmc_chan_read_done(struct qmc_chan *chan) 557 487 { 558 - void (*complete)(void *context, size_t size); 488 + void (*complete)(void *context, size_t size, unsigned int flags); 559 489 struct qmc_xfer_desc *xfer_desc; 560 490 unsigned long flags; 561 - cbd_t *__iomem bd; 491 + cbd_t __iomem *bd; 562 492 void *context; 563 493 u16 datalen; 564 494 u16 ctrl; ··· 597 527 598 528 if (complete) { 599 529 spin_unlock_irqrestore(&chan->rx_lock, flags); 600 - complete(context, datalen); 530 + 531 + /* 532 + * Avoid conversion between internal hardware flags and 533 + * the software API flags. 534 + * -> Be sure that the software API flags are consistent 535 + * with the hardware flags 536 + */ 537 + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_LAST != QMC_BD_RX_L); 538 + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_FIRST != QMC_BD_RX_F); 539 + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_OVF != QMC_BD_RX_LG); 540 + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_UNA != QMC_BD_RX_NO); 541 + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_ABORT != QMC_BD_RX_AB); 542 + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_CRC != QMC_BD_RX_CR); 543 + 544 + complete(context, datalen, 545 + ctrl & (QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | 546 + QMC_BD_RX_NO | QMC_BD_RX_AB | QMC_BD_RX_CR)); 601 547 spin_lock_irqsave(&chan->rx_lock, flags); 602 548 } 603 549 ··· 623 537 624 538 end: 625 539 spin_unlock_irqrestore(&chan->rx_lock, flags); 540 + } 541 + 542 + static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct tsa_serial_info *info, 543 + bool enable) 544 + { 545 + unsigned int i; 546 + u16 curr; 547 + u16 val; 548 + 549 + /* 550 + * Use a common Tx/Rx 64 entries table. 551 + * Tx and Rx related stuffs must be identical 552 + */ 553 + if (chan->tx_ts_mask != chan->rx_ts_mask) { 554 + dev_err(chan->qmc->dev, "chan %u uses different Rx and Tx TS\n", chan->id); 555 + return -EINVAL; 556 + } 557 + 558 + val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); 559 + 560 + /* Check entries based on Rx stuff*/ 561 + for (i = 0; i < info->nb_rx_ts; i++) { 562 + if (!(chan->rx_ts_mask & (((u64)1) << i))) 563 + continue; 564 + 565 + curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2)); 566 + if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) { 567 + dev_err(chan->qmc->dev, "chan %u TxRx entry %d already used\n", 568 + chan->id, i); 569 + return -EBUSY; 570 + } 571 + } 572 + 573 + /* Set entries based on Rx stuff*/ 574 + for (i = 0; i < info->nb_rx_ts; i++) { 575 + if (!(chan->rx_ts_mask & (((u64)1) << i))) 576 + continue; 577 + 578 + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 579 + ~QMC_TSA_WRAP, enable ? val : 0x0000); 580 + } 581 + 582 + return 0; 583 + } 584 + 585 + static int qmc_chan_setup_tsa_32rx(struct qmc_chan *chan, const struct tsa_serial_info *info, 586 + bool enable) 587 + { 588 + unsigned int i; 589 + u16 curr; 590 + u16 val; 591 + 592 + /* Use a Rx 32 entries table */ 593 + 594 + val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); 595 + 596 + /* Check entries based on Rx stuff */ 597 + for (i = 0; i < info->nb_rx_ts; i++) { 598 + if (!(chan->rx_ts_mask & (((u64)1) << i))) 599 + continue; 600 + 601 + curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2)); 602 + if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) { 603 + dev_err(chan->qmc->dev, "chan %u Rx entry %d already used\n", 604 + chan->id, i); 605 + return -EBUSY; 606 + } 607 + } 608 + 609 + /* Set entries based on Rx stuff */ 610 + for (i = 0; i < info->nb_rx_ts; i++) { 611 + if (!(chan->rx_ts_mask & (((u64)1) << i))) 612 + continue; 613 + 614 + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 615 + ~QMC_TSA_WRAP, enable ? val : 0x0000); 616 + } 617 + 618 + return 0; 619 + } 620 + 621 + static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info, 622 + bool enable) 623 + { 624 + unsigned int i; 625 + u16 curr; 626 + u16 val; 627 + 628 + /* Use a Tx 32 entries table */ 629 + 630 + val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); 631 + 632 + /* Check entries based on Tx stuff */ 633 + for (i = 0; i < info->nb_tx_ts; i++) { 634 + if (!(chan->tx_ts_mask & (((u64)1) << i))) 635 + continue; 636 + 637 + curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2)); 638 + if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) { 639 + dev_err(chan->qmc->dev, "chan %u Tx entry %d already used\n", 640 + chan->id, i); 641 + return -EBUSY; 642 + } 643 + } 644 + 645 + /* Set entries based on Tx stuff */ 646 + for (i = 0; i < info->nb_tx_ts; i++) { 647 + if (!(chan->tx_ts_mask & (((u64)1) << i))) 648 + continue; 649 + 650 + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), 651 + ~QMC_TSA_WRAP, enable ? val : 0x0000); 652 + } 653 + 654 + return 0; 655 + } 656 + 657 + static int qmc_chan_setup_tsa_tx(struct qmc_chan *chan, bool enable) 658 + { 659 + struct tsa_serial_info info; 660 + int ret; 661 + 662 + /* Retrieve info from the TSA related serial */ 663 + ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info); 664 + if (ret) 665 + return ret; 666 + 667 + /* Setup entries */ 668 + if (chan->qmc->is_tsa_64rxtx) 669 + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); 670 + 671 + return qmc_chan_setup_tsa_32tx(chan, &info, enable); 672 + } 673 + 674 + static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan, bool enable) 675 + { 676 + struct tsa_serial_info info; 677 + int ret; 678 + 679 + /* Retrieve info from the TSA related serial */ 680 + ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info); 681 + if (ret) 682 + return ret; 683 + 684 + /* Setup entries */ 685 + if (chan->qmc->is_tsa_64rxtx) 686 + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); 687 + 688 + return qmc_chan_setup_tsa_32rx(chan, &info, enable); 626 689 } 627 690 628 691 static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode) ··· 786 551 787 552 spin_lock_irqsave(&chan->rx_lock, flags); 788 553 554 + if (chan->is_rx_stopped) { 555 + /* The channel is already stopped -> simply return ok */ 556 + ret = 0; 557 + goto end; 558 + } 559 + 789 560 /* Send STOP RECEIVE command */ 790 561 ret = qmc_chan_command(chan, 0x0); 791 562 if (ret) { ··· 801 560 } 802 561 803 562 chan->is_rx_stopped = true; 563 + 564 + if (!chan->qmc->is_tsa_64rxtx || chan->is_tx_stopped) { 565 + ret = qmc_chan_setup_tsa_rx(chan, false); 566 + if (ret) { 567 + dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n", 568 + chan->id, ret); 569 + goto end; 570 + } 571 + } 804 572 805 573 end: 806 574 spin_unlock_irqrestore(&chan->rx_lock, flags); ··· 823 573 824 574 spin_lock_irqsave(&chan->tx_lock, flags); 825 575 576 + if (chan->is_tx_stopped) { 577 + /* The channel is already stopped -> simply return ok */ 578 + ret = 0; 579 + goto end; 580 + } 581 + 826 582 /* Send STOP TRANSMIT command */ 827 583 ret = qmc_chan_command(chan, 0x1); 828 584 if (ret) { ··· 839 583 840 584 chan->is_tx_stopped = true; 841 585 586 + if (!chan->qmc->is_tsa_64rxtx || chan->is_rx_stopped) { 587 + ret = qmc_chan_setup_tsa_tx(chan, false); 588 + if (ret) { 589 + dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n", 590 + chan->id, ret); 591 + goto end; 592 + } 593 + } 594 + 842 595 end: 843 596 spin_unlock_irqrestore(&chan->tx_lock, flags); 844 597 return ret; 845 598 } 846 599 600 + static int qmc_chan_start_rx(struct qmc_chan *chan); 601 + 847 602 int qmc_chan_stop(struct qmc_chan *chan, int direction) 848 603 { 849 - int ret; 604 + bool is_rx_rollback_needed = false; 605 + unsigned long flags; 606 + int ret = 0; 607 + 608 + spin_lock_irqsave(&chan->ts_lock, flags); 850 609 851 610 if (direction & QMC_CHAN_READ) { 611 + is_rx_rollback_needed = !chan->is_rx_stopped; 852 612 ret = qmc_chan_stop_rx(chan); 853 613 if (ret) 854 - return ret; 614 + goto end; 855 615 } 856 616 857 617 if (direction & QMC_CHAN_WRITE) { 858 618 ret = qmc_chan_stop_tx(chan); 859 - if (ret) 860 - return ret; 619 + if (ret) { 620 + /* Restart rx if needed */ 621 + if (is_rx_rollback_needed) 622 + qmc_chan_start_rx(chan); 623 + goto end; 624 + } 861 625 } 862 626 863 - return 0; 627 + end: 628 + spin_unlock_irqrestore(&chan->ts_lock, flags); 629 + return ret; 864 630 } 865 631 EXPORT_SYMBOL(qmc_chan_stop); 866 632 867 - static void qmc_chan_start_rx(struct qmc_chan *chan) 633 + static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan) 634 + { 635 + struct tsa_serial_info info; 636 + u16 first_rx, last_tx; 637 + u16 trnsync; 638 + int ret; 639 + 640 + /* Retrieve info from the TSA related serial */ 641 + ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info); 642 + if (ret) 643 + return ret; 644 + 645 + /* Find the first Rx TS allocated to the channel */ 646 + first_rx = chan->rx_ts_mask ? __ffs64(chan->rx_ts_mask) + 1 : 0; 647 + 648 + /* Find the last Tx TS allocated to the channel */ 649 + last_tx = fls64(chan->tx_ts_mask); 650 + 651 + trnsync = 0; 652 + if (info.nb_rx_ts) 653 + trnsync |= QMC_SPE_TRNSYNC_RX((first_rx % info.nb_rx_ts) * 2); 654 + if (info.nb_tx_ts) 655 + trnsync |= QMC_SPE_TRNSYNC_TX((last_tx % info.nb_tx_ts) * 2); 656 + 657 + qmc_write16(chan->s_param + QMC_SPE_TRNSYNC, trnsync); 658 + 659 + dev_dbg(qmc->dev, "chan %u: trnsync=0x%04x, rx %u/%u 0x%llx, tx %u/%u 0x%llx\n", 660 + chan->id, trnsync, 661 + first_rx, info.nb_rx_ts, chan->rx_ts_mask, 662 + last_tx, info.nb_tx_ts, chan->tx_ts_mask); 663 + 664 + return 0; 665 + } 666 + 667 + static int qmc_chan_start_rx(struct qmc_chan *chan) 868 668 { 869 669 unsigned long flags; 670 + int ret; 870 671 871 672 spin_lock_irqsave(&chan->rx_lock, flags); 673 + 674 + if (!chan->is_rx_stopped) { 675 + /* The channel is already started -> simply return ok */ 676 + ret = 0; 677 + goto end; 678 + } 679 + 680 + ret = qmc_chan_setup_tsa_rx(chan, true); 681 + if (ret) { 682 + dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n", 683 + chan->id, ret); 684 + goto end; 685 + } 686 + 687 + ret = qmc_setup_chan_trnsync(chan->qmc, chan); 688 + if (ret) { 689 + dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n", 690 + chan->id, ret); 691 + goto end; 692 + } 872 693 873 694 /* Restart the receiver */ 874 695 if (chan->mode == QMC_TRANSPARENT) ··· 957 624 958 625 chan->is_rx_stopped = false; 959 626 627 + end: 960 628 spin_unlock_irqrestore(&chan->rx_lock, flags); 629 + return ret; 961 630 } 962 631 963 - static void qmc_chan_start_tx(struct qmc_chan *chan) 632 + static int qmc_chan_start_tx(struct qmc_chan *chan) 964 633 { 965 634 unsigned long flags; 635 + int ret; 966 636 967 637 spin_lock_irqsave(&chan->tx_lock, flags); 638 + 639 + if (!chan->is_tx_stopped) { 640 + /* The channel is already started -> simply return ok */ 641 + ret = 0; 642 + goto end; 643 + } 644 + 645 + ret = qmc_chan_setup_tsa_tx(chan, true); 646 + if (ret) { 647 + dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n", 648 + chan->id, ret); 649 + goto end; 650 + } 651 + 652 + ret = qmc_setup_chan_trnsync(chan->qmc, chan); 653 + if (ret) { 654 + dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n", 655 + chan->id, ret); 656 + goto end; 657 + } 968 658 969 659 /* 970 660 * Enable channel transmitter as it could be disabled if ··· 1000 644 1001 645 chan->is_tx_stopped = false; 1002 646 647 + end: 1003 648 spin_unlock_irqrestore(&chan->tx_lock, flags); 649 + return ret; 1004 650 } 1005 651 1006 652 int qmc_chan_start(struct qmc_chan *chan, int direction) 1007 653 { 1008 - if (direction & QMC_CHAN_READ) 1009 - qmc_chan_start_rx(chan); 654 + bool is_rx_rollback_needed = false; 655 + unsigned long flags; 656 + int ret = 0; 1010 657 1011 - if (direction & QMC_CHAN_WRITE) 1012 - qmc_chan_start_tx(chan); 658 + spin_lock_irqsave(&chan->ts_lock, flags); 1013 659 1014 - return 0; 660 + if (direction & QMC_CHAN_READ) { 661 + is_rx_rollback_needed = chan->is_rx_stopped; 662 + ret = qmc_chan_start_rx(chan); 663 + if (ret) 664 + goto end; 665 + } 666 + 667 + if (direction & QMC_CHAN_WRITE) { 668 + ret = qmc_chan_start_tx(chan); 669 + if (ret) { 670 + /* Restop rx if needed */ 671 + if (is_rx_rollback_needed) 672 + qmc_chan_stop_rx(chan); 673 + goto end; 674 + } 675 + } 676 + 677 + end: 678 + spin_unlock_irqrestore(&chan->ts_lock, flags); 679 + return ret; 1015 680 } 1016 681 EXPORT_SYMBOL(qmc_chan_start); 1017 682 ··· 1040 663 { 1041 664 struct qmc_xfer_desc *xfer_desc; 1042 665 unsigned long flags; 1043 - cbd_t *__iomem bd; 666 + cbd_t __iomem *bd; 1044 667 u16 ctrl; 1045 668 1046 669 spin_lock_irqsave(&chan->rx_lock, flags); ··· 1062 685 qmc_read16(chan->s_param + QMC_SPE_RBASE)); 1063 686 1064 687 chan->rx_pending = 0; 1065 - chan->is_rx_stopped = false; 1066 688 1067 689 spin_unlock_irqrestore(&chan->rx_lock, flags); 1068 690 } ··· 1070 694 { 1071 695 struct qmc_xfer_desc *xfer_desc; 1072 696 unsigned long flags; 1073 - cbd_t *__iomem bd; 697 + cbd_t __iomem *bd; 1074 698 u16 ctrl; 1075 699 1076 700 spin_lock_irqsave(&chan->tx_lock, flags); ··· 1117 741 static int qmc_check_chans(struct qmc *qmc) 1118 742 { 1119 743 struct tsa_serial_info info; 1120 - bool is_one_table = false; 1121 744 struct qmc_chan *chan; 1122 - u64 tx_ts_mask = 0; 1123 - u64 rx_ts_mask = 0; 1124 745 u64 tx_ts_assigned_mask; 1125 746 u64 rx_ts_assigned_mask; 1126 747 int ret; ··· 1141 768 dev_err(qmc->dev, "Number of TSA Tx/Rx TS assigned are not equal\n"); 1142 769 return -EINVAL; 1143 770 } 1144 - is_one_table = true; 1145 771 } 1146 772 1147 773 tx_ts_assigned_mask = info.nb_tx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_tx_ts) - 1; 1148 774 rx_ts_assigned_mask = info.nb_rx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_rx_ts) - 1; 1149 775 1150 776 list_for_each_entry(chan, &qmc->chan_head, list) { 1151 - if (chan->tx_ts_mask > tx_ts_assigned_mask) { 1152 - dev_err(qmc->dev, "chan %u uses TSA unassigned Tx TS\n", chan->id); 1153 - return -EINVAL; 1154 - } 1155 - if (tx_ts_mask & chan->tx_ts_mask) { 1156 - dev_err(qmc->dev, "chan %u uses an already used Tx TS\n", chan->id); 777 + if (chan->tx_ts_mask_avail > tx_ts_assigned_mask) { 778 + dev_err(qmc->dev, "chan %u can use TSA unassigned Tx TS\n", chan->id); 1157 779 return -EINVAL; 1158 780 } 1159 781 1160 - if (chan->rx_ts_mask > rx_ts_assigned_mask) { 1161 - dev_err(qmc->dev, "chan %u uses TSA unassigned Rx TS\n", chan->id); 782 + if (chan->rx_ts_mask_avail > rx_ts_assigned_mask) { 783 + dev_err(qmc->dev, "chan %u can use TSA unassigned Rx TS\n", chan->id); 1162 784 return -EINVAL; 1163 785 } 1164 - if (rx_ts_mask & chan->rx_ts_mask) { 1165 - dev_err(qmc->dev, "chan %u uses an already used Rx TS\n", chan->id); 1166 - return -EINVAL; 1167 - } 1168 - 1169 - if (is_one_table && (chan->tx_ts_mask != chan->rx_ts_mask)) { 1170 - dev_err(qmc->dev, "chan %u uses different Rx and Tx TS\n", chan->id); 1171 - return -EINVAL; 1172 - } 1173 - 1174 - tx_ts_mask |= chan->tx_ts_mask; 1175 - rx_ts_mask |= chan->rx_ts_mask; 1176 786 } 1177 787 1178 788 return 0; ··· 1201 845 } 1202 846 1203 847 chan->id = chan_id; 848 + spin_lock_init(&chan->ts_lock); 1204 849 spin_lock_init(&chan->rx_lock); 1205 850 spin_lock_init(&chan->tx_lock); 1206 851 ··· 1212 855 of_node_put(chan_np); 1213 856 return ret; 1214 857 } 1215 - chan->tx_ts_mask = ts_mask; 858 + chan->tx_ts_mask_avail = ts_mask; 859 + chan->tx_ts_mask = chan->tx_ts_mask_avail; 1216 860 1217 861 ret = of_property_read_u64(chan_np, "fsl,rx-ts-mask", &ts_mask); 1218 862 if (ret) { ··· 1222 864 of_node_put(chan_np); 1223 865 return ret; 1224 866 } 1225 - chan->rx_ts_mask = ts_mask; 867 + chan->rx_ts_mask_avail = ts_mask; 868 + chan->rx_ts_mask = chan->rx_ts_mask_avail; 1226 869 1227 870 mode = "transparent"; 1228 871 ret = of_property_read_string(chan_np, "fsl,operational-mode", &mode); ··· 1254 895 return qmc_check_chans(qmc); 1255 896 } 1256 897 1257 - static int qmc_setup_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *info) 898 + static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *info) 1258 899 { 1259 - struct qmc_chan *chan; 1260 900 unsigned int i; 1261 901 u16 val; 1262 902 ··· 1264 906 * Everything was previously checked, Tx and Rx related stuffs are 1265 907 * identical -> Used Rx related stuff to build the table 1266 908 */ 909 + qmc->is_tsa_64rxtx = true; 1267 910 1268 911 /* Invalidate all entries */ 1269 912 for (i = 0; i < 64; i++) 1270 913 qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000); 1271 - 1272 - /* Set entries based on Rx stuff*/ 1273 - list_for_each_entry(chan, &qmc->chan_head, list) { 1274 - for (i = 0; i < info->nb_rx_ts; i++) { 1275 - if (!(chan->rx_ts_mask & (((u64)1) << i))) 1276 - continue; 1277 - 1278 - val = QMC_TSA_VALID | QMC_TSA_MASK | 1279 - QMC_TSA_CHANNEL(chan->id); 1280 - qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), val); 1281 - } 1282 - } 1283 914 1284 915 /* Set Wrap bit on last entry */ 1285 916 qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATRX + ((info->nb_rx_ts - 1) * 2), ··· 1284 937 return 0; 1285 938 } 1286 939 1287 - static int qmc_setup_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info *info) 940 + static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info *info) 1288 941 { 1289 - struct qmc_chan *chan; 1290 942 unsigned int i; 1291 943 u16 val; 1292 944 ··· 1293 947 * Use a Tx 32 entries table and a Rx 32 entries table. 1294 948 * Everything was previously checked. 1295 949 */ 950 + qmc->is_tsa_64rxtx = false; 1296 951 1297 952 /* Invalidate all entries */ 1298 953 for (i = 0; i < 32; i++) { 1299 954 qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000); 1300 955 qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), 0x0000); 1301 - } 1302 - 1303 - /* Set entries based on Rx and Tx stuff*/ 1304 - list_for_each_entry(chan, &qmc->chan_head, list) { 1305 - /* Rx part */ 1306 - for (i = 0; i < info->nb_rx_ts; i++) { 1307 - if (!(chan->rx_ts_mask & (((u64)1) << i))) 1308 - continue; 1309 - 1310 - val = QMC_TSA_VALID | QMC_TSA_MASK | 1311 - QMC_TSA_CHANNEL(chan->id); 1312 - qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), val); 1313 - } 1314 - /* Tx part */ 1315 - for (i = 0; i < info->nb_tx_ts; i++) { 1316 - if (!(chan->tx_ts_mask & (((u64)1) << i))) 1317 - continue; 1318 - 1319 - val = QMC_TSA_VALID | QMC_TSA_MASK | 1320 - QMC_TSA_CHANNEL(chan->id); 1321 - qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), val); 1322 - } 1323 956 } 1324 957 1325 958 /* Set Wrap bit on last entries */ ··· 1320 995 return 0; 1321 996 } 1322 997 1323 - static int qmc_setup_tsa(struct qmc *qmc) 998 + static int qmc_init_tsa(struct qmc *qmc) 1324 999 { 1325 1000 struct tsa_serial_info info; 1326 1001 int ret; ··· 1331 1006 return ret; 1332 1007 1333 1008 /* 1334 - * Setup one common 64 entries table or two 32 entries (one for Tx and 1335 - * one for Tx) according to assigned TS numbers. 1009 + * Initialize one common 64 entries table or two 32 entries (one for Tx 1010 + * and one for Tx) according to assigned TS numbers. 1336 1011 */ 1337 1012 return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ? 1338 - qmc_setup_tsa_64rxtx(qmc, &info) : 1339 - qmc_setup_tsa_32rx_32tx(qmc, &info); 1340 - } 1341 - 1342 - static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan) 1343 - { 1344 - struct tsa_serial_info info; 1345 - u16 first_rx, last_tx; 1346 - u16 trnsync; 1347 - int ret; 1348 - 1349 - /* Retrieve info from the TSA related serial */ 1350 - ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info); 1351 - if (ret) 1352 - return ret; 1353 - 1354 - /* Find the first Rx TS allocated to the channel */ 1355 - first_rx = chan->rx_ts_mask ? __ffs64(chan->rx_ts_mask) + 1 : 0; 1356 - 1357 - /* Find the last Tx TS allocated to the channel */ 1358 - last_tx = fls64(chan->tx_ts_mask); 1359 - 1360 - trnsync = 0; 1361 - if (info.nb_rx_ts) 1362 - trnsync |= QMC_SPE_TRNSYNC_RX((first_rx % info.nb_rx_ts) * 2); 1363 - if (info.nb_tx_ts) 1364 - trnsync |= QMC_SPE_TRNSYNC_TX((last_tx % info.nb_tx_ts) * 2); 1365 - 1366 - qmc_write16(chan->s_param + QMC_SPE_TRNSYNC, trnsync); 1367 - 1368 - dev_dbg(qmc->dev, "chan %u: trnsync=0x%04x, rx %u/%u 0x%llx, tx %u/%u 0x%llx\n", 1369 - chan->id, trnsync, 1370 - first_rx, info.nb_rx_ts, chan->rx_ts_mask, 1371 - last_tx, info.nb_tx_ts, chan->tx_ts_mask); 1372 - 1373 - return 0; 1013 + qmc_init_tsa_64rxtx(qmc, &info) : 1014 + qmc_init_tsa_32rx_32tx(qmc, &info); 1374 1015 } 1375 1016 1376 1017 static int qmc_setup_chan(struct qmc *qmc, struct qmc_chan *chan) ··· 1658 1367 qmc_write32(qmc->scc_pram + QMC_GBL_C_MASK32, 0xDEBB20E3); 1659 1368 qmc_write16(qmc->scc_pram + QMC_GBL_C_MASK16, 0xF0B8); 1660 1369 1661 - ret = qmc_setup_tsa(qmc); 1370 + ret = qmc_init_tsa(qmc); 1662 1371 if (ret) 1663 1372 goto err_tsa_serial_disconnect; 1664 1373 ··· 1696 1405 1697 1406 platform_set_drvdata(pdev, qmc); 1698 1407 1408 + /* Populate channel related devices */ 1409 + ret = devm_of_platform_populate(qmc->dev); 1410 + if (ret) 1411 + goto err_disable_txrx; 1412 + 1699 1413 return 0; 1414 + 1415 + err_disable_txrx: 1416 + qmc_setbits32(qmc->scc_regs + SCC_GSMRL, 0); 1700 1417 1701 1418 err_disable_intr: 1702 1419 qmc_write16(qmc->scc_regs + SCC_SCCM, 0); ··· 1744 1445 }; 1745 1446 module_platform_driver(qmc_driver); 1746 1447 1747 - struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char *phandle_name) 1448 + static struct qmc_chan *qmc_chan_get_from_qmc(struct device_node *qmc_np, unsigned int chan_index) 1748 1449 { 1749 - struct of_phandle_args out_args; 1750 1450 struct platform_device *pdev; 1751 1451 struct qmc_chan *qmc_chan; 1752 1452 struct qmc *qmc; 1753 - int ret; 1754 1453 1755 - ret = of_parse_phandle_with_fixed_args(np, phandle_name, 1, 0, 1756 - &out_args); 1757 - if (ret < 0) 1758 - return ERR_PTR(ret); 1759 - 1760 - if (!of_match_node(qmc_driver.driver.of_match_table, out_args.np)) { 1761 - of_node_put(out_args.np); 1454 + if (!of_match_node(qmc_driver.driver.of_match_table, qmc_np)) 1762 1455 return ERR_PTR(-EINVAL); 1763 - } 1764 1456 1765 - pdev = of_find_device_by_node(out_args.np); 1766 - of_node_put(out_args.np); 1457 + pdev = of_find_device_by_node(qmc_np); 1767 1458 if (!pdev) 1768 1459 return ERR_PTR(-ENODEV); 1769 1460 ··· 1763 1474 return ERR_PTR(-EPROBE_DEFER); 1764 1475 } 1765 1476 1766 - if (out_args.args_count != 1) { 1477 + if (chan_index >= ARRAY_SIZE(qmc->chans)) { 1767 1478 platform_device_put(pdev); 1768 1479 return ERR_PTR(-EINVAL); 1769 1480 } 1770 1481 1771 - if (out_args.args[0] >= ARRAY_SIZE(qmc->chans)) { 1772 - platform_device_put(pdev); 1773 - return ERR_PTR(-EINVAL); 1774 - } 1775 - 1776 - qmc_chan = qmc->chans[out_args.args[0]]; 1482 + qmc_chan = qmc->chans[chan_index]; 1777 1483 if (!qmc_chan) { 1778 1484 platform_device_put(pdev); 1779 1485 return ERR_PTR(-ENOENT); ··· 1776 1492 1777 1493 return qmc_chan; 1778 1494 } 1495 + 1496 + struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char *phandle_name) 1497 + { 1498 + struct of_phandle_args out_args; 1499 + struct qmc_chan *qmc_chan; 1500 + int ret; 1501 + 1502 + ret = of_parse_phandle_with_fixed_args(np, phandle_name, 1, 0, 1503 + &out_args); 1504 + if (ret < 0) 1505 + return ERR_PTR(ret); 1506 + 1507 + if (out_args.args_count != 1) { 1508 + of_node_put(out_args.np); 1509 + return ERR_PTR(-EINVAL); 1510 + } 1511 + 1512 + qmc_chan = qmc_chan_get_from_qmc(out_args.np, out_args.args[0]); 1513 + of_node_put(out_args.np); 1514 + return qmc_chan; 1515 + } 1779 1516 EXPORT_SYMBOL(qmc_chan_get_byphandle); 1517 + 1518 + struct qmc_chan *qmc_chan_get_bychild(struct device_node *np) 1519 + { 1520 + struct device_node *qmc_np; 1521 + u32 chan_index; 1522 + int ret; 1523 + 1524 + qmc_np = np->parent; 1525 + ret = of_property_read_u32(np, "reg", &chan_index); 1526 + if (ret) 1527 + return ERR_PTR(-EINVAL); 1528 + 1529 + return qmc_chan_get_from_qmc(qmc_np, chan_index); 1530 + } 1531 + EXPORT_SYMBOL(qmc_chan_get_bychild); 1780 1532 1781 1533 void qmc_chan_put(struct qmc_chan *chan) 1782 1534 { ··· 1849 1529 return qmc_chan; 1850 1530 } 1851 1531 EXPORT_SYMBOL(devm_qmc_chan_get_byphandle); 1532 + 1533 + struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, 1534 + struct device_node *np) 1535 + { 1536 + struct qmc_chan *qmc_chan; 1537 + struct qmc_chan **dr; 1538 + 1539 + dr = devres_alloc(devm_qmc_chan_release, sizeof(*dr), GFP_KERNEL); 1540 + if (!dr) 1541 + return ERR_PTR(-ENOMEM); 1542 + 1543 + qmc_chan = qmc_chan_get_bychild(np); 1544 + if (!IS_ERR(qmc_chan)) { 1545 + *dr = qmc_chan; 1546 + devres_add(dev, dr); 1547 + } else { 1548 + devres_free(dr); 1549 + } 1550 + 1551 + return qmc_chan; 1552 + } 1553 + EXPORT_SYMBOL(devm_qmc_chan_get_bychild); 1852 1554 1853 1555 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>"); 1854 1556 MODULE_DESCRIPTION("CPM QMC driver");
+11 -11
drivers/soc/fsl/qe/tsa.c
··· 98 98 #define TSA_SIRP 0x10 99 99 100 100 struct tsa_entries_area { 101 - void *__iomem entries_start; 102 - void *__iomem entries_next; 103 - void *__iomem last_entry; 101 + void __iomem *entries_start; 102 + void __iomem *entries_next; 103 + void __iomem *last_entry; 104 104 }; 105 105 106 106 struct tsa_tdm { ··· 117 117 118 118 struct tsa { 119 119 struct device *dev; 120 - void *__iomem si_regs; 121 - void *__iomem si_ram; 120 + void __iomem *si_regs; 121 + void __iomem *si_ram; 122 122 resource_size_t si_ram_sz; 123 123 spinlock_t lock; 124 124 int tdms; /* TSA_TDMx ORed */ ··· 135 135 return container_of(tsa_serial, struct tsa, serials[tsa_serial->id]); 136 136 } 137 137 138 - static inline void tsa_write32(void *__iomem addr, u32 val) 138 + static inline void tsa_write32(void __iomem *addr, u32 val) 139 139 { 140 140 iowrite32be(val, addr); 141 141 } 142 142 143 - static inline void tsa_write8(void *__iomem addr, u32 val) 143 + static inline void tsa_write8(void __iomem *addr, u32 val) 144 144 { 145 145 iowrite8(val, addr); 146 146 } 147 147 148 - static inline u32 tsa_read32(void *__iomem addr) 148 + static inline u32 tsa_read32(void __iomem *addr) 149 149 { 150 150 return ioread32be(addr); 151 151 } 152 152 153 - static inline void tsa_clrbits32(void *__iomem addr, u32 clr) 153 + static inline void tsa_clrbits32(void __iomem *addr, u32 clr) 154 154 { 155 155 tsa_write32(addr, tsa_read32(addr) & ~clr); 156 156 } 157 157 158 - static inline void tsa_clrsetbits32(void *__iomem addr, u32 clr, u32 set) 158 + static inline void tsa_clrsetbits32(void __iomem *addr, u32 clr, u32 set) 159 159 { 160 160 tsa_write32(addr, (tsa_read32(addr) & ~clr) | set); 161 161 } ··· 313 313 static int tsa_add_entry(struct tsa *tsa, struct tsa_entries_area *area, 314 314 u32 count, u32 serial_id) 315 315 { 316 - void *__iomem addr; 316 + void __iomem *addr; 317 317 u32 left; 318 318 u32 val; 319 319 u32 cnt;
+119 -33
drivers/soc/hisilicon/kunpeng_hccs.c
··· 85 85 struct hccs_register_ctx ctx = {0}; 86 86 acpi_status status; 87 87 88 - if (!acpi_has_method(handle, METHOD_NAME__CRS)) 88 + if (!acpi_has_method(handle, METHOD_NAME__CRS)) { 89 + dev_err(hdev->dev, "No _CRS method.\n"); 89 90 return -ENODEV; 91 + } 90 92 91 93 ctx.dev = hdev->dev; 92 94 status = acpi_walk_resources(handle, METHOD_NAME__CRS, ··· 108 106 else 109 107 pr_debug("TX completed. CMD sent:0x%x, ret:%d\n", 110 108 *(u8 *)msg, ret); 109 + } 110 + 111 + static void hccs_pcc_rx_callback(struct mbox_client *cl, void *mssg) 112 + { 113 + struct hccs_mbox_client_info *cl_info = 114 + container_of(cl, struct hccs_mbox_client_info, client); 115 + 116 + complete(&cl_info->done); 111 117 } 112 118 113 119 static void hccs_unregister_pcc_channel(struct hccs_dev *hdev) ··· 139 129 cl->tx_block = false; 140 130 cl->knows_txdone = true; 141 131 cl->tx_done = hccs_chan_tx_done; 132 + cl->rx_callback = hdev->verspec_data->rx_callback; 133 + init_completion(&cl_info->done); 134 + 142 135 pcc_chan = pcc_mbox_request_channel(cl, hdev->chan_id); 143 136 if (IS_ERR(pcc_chan)) { 144 137 dev_err(dev, "PPC channel request failed.\n"); ··· 158 145 */ 159 146 cl_info->deadline_us = 160 147 HCCS_PCC_CMD_WAIT_RETRIES_NUM * pcc_chan->latency; 161 - if (cl_info->mbox_chan->mbox->txdone_irq) { 148 + if (!hdev->verspec_data->has_txdone_irq && 149 + cl_info->mbox_chan->mbox->txdone_irq) { 162 150 dev_err(dev, "PCC IRQ in PCCT is enabled.\n"); 151 + rc = -EINVAL; 152 + goto err_mbx_channel_free; 153 + } else if (hdev->verspec_data->has_txdone_irq && 154 + !cl_info->mbox_chan->mbox->txdone_irq) { 155 + dev_err(dev, "PCC IRQ in PCCT isn't supported.\n"); 163 156 rc = -EINVAL; 164 157 goto err_mbx_channel_free; 165 158 } ··· 174 155 cl_info->pcc_comm_addr = ioremap(pcc_chan->shmem_base_addr, 175 156 pcc_chan->shmem_size); 176 157 if (!cl_info->pcc_comm_addr) { 177 - dev_err(dev, "Failed to ioremap PCC communication region for channel-%d.\n", 158 + dev_err(dev, "Failed to ioremap PCC communication region for channel-%u.\n", 178 159 hdev->chan_id); 179 160 rc = -ENOMEM; 180 161 goto err_mbx_channel_free; ··· 189 170 return rc; 190 171 } 191 172 192 - static int hccs_check_chan_cmd_complete(struct hccs_dev *hdev) 173 + static int hccs_wait_cmd_complete_by_poll(struct hccs_dev *hdev) 193 174 { 194 175 struct hccs_mbox_client_info *cl_info = &hdev->cl_info; 195 176 struct acpi_pcct_shared_memory __iomem *comm_base = ··· 211 192 return ret; 212 193 } 213 194 195 + static int hccs_wait_cmd_complete_by_irq(struct hccs_dev *hdev) 196 + { 197 + struct hccs_mbox_client_info *cl_info = &hdev->cl_info; 198 + 199 + if (!wait_for_completion_timeout(&cl_info->done, 200 + usecs_to_jiffies(cl_info->deadline_us))) { 201 + dev_err(hdev->dev, "PCC command executed timeout!\n"); 202 + return -ETIMEDOUT; 203 + } 204 + 205 + return 0; 206 + } 207 + 208 + static inline void hccs_fill_pcc_shared_mem_region(struct hccs_dev *hdev, 209 + u8 cmd, 210 + struct hccs_desc *desc, 211 + void __iomem *comm_space, 212 + u16 space_size) 213 + { 214 + struct acpi_pcct_shared_memory tmp = { 215 + .signature = PCC_SIGNATURE | hdev->chan_id, 216 + .command = cmd, 217 + .status = 0, 218 + }; 219 + 220 + memcpy_toio(hdev->cl_info.pcc_comm_addr, (void *)&tmp, 221 + sizeof(struct acpi_pcct_shared_memory)); 222 + 223 + /* Copy the message to the PCC comm space */ 224 + memcpy_toio(comm_space, (void *)desc, space_size); 225 + } 226 + 227 + static inline void hccs_fill_ext_pcc_shared_mem_region(struct hccs_dev *hdev, 228 + u8 cmd, 229 + struct hccs_desc *desc, 230 + void __iomem *comm_space, 231 + u16 space_size) 232 + { 233 + struct acpi_pcct_ext_pcc_shared_memory tmp = { 234 + .signature = PCC_SIGNATURE | hdev->chan_id, 235 + .flags = PCC_CMD_COMPLETION_NOTIFY, 236 + .length = HCCS_PCC_SHARE_MEM_BYTES, 237 + .command = cmd, 238 + }; 239 + 240 + memcpy_toio(hdev->cl_info.pcc_comm_addr, (void *)&tmp, 241 + sizeof(struct acpi_pcct_ext_pcc_shared_memory)); 242 + 243 + /* Copy the message to the PCC comm space */ 244 + memcpy_toio(comm_space, (void *)desc, space_size); 245 + } 246 + 214 247 static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd, 215 248 struct hccs_desc *desc) 216 249 { 250 + const struct hccs_verspecific_data *verspec_data = hdev->verspec_data; 217 251 struct hccs_mbox_client_info *cl_info = &hdev->cl_info; 218 - void __iomem *comm_space = cl_info->pcc_comm_addr + 219 - sizeof(struct acpi_pcct_shared_memory); 220 252 struct hccs_fw_inner_head *fw_inner_head; 221 - struct acpi_pcct_shared_memory tmp = {0}; 222 - u16 comm_space_size; 253 + void __iomem *comm_space; 254 + u16 space_size; 223 255 int ret; 224 256 225 - /* Write signature for this subspace */ 226 - tmp.signature = PCC_SIGNATURE | hdev->chan_id; 227 - /* Write to the shared command region */ 228 - tmp.command = cmd; 229 - /* Clear cmd complete bit */ 230 - tmp.status = 0; 231 - memcpy_toio(cl_info->pcc_comm_addr, (void *)&tmp, 232 - sizeof(struct acpi_pcct_shared_memory)); 233 - 234 - /* Copy the message to the PCC comm space */ 235 - comm_space_size = HCCS_PCC_SHARE_MEM_BYTES - 236 - sizeof(struct acpi_pcct_shared_memory); 237 - memcpy_toio(comm_space, (void *)desc, comm_space_size); 257 + comm_space = cl_info->pcc_comm_addr + verspec_data->shared_mem_size; 258 + space_size = HCCS_PCC_SHARE_MEM_BYTES - verspec_data->shared_mem_size; 259 + verspec_data->fill_pcc_shared_mem(hdev, cmd, desc, 260 + comm_space, space_size); 261 + if (verspec_data->has_txdone_irq) 262 + reinit_completion(&cl_info->done); 238 263 239 264 /* Ring doorbell */ 240 265 ret = mbox_send_message(cl_info->mbox_chan, &cmd); ··· 288 225 goto end; 289 226 } 290 227 291 - /* Wait for completion */ 292 - ret = hccs_check_chan_cmd_complete(hdev); 228 + ret = verspec_data->wait_cmd_complete(hdev); 293 229 if (ret) 294 230 goto end; 295 231 296 232 /* Copy response data */ 297 - memcpy_fromio((void *)desc, comm_space, comm_space_size); 233 + memcpy_fromio((void *)desc, comm_space, space_size); 298 234 fw_inner_head = &desc->rsp.fw_inner_head; 299 235 if (fw_inner_head->retStatus) { 300 236 dev_err(hdev->dev, "Execute PCC command failed, error code = %u.\n", ··· 302 240 } 303 241 304 242 end: 305 - mbox_client_txdone(cl_info->mbox_chan, ret); 243 + if (verspec_data->has_txdone_irq) 244 + mbox_chan_txdone(cl_info->mbox_chan, ret); 245 + else 246 + mbox_client_txdone(cl_info->mbox_chan, ret); 306 247 return ret; 307 248 } 308 249 ··· 592 527 593 528 static int hccs_query_all_port_info_on_platform(struct hccs_dev *hdev) 594 529 { 595 - 596 530 struct device *dev = hdev->dev; 597 531 struct hccs_chip_info *chip; 598 532 struct hccs_die_info *die; ··· 1161 1097 int ret; 1162 1098 1163 1099 ret = kobject_init_and_add(&port->kobj, &hccs_port_type, 1164 - &die->kobj, "hccs%d", port->port_id); 1100 + &die->kobj, "hccs%u", port->port_id); 1165 1101 if (ret) { 1166 1102 kobject_put(&port->kobj); 1167 1103 return ret; ··· 1179 1115 u16 i; 1180 1116 1181 1117 ret = kobject_init_and_add(&die->kobj, &hccs_die_type, 1182 - &chip->kobj, "die%d", die->die_id); 1118 + &chip->kobj, "die%u", die->die_id); 1183 1119 if (ret) { 1184 1120 kobject_put(&die->kobj); 1185 1121 return ret; ··· 1189 1125 port = &die->ports[i]; 1190 1126 ret = hccs_create_hccs_dir(hdev, die, port); 1191 1127 if (ret) { 1192 - dev_err(hdev->dev, "create hccs%d dir failed.\n", 1128 + dev_err(hdev->dev, "create hccs%u dir failed.\n", 1193 1129 port->port_id); 1194 1130 goto err; 1195 1131 } ··· 1211 1147 u16 id; 1212 1148 1213 1149 ret = kobject_init_and_add(&chip->kobj, &hccs_chip_type, 1214 - &hdev->dev->kobj, "chip%d", chip->chip_id); 1150 + &hdev->dev->kobj, "chip%u", chip->chip_id); 1215 1151 if (ret) { 1216 1152 kobject_put(&chip->kobj); 1217 1153 return ret; ··· 1242 1178 chip = &hdev->chips[id]; 1243 1179 ret = hccs_create_chip_dir(hdev, chip); 1244 1180 if (ret) { 1245 - dev_err(hdev->dev, "init chip%d dir failed!\n", id); 1181 + dev_err(hdev->dev, "init chip%u dir failed!\n", id); 1246 1182 goto err; 1247 1183 } 1248 1184 } ··· 1275 1211 hdev->acpi_dev = acpi_dev; 1276 1212 hdev->dev = &pdev->dev; 1277 1213 platform_set_drvdata(pdev, hdev); 1214 + 1215 + /* 1216 + * Here would never be failure as the driver and device has been matched. 1217 + */ 1218 + hdev->verspec_data = acpi_device_get_match_data(hdev->dev); 1278 1219 1279 1220 mutex_init(&hdev->lock); 1280 1221 rc = hccs_get_pcc_chan_id(hdev); ··· 1317 1248 hccs_unregister_pcc_channel(hdev); 1318 1249 } 1319 1250 1251 + static const struct hccs_verspecific_data hisi04b1_verspec_data = { 1252 + .rx_callback = NULL, 1253 + .wait_cmd_complete = hccs_wait_cmd_complete_by_poll, 1254 + .fill_pcc_shared_mem = hccs_fill_pcc_shared_mem_region, 1255 + .shared_mem_size = sizeof(struct acpi_pcct_shared_memory), 1256 + .has_txdone_irq = false, 1257 + }; 1258 + 1259 + static const struct hccs_verspecific_data hisi04b2_verspec_data = { 1260 + .rx_callback = hccs_pcc_rx_callback, 1261 + .wait_cmd_complete = hccs_wait_cmd_complete_by_irq, 1262 + .fill_pcc_shared_mem = hccs_fill_ext_pcc_shared_mem_region, 1263 + .shared_mem_size = sizeof(struct acpi_pcct_ext_pcc_shared_memory), 1264 + .has_txdone_irq = true, 1265 + }; 1266 + 1320 1267 static const struct acpi_device_id hccs_acpi_match[] = { 1321 - { "HISI04B1"}, 1322 - { ""}, 1268 + { "HISI04B1", (unsigned long)&hisi04b1_verspec_data}, 1269 + { "HISI04B2", (unsigned long)&hisi04b2_verspec_data}, 1270 + { } 1323 1271 }; 1324 1272 MODULE_DEVICE_TABLE(acpi, hccs_acpi_match); 1325 1273
+15
drivers/soc/hisilicon/kunpeng_hccs.h
··· 51 51 struct pcc_mbox_chan *pcc_chan; 52 52 u64 deadline_us; 53 53 void __iomem *pcc_comm_addr; 54 + struct completion done; 55 + }; 56 + 57 + struct hccs_desc; 58 + 59 + struct hccs_verspecific_data { 60 + void (*rx_callback)(struct mbox_client *cl, void *mssg); 61 + int (*wait_cmd_complete)(struct hccs_dev *hdev); 62 + void (*fill_pcc_shared_mem)(struct hccs_dev *hdev, 63 + u8 cmd, struct hccs_desc *desc, 64 + void __iomem *comm_space, 65 + u16 space_size); 66 + u16 shared_mem_size; 67 + bool has_txdone_irq; 54 68 }; 55 69 56 70 struct hccs_dev { 57 71 struct device *dev; 58 72 struct acpi_device *acpi_dev; 73 + const struct hccs_verspecific_data *verspec_data; 59 74 u64 caps; 60 75 u8 chip_num; 61 76 struct hccs_chip_info *chips;
+210
drivers/soc/mediatek/mt8188-mmsys.h
··· 3 3 #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H 4 4 #define __SOC_MEDIATEK_MT8188_MMSYS_H 5 5 6 + #include <linux/soc/mediatek/mtk-mmsys.h> 7 + #include <dt-bindings/reset/mt8188-resets.h> 8 + 9 + #define MT8188_VDO0_SW0_RST_B 0x190 6 10 #define MT8188_VDO0_OVL_MOUT_EN 0xf14 7 11 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) 8 12 #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) ··· 70 66 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(17) 71 67 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) 72 68 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) 69 + 70 + #define MT8188_VDO1_SW0_RST_B 0x1d0 71 + #define MT8188_VDO1_HDR_TOP_CFG 0xd00 72 + #define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 73 + #define MT8188_VDO1_MIXER_IN1_PAD 0xd40 74 + #define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c 75 + #define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 76 + #define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 77 + #define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 78 + #define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 79 + #define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 80 + #define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 81 + #define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10 82 + #define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 83 + #define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 84 + #define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 85 + #define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18 86 + #define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2) 87 + #define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3) 88 + #define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24 89 + #define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 90 + #define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28 91 + #define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 92 + #define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c 93 + #define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 94 + #define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30 95 + #define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 96 + #define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34 97 + #define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 98 + #define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c 99 + #define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 100 + #define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 101 + #define MT8188_SOUT_TO_MIXER_IN1_SEL 1 102 + #define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 103 + #define MT8188_SOUT_TO_MIXER_IN2_SEL 1 104 + #define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 105 + #define MT8188_SOUT_TO_MIXER_IN3_SEL 1 106 + #define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c 107 + #define MT8188_SOUT_TO_MIXER_IN4_SEL 1 108 + #define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 109 + #define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 110 + #define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58 111 + #define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0 112 + #define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c 113 + #define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0 114 + #define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60 115 + #define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0 116 + #define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64 117 + #define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0 118 + #define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 119 + #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 120 + 121 + static const u8 mmsys_mt8188_vdo0_rst_tb[] = { 122 + [MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0), 123 + [MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2), 124 + [MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4), 125 + [MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6), 126 + [MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8), 127 + [MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10), 128 + [MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17), 129 + [MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19), 130 + [MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21), 131 + [MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22), 132 + [MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23), 133 + [MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24), 134 + [MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25), 135 + [MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26), 136 + [MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27), 137 + [MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28), 138 + [MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29), 139 + [MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30), 140 + [MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31), 141 + }; 142 + 143 + static const u8 mmsys_mt8188_vdo1_rst_tb[] = { 144 + [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0), 145 + [MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1), 146 + [MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2), 147 + [MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3), 148 + [MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4), 149 + [MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5), 150 + [MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6), 151 + [MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7), 152 + [MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8), 153 + [MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9), 154 + [MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10), 155 + [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11), 156 + [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0), 157 + [MT8188_VDO1_RST_VPP_MERGE4] = MMSYS_RST_NR(1, 1), 158 + [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 2), 159 + [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 3), 160 + [MT8188_VDO1_RST_DISP_MUTEX] = MMSYS_RST_NR(1, 4), 161 + [MT8188_VDO1_RST_MDP_RDMA4] = MMSYS_RST_NR(1, 5), 162 + [MT8188_VDO1_RST_MDP_RDMA5] = MMSYS_RST_NR(1, 6), 163 + [MT8188_VDO1_RST_MDP_RDMA6] = MMSYS_RST_NR(1, 7), 164 + [MT8188_VDO1_RST_MDP_RDMA7] = MMSYS_RST_NR(1, 8), 165 + [MT8188_VDO1_RST_DP_INTF1_MMCK] = MMSYS_RST_NR(1, 9), 166 + [MT8188_VDO1_RST_DPI0_MM_CK] = MMSYS_RST_NR(1, 10), 167 + [MT8188_VDO1_RST_DPI1_MM_CK] = MMSYS_RST_NR(1, 11), 168 + [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = MMSYS_RST_NR(1, 13), 169 + [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = MMSYS_RST_NR(1, 14), 170 + [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = MMSYS_RST_NR(1, 15), 171 + [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = MMSYS_RST_NR(1, 16), 172 + [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = MMSYS_RST_NR(1, 17), 173 + [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 18), 174 + [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 19), 175 + [MT8188_VDO1_RST_PADDING0] = MMSYS_RST_NR(1, 20), 176 + [MT8188_VDO1_RST_PADDING1] = MMSYS_RST_NR(1, 21), 177 + [MT8188_VDO1_RST_PADDING2] = MMSYS_RST_NR(1, 22), 178 + [MT8188_VDO1_RST_PADDING3] = MMSYS_RST_NR(1, 23), 179 + [MT8188_VDO1_RST_PADDING4] = MMSYS_RST_NR(1, 24), 180 + [MT8188_VDO1_RST_PADDING5] = MMSYS_RST_NR(1, 25), 181 + [MT8188_VDO1_RST_PADDING6] = MMSYS_RST_NR(1, 26), 182 + [MT8188_VDO1_RST_PADDING7] = MMSYS_RST_NR(1, 27), 183 + [MT8188_VDO1_RST_DISP_RSZ0] = MMSYS_RST_NR(1, 28), 184 + [MT8188_VDO1_RST_DISP_RSZ1] = MMSYS_RST_NR(1, 29), 185 + [MT8188_VDO1_RST_DISP_RSZ2] = MMSYS_RST_NR(1, 30), 186 + [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31), 187 + [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0), 188 + [MT8188_VDO1_RST_HDR_GFX_FE0] = MMSYS_RST_NR(2, 1), 189 + [MT8188_VDO1_RST_HDR_VDO_BE] = MMSYS_RST_NR(2, 2), 190 + [MT8188_VDO1_RST_HDR_VDO_FE1] = MMSYS_RST_NR(2, 16), 191 + [MT8188_VDO1_RST_HDR_GFX_FE1] = MMSYS_RST_NR(2, 17), 192 + [MT8188_VDO1_RST_DISP_MIXER] = MMSYS_RST_NR(2, 18), 193 + [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 19), 194 + [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 20), 195 + [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 21), 196 + [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 22), 197 + [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23), 198 + }; 73 199 74 200 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { 75 201 { ··· 278 144 MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, 279 145 MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE 280 146 }, 147 + }; 148 + 149 + static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = { 150 + { 151 + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, 152 + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), 153 + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 154 + }, { 155 + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, 156 + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), 157 + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 158 + }, { 159 + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, 160 + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), 161 + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 162 + }, { 163 + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 164 + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), 165 + MT8188_SOUT_TO_MIXER_IN1_SEL 166 + }, { 167 + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 168 + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), 169 + MT8188_SOUT_TO_MIXER_IN2_SEL 170 + }, { 171 + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 172 + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), 173 + MT8188_SOUT_TO_MIXER_IN3_SEL 174 + }, { 175 + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 176 + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), 177 + MT8188_SOUT_TO_MIXER_IN4_SEL 178 + }, { 179 + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 180 + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), 181 + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 182 + }, { 183 + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 184 + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), 185 + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 186 + }, { 187 + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 188 + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), 189 + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 190 + }, { 191 + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 192 + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), 193 + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 194 + }, { 195 + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 196 + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), 197 + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 198 + }, { 199 + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 200 + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), 201 + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 202 + }, { 203 + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 204 + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), 205 + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 206 + }, { 207 + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 208 + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), 209 + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 210 + }, { 211 + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 212 + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 213 + MT8188_MERGE4_SOUT_TO_DPI1_SEL 214 + }, { 215 + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 216 + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), 217 + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 218 + }, { 219 + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 220 + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), 221 + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL 222 + } 281 223 }; 282 224 283 225 #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
+39
drivers/soc/mediatek/mtk-mmsys.c
··· 87 87 .clk_driver = "clk-mt8188-vdo0", 88 88 .routes = mmsys_mt8188_routing_table, 89 89 .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), 90 + .sw0_rst_offset = MT8188_VDO0_SW0_RST_B, 91 + .rst_tb = mmsys_mt8188_vdo0_rst_tb, 92 + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), 93 + }; 94 + 95 + static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { 96 + .clk_driver = "clk-mt8188-vdo1", 97 + .routes = mmsys_mt8188_vdo1_routing_table, 98 + .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), 99 + .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, 100 + .rst_tb = mmsys_mt8188_vdo1_rst_tb, 101 + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), 102 + .vsync_len = 1, 103 + }; 104 + 105 + static const struct mtk_mmsys_driver_data mt8188_vppsys0_driver_data = { 106 + .clk_driver = "clk-mt8188-vpp0", 107 + .is_vppsys = true, 108 + }; 109 + 110 + static const struct mtk_mmsys_driver_data mt8188_vppsys1_driver_data = { 111 + .clk_driver = "clk-mt8188-vpp1", 112 + .is_vppsys = true, 90 113 }; 91 114 92 115 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { ··· 192 169 if (cur == routes[i].from_comp && next == routes[i].to_comp) 193 170 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 194 171 routes[i].val, NULL); 172 + 173 + if (mmsys->data->vsync_len) 174 + mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0), 175 + mmsys->data->vsync_len, NULL); 195 176 } 196 177 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); 197 178 ··· 329 302 u32 offset; 330 303 u32 reg; 331 304 305 + if (mmsys->data->rst_tb) { 306 + if (id >= mmsys->data->num_resets) { 307 + dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n", 308 + id, mmsys->data->num_resets); 309 + return -EINVAL; 310 + } 311 + id = mmsys->data->rst_tb[id]; 312 + } 313 + 332 314 offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); 333 315 id = id % MMSYS_SW_RESET_PER_REG; 334 316 reg = mmsys->data->sw0_rst_offset + offset; ··· 465 429 { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, 466 430 { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data }, 467 431 { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data }, 432 + { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data }, 433 + { .compatible = "mediatek,mt8188-vppsys0", .data = &mt8188_vppsys0_driver_data }, 434 + { .compatible = "mediatek,mt8188-vppsys1", .data = &mt8188_vppsys1_driver_data }, 468 435 { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data }, 469 436 /* "mediatek,mt8195-mmsys" compatible is deprecated */ 470 437 { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
+32
drivers/soc/mediatek/mtk-mmsys.h
··· 78 78 #define DSI_SEL_IN_RDMA 0x1 79 79 #define DSI_SEL_IN_MASK 0x1 80 80 81 + #define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) 82 + 81 83 struct mtk_mmsys_routes { 82 84 u32 from_comp; 83 85 u32 to_comp; ··· 88 86 u32 val; 89 87 }; 90 88 89 + /** 90 + * struct mtk_mmsys_driver_data - Settings of the mmsys 91 + * @clk_driver: Clock driver name that the mmsys is using 92 + * (defined in drivers/clk/mediatek/clk-*.c). 93 + * @routes: Routing table of the mmsys. 94 + * It provides mux settings from one module to another. 95 + * @num_routes: Array size of the routes. 96 + * @sw0_rst_offset: Register offset for the reset control. 97 + * @num_resets: Number of reset bits that are defined 98 + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) 99 + * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver. 100 + * @vsync_len: VSYNC length of the MIXER. 101 + * VSYNC is usually triggered by the connector, so its length is a 102 + * fixed value when the frame rate is decided, but ETHDR and 103 + * MIXER generate their own VSYNC due to hardware design, therefore 104 + * MIXER has to sync with ETHDR by adjusting VSYNC length. 105 + * On MT8195, there is no such setting so we use the gap between 106 + * falling edge and rising edge of SOF (Start of Frame) signal to 107 + * do the job, but since MT8188, VSYNC_LEN setting is introduced to 108 + * solve the problem and is given 0x40 (ticks) as the default value. 109 + * Please notice that this value has to be set to 1 (minimum) if 110 + * ETHDR is bypassed, otherwise MIXER could wait too long and causing 111 + * underflow. 112 + * 113 + * Each MMSYS (multi-media system) may have different settings, they may use 114 + * different clock sources, mux settings, reset control ...etc., and these 115 + * differences are all stored here. 116 + */ 91 117 struct mtk_mmsys_driver_data { 92 118 const char *clk_driver; 93 119 const struct mtk_mmsys_routes *routes; 94 120 const unsigned int num_routes; 95 121 const u16 sw0_rst_offset; 122 + const u8 *rst_tb; 96 123 const u32 num_resets; 97 124 const bool is_vppsys; 125 + const u8 vsync_len; 98 126 }; 99 127 100 128 /*
+51
drivers/soc/mediatek/mtk-mutex.c
··· 133 133 #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 134 134 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 135 135 136 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 137 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 138 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 139 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 140 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 141 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 142 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 143 + #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 144 + #define MT8188_MUTEX_MOD_DISP1_PADDING0 8 145 + #define MT8188_MUTEX_MOD_DISP1_PADDING1 9 146 + #define MT8188_MUTEX_MOD_DISP1_PADDING2 10 147 + #define MT8188_MUTEX_MOD_DISP1_PADDING3 11 148 + #define MT8188_MUTEX_MOD_DISP1_PADDING4 12 149 + #define MT8188_MUTEX_MOD_DISP1_PADDING5 13 150 + #define MT8188_MUTEX_MOD_DISP1_PADDING6 14 151 + #define MT8188_MUTEX_MOD_DISP1_PADDING7 15 152 + #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 153 + #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 154 + #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 155 + #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 156 + #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 157 + #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 158 + #define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 159 + 136 160 #define MT8195_MUTEX_MOD_DISP_OVL0 0 137 161 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 138 162 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 ··· 288 264 #define MT8183_MUTEX_SOF_DPI0 2 289 265 #define MT8188_MUTEX_SOF_DSI0 1 290 266 #define MT8188_MUTEX_SOF_DP_INTF0 3 267 + #define MT8188_MUTEX_SOF_DP_INTF1 4 291 268 #define MT8195_MUTEX_SOF_DSI0 1 292 269 #define MT8195_MUTEX_SOF_DSI1 2 293 270 #define MT8195_MUTEX_SOF_DP_INTF0 3 ··· 300 275 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) 301 276 #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) 302 277 #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) 278 + #define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) 303 279 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) 304 280 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) 305 281 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) ··· 471 445 [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, 472 446 [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, 473 447 [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, 448 + [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1, 449 + [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER, 450 + [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, 451 + [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, 452 + [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, 453 + [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, 454 + [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, 455 + [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, 456 + [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, 457 + [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, 458 + [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0, 459 + [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1, 460 + [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2, 461 + [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3, 462 + [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4, 463 + [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5, 464 + [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6, 465 + [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7, 466 + [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, 467 + [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, 468 + [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, 469 + [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, 470 + [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, 474 471 }; 475 472 476 473 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { ··· 654 605 MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, 655 606 [MUTEX_SOF_DP_INTF0] = 656 607 MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, 608 + [MUTEX_SOF_DP_INTF1] = 609 + MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, 657 610 }; 658 611 659 612 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+1011 -685
drivers/soc/mediatek/mtk-svs.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * Copyright (C) 2022 MediaTek Inc. 4 + * Copyright (C) 2022 Collabora Ltd. 5 + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 4 6 */ 5 7 6 8 #include <linux/bitfield.h> ··· 33 31 #include <linux/slab.h> 34 32 #include <linux/spinlock.h> 35 33 #include <linux/thermal.h> 36 - 37 - /* svs bank 1-line software id */ 38 - #define SVSB_CPU_LITTLE BIT(0) 39 - #define SVSB_CPU_BIG BIT(1) 40 - #define SVSB_CCI BIT(2) 41 - #define SVSB_GPU BIT(3) 42 - 43 - /* svs bank 2-line type */ 44 - #define SVSB_LOW BIT(8) 45 - #define SVSB_HIGH BIT(9) 46 34 47 35 /* svs bank mode support */ 48 36 #define SVSB_MODE_ALL_DISABLE 0 ··· 120 128 #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16) 121 129 #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24) 122 130 131 + /* SVS Thermal Coefficients */ 132 + #define SVSB_TS_COEFF_MT8195 250460 133 + #define SVSB_TS_COEFF_MT8186 204650 134 + 135 + /* Algo helpers */ 136 + #define FUSE_DATA_NOT_VALID U32_MAX 137 + 123 138 /* svs bank related setting */ 124 139 #define BITS8 8 125 140 #define MAX_OPP_ENTRIES 16 ··· 172 173 173 174 #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} 174 175 #endif 176 + 177 + /** 178 + * enum svsb_sw_id - SVS Bank Software ID 179 + * @SVSB_SWID_CPU_LITTLE: CPU little cluster Bank 180 + * @SVSB_SWID_CPU_BIG: CPU big cluster Bank 181 + * @SVSB_SWID_CCI: Cache Coherent Interconnect Bank 182 + * @SVSB_SWID_GPU: GPU Bank 183 + * @SVSB_SWID_MAX: Total number of Banks 184 + */ 185 + enum svsb_sw_id { 186 + SVSB_SWID_CPU_LITTLE, 187 + SVSB_SWID_CPU_BIG, 188 + SVSB_SWID_CCI, 189 + SVSB_SWID_GPU, 190 + SVSB_SWID_MAX 191 + }; 192 + 193 + /** 194 + * enum svsb_type - SVS Bank 2-line: Type and Role 195 + * @SVSB_TYPE_NONE: One-line type Bank - Global role 196 + * @SVSB_TYPE_LOW: Two-line type Bank - Low bank role 197 + * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role 198 + * @SVSB_TYPE_MAX: Total number of bank types 199 + */ 200 + enum svsb_type { 201 + SVSB_TYPE_NONE, 202 + SVSB_TYPE_LOW, 203 + SVSB_TYPE_HIGH, 204 + SVSB_TYPE_MAX 205 + }; 175 206 176 207 /** 177 208 * enum svsb_phase - svs bank phase enumeration ··· 285 256 }; 286 257 287 258 static const u32 svs_regs_v2[] = { 288 - [DESCHAR] = 0xc00, 289 - [TEMPCHAR] = 0xc04, 290 - [DETCHAR] = 0xc08, 291 - [AGECHAR] = 0xc0c, 292 - [DCCONFIG] = 0xc10, 293 - [AGECONFIG] = 0xc14, 294 - [FREQPCT30] = 0xc18, 295 - [FREQPCT74] = 0xc1c, 296 - [LIMITVALS] = 0xc20, 297 - [VBOOT] = 0xc24, 298 - [DETWINDOW] = 0xc28, 299 - [CONFIG] = 0xc2c, 300 - [TSCALCS] = 0xc30, 301 - [RUNCONFIG] = 0xc34, 302 - [SVSEN] = 0xc38, 303 - [INIT2VALS] = 0xc3c, 304 - [DCVALUES] = 0xc40, 305 - [AGEVALUES] = 0xc44, 306 - [VOP30] = 0xc48, 307 - [VOP74] = 0xc4c, 308 - [TEMP] = 0xc50, 309 - [INTSTS] = 0xc54, 310 - [INTSTSRAW] = 0xc58, 311 - [INTEN] = 0xc5c, 312 - [CHKINT] = 0xc60, 313 - [CHKSHIFT] = 0xc64, 314 - [STATUS] = 0xc68, 315 - [VDESIGN30] = 0xc6c, 316 - [VDESIGN74] = 0xc70, 317 - [DVT30] = 0xc74, 318 - [DVT74] = 0xc78, 319 - [AGECOUNT] = 0xc7c, 320 - [SMSTATE0] = 0xc80, 321 - [SMSTATE1] = 0xc84, 322 - [CTL0] = 0xc88, 323 - [DESDETSEC] = 0xce0, 324 - [TEMPAGESEC] = 0xce4, 325 - [CTRLSPARE0] = 0xcf0, 326 - [CTRLSPARE1] = 0xcf4, 327 - [CTRLSPARE2] = 0xcf8, 328 - [CTRLSPARE3] = 0xcfc, 329 - [CORESEL] = 0xf00, 330 - [THERMINTST] = 0xf04, 331 - [INTST] = 0xf08, 332 - [THSTAGE0ST] = 0xf0c, 333 - [THSTAGE1ST] = 0xf10, 334 - [THSTAGE2ST] = 0xf14, 335 - [THAHBST0] = 0xf18, 336 - [THAHBST1] = 0xf1c, 337 - [SPARE0] = 0xf20, 338 - [SPARE1] = 0xf24, 339 - [SPARE2] = 0xf28, 340 - [SPARE3] = 0xf2c, 341 - [THSLPEVEB] = 0xf30, 259 + [DESCHAR] = 0x00, 260 + [TEMPCHAR] = 0x04, 261 + [DETCHAR] = 0x08, 262 + [AGECHAR] = 0x0c, 263 + [DCCONFIG] = 0x10, 264 + [AGECONFIG] = 0x14, 265 + [FREQPCT30] = 0x18, 266 + [FREQPCT74] = 0x1c, 267 + [LIMITVALS] = 0x20, 268 + [VBOOT] = 0x24, 269 + [DETWINDOW] = 0x28, 270 + [CONFIG] = 0x2c, 271 + [TSCALCS] = 0x30, 272 + [RUNCONFIG] = 0x34, 273 + [SVSEN] = 0x38, 274 + [INIT2VALS] = 0x3c, 275 + [DCVALUES] = 0x40, 276 + [AGEVALUES] = 0x44, 277 + [VOP30] = 0x48, 278 + [VOP74] = 0x4c, 279 + [TEMP] = 0x50, 280 + [INTSTS] = 0x54, 281 + [INTSTSRAW] = 0x58, 282 + [INTEN] = 0x5c, 283 + [CHKINT] = 0x60, 284 + [CHKSHIFT] = 0x64, 285 + [STATUS] = 0x68, 286 + [VDESIGN30] = 0x6c, 287 + [VDESIGN74] = 0x70, 288 + [DVT30] = 0x74, 289 + [DVT74] = 0x78, 290 + [AGECOUNT] = 0x7c, 291 + [SMSTATE0] = 0x80, 292 + [SMSTATE1] = 0x84, 293 + [CTL0] = 0x88, 294 + [DESDETSEC] = 0xe0, 295 + [TEMPAGESEC] = 0xe4, 296 + [CTRLSPARE0] = 0xf0, 297 + [CTRLSPARE1] = 0xf4, 298 + [CTRLSPARE2] = 0xf8, 299 + [CTRLSPARE3] = 0xfc, 300 + [CORESEL] = 0x300, 301 + [THERMINTST] = 0x304, 302 + [INTST] = 0x308, 303 + [THSTAGE0ST] = 0x30c, 304 + [THSTAGE1ST] = 0x310, 305 + [THSTAGE2ST] = 0x314, 306 + [THAHBST0] = 0x318, 307 + [THAHBST1] = 0x31c, 308 + [SPARE0] = 0x320, 309 + [SPARE1] = 0x324, 310 + [SPARE2] = 0x328, 311 + [SPARE3] = 0x32c, 312 + [THSLPEVEB] = 0x330, 313 + }; 314 + 315 + static const char * const svs_swid_names[SVSB_SWID_MAX] = { 316 + "SVSB_CPU_LITTLE", "SVSB_CPU_BIG", "SVSB_CCI", "SVSB_GPU" 317 + }; 318 + 319 + static const char * const svs_type_names[SVSB_TYPE_MAX] = { 320 + "", "_LOW", "_HIGH" 321 + }; 322 + 323 + enum svs_fusemap_dev { 324 + BDEV_BDES, 325 + BDEV_MDES, 326 + BDEV_MTDES, 327 + BDEV_DCBDET, 328 + BDEV_DCMDET, 329 + BDEV_MAX 330 + }; 331 + 332 + enum svs_fusemap_glb { 333 + GLB_FT_PGM, 334 + GLB_VMIN, 335 + GLB_MAX 336 + }; 337 + 338 + struct svs_fusemap { 339 + s8 index; 340 + u8 ofst; 342 341 }; 343 342 344 343 /** ··· 374 317 * @base: svs platform register base 375 318 * @dev: svs platform device 376 319 * @main_clk: main clock for svs bank 377 - * @pbank: svs bank pointer needing to be protected by spin_lock section 378 320 * @banks: svs banks that svs platform supports 379 321 * @rst: svs platform reset control 380 322 * @efuse_max: total number of svs efuse 381 323 * @tefuse_max: total number of thermal efuse 382 324 * @regs: svs platform registers map 383 - * @bank_max: total number of svs banks 384 325 * @efuse: svs efuse data received from NVMEM framework 385 326 * @tefuse: thermal efuse data received from NVMEM framework 327 + * @ts_coeff: thermal sensors coefficient 328 + * @bank_max: total number of svs banks 386 329 */ 387 330 struct svs_platform { 388 331 void __iomem *base; 389 332 struct device *dev; 390 333 struct clk *main_clk; 391 - struct svs_bank *pbank; 392 334 struct svs_bank *banks; 393 335 struct reset_control *rst; 394 336 size_t efuse_max; 395 337 size_t tefuse_max; 396 338 const u32 *regs; 397 - u32 bank_max; 398 339 u32 *efuse; 399 340 u32 *tefuse; 341 + u32 ts_coeff; 342 + u16 bank_max; 400 343 }; 401 344 402 345 struct svs_platform_data { 403 346 char *name; 404 347 struct svs_bank *banks; 405 - bool (*efuse_parsing)(struct svs_platform *svsp); 348 + bool (*efuse_parsing)(struct svs_platform *svsp, const struct svs_platform_data *pdata); 406 349 int (*probe)(struct svs_platform *svsp); 350 + const struct svs_fusemap *glb_fuse_map; 407 351 const u32 *regs; 408 - u32 bank_max; 352 + u32 ts_coeff; 353 + u16 bank_max; 354 + }; 355 + 356 + /** 357 + * struct svs_bank_pdata - SVS Bank immutable config parameters 358 + * @dev_fuse_map: Bank fuse map data 359 + * @buck_name: Regulator name 360 + * @tzone_name: Thermal zone name 361 + * @age_config: Bank age configuration 362 + * @ctl0: TS-x selection 363 + * @dc_config: Bank dc configuration 364 + * @int_st: Bank interrupt identification 365 + * @turn_freq_base: Reference frequency for 2-line turn point 366 + * @tzone_htemp: Thermal zone high temperature threshold 367 + * @tzone_ltemp: Thermal zone low temperature threshold 368 + * @volt_step: Bank voltage step 369 + * @volt_base: Bank voltage base 370 + * @tzone_htemp_voffset: Thermal zone high temperature voltage offset 371 + * @tzone_ltemp_voffset: Thermal zone low temperature voltage offset 372 + * @chk_shift: Bank chicken shift 373 + * @cpu_id: CPU core ID for SVS CPU bank use only 374 + * @opp_count: Bank opp count 375 + * @vboot: Voltage request for bank init01 only 376 + * @vco: Bank VCO value 377 + * @sw_id: Bank software identification 378 + * @type: SVS Bank Type (1 or 2-line) and Role (high/low) 379 + * @set_freq_pct: function pointer to set bank frequency percent table 380 + * @get_volts: function pointer to get bank voltages 381 + */ 382 + struct svs_bank_pdata { 383 + const struct svs_fusemap *dev_fuse_map; 384 + char *buck_name; 385 + char *tzone_name; 386 + u32 age_config; 387 + u32 ctl0; 388 + u32 dc_config; 389 + u32 int_st; 390 + u32 turn_freq_base; 391 + u32 tzone_htemp; 392 + u32 tzone_ltemp; 393 + u32 volt_step; 394 + u32 volt_base; 395 + u16 tzone_htemp_voffset; 396 + u16 tzone_ltemp_voffset; 397 + u8 chk_shift; 398 + u8 cpu_id; 399 + u8 opp_count; 400 + u8 vboot; 401 + u8 vco; 402 + u8 sw_id; 403 + u8 type; 404 + 405 + /* Callbacks */ 406 + void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb); 407 + void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb); 409 408 }; 410 409 411 410 /** 412 411 * struct svs_bank - svs bank representation 412 + * @pdata: SVS Bank immutable config parameters 413 413 * @dev: bank device 414 414 * @opp_dev: device for opp table/buck control 415 415 * @init_completion: the timeout completion for bank init 416 416 * @buck: regulator used by opp_dev 417 417 * @tzd: thermal zone device for getting temperature 418 418 * @lock: mutex lock to protect voltage update process 419 - * @set_freq_pct: function pointer to set bank frequency percent table 420 - * @get_volts: function pointer to get bank voltages 421 419 * @name: bank name 422 - * @buck_name: regulator name 423 - * @tzone_name: thermal zone name 424 420 * @phase: bank current phase 425 421 * @volt_od: bank voltage overdrive 426 422 * @reg_data: bank register data in different phase for debug purpose 427 423 * @pm_runtime_enabled_count: bank pm runtime enabled count 428 - * @mode_support: bank mode support. 424 + * @mode_support: bank mode support 429 425 * @freq_base: reference frequency for bank init 430 - * @turn_freq_base: refenrece frequency for 2-line turn point 431 - * @vboot: voltage request for bank init01 only 432 426 * @opp_dfreq: default opp frequency table 433 427 * @opp_dvolt: default opp voltage table 434 428 * @freq_pct: frequency percent table for bank init 435 429 * @volt: bank voltage table 436 - * @volt_step: bank voltage step 437 - * @volt_base: bank voltage base 438 430 * @volt_flags: bank voltage flags 439 431 * @vmax: bank voltage maximum 440 432 * @vmin: bank voltage minimum 441 - * @age_config: bank age configuration 442 433 * @age_voffset_in: bank age voltage offset 443 - * @dc_config: bank dc configuration 444 434 * @dc_voffset_in: bank dc voltage offset 445 435 * @dvt_fixed: bank dvt fixed value 446 - * @vco: bank VCO value 447 - * @chk_shift: bank chicken shift 448 436 * @core_sel: bank selection 449 - * @opp_count: bank opp count 450 - * @int_st: bank interrupt identification 451 - * @sw_id: bank software identification 452 - * @cpu_id: cpu core id for SVS CPU bank use only 453 - * @ctl0: TS-x selection 454 437 * @temp: bank temperature 455 - * @tzone_htemp: thermal zone high temperature threshold 456 - * @tzone_htemp_voffset: thermal zone high temperature voltage offset 457 - * @tzone_ltemp: thermal zone low temperature threshold 458 - * @tzone_ltemp_voffset: thermal zone low temperature voltage offset 459 438 * @bts: svs efuse data 460 439 * @mts: svs efuse data 461 440 * @bdes: svs efuse data ··· 501 408 * @dcmdet: svs efuse data 502 409 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank 503 410 * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden 504 - * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank 505 411 * 506 - * Svs bank will generate suitalbe voltages by below general math equation 412 + * Svs bank will generate suitable voltages by below general math equation 507 413 * and provide these voltages to opp voltage table. 508 414 * 509 415 * opp_volt[i] = (volt[i] * volt_step) + volt_base; 510 416 */ 511 417 struct svs_bank { 418 + const struct svs_bank_pdata pdata; 512 419 struct device *dev; 513 420 struct device *opp_dev; 514 421 struct completion init_completion; 515 422 struct regulator *buck; 516 423 struct thermal_zone_device *tzd; 517 - struct mutex lock; /* lock to protect voltage update process */ 518 - void (*set_freq_pct)(struct svs_platform *svsp); 519 - void (*get_volts)(struct svs_platform *svsp); 424 + struct mutex lock; 425 + int pm_runtime_enabled_count; 426 + short int volt_od; 520 427 char *name; 521 - char *buck_name; 522 - char *tzone_name; 523 428 enum svsb_phase phase; 524 - s32 volt_od; 525 429 u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; 526 - u32 pm_runtime_enabled_count; 527 - u32 mode_support; 528 - u32 freq_base; 529 - u32 turn_freq_base; 530 - u32 vboot; 430 + u8 mode_support; 531 431 u32 opp_dfreq[MAX_OPP_ENTRIES]; 532 432 u32 opp_dvolt[MAX_OPP_ENTRIES]; 533 433 u32 freq_pct[MAX_OPP_ENTRIES]; 534 434 u32 volt[MAX_OPP_ENTRIES]; 535 - u32 volt_step; 536 - u32 volt_base; 537 435 u32 volt_flags; 538 - u32 vmax; 539 - u32 vmin; 540 - u32 age_config; 541 - u32 age_voffset_in; 542 - u32 dc_config; 543 - u32 dc_voffset_in; 544 - u32 dvt_fixed; 545 - u32 vco; 546 - u32 chk_shift; 547 - u32 core_sel; 548 - u32 opp_count; 549 - u32 int_st; 550 - u32 sw_id; 551 - u32 cpu_id; 552 - u32 ctl0; 553 - u32 temp; 554 - u32 tzone_htemp; 555 - u32 tzone_htemp_voffset; 556 - u32 tzone_ltemp; 557 - u32 tzone_ltemp_voffset; 558 - u32 bts; 559 - u32 mts; 560 - u32 bdes; 561 - u32 mdes; 562 - u32 mtdes; 563 - u32 dcbdet; 564 - u32 dcmdet; 436 + u32 freq_base; 565 437 u32 turn_pt; 566 438 u32 vbin_turn_pt; 567 - u32 type; 439 + u32 core_sel; 440 + u32 temp; 441 + u16 age_voffset_in; 442 + u16 dc_voffset_in; 443 + u8 dvt_fixed; 444 + u8 vmax; 445 + u8 vmin; 446 + u16 bts; 447 + u16 mts; 448 + u16 bdes; 449 + u16 mdes; 450 + u8 mtdes; 451 + u8 dcbdet; 452 + u8 dcmdet; 568 453 }; 569 454 570 455 static u32 percent(u32 numerator, u32 denominator) ··· 565 494 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); 566 495 } 567 496 568 - static void svs_switch_bank(struct svs_platform *svsp) 497 + static void svs_switch_bank(struct svs_platform *svsp, struct svs_bank *svsb) 569 498 { 570 - struct svs_bank *svsb = svsp->pbank; 571 - 572 499 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); 573 500 } 574 501 ··· 584 515 585 516 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) 586 517 { 518 + const struct svs_bank_pdata *bdata = &svsb->pdata; 587 519 struct dev_pm_opp *opp; 588 520 u32 i, opp_u_volt; 589 521 590 - for (i = 0; i < svsb->opp_count; i++) { 522 + for (i = 0; i < bdata->opp_count; i++) { 591 523 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 592 524 svsb->opp_dfreq[i], 593 525 true); ··· 600 530 601 531 opp_u_volt = dev_pm_opp_get_voltage(opp); 602 532 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, 603 - svsb->volt_step, 604 - svsb->volt_base); 533 + bdata->volt_step, 534 + bdata->volt_base); 605 535 dev_pm_opp_put(opp); 606 536 } 607 537 ··· 611 541 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) 612 542 { 613 543 int ret = -EPERM, tzone_temp = 0; 544 + const struct svs_bank_pdata *bdata = &svsb->pdata; 614 545 u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop; 615 546 616 547 mutex_lock(&svsb->lock); ··· 620 549 * 2-line bank updates its corresponding opp volts. 621 550 * 1-line bank updates all opp volts. 622 551 */ 623 - if (svsb->type == SVSB_HIGH) { 552 + if (bdata->type == SVSB_TYPE_HIGH) { 624 553 opp_start = 0; 625 554 opp_stop = svsb->turn_pt; 626 - } else if (svsb->type == SVSB_LOW) { 555 + } else if (bdata->type == SVSB_TYPE_LOW) { 627 556 opp_start = svsb->turn_pt; 628 - opp_stop = svsb->opp_count; 557 + opp_stop = bdata->opp_count; 629 558 } else { 630 559 opp_start = 0; 631 - opp_stop = svsb->opp_count; 560 + opp_stop = bdata->opp_count; 632 561 } 633 562 634 563 /* Get thermal effect */ ··· 637 566 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && 638 567 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { 639 568 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", 640 - svsb->tzone_name, ret, svsb->temp); 569 + bdata->tzone_name, ret, svsb->temp); 641 570 svsb->phase = SVSB_PHASE_ERROR; 642 571 } 643 572 644 - if (tzone_temp >= svsb->tzone_htemp) 645 - temp_voffset += svsb->tzone_htemp_voffset; 646 - else if (tzone_temp <= svsb->tzone_ltemp) 647 - temp_voffset += svsb->tzone_ltemp_voffset; 573 + if (tzone_temp >= bdata->tzone_htemp) 574 + temp_voffset += bdata->tzone_htemp_voffset; 575 + else if (tzone_temp <= bdata->tzone_ltemp) 576 + temp_voffset += bdata->tzone_ltemp_voffset; 648 577 649 578 /* 2-line bank update all opp volts when running mon mode */ 650 - if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH || 651 - svsb->type == SVSB_LOW)) { 579 + if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH || 580 + bdata->type == SVSB_TYPE_LOW)) { 652 581 opp_start = 0; 653 - opp_stop = svsb->opp_count; 582 + opp_stop = bdata->opp_count; 654 583 } 655 584 } 656 585 ··· 667 596 case SVSB_PHASE_MON: 668 597 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); 669 598 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, 670 - svsb->volt_step, 671 - svsb->volt_base); 599 + bdata->volt_step, 600 + bdata->volt_base); 672 601 break; 673 602 default: 674 603 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); ··· 703 632 return; 704 633 705 634 spin_lock_irqsave(&svs_lock, flags); 706 - svsp->pbank = svsb; 707 - svs_switch_bank(svsp); 635 + svs_switch_bank(svsp, svsb); 708 636 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 709 637 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 710 638 spin_unlock_irqrestore(&svs_lock, flags); ··· 830 760 svsb->name, tzone_temp, svsb->vbin_turn_pt, 831 761 svsb->turn_pt); 832 762 833 - for (i = 0; i < svsb->opp_count; i++) { 763 + for (i = 0; i < svsb->pdata.opp_count; i++) { 834 764 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 835 765 svsb->opp_dfreq[i], true); 836 766 if (IS_ERR(opp)) { ··· 935 865 return DIV_ROUND_UP(vx, 100); 936 866 } 937 867 938 - static void svs_get_bank_volts_v3(struct svs_platform *svsp) 868 + static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb) 939 869 { 940 - struct svs_bank *svsb = svsp->pbank; 870 + const struct svs_bank_pdata *bdata = &svsb->pdata; 941 871 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; 942 872 u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; 943 - u32 middle_index = (svsb->opp_count / 2); 873 + u32 middle_index = (bdata->opp_count / 2); 944 874 945 875 if (svsb->phase == SVSB_PHASE_MON && 946 876 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) ··· 951 881 952 882 /* Target is to set svsb->volt[] by algorithm */ 953 883 if (turn_pt < middle_index) { 954 - if (svsb->type == SVSB_HIGH) { 884 + if (bdata->type == SVSB_TYPE_HIGH) { 955 885 /* volt[0] ~ volt[turn_pt - 1] */ 956 886 for (i = 0; i < turn_pt; i++) { 957 887 b_sft = BITS8 * (shift_byte % REG_BYTES); ··· 960 890 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 961 891 shift_byte++; 962 892 } 963 - } else if (svsb->type == SVSB_LOW) { 893 + } else if (bdata->type == SVSB_TYPE_LOW) { 964 894 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ 965 - j = svsb->opp_count - 7; 895 + j = bdata->opp_count - 7; 966 896 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); 967 897 shift_byte++; 968 - for (i = j; i < svsb->opp_count; i++) { 898 + for (i = j; i < bdata->opp_count; i++) { 969 899 b_sft = BITS8 * (shift_byte % REG_BYTES); 970 900 vop = (shift_byte < REG_BYTES) ? &vop30 : 971 901 &vop74; ··· 982 912 svsb->freq_pct[i]); 983 913 } 984 914 } else { 985 - if (svsb->type == SVSB_HIGH) { 915 + if (bdata->type == SVSB_TYPE_HIGH) { 986 916 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ 987 917 j = turn_pt - 7; 988 918 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); ··· 1002 932 svsb->volt[0], 1003 933 svsb->volt[j], 1004 934 svsb->freq_pct[i]); 1005 - } else if (svsb->type == SVSB_LOW) { 935 + } else if (bdata->type == SVSB_TYPE_LOW) { 1006 936 /* volt[turn_pt] ~ volt[opp_count - 1] */ 1007 - for (i = turn_pt; i < svsb->opp_count; i++) { 937 + for (i = turn_pt; i < bdata->opp_count; i++) { 1008 938 b_sft = BITS8 * (shift_byte % REG_BYTES); 1009 939 vop = (shift_byte < REG_BYTES) ? &vop30 : 1010 940 &vop74; ··· 1014 944 } 1015 945 } 1016 946 1017 - if (svsb->type == SVSB_HIGH) { 947 + if (bdata->type == SVSB_TYPE_HIGH) { 1018 948 opp_start = 0; 1019 949 opp_stop = svsb->turn_pt; 1020 - } else if (svsb->type == SVSB_LOW) { 950 + } else if (bdata->type == SVSB_TYPE_LOW) { 1021 951 opp_start = svsb->turn_pt; 1022 - opp_stop = svsb->opp_count; 952 + opp_stop = bdata->opp_count; 1023 953 } 1024 954 1025 955 for (i = opp_start; i < opp_stop; i++) ··· 1029 959 /* For voltage bin support */ 1030 960 if (svsb->opp_dfreq[0] > svsb->freq_base) { 1031 961 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], 1032 - svsb->volt_step, 1033 - svsb->volt_base); 962 + bdata->volt_step, 963 + bdata->volt_base); 1034 964 1035 965 /* Find voltage bin turn point */ 1036 - for (i = 0; i < svsb->opp_count; i++) { 966 + for (i = 0; i < bdata->opp_count; i++) { 1037 967 if (svsb->opp_dfreq[i] <= svsb->freq_base) { 1038 968 svsb->vbin_turn_pt = i; 1039 969 break; ··· 1050 980 } 1051 981 } 1052 982 1053 - static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) 983 + static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb) 1054 984 { 1055 - struct svs_bank *svsb = svsp->pbank; 985 + const struct svs_bank_pdata *bdata = &svsb->pdata; 1056 986 u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; 1057 987 u32 b_sft, shift_byte = 0, turn_pt; 1058 - u32 middle_index = (svsb->opp_count / 2); 988 + u32 middle_index = (bdata->opp_count / 2); 1059 989 1060 - for (i = 0; i < svsb->opp_count; i++) { 1061 - if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { 990 + for (i = 0; i < bdata->opp_count; i++) { 991 + if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) { 1062 992 svsb->turn_pt = i; 1063 993 break; 1064 994 } ··· 1068 998 1069 999 /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ 1070 1000 if (turn_pt < middle_index) { 1071 - if (svsb->type == SVSB_HIGH) { 1001 + if (bdata->type == SVSB_TYPE_HIGH) { 1072 1002 /* 1073 1003 * If we don't handle this situation, 1074 - * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0" 1075 - * and this leads SVSB_LOW to work abnormally. 1004 + * SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0" 1005 + * and this leads SVSB_TYPE_LOW to work abnormally. 1076 1006 */ 1077 1007 if (turn_pt == 0) 1078 1008 freq_pct30 = svsb->freq_pct[0]; ··· 1085 1015 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1086 1016 shift_byte++; 1087 1017 } 1088 - } else if (svsb->type == SVSB_LOW) { 1018 + } else if (bdata->type == SVSB_TYPE_LOW) { 1089 1019 /* 1090 1020 * freq_pct[turn_pt] + 1091 1021 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] 1092 1022 */ 1093 1023 freq_pct30 = svsb->freq_pct[turn_pt]; 1094 1024 shift_byte++; 1095 - j = svsb->opp_count - 7; 1096 - for (i = j; i < svsb->opp_count; i++) { 1025 + j = bdata->opp_count - 7; 1026 + for (i = j; i < bdata->opp_count; i++) { 1097 1027 b_sft = BITS8 * (shift_byte % REG_BYTES); 1098 1028 freq_pct = (shift_byte < REG_BYTES) ? 1099 1029 &freq_pct30 : &freq_pct74; ··· 1102 1032 } 1103 1033 } 1104 1034 } else { 1105 - if (svsb->type == SVSB_HIGH) { 1035 + if (bdata->type == SVSB_TYPE_HIGH) { 1106 1036 /* 1107 1037 * freq_pct[0] + 1108 1038 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] ··· 1117 1047 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1118 1048 shift_byte++; 1119 1049 } 1120 - } else if (svsb->type == SVSB_LOW) { 1050 + } else if (bdata->type == SVSB_TYPE_LOW) { 1121 1051 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ 1122 - for (i = turn_pt; i < svsb->opp_count; i++) { 1052 + for (i = turn_pt; i < bdata->opp_count; i++) { 1123 1053 b_sft = BITS8 * (shift_byte % REG_BYTES); 1124 1054 freq_pct = (shift_byte < REG_BYTES) ? 1125 1055 &freq_pct30 : &freq_pct74; ··· 1133 1063 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30); 1134 1064 } 1135 1065 1136 - static void svs_get_bank_volts_v2(struct svs_platform *svsp) 1066 + static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb) 1137 1067 { 1138 - struct svs_bank *svsb = svsp->pbank; 1068 + const struct svs_bank_pdata *bdata = &svsb->pdata; 1139 1069 u32 temp, i; 1140 1070 1141 1071 temp = svs_readl_relaxed(svsp, VOP74); ··· 1163 1093 svsb->volt[14], 1164 1094 svsb->freq_pct[15]); 1165 1095 1166 - for (i = 0; i < svsb->opp_count; i++) 1096 + for (i = 0; i < bdata->opp_count; i++) 1167 1097 svsb->volt[i] += svsb->volt_od; 1168 1098 1169 1099 /* For voltage bin support */ 1170 1100 if (svsb->opp_dfreq[0] > svsb->freq_base) { 1171 1101 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], 1172 - svsb->volt_step, 1173 - svsb->volt_base); 1102 + bdata->volt_step, 1103 + bdata->volt_base); 1174 1104 1175 1105 /* Find voltage bin turn point */ 1176 - for (i = 0; i < svsb->opp_count; i++) { 1106 + for (i = 0; i < bdata->opp_count; i++) { 1177 1107 if (svsb->opp_dfreq[i] <= svsb->freq_base) { 1178 1108 svsb->vbin_turn_pt = i; 1179 1109 break; ··· 1190 1120 } 1191 1121 } 1192 1122 1193 - static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) 1123 + static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp, struct svs_bank *svsb) 1194 1124 { 1195 - struct svs_bank *svsb = svsp->pbank; 1196 1125 u32 freqpct74_val, freqpct30_val; 1197 1126 1198 1127 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | ··· 1209 1140 } 1210 1141 1211 1142 static void svs_set_bank_phase(struct svs_platform *svsp, 1143 + unsigned int bank_idx, 1212 1144 enum svsb_phase target_phase) 1213 1145 { 1214 - struct svs_bank *svsb = svsp->pbank; 1146 + struct svs_bank *svsb = &svsp->banks[bank_idx]; 1147 + const struct svs_bank_pdata *bdata = &svsb->pdata; 1215 1148 u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; 1216 1149 1217 - svs_switch_bank(svsp); 1150 + svs_switch_bank(svsp, svsb); 1218 1151 1219 1152 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | 1220 1153 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); 1221 1154 svs_writel_relaxed(svsp, des_char, DESCHAR); 1222 1155 1223 - temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | 1156 + temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) | 1224 1157 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | 1225 1158 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); 1226 1159 svs_writel_relaxed(svsp, temp_char, TEMPCHAR); ··· 1231 1160 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); 1232 1161 svs_writel_relaxed(svsp, det_char, DETCHAR); 1233 1162 1234 - svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); 1235 - svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); 1163 + svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG); 1164 + svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG); 1236 1165 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); 1237 1166 1238 - svsb->set_freq_pct(svsp); 1167 + bdata->set_freq_pct(svsp, svsb); 1239 1168 1240 1169 limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | 1241 1170 FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | ··· 1245 1174 1246 1175 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW); 1247 1176 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG); 1248 - svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); 1249 - svs_writel_relaxed(svsp, svsb->ctl0, CTL0); 1177 + svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT); 1178 + svs_writel_relaxed(svsp, bdata->ctl0, CTL0); 1250 1179 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1251 1180 1252 1181 switch (target_phase) { 1253 1182 case SVSB_PHASE_INIT01: 1254 - svs_writel_relaxed(svsp, svsb->vboot, VBOOT); 1183 + svs_writel_relaxed(svsp, bdata->vboot, VBOOT); 1255 1184 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1256 1185 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN); 1257 1186 break; ··· 1277 1206 } 1278 1207 1279 1208 static inline void svs_save_bank_register_data(struct svs_platform *svsp, 1209 + unsigned short bank_idx, 1280 1210 enum svsb_phase phase) 1281 1211 { 1282 - struct svs_bank *svsb = svsp->pbank; 1212 + struct svs_bank *svsb = &svsp->banks[bank_idx]; 1283 1213 enum svs_reg_index rg_i; 1284 1214 1285 1215 for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++) 1286 1216 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); 1287 1217 } 1288 1218 1289 - static inline void svs_error_isr_handler(struct svs_platform *svsp) 1219 + static inline void svs_error_isr_handler(struct svs_platform *svsp, 1220 + unsigned short bank_idx) 1290 1221 { 1291 - struct svs_bank *svsb = svsp->pbank; 1222 + struct svs_bank *svsb = &svsp->banks[bank_idx]; 1292 1223 1293 1224 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", 1294 1225 __func__, svs_readl_relaxed(svsp, CORESEL)); ··· 1302 1229 svs_readl_relaxed(svsp, SMSTATE1)); 1303 1230 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); 1304 1231 1305 - svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR); 1232 + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_ERROR); 1306 1233 1307 1234 svsb->phase = SVSB_PHASE_ERROR; 1308 1235 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1309 1236 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1310 1237 } 1311 1238 1312 - static inline void svs_init01_isr_handler(struct svs_platform *svsp) 1239 + static inline void svs_init01_isr_handler(struct svs_platform *svsp, 1240 + unsigned short bank_idx) 1313 1241 { 1314 - struct svs_bank *svsb = svsp->pbank; 1242 + struct svs_bank *svsb = &svsp->banks[bank_idx]; 1243 + u32 val; 1315 1244 1316 1245 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", 1317 1246 __func__, svs_readl_relaxed(svsp, VDESIGN74), 1318 1247 svs_readl_relaxed(svsp, VDESIGN30), 1319 1248 svs_readl_relaxed(svsp, DCVALUES)); 1320 1249 1321 - svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); 1250 + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT01); 1322 1251 1323 1252 svsb->phase = SVSB_PHASE_INIT01; 1324 - svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & 1325 - GENMASK(15, 0)) + 1; 1253 + val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1; 1254 + svsb->dc_voffset_in = val & GENMASK(15, 0); 1326 1255 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || 1327 1256 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && 1328 1257 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) ··· 1338 1263 svsb->core_sel &= ~SVSB_DET_CLK_EN; 1339 1264 } 1340 1265 1341 - static inline void svs_init02_isr_handler(struct svs_platform *svsp) 1266 + static inline void svs_init02_isr_handler(struct svs_platform *svsp, 1267 + unsigned short bank_idx) 1342 1268 { 1343 - struct svs_bank *svsb = svsp->pbank; 1269 + struct svs_bank *svsb = &svsp->banks[bank_idx]; 1270 + const struct svs_bank_pdata *bdata = &svsb->pdata; 1344 1271 1345 1272 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", 1346 1273 __func__, svs_readl_relaxed(svsp, VOP74), 1347 1274 svs_readl_relaxed(svsp, VOP30), 1348 1275 svs_readl_relaxed(svsp, DCVALUES)); 1349 1276 1350 - svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02); 1277 + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02); 1351 1278 1352 1279 svsb->phase = SVSB_PHASE_INIT02; 1353 - svsb->get_volts(svsp); 1280 + bdata->get_volts(svsp, svsb); 1354 1281 1355 1282 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1356 1283 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); 1357 1284 } 1358 1285 1359 - static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) 1286 + static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp, 1287 + unsigned short bank_idx) 1360 1288 { 1361 - struct svs_bank *svsb = svsp->pbank; 1289 + struct svs_bank *svsb = &svsp->banks[bank_idx]; 1290 + const struct svs_bank_pdata *bdata = &svsb->pdata; 1362 1291 1363 - svs_save_bank_register_data(svsp, SVSB_PHASE_MON); 1292 + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON); 1364 1293 1365 1294 svsb->phase = SVSB_PHASE_MON; 1366 - svsb->get_volts(svsp); 1295 + bdata->get_volts(svsp, svsb); 1367 1296 1368 1297 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); 1369 1298 svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); ··· 1376 1297 static irqreturn_t svs_isr(int irq, void *data) 1377 1298 { 1378 1299 struct svs_platform *svsp = data; 1300 + const struct svs_bank_pdata *bdata; 1379 1301 struct svs_bank *svsb = NULL; 1380 1302 unsigned long flags; 1381 1303 u32 idx, int_sts, svs_en; 1382 1304 1383 1305 for (idx = 0; idx < svsp->bank_max; idx++) { 1384 1306 svsb = &svsp->banks[idx]; 1307 + bdata = &svsb->pdata; 1385 1308 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); 1386 1309 1387 1310 spin_lock_irqsave(&svs_lock, flags); 1388 - svsp->pbank = svsb; 1389 1311 1390 1312 /* Find out which svs bank fires interrupt */ 1391 - if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { 1313 + if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) { 1392 1314 spin_unlock_irqrestore(&svs_lock, flags); 1393 1315 continue; 1394 1316 } 1395 1317 1396 - svs_switch_bank(svsp); 1318 + svs_switch_bank(svsp, svsb); 1397 1319 int_sts = svs_readl_relaxed(svsp, INTSTS); 1398 1320 svs_en = svs_readl_relaxed(svsp, SVSEN); 1399 1321 1400 1322 if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1401 1323 svs_en == SVSB_PTPEN_INIT01) 1402 - svs_init01_isr_handler(svsp); 1324 + svs_init01_isr_handler(svsp, idx); 1403 1325 else if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1404 1326 svs_en == SVSB_PTPEN_INIT02) 1405 - svs_init02_isr_handler(svsp); 1327 + svs_init02_isr_handler(svsp, idx); 1406 1328 else if (int_sts & SVSB_INTSTS_FLD_MONVOP) 1407 - svs_mon_mode_isr_handler(svsp); 1329 + svs_mon_mode_isr_handler(svsp, idx); 1408 1330 else 1409 - svs_error_isr_handler(svsp); 1331 + svs_error_isr_handler(svsp, idx); 1410 1332 1411 1333 spin_unlock_irqrestore(&svs_lock, flags); 1412 1334 break; ··· 1422 1342 return IRQ_HANDLED; 1423 1343 } 1424 1344 1345 + static bool svs_mode_available(struct svs_platform *svsp, u8 mode) 1346 + { 1347 + int i; 1348 + 1349 + for (i = 0; i < svsp->bank_max; i++) 1350 + if (svsp->banks[i].mode_support & mode) 1351 + return true; 1352 + return false; 1353 + } 1354 + 1425 1355 static int svs_init01(struct svs_platform *svsp) 1426 1356 { 1357 + const struct svs_bank_pdata *bdata; 1427 1358 struct svs_bank *svsb; 1428 1359 unsigned long flags, time_left; 1429 1360 bool search_done; 1430 1361 int ret = 0, r; 1431 1362 u32 opp_freq, opp_vboot, buck_volt, idx, i; 1363 + 1364 + if (!svs_mode_available(svsp, SVSB_MODE_INIT01)) 1365 + return 0; 1432 1366 1433 1367 /* Keep CPUs' core power on for svs_init01 initialization */ 1434 1368 cpuidle_pause_and_lock(); ··· 1450 1356 /* Svs bank init01 preparation - power enable */ 1451 1357 for (idx = 0; idx < svsp->bank_max; idx++) { 1452 1358 svsb = &svsp->banks[idx]; 1359 + bdata = &svsb->pdata; 1453 1360 1454 1361 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1455 1362 continue; ··· 1458 1363 ret = regulator_enable(svsb->buck); 1459 1364 if (ret) { 1460 1365 dev_err(svsb->dev, "%s enable fail: %d\n", 1461 - svsb->buck_name, ret); 1366 + bdata->buck_name, ret); 1462 1367 goto svs_init01_resume_cpuidle; 1463 1368 } 1464 1369 ··· 1488 1393 */ 1489 1394 for (idx = 0; idx < svsp->bank_max; idx++) { 1490 1395 svsb = &svsp->banks[idx]; 1396 + bdata = &svsb->pdata; 1491 1397 1492 1398 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1493 1399 continue; ··· 1498 1402 * fix to that freq until svs_init01 is done. 1499 1403 */ 1500 1404 search_done = false; 1501 - opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1502 - svsb->volt_step, 1503 - svsb->volt_base); 1405 + opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, 1406 + bdata->volt_step, 1407 + bdata->volt_base); 1504 1408 1505 - for (i = 0; i < svsb->opp_count; i++) { 1409 + for (i = 0; i < bdata->opp_count; i++) { 1506 1410 opp_freq = svsb->opp_dfreq[i]; 1507 1411 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { 1508 1412 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, ··· 1534 1438 /* Svs bank init01 begins */ 1535 1439 for (idx = 0; idx < svsp->bank_max; idx++) { 1536 1440 svsb = &svsp->banks[idx]; 1441 + bdata = &svsb->pdata; 1537 1442 1538 1443 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1539 1444 continue; 1540 1445 1541 - opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1542 - svsb->volt_step, 1543 - svsb->volt_base); 1446 + opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, 1447 + bdata->volt_step, 1448 + bdata->volt_base); 1544 1449 1545 1450 buck_volt = regulator_get_voltage(svsb->buck); 1546 1451 if (buck_volt != opp_vboot) { ··· 1553 1456 } 1554 1457 1555 1458 spin_lock_irqsave(&svs_lock, flags); 1556 - svsp->pbank = svsb; 1557 - svs_set_bank_phase(svsp, SVSB_PHASE_INIT01); 1459 + svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT01); 1558 1460 spin_unlock_irqrestore(&svs_lock, flags); 1559 1461 1560 1462 time_left = wait_for_completion_timeout(&svsb->init_completion, ··· 1568 1472 svs_init01_finish: 1569 1473 for (idx = 0; idx < svsp->bank_max; idx++) { 1570 1474 svsb = &svsp->banks[idx]; 1475 + bdata = &svsb->pdata; 1571 1476 1572 1477 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1573 1478 continue; 1574 1479 1575 - for (i = 0; i < svsb->opp_count; i++) { 1480 + for (i = 0; i < bdata->opp_count; i++) { 1576 1481 r = dev_pm_opp_enable(svsb->opp_dev, 1577 1482 svsb->opp_dfreq[i]); 1578 1483 if (r) ··· 1599 1502 r = regulator_disable(svsb->buck); 1600 1503 if (r) 1601 1504 dev_err(svsb->dev, "%s disable fail: %d\n", 1602 - svsb->buck_name, r); 1505 + bdata->buck_name, r); 1603 1506 } 1604 1507 1605 1508 svs_init01_resume_cpuidle: ··· 1610 1513 1611 1514 static int svs_init02(struct svs_platform *svsp) 1612 1515 { 1516 + const struct svs_bank_pdata *bdata; 1613 1517 struct svs_bank *svsb; 1614 1518 unsigned long flags, time_left; 1615 1519 int ret; 1616 1520 u32 idx; 1521 + 1522 + if (!svs_mode_available(svsp, SVSB_MODE_INIT02)) 1523 + return 0; 1617 1524 1618 1525 for (idx = 0; idx < svsp->bank_max; idx++) { 1619 1526 svsb = &svsp->banks[idx]; ··· 1627 1526 1628 1527 reinit_completion(&svsb->init_completion); 1629 1528 spin_lock_irqsave(&svs_lock, flags); 1630 - svsp->pbank = svsb; 1631 - svs_set_bank_phase(svsp, SVSB_PHASE_INIT02); 1529 + svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT02); 1632 1530 spin_unlock_irqrestore(&svs_lock, flags); 1633 1531 1634 1532 time_left = wait_for_completion_timeout(&svsb->init_completion, ··· 1646 1546 */ 1647 1547 for (idx = 0; idx < svsp->bank_max; idx++) { 1648 1548 svsb = &svsp->banks[idx]; 1549 + bdata = &svsb->pdata; 1649 1550 1650 1551 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1651 1552 continue; 1652 1553 1653 - if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { 1554 + if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) { 1654 1555 if (svs_sync_bank_volts_from_opp(svsb)) { 1655 1556 dev_err(svsb->dev, "sync volt fail\n"); 1656 1557 ret = -EPERM; ··· 1684 1583 continue; 1685 1584 1686 1585 spin_lock_irqsave(&svs_lock, flags); 1687 - svsp->pbank = svsb; 1688 - svs_set_bank_phase(svsp, SVSB_PHASE_MON); 1586 + svs_set_bank_phase(svsp, idx, SVSB_PHASE_MON); 1689 1587 spin_unlock_irqrestore(&svs_lock, flags); 1690 1588 } 1691 1589 } ··· 1709 1609 static int svs_suspend(struct device *dev) 1710 1610 { 1711 1611 struct svs_platform *svsp = dev_get_drvdata(dev); 1712 - struct svs_bank *svsb; 1713 1612 int ret; 1714 1613 u32 idx; 1715 1614 1716 1615 for (idx = 0; idx < svsp->bank_max; idx++) { 1717 - svsb = &svsp->banks[idx]; 1616 + struct svs_bank *svsb = &svsp->banks[idx]; 1617 + 1718 1618 svs_bank_disable_and_restore_default_volts(svsp, svsb); 1719 1619 } 1720 1620 ··· 1765 1665 1766 1666 static int svs_bank_resource_setup(struct svs_platform *svsp) 1767 1667 { 1668 + const struct svs_bank_pdata *bdata; 1768 1669 struct svs_bank *svsb; 1769 1670 struct dev_pm_opp *opp; 1770 1671 unsigned long freq; ··· 1776 1675 1777 1676 for (idx = 0; idx < svsp->bank_max; idx++) { 1778 1677 svsb = &svsp->banks[idx]; 1678 + bdata = &svsb->pdata; 1779 1679 1780 - switch (svsb->sw_id) { 1781 - case SVSB_CPU_LITTLE: 1782 - svsb->name = "SVSB_CPU_LITTLE"; 1783 - break; 1784 - case SVSB_CPU_BIG: 1785 - svsb->name = "SVSB_CPU_BIG"; 1786 - break; 1787 - case SVSB_CCI: 1788 - svsb->name = "SVSB_CCI"; 1789 - break; 1790 - case SVSB_GPU: 1791 - if (svsb->type == SVSB_HIGH) 1792 - svsb->name = "SVSB_GPU_HIGH"; 1793 - else if (svsb->type == SVSB_LOW) 1794 - svsb->name = "SVSB_GPU_LOW"; 1795 - else 1796 - svsb->name = "SVSB_GPU"; 1797 - break; 1798 - default: 1799 - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1680 + if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) { 1681 + dev_err(svsb->dev, "unknown bank sw_id or type\n"); 1800 1682 return -EINVAL; 1801 1683 } 1802 1684 1803 - svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), 1804 - GFP_KERNEL); 1685 + svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL); 1805 1686 if (!svsb->dev) 1687 + return -ENOMEM; 1688 + 1689 + svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s", 1690 + svs_swid_names[bdata->sw_id], 1691 + svs_type_names[bdata->type]); 1692 + if (!svsb->name) 1806 1693 return -ENOMEM; 1807 1694 1808 1695 ret = dev_set_name(svsb->dev, "%s", svsb->name); ··· 1810 1721 1811 1722 if (svsb->mode_support & SVSB_MODE_INIT01) { 1812 1723 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, 1813 - svsb->buck_name); 1724 + bdata->buck_name); 1814 1725 if (IS_ERR(svsb->buck)) { 1815 1726 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", 1816 - svsb->buck_name); 1727 + bdata->buck_name); 1817 1728 return PTR_ERR(svsb->buck); 1818 1729 } 1819 1730 } 1820 1731 1821 - if (!IS_ERR_OR_NULL(svsb->tzone_name)) { 1822 - svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); 1732 + if (!IS_ERR_OR_NULL(bdata->tzone_name)) { 1733 + svsb->tzd = thermal_zone_get_zone_by_name(bdata->tzone_name); 1823 1734 if (IS_ERR(svsb->tzd)) { 1824 1735 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", 1825 - svsb->tzone_name); 1736 + bdata->tzone_name); 1826 1737 return PTR_ERR(svsb->tzd); 1827 1738 } 1828 1739 } 1829 1740 1830 1741 count = dev_pm_opp_get_opp_count(svsb->opp_dev); 1831 - if (svsb->opp_count != count) { 1742 + if (bdata->opp_count != count) { 1832 1743 dev_err(svsb->dev, 1833 1744 "opp_count not \"%u\" but get \"%d\"?\n", 1834 - svsb->opp_count, count); 1745 + bdata->opp_count, count); 1835 1746 return count; 1836 1747 } 1837 1748 1838 - for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { 1749 + for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) { 1839 1750 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); 1840 1751 if (IS_ERR(opp)) { 1841 1752 dev_err(svsb->dev, "cannot find freq = %ld\n", ··· 1869 1780 1870 1781 *svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max); 1871 1782 if (IS_ERR(*svsp_efuse)) { 1872 - dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n", 1873 - nvmem_cell_name, PTR_ERR(*svsp_efuse)); 1874 1783 nvmem_cell_put(cell); 1875 1784 return PTR_ERR(*svsp_efuse); 1876 1785 } ··· 1879 1792 return 0; 1880 1793 } 1881 1794 1882 - static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) 1795 + static u32 svs_get_fuse_val(u32 *fuse_array, const struct svs_fusemap *fmap, u8 nbits) 1883 1796 { 1884 - struct svs_bank *svsb; 1885 - u32 idx, i, vmin, golden_temp; 1886 - int ret; 1797 + u32 val; 1887 1798 1888 - for (i = 0; i < svsp->efuse_max; i++) 1799 + if (fmap->index < 0) 1800 + return FUSE_DATA_NOT_VALID; 1801 + 1802 + val = fuse_array[fmap->index] >> fmap->ofst; 1803 + val &= GENMASK(nbits - 1, 0); 1804 + 1805 + return val; 1806 + } 1807 + 1808 + static bool svs_is_available(struct svs_platform *svsp) 1809 + { 1810 + int i, num_populated = 0; 1811 + 1812 + /* If at least two fuse arrays are populated, SVS is calibrated */ 1813 + for (i = 0; i < svsp->efuse_max; i++) { 1889 1814 if (svsp->efuse[i]) 1890 - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1891 - i, svsp->efuse[i]); 1815 + num_populated++; 1892 1816 1893 - if (!svsp->efuse[9]) { 1894 - dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); 1895 - return false; 1817 + if (num_populated > 1) 1818 + return true; 1896 1819 } 1897 1820 1898 - /* Svs efuse parsing */ 1899 - vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); 1821 + return false; 1822 + } 1900 1823 1901 - for (idx = 0; idx < svsp->bank_max; idx++) { 1902 - svsb = &svsp->banks[idx]; 1824 + static bool svs_common_parse_efuse(struct svs_platform *svsp, 1825 + const struct svs_platform_data *pdata) 1826 + { 1827 + const struct svs_fusemap *gfmap = pdata->glb_fuse_map; 1828 + struct svs_fusemap tfm = { 0, 24 }; 1829 + u32 golden_temp, val; 1830 + u8 ft_pgm, vmin; 1831 + int i; 1903 1832 1904 - if (vmin == 0x1) 1833 + if (!svs_is_available(svsp)) 1834 + return false; 1835 + 1836 + /* Get golden temperature from SVS-Thermal calibration */ 1837 + val = svs_get_fuse_val(svsp->tefuse, &tfm, 8); 1838 + 1839 + /* If golden temp is not programmed, use the default of 50 */ 1840 + golden_temp = val ? val : 50; 1841 + 1842 + /* Parse fused SVS calibration */ 1843 + ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8); 1844 + vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2); 1845 + 1846 + for (i = 0; i < svsp->bank_max; i++) { 1847 + struct svs_bank *svsb = &svsp->banks[i]; 1848 + const struct svs_bank_pdata *bdata = &svsb->pdata; 1849 + const struct svs_fusemap *dfmap = bdata->dev_fuse_map; 1850 + 1851 + if (vmin == 1) 1905 1852 svsb->vmin = 0x1e; 1906 1853 1907 - if (svsb->type == SVSB_LOW) { 1908 - svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); 1909 - svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); 1910 - svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); 1911 - svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); 1912 - svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); 1913 - } else if (svsb->type == SVSB_HIGH) { 1914 - svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); 1915 - svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); 1916 - svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); 1917 - svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1918 - svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); 1919 - } 1854 + if (ft_pgm == 0) 1855 + svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; 1920 1856 1857 + svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); 1858 + svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); 1859 + svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); 1860 + svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); 1861 + svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); 1921 1862 svsb->vmax += svsb->dvt_fixed; 1922 - } 1923 1863 1924 - ret = svs_get_efuse_data(svsp, "t-calibration-data", 1925 - &svsp->tefuse, &svsp->tefuse_max); 1926 - if (ret) 1927 - return false; 1928 - 1929 - for (i = 0; i < svsp->tefuse_max; i++) 1930 - if (svsp->tefuse[i] != 0) 1931 - break; 1932 - 1933 - if (i == svsp->tefuse_max) 1934 - golden_temp = 50; /* All thermal efuse data are 0 */ 1935 - else 1936 - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); 1937 - 1938 - for (idx = 0; idx < svsp->bank_max; idx++) { 1939 - svsb = &svsp->banks[idx]; 1940 - svsb->mts = 500; 1941 - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; 1864 + svsb->mts = (svsp->ts_coeff * 2) / 1000; 1865 + svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4; 1942 1866 } 1943 1867 1944 1868 return true; 1945 1869 } 1946 1870 1947 - static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) 1871 + static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, 1872 + const struct svs_platform_data *pdata) 1948 1873 { 1949 1874 struct svs_bank *svsb; 1950 - u32 idx, i, golden_temp; 1951 - int ret; 1952 - 1953 - for (i = 0; i < svsp->efuse_max; i++) 1954 - if (svsp->efuse[i]) 1955 - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1956 - i, svsp->efuse[i]); 1957 - 1958 - if (!svsp->efuse[5]) { 1959 - dev_notice(svsp->dev, "svs_efuse[5] = 0x0?\n"); 1960 - return false; 1961 - } 1962 - 1963 - /* Svs efuse parsing */ 1964 - for (idx = 0; idx < svsp->bank_max; idx++) { 1965 - svsb = &svsp->banks[idx]; 1966 - 1967 - if (svsb->type == SVSB_LOW) { 1968 - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); 1969 - svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); 1970 - svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); 1971 - svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); 1972 - svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); 1973 - } else if (svsb->type == SVSB_HIGH) { 1974 - svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); 1975 - svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); 1976 - svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); 1977 - svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); 1978 - svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); 1979 - } 1980 - 1981 - svsb->vmax += svsb->dvt_fixed; 1982 - } 1983 - 1984 - ret = svs_get_efuse_data(svsp, "t-calibration-data", 1985 - &svsp->tefuse, &svsp->tefuse_max); 1986 - if (ret) 1987 - return false; 1988 - 1989 - for (i = 0; i < svsp->tefuse_max; i++) 1990 - if (svsp->tefuse[i] != 0) 1991 - break; 1992 - 1993 - if (i == svsp->tefuse_max) 1994 - golden_temp = 50; /* All thermal efuse data are 0 */ 1995 - else 1996 - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); 1997 - 1998 - for (idx = 0; idx < svsp->bank_max; idx++) { 1999 - svsb = &svsp->banks[idx]; 2000 - svsb->mts = 500; 2001 - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; 2002 - } 2003 - 2004 - return true; 2005 - } 2006 - 2007 - static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) 2008 - { 2009 - struct svs_bank *svsb; 1875 + const struct svs_bank_pdata *bdata; 2010 1876 int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; 2011 1877 int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t; 2012 1878 int o_slope, o_slope_sign, ts_id; 2013 1879 u32 idx, i, ft_pgm, mts, temp0, temp1, temp2; 2014 - int ret; 2015 1880 2016 1881 for (i = 0; i < svsp->efuse_max; i++) 2017 1882 if (svsp->efuse[i]) ··· 1976 1937 } 1977 1938 1978 1939 /* Svs efuse parsing */ 1979 - ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); 1940 + ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4); 1980 1941 1981 1942 for (idx = 0; idx < svsp->bank_max; idx++) { 1982 1943 svsb = &svsp->banks[idx]; 1944 + bdata = &svsb->pdata; 1945 + const struct svs_fusemap *dfmap = bdata->dev_fuse_map; 1983 1946 1984 1947 if (ft_pgm <= 1) 1985 1948 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; 1986 1949 1987 - switch (svsb->sw_id) { 1988 - case SVSB_CPU_LITTLE: 1989 - svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); 1990 - svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); 1991 - svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); 1992 - svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); 1993 - svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1950 + svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); 1951 + svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); 1952 + svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); 1953 + svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); 1954 + svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); 1994 1955 1956 + switch (bdata->sw_id) { 1957 + case SVSB_SWID_CPU_LITTLE: 1958 + case SVSB_SWID_CCI: 1995 1959 if (ft_pgm <= 3) 1996 1960 svsb->volt_od += 10; 1997 1961 else 1998 1962 svsb->volt_od += 2; 1999 1963 break; 2000 - case SVSB_CPU_BIG: 2001 - svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); 2002 - svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); 2003 - svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); 2004 - svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); 2005 - svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); 2006 - 1964 + case SVSB_SWID_CPU_BIG: 2007 1965 if (ft_pgm <= 3) 2008 1966 svsb->volt_od += 15; 2009 1967 else 2010 1968 svsb->volt_od += 12; 2011 1969 break; 2012 - case SVSB_CCI: 2013 - svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); 2014 - svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); 2015 - svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); 2016 - svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); 2017 - svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); 2018 - 2019 - if (ft_pgm <= 3) 2020 - svsb->volt_od += 10; 2021 - else 2022 - svsb->volt_od += 2; 2023 - break; 2024 - case SVSB_GPU: 2025 - svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); 2026 - svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); 2027 - svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); 2028 - svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); 2029 - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); 2030 - 2031 - if (ft_pgm >= 2) { 1970 + case SVSB_SWID_GPU: 1971 + if (ft_pgm != FUSE_DATA_NOT_VALID && ft_pgm >= 2) { 2032 1972 svsb->freq_base = 800000000; /* 800MHz */ 2033 1973 svsb->dvt_fixed = 2; 2034 1974 } 2035 1975 break; 2036 1976 default: 2037 - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1977 + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); 2038 1978 return false; 2039 1979 } 2040 1980 } 2041 - 2042 - ret = svs_get_efuse_data(svsp, "t-calibration-data", 2043 - &svsp->tefuse, &svsp->tefuse_max); 2044 - if (ret) 2045 - return false; 2046 1981 2047 1982 /* Thermal efuse parsing */ 2048 1983 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); ··· 2077 2064 2078 2065 for (idx = 0; idx < svsp->bank_max; idx++) { 2079 2066 svsb = &svsp->banks[idx]; 2067 + bdata = &svsb->pdata; 2080 2068 svsb->mts = mts; 2081 2069 2082 - switch (svsb->sw_id) { 2083 - case SVSB_CPU_LITTLE: 2070 + switch (bdata->sw_id) { 2071 + case SVSB_SWID_CPU_LITTLE: 2084 2072 tb_roomt = x_roomt[3]; 2085 2073 break; 2086 - case SVSB_CPU_BIG: 2074 + case SVSB_SWID_CPU_BIG: 2087 2075 tb_roomt = x_roomt[4]; 2088 2076 break; 2089 - case SVSB_CCI: 2077 + case SVSB_SWID_CCI: 2090 2078 tb_roomt = x_roomt[3]; 2091 2079 break; 2092 - case SVSB_GPU: 2080 + case SVSB_SWID_GPU: 2093 2081 tb_roomt = x_roomt[1]; 2094 2082 break; 2095 2083 default: 2096 - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 2084 + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); 2097 2085 goto remove_mt8183_svsb_mon_mode; 2098 2086 } 2099 2087 ··· 2167 2153 static int svs_mt8192_platform_probe(struct svs_platform *svsp) 2168 2154 { 2169 2155 struct device *dev; 2170 - struct svs_bank *svsb; 2171 2156 u32 idx; 2172 2157 2173 2158 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); ··· 2174 2161 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), 2175 2162 "cannot get svs reset control\n"); 2176 2163 2177 - dev = svs_add_device_link(svsp, "lvts"); 2164 + dev = svs_add_device_link(svsp, "thermal-sensor"); 2178 2165 if (IS_ERR(dev)) 2179 2166 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2180 2167 "failed to get lvts device\n"); 2181 2168 2182 2169 for (idx = 0; idx < svsp->bank_max; idx++) { 2183 - svsb = &svsp->banks[idx]; 2170 + struct svs_bank *svsb = &svsp->banks[idx]; 2171 + const struct svs_bank_pdata *bdata = &svsb->pdata; 2184 2172 2185 - if (svsb->type == SVSB_HIGH) 2186 - svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2187 - else if (svsb->type == SVSB_LOW) 2188 - svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); 2173 + switch (bdata->sw_id) { 2174 + case SVSB_SWID_CPU_LITTLE: 2175 + case SVSB_SWID_CPU_BIG: 2176 + svsb->opp_dev = get_cpu_device(bdata->cpu_id); 2177 + break; 2178 + case SVSB_SWID_CCI: 2179 + svsb->opp_dev = svs_add_device_link(svsp, "cci"); 2180 + break; 2181 + case SVSB_SWID_GPU: 2182 + if (bdata->type == SVSB_TYPE_LOW) 2183 + svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); 2184 + else 2185 + svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2186 + break; 2187 + default: 2188 + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); 2189 + return -EINVAL; 2190 + } 2189 2191 2190 2192 if (IS_ERR(svsb->opp_dev)) 2191 2193 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), ··· 2214 2186 static int svs_mt8183_platform_probe(struct svs_platform *svsp) 2215 2187 { 2216 2188 struct device *dev; 2217 - struct svs_bank *svsb; 2218 2189 u32 idx; 2219 2190 2220 - dev = svs_add_device_link(svsp, "thermal"); 2191 + dev = svs_add_device_link(svsp, "thermal-sensor"); 2221 2192 if (IS_ERR(dev)) 2222 2193 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2223 2194 "failed to get thermal device\n"); 2224 2195 2225 2196 for (idx = 0; idx < svsp->bank_max; idx++) { 2226 - svsb = &svsp->banks[idx]; 2197 + struct svs_bank *svsb = &svsp->banks[idx]; 2198 + const struct svs_bank_pdata *bdata = &svsb->pdata; 2227 2199 2228 - switch (svsb->sw_id) { 2229 - case SVSB_CPU_LITTLE: 2230 - case SVSB_CPU_BIG: 2231 - svsb->opp_dev = get_cpu_device(svsb->cpu_id); 2200 + switch (bdata->sw_id) { 2201 + case SVSB_SWID_CPU_LITTLE: 2202 + case SVSB_SWID_CPU_BIG: 2203 + svsb->opp_dev = get_cpu_device(bdata->cpu_id); 2232 2204 break; 2233 - case SVSB_CCI: 2205 + case SVSB_SWID_CCI: 2234 2206 svsb->opp_dev = svs_add_device_link(svsp, "cci"); 2235 2207 break; 2236 - case SVSB_GPU: 2208 + case SVSB_SWID_GPU: 2237 2209 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2238 2210 break; 2239 2211 default: 2240 - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 2212 + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); 2241 2213 return -EINVAL; 2242 2214 } 2243 2215 ··· 2250 2222 return 0; 2251 2223 } 2252 2224 2253 - static struct svs_bank svs_mt8192_banks[] = { 2225 + static struct svs_bank svs_mt8195_banks[] = { 2254 2226 { 2255 - .sw_id = SVSB_GPU, 2256 - .type = SVSB_LOW, 2257 - .set_freq_pct = svs_set_bank_freq_pct_v3, 2258 - .get_volts = svs_get_bank_volts_v3, 2259 - .tzone_name = "gpu1", 2260 - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2261 - .mode_support = SVSB_MODE_INIT02, 2262 - .opp_count = MAX_OPP_ENTRIES, 2263 - .freq_base = 688000000, 2264 - .turn_freq_base = 688000000, 2265 - .volt_step = 6250, 2266 - .volt_base = 400000, 2267 - .vmax = 0x60, 2268 - .vmin = 0x1a, 2269 - .age_config = 0x555555, 2270 - .dc_config = 0x1, 2271 - .dvt_fixed = 0x1, 2272 - .vco = 0x18, 2273 - .chk_shift = 0x87, 2274 - .core_sel = 0x0fff0100, 2275 - .int_st = BIT(0), 2276 - .ctl0 = 0x00540003, 2277 - .tzone_htemp = 85000, 2278 - .tzone_htemp_voffset = 0, 2279 - .tzone_ltemp = 25000, 2280 - .tzone_ltemp_voffset = 7, 2227 + .pdata = (const struct svs_bank_pdata) { 2228 + .sw_id = SVSB_SWID_GPU, 2229 + .type = SVSB_TYPE_LOW, 2230 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2231 + .get_volts = svs_get_bank_volts_v3, 2232 + .opp_count = MAX_OPP_ENTRIES, 2233 + .turn_freq_base = 640000000, 2234 + .volt_step = 6250, 2235 + .volt_base = 400000, 2236 + .age_config = 0x555555, 2237 + .dc_config = 0x1, 2238 + .vco = 0x18, 2239 + .chk_shift = 0x87, 2240 + .int_st = BIT(0), 2241 + .ctl0 = 0x00540003, 2242 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2243 + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 } 2244 + } 2245 + }, 2246 + .mode_support = SVSB_MODE_INIT02, 2247 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2248 + .freq_base = 640000000, 2249 + .core_sel = 0x0fff0100, 2250 + .dvt_fixed = 0x1, 2251 + .vmax = 0x38, 2252 + .vmin = 0x14, 2281 2253 }, 2282 2254 { 2283 - .sw_id = SVSB_GPU, 2284 - .type = SVSB_HIGH, 2285 - .set_freq_pct = svs_set_bank_freq_pct_v3, 2286 - .get_volts = svs_get_bank_volts_v3, 2287 - .tzone_name = "gpu1", 2288 - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | 2289 - SVSB_MON_VOLT_IGNORE, 2290 - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2291 - .opp_count = MAX_OPP_ENTRIES, 2292 - .freq_base = 902000000, 2293 - .turn_freq_base = 688000000, 2294 - .volt_step = 6250, 2295 - .volt_base = 400000, 2296 - .vmax = 0x60, 2297 - .vmin = 0x1a, 2298 - .age_config = 0x555555, 2299 - .dc_config = 0x1, 2300 - .dvt_fixed = 0x6, 2301 - .vco = 0x18, 2302 - .chk_shift = 0x87, 2303 - .core_sel = 0x0fff0101, 2304 - .int_st = BIT(1), 2305 - .ctl0 = 0x00540003, 2306 - .tzone_htemp = 85000, 2307 - .tzone_htemp_voffset = 0, 2308 - .tzone_ltemp = 25000, 2309 - .tzone_ltemp_voffset = 7, 2255 + .pdata = (const struct svs_bank_pdata) { 2256 + .sw_id = SVSB_SWID_GPU, 2257 + .type = SVSB_TYPE_HIGH, 2258 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2259 + .get_volts = svs_get_bank_volts_v3, 2260 + .tzone_name = "gpu", 2261 + .opp_count = MAX_OPP_ENTRIES, 2262 + .turn_freq_base = 640000000, 2263 + .volt_step = 6250, 2264 + .volt_base = 400000, 2265 + .age_config = 0x555555, 2266 + .dc_config = 0x1, 2267 + .vco = 0x18, 2268 + .chk_shift = 0x87, 2269 + .int_st = BIT(1), 2270 + .ctl0 = 0x00540003, 2271 + .tzone_htemp = 85000, 2272 + .tzone_htemp_voffset = 0, 2273 + .tzone_ltemp = 25000, 2274 + .tzone_ltemp_voffset = 7, 2275 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2276 + { 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 } 2277 + }, 2278 + }, 2279 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, 2280 + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2281 + .freq_base = 880000000, 2282 + .core_sel = 0x0fff0101, 2283 + .dvt_fixed = 0x6, 2284 + .vmax = 0x38, 2285 + .vmin = 0x14, 2286 + }, 2287 + }; 2288 + 2289 + static struct svs_bank svs_mt8192_banks[] = { 2290 + { 2291 + .pdata = (const struct svs_bank_pdata) { 2292 + .sw_id = SVSB_SWID_GPU, 2293 + .type = SVSB_TYPE_LOW, 2294 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2295 + .get_volts = svs_get_bank_volts_v3, 2296 + .tzone_name = "gpu", 2297 + .opp_count = MAX_OPP_ENTRIES, 2298 + .turn_freq_base = 688000000, 2299 + .volt_step = 6250, 2300 + .volt_base = 400000, 2301 + .age_config = 0x555555, 2302 + .dc_config = 0x1, 2303 + .vco = 0x18, 2304 + .chk_shift = 0x87, 2305 + .int_st = BIT(0), 2306 + .ctl0 = 0x00540003, 2307 + .tzone_htemp = 85000, 2308 + .tzone_htemp_voffset = 0, 2309 + .tzone_ltemp = 25000, 2310 + .tzone_ltemp_voffset = 7, 2311 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2312 + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 } 2313 + } 2314 + }, 2315 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2316 + .mode_support = SVSB_MODE_INIT02, 2317 + .freq_base = 688000000, 2318 + .core_sel = 0x0fff0100, 2319 + .dvt_fixed = 0x1, 2320 + .vmax = 0x60, 2321 + .vmin = 0x1a, 2322 + }, 2323 + { 2324 + .pdata = (const struct svs_bank_pdata) { 2325 + .sw_id = SVSB_SWID_GPU, 2326 + .type = SVSB_TYPE_HIGH, 2327 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2328 + .get_volts = svs_get_bank_volts_v3, 2329 + .tzone_name = "gpu", 2330 + .opp_count = MAX_OPP_ENTRIES, 2331 + .turn_freq_base = 688000000, 2332 + .volt_step = 6250, 2333 + .volt_base = 400000, 2334 + .age_config = 0x555555, 2335 + .dc_config = 0x1, 2336 + .vco = 0x18, 2337 + .chk_shift = 0x87, 2338 + .int_st = BIT(1), 2339 + .ctl0 = 0x00540003, 2340 + .tzone_htemp = 85000, 2341 + .tzone_htemp_voffset = 0, 2342 + .tzone_ltemp = 25000, 2343 + .tzone_ltemp_voffset = 7, 2344 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2345 + { 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 } 2346 + } 2347 + }, 2348 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, 2349 + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2350 + .freq_base = 902000000, 2351 + .core_sel = 0x0fff0101, 2352 + .dvt_fixed = 0x6, 2353 + .vmax = 0x60, 2354 + .vmin = 0x1a, 2310 2355 }, 2311 2356 }; 2312 2357 2313 2358 static struct svs_bank svs_mt8188_banks[] = { 2314 2359 { 2315 - .sw_id = SVSB_GPU, 2316 - .type = SVSB_LOW, 2317 - .set_freq_pct = svs_set_bank_freq_pct_v3, 2318 - .get_volts = svs_get_bank_volts_v3, 2319 - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2320 - .mode_support = SVSB_MODE_INIT02, 2321 - .opp_count = MAX_OPP_ENTRIES, 2322 - .freq_base = 640000000, 2323 - .turn_freq_base = 640000000, 2324 - .volt_step = 6250, 2325 - .volt_base = 400000, 2326 - .vmax = 0x38, 2327 - .vmin = 0x1c, 2328 - .age_config = 0x555555, 2329 - .dc_config = 0x555555, 2330 - .dvt_fixed = 0x1, 2331 - .vco = 0x10, 2332 - .chk_shift = 0x87, 2333 - .core_sel = 0x0fff0000, 2334 - .int_st = BIT(0), 2335 - .ctl0 = 0x00100003, 2360 + .pdata = (const struct svs_bank_pdata) { 2361 + .sw_id = SVSB_SWID_GPU, 2362 + .type = SVSB_TYPE_LOW, 2363 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2364 + .get_volts = svs_get_bank_volts_v3, 2365 + .opp_count = MAX_OPP_ENTRIES, 2366 + .turn_freq_base = 640000000, 2367 + .volt_step = 6250, 2368 + .volt_base = 400000, 2369 + .age_config = 0x555555, 2370 + .dc_config = 0x555555, 2371 + .vco = 0x10, 2372 + .chk_shift = 0x87, 2373 + .int_st = BIT(0), 2374 + .ctl0 = 0x00100003, 2375 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2376 + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } 2377 + } 2378 + }, 2379 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2380 + .mode_support = SVSB_MODE_INIT02, 2381 + .freq_base = 640000000, 2382 + .core_sel = 0x0fff0000, 2383 + .dvt_fixed = 0x1, 2384 + .vmax = 0x38, 2385 + .vmin = 0x1c, 2336 2386 }, 2337 2387 { 2338 - .sw_id = SVSB_GPU, 2339 - .type = SVSB_HIGH, 2340 - .set_freq_pct = svs_set_bank_freq_pct_v3, 2341 - .get_volts = svs_get_bank_volts_v3, 2342 - .tzone_name = "gpu1", 2343 - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | 2344 - SVSB_MON_VOLT_IGNORE, 2345 - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2346 - .opp_count = MAX_OPP_ENTRIES, 2347 - .freq_base = 880000000, 2348 - .turn_freq_base = 640000000, 2349 - .volt_step = 6250, 2350 - .volt_base = 400000, 2351 - .vmax = 0x38, 2352 - .vmin = 0x1c, 2353 - .age_config = 0x555555, 2354 - .dc_config = 0x555555, 2355 - .dvt_fixed = 0x4, 2356 - .vco = 0x10, 2357 - .chk_shift = 0x87, 2358 - .core_sel = 0x0fff0001, 2359 - .int_st = BIT(1), 2360 - .ctl0 = 0x00100003, 2361 - .tzone_htemp = 85000, 2362 - .tzone_htemp_voffset = 0, 2363 - .tzone_ltemp = 25000, 2364 - .tzone_ltemp_voffset = 7, 2388 + .pdata = (const struct svs_bank_pdata) { 2389 + .sw_id = SVSB_SWID_GPU, 2390 + .type = SVSB_TYPE_HIGH, 2391 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2392 + .get_volts = svs_get_bank_volts_v3, 2393 + .tzone_name = "gpu", 2394 + .opp_count = MAX_OPP_ENTRIES, 2395 + .turn_freq_base = 640000000, 2396 + .volt_step = 6250, 2397 + .volt_base = 400000, 2398 + .age_config = 0x555555, 2399 + .dc_config = 0x555555, 2400 + .vco = 0x10, 2401 + .chk_shift = 0x87, 2402 + .int_st = BIT(1), 2403 + .ctl0 = 0x00100003, 2404 + .tzone_htemp = 85000, 2405 + .tzone_htemp_voffset = 0, 2406 + .tzone_ltemp = 25000, 2407 + .tzone_ltemp_voffset = 7, 2408 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2409 + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } 2410 + } 2411 + }, 2412 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, 2413 + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2414 + .freq_base = 880000000, 2415 + .core_sel = 0x0fff0001, 2416 + .dvt_fixed = 0x4, 2417 + .vmax = 0x38, 2418 + .vmin = 0x1c, 2419 + }, 2420 + }; 2421 + 2422 + static struct svs_bank svs_mt8186_banks[] = { 2423 + { 2424 + .pdata = (const struct svs_bank_pdata) { 2425 + .sw_id = SVSB_SWID_CPU_BIG, 2426 + .type = SVSB_TYPE_LOW, 2427 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2428 + .get_volts = svs_get_bank_volts_v3, 2429 + .cpu_id = 6, 2430 + .opp_count = MAX_OPP_ENTRIES, 2431 + .turn_freq_base = 1670000000, 2432 + .volt_step = 6250, 2433 + .volt_base = 400000, 2434 + .age_config = 0x1, 2435 + .dc_config = 0x1, 2436 + .vco = 0x10, 2437 + .chk_shift = 0x87, 2438 + .int_st = BIT(0), 2439 + .ctl0 = 0x00540003, 2440 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2441 + { 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 } 2442 + } 2443 + }, 2444 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2445 + .volt_od = 4, 2446 + .mode_support = SVSB_MODE_INIT02, 2447 + .freq_base = 1670000000, 2448 + .core_sel = 0x0fff0100, 2449 + .dvt_fixed = 0x3, 2450 + .vmax = 0x59, 2451 + .vmin = 0x20, 2452 + }, 2453 + { 2454 + .pdata = (const struct svs_bank_pdata) { 2455 + .sw_id = SVSB_SWID_CPU_BIG, 2456 + .type = SVSB_TYPE_HIGH, 2457 + .set_freq_pct = svs_set_bank_freq_pct_v3, 2458 + .get_volts = svs_get_bank_volts_v3, 2459 + .cpu_id = 6, 2460 + .tzone_name = "cpu-big", 2461 + .opp_count = MAX_OPP_ENTRIES, 2462 + .turn_freq_base = 1670000000, 2463 + .volt_step = 6250, 2464 + .volt_base = 400000, 2465 + .age_config = 0x1, 2466 + .dc_config = 0x1, 2467 + .vco = 0x10, 2468 + .chk_shift = 0x87, 2469 + .int_st = BIT(1), 2470 + .ctl0 = 0x00540003, 2471 + .tzone_htemp = 85000, 2472 + .tzone_htemp_voffset = 8, 2473 + .tzone_ltemp = 25000, 2474 + .tzone_ltemp_voffset = 8, 2475 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2476 + { 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 } 2477 + } 2478 + }, 2479 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, 2480 + .volt_od = 4, 2481 + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2482 + .freq_base = 2050000000, 2483 + .core_sel = 0x0fff0101, 2484 + .dvt_fixed = 0x6, 2485 + .vmax = 0x73, 2486 + .vmin = 0x20, 2487 + }, 2488 + { 2489 + .pdata = (const struct svs_bank_pdata) { 2490 + .sw_id = SVSB_SWID_CPU_LITTLE, 2491 + .set_freq_pct = svs_set_bank_freq_pct_v2, 2492 + .get_volts = svs_get_bank_volts_v2, 2493 + .cpu_id = 0, 2494 + .tzone_name = "cpu-little", 2495 + .opp_count = MAX_OPP_ENTRIES, 2496 + .volt_step = 6250, 2497 + .volt_base = 400000, 2498 + .age_config = 0x1, 2499 + .dc_config = 0x1, 2500 + .vco = 0x10, 2501 + .chk_shift = 0x87, 2502 + .int_st = BIT(2), 2503 + .ctl0 = 0x3210000f, 2504 + .tzone_htemp = 85000, 2505 + .tzone_htemp_voffset = 8, 2506 + .tzone_ltemp = 25000, 2507 + .tzone_ltemp_voffset = 8, 2508 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2509 + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } 2510 + } 2511 + }, 2512 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, 2513 + .volt_od = 3, 2514 + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2515 + .freq_base = 2000000000, 2516 + .core_sel = 0x0fff0102, 2517 + .dvt_fixed = 0x6, 2518 + .vmax = 0x65, 2519 + .vmin = 0x20, 2520 + }, 2521 + { 2522 + .pdata = (const struct svs_bank_pdata) { 2523 + .sw_id = SVSB_SWID_CCI, 2524 + .set_freq_pct = svs_set_bank_freq_pct_v2, 2525 + .get_volts = svs_get_bank_volts_v2, 2526 + .tzone_name = "cci", 2527 + .opp_count = MAX_OPP_ENTRIES, 2528 + .volt_step = 6250, 2529 + .volt_base = 400000, 2530 + .age_config = 0x1, 2531 + .dc_config = 0x1, 2532 + .vco = 0x10, 2533 + .chk_shift = 0x87, 2534 + .int_st = BIT(3), 2535 + .ctl0 = 0x3210000f, 2536 + .tzone_htemp = 85000, 2537 + .tzone_htemp_voffset = 8, 2538 + .tzone_ltemp = 25000, 2539 + .tzone_ltemp_voffset = 8, 2540 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2541 + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } 2542 + } 2543 + }, 2544 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, 2545 + .volt_od = 3, 2546 + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2547 + .freq_base = 1400000000, 2548 + .core_sel = 0x0fff0103, 2549 + .dvt_fixed = 0x6, 2550 + .vmax = 0x65, 2551 + .vmin = 0x20, 2552 + }, 2553 + { 2554 + .pdata = (const struct svs_bank_pdata) { 2555 + .sw_id = SVSB_SWID_GPU, 2556 + .set_freq_pct = svs_set_bank_freq_pct_v2, 2557 + .get_volts = svs_get_bank_volts_v2, 2558 + .tzone_name = "gpu", 2559 + .opp_count = MAX_OPP_ENTRIES, 2560 + .volt_step = 6250, 2561 + .volt_base = 400000, 2562 + .age_config = 0x555555, 2563 + .dc_config = 0x1, 2564 + .vco = 0x10, 2565 + .chk_shift = 0x87, 2566 + .int_st = BIT(4), 2567 + .ctl0 = 0x00100003, 2568 + .tzone_htemp = 85000, 2569 + .tzone_htemp_voffset = 8, 2570 + .tzone_ltemp = 25000, 2571 + .tzone_ltemp_voffset = 7, 2572 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2573 + { 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 } 2574 + } 2575 + }, 2576 + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, 2577 + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2578 + .freq_base = 850000000, 2579 + .core_sel = 0x0fff0104, 2580 + .dvt_fixed = 0x4, 2581 + .vmax = 0x58, 2582 + .vmin = 0x20, 2365 2583 }, 2366 2584 }; 2367 2585 2368 2586 static struct svs_bank svs_mt8183_banks[] = { 2369 2587 { 2370 - .sw_id = SVSB_CPU_LITTLE, 2371 - .set_freq_pct = svs_set_bank_freq_pct_v2, 2372 - .get_volts = svs_get_bank_volts_v2, 2373 - .cpu_id = 0, 2374 - .buck_name = "proc", 2375 - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2376 - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2377 - .opp_count = MAX_OPP_ENTRIES, 2378 - .freq_base = 1989000000, 2379 - .vboot = 0x30, 2380 - .volt_step = 6250, 2381 - .volt_base = 500000, 2382 - .vmax = 0x64, 2383 - .vmin = 0x18, 2384 - .age_config = 0x555555, 2385 - .dc_config = 0x555555, 2386 - .dvt_fixed = 0x7, 2387 - .vco = 0x10, 2388 - .chk_shift = 0x77, 2389 - .core_sel = 0x8fff0000, 2390 - .int_st = BIT(0), 2391 - .ctl0 = 0x00010001, 2588 + .pdata = (const struct svs_bank_pdata) { 2589 + .sw_id = SVSB_SWID_CPU_LITTLE, 2590 + .set_freq_pct = svs_set_bank_freq_pct_v2, 2591 + .get_volts = svs_get_bank_volts_v2, 2592 + .cpu_id = 0, 2593 + .buck_name = "proc", 2594 + .opp_count = MAX_OPP_ENTRIES, 2595 + .vboot = 0x30, 2596 + .volt_step = 6250, 2597 + .volt_base = 500000, 2598 + .age_config = 0x555555, 2599 + .dc_config = 0x555555, 2600 + .vco = 0x10, 2601 + .chk_shift = 0x77, 2602 + .int_st = BIT(0), 2603 + .ctl0 = 0x00010001, 2604 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2605 + { 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 } 2606 + } 2607 + }, 2608 + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2609 + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2610 + .freq_base = 1989000000, 2611 + .core_sel = 0x8fff0000, 2612 + .dvt_fixed = 0x7, 2613 + .vmax = 0x64, 2614 + .vmin = 0x18, 2615 + 2392 2616 }, 2393 2617 { 2394 - .sw_id = SVSB_CPU_BIG, 2395 - .set_freq_pct = svs_set_bank_freq_pct_v2, 2396 - .get_volts = svs_get_bank_volts_v2, 2397 - .cpu_id = 4, 2398 - .buck_name = "proc", 2399 - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2400 - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2401 - .opp_count = MAX_OPP_ENTRIES, 2402 - .freq_base = 1989000000, 2403 - .vboot = 0x30, 2404 - .volt_step = 6250, 2405 - .volt_base = 500000, 2406 - .vmax = 0x58, 2407 - .vmin = 0x10, 2408 - .age_config = 0x555555, 2409 - .dc_config = 0x555555, 2410 - .dvt_fixed = 0x7, 2411 - .vco = 0x10, 2412 - .chk_shift = 0x77, 2413 - .core_sel = 0x8fff0001, 2414 - .int_st = BIT(1), 2415 - .ctl0 = 0x00000001, 2618 + .pdata = (const struct svs_bank_pdata) { 2619 + .sw_id = SVSB_SWID_CPU_BIG, 2620 + .set_freq_pct = svs_set_bank_freq_pct_v2, 2621 + .get_volts = svs_get_bank_volts_v2, 2622 + .cpu_id = 4, 2623 + .buck_name = "proc", 2624 + .opp_count = MAX_OPP_ENTRIES, 2625 + .vboot = 0x30, 2626 + .volt_step = 6250, 2627 + .volt_base = 500000, 2628 + .age_config = 0x555555, 2629 + .dc_config = 0x555555, 2630 + .vco = 0x10, 2631 + .chk_shift = 0x77, 2632 + .int_st = BIT(1), 2633 + .ctl0 = 0x00000001, 2634 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2635 + { 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 } 2636 + } 2637 + }, 2638 + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2639 + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2640 + .freq_base = 1989000000, 2641 + .core_sel = 0x8fff0001, 2642 + .dvt_fixed = 0x7, 2643 + .vmax = 0x58, 2644 + .vmin = 0x10, 2645 + 2416 2646 }, 2417 2647 { 2418 - .sw_id = SVSB_CCI, 2419 - .set_freq_pct = svs_set_bank_freq_pct_v2, 2420 - .get_volts = svs_get_bank_volts_v2, 2421 - .buck_name = "proc", 2422 - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2423 - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2424 - .opp_count = MAX_OPP_ENTRIES, 2425 - .freq_base = 1196000000, 2426 - .vboot = 0x30, 2427 - .volt_step = 6250, 2428 - .volt_base = 500000, 2429 - .vmax = 0x64, 2430 - .vmin = 0x18, 2431 - .age_config = 0x555555, 2432 - .dc_config = 0x555555, 2433 - .dvt_fixed = 0x7, 2434 - .vco = 0x10, 2435 - .chk_shift = 0x77, 2436 - .core_sel = 0x8fff0002, 2437 - .int_st = BIT(2), 2438 - .ctl0 = 0x00100003, 2648 + .pdata = (const struct svs_bank_pdata) { 2649 + .sw_id = SVSB_SWID_CCI, 2650 + .set_freq_pct = svs_set_bank_freq_pct_v2, 2651 + .get_volts = svs_get_bank_volts_v2, 2652 + .buck_name = "proc", 2653 + .opp_count = MAX_OPP_ENTRIES, 2654 + .vboot = 0x30, 2655 + .volt_step = 6250, 2656 + .volt_base = 500000, 2657 + .age_config = 0x555555, 2658 + .dc_config = 0x555555, 2659 + .vco = 0x10, 2660 + .chk_shift = 0x77, 2661 + .int_st = BIT(2), 2662 + .ctl0 = 0x00100003, 2663 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2664 + { 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 } 2665 + } 2666 + }, 2667 + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2668 + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2669 + .freq_base = 1196000000, 2670 + .core_sel = 0x8fff0002, 2671 + .dvt_fixed = 0x7, 2672 + .vmax = 0x64, 2673 + .vmin = 0x18, 2439 2674 }, 2440 2675 { 2441 - .sw_id = SVSB_GPU, 2442 - .set_freq_pct = svs_set_bank_freq_pct_v2, 2443 - .get_volts = svs_get_bank_volts_v2, 2444 - .buck_name = "mali", 2445 - .tzone_name = "tzts2", 2446 - .volt_flags = SVSB_INIT01_PD_REQ | 2447 - SVSB_INIT01_VOLT_INC_ONLY, 2448 - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | 2449 - SVSB_MODE_MON, 2450 - .opp_count = MAX_OPP_ENTRIES, 2451 - .freq_base = 900000000, 2452 - .vboot = 0x30, 2453 - .volt_step = 6250, 2454 - .volt_base = 500000, 2455 - .vmax = 0x40, 2456 - .vmin = 0x14, 2457 - .age_config = 0x555555, 2458 - .dc_config = 0x555555, 2459 - .dvt_fixed = 0x3, 2460 - .vco = 0x10, 2461 - .chk_shift = 0x77, 2462 - .core_sel = 0x8fff0003, 2463 - .int_st = BIT(3), 2464 - .ctl0 = 0x00050001, 2465 - .tzone_htemp = 85000, 2466 - .tzone_htemp_voffset = 0, 2467 - .tzone_ltemp = 25000, 2468 - .tzone_ltemp_voffset = 3, 2676 + .pdata = (const struct svs_bank_pdata) { 2677 + .sw_id = SVSB_SWID_GPU, 2678 + .set_freq_pct = svs_set_bank_freq_pct_v2, 2679 + .get_volts = svs_get_bank_volts_v2, 2680 + .buck_name = "mali", 2681 + .tzone_name = "gpu", 2682 + .opp_count = MAX_OPP_ENTRIES, 2683 + .vboot = 0x30, 2684 + .volt_step = 6250, 2685 + .volt_base = 500000, 2686 + .age_config = 0x555555, 2687 + .dc_config = 0x555555, 2688 + .vco = 0x10, 2689 + .chk_shift = 0x77, 2690 + .int_st = BIT(3), 2691 + .ctl0 = 0x00050001, 2692 + .tzone_htemp = 85000, 2693 + .tzone_htemp_voffset = 0, 2694 + .tzone_ltemp = 25000, 2695 + .tzone_ltemp_voffset = 3, 2696 + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { 2697 + { 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 } 2698 + } 2699 + }, 2700 + .volt_flags = SVSB_INIT01_PD_REQ | SVSB_INIT01_VOLT_INC_ONLY, 2701 + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | SVSB_MODE_MON, 2702 + .freq_base = 900000000, 2703 + .core_sel = 0x8fff0003, 2704 + .dvt_fixed = 0x3, 2705 + .vmax = 0x40, 2706 + .vmin = 0x14, 2469 2707 }, 2708 + }; 2709 + 2710 + static const struct svs_platform_data svs_mt8195_platform_data = { 2711 + .name = "mt8195-svs", 2712 + .banks = svs_mt8195_banks, 2713 + .efuse_parsing = svs_common_parse_efuse, 2714 + .probe = svs_mt8192_platform_probe, 2715 + .regs = svs_regs_v2, 2716 + .bank_max = ARRAY_SIZE(svs_mt8195_banks), 2717 + .ts_coeff = SVSB_TS_COEFF_MT8195, 2718 + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { 2719 + { 0, 0 }, { 19, 4 } 2720 + } 2470 2721 }; 2471 2722 2472 2723 static const struct svs_platform_data svs_mt8192_platform_data = { 2473 2724 .name = "mt8192-svs", 2474 2725 .banks = svs_mt8192_banks, 2475 - .efuse_parsing = svs_mt8192_efuse_parsing, 2726 + .efuse_parsing = svs_common_parse_efuse, 2476 2727 .probe = svs_mt8192_platform_probe, 2477 2728 .regs = svs_regs_v2, 2478 2729 .bank_max = ARRAY_SIZE(svs_mt8192_banks), 2730 + .ts_coeff = SVSB_TS_COEFF_MT8195, 2731 + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { 2732 + /* FT_PGM not present */ 2733 + { -1, 0 }, { 19, 4 } 2734 + } 2479 2735 }; 2480 2736 2481 2737 static const struct svs_platform_data svs_mt8188_platform_data = { 2482 2738 .name = "mt8188-svs", 2483 2739 .banks = svs_mt8188_banks, 2484 - .efuse_parsing = svs_mt8188_efuse_parsing, 2740 + .efuse_parsing = svs_common_parse_efuse, 2485 2741 .probe = svs_mt8192_platform_probe, 2486 2742 .regs = svs_regs_v2, 2487 2743 .bank_max = ARRAY_SIZE(svs_mt8188_banks), 2744 + .ts_coeff = SVSB_TS_COEFF_MT8195, 2745 + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { 2746 + /* FT_PGM and VMIN not present */ 2747 + { -1, 0 }, { -1, 0 } 2748 + } 2749 + }; 2750 + 2751 + static const struct svs_platform_data svs_mt8186_platform_data = { 2752 + .name = "mt8186-svs", 2753 + .banks = svs_mt8186_banks, 2754 + .efuse_parsing = svs_common_parse_efuse, 2755 + .probe = svs_mt8192_platform_probe, 2756 + .regs = svs_regs_v2, 2757 + .bank_max = ARRAY_SIZE(svs_mt8186_banks), 2758 + .ts_coeff = SVSB_TS_COEFF_MT8186, 2759 + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { 2760 + /* FT_PGM and VMIN not present */ 2761 + { -1, 0 }, { -1, 0 } 2762 + } 2488 2763 }; 2489 2764 2490 2765 static const struct svs_platform_data svs_mt8183_platform_data = { ··· 2797 2466 .probe = svs_mt8183_platform_probe, 2798 2467 .regs = svs_regs_v2, 2799 2468 .bank_max = ARRAY_SIZE(svs_mt8183_banks), 2469 + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { 2470 + /* VMIN not present */ 2471 + { 0, 4 }, { -1, 0 } 2472 + } 2800 2473 }; 2801 2474 2802 2475 static const struct of_device_id svs_of_match[] = { 2803 - { 2804 - .compatible = "mediatek,mt8192-svs", 2805 - .data = &svs_mt8192_platform_data, 2806 - }, { 2807 - .compatible = "mediatek,mt8188-svs", 2808 - .data = &svs_mt8188_platform_data, 2809 - }, { 2810 - .compatible = "mediatek,mt8183-svs", 2811 - .data = &svs_mt8183_platform_data, 2812 - }, { 2813 - /* Sentinel */ 2814 - }, 2476 + { .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data }, 2477 + { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data }, 2478 + { .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data }, 2479 + { .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data }, 2480 + { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data }, 2481 + { /* sentinel */ } 2815 2482 }; 2816 2483 MODULE_DEVICE_TABLE(of, svs_of_match); 2817 2484 ··· 2829 2500 svsp->banks = svsp_data->banks; 2830 2501 svsp->regs = svsp_data->regs; 2831 2502 svsp->bank_max = svsp_data->bank_max; 2503 + svsp->ts_coeff = svsp_data->ts_coeff; 2832 2504 2833 2505 ret = svsp_data->probe(svsp); 2834 2506 if (ret) ··· 2837 2507 2838 2508 ret = svs_get_efuse_data(svsp, "svs-calibration-data", 2839 2509 &svsp->efuse, &svsp->efuse_max); 2510 + if (ret) 2511 + return dev_err_probe(&pdev->dev, ret, "Cannot read SVS calibration\n"); 2512 + 2513 + ret = svs_get_efuse_data(svsp, "t-calibration-data", 2514 + &svsp->tefuse, &svsp->tefuse_max); 2840 2515 if (ret) { 2841 - ret = -EPERM; 2516 + dev_err_probe(&pdev->dev, ret, "Cannot read SVS-Thermal calibration\n"); 2842 2517 goto svs_probe_free_efuse; 2843 2518 } 2844 2519 2845 - if (!svsp_data->efuse_parsing(svsp)) { 2846 - dev_err(svsp->dev, "efuse data parsing failed\n"); 2847 - ret = -EPERM; 2520 + if (!svsp_data->efuse_parsing(svsp, svsp_data)) { 2521 + ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n"); 2848 2522 goto svs_probe_free_tefuse; 2849 2523 } 2850 2524 2851 2525 ret = svs_bank_resource_setup(svsp); 2852 2526 if (ret) { 2853 - dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); 2527 + dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n"); 2854 2528 goto svs_probe_free_tefuse; 2855 2529 } 2856 2530 ··· 2866 2532 2867 2533 svsp->main_clk = devm_clk_get(svsp->dev, "main"); 2868 2534 if (IS_ERR(svsp->main_clk)) { 2869 - dev_err(svsp->dev, "failed to get clock: %ld\n", 2870 - PTR_ERR(svsp->main_clk)); 2871 - ret = PTR_ERR(svsp->main_clk); 2535 + ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk), 2536 + "failed to get clock\n"); 2872 2537 goto svs_probe_free_tefuse; 2873 2538 } 2874 2539 2875 2540 ret = clk_prepare_enable(svsp->main_clk); 2876 2541 if (ret) { 2877 - dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); 2542 + dev_err_probe(svsp->dev, ret, "cannot enable main clk\n"); 2878 2543 goto svs_probe_free_tefuse; 2879 2544 } 2880 2545 2881 2546 svsp->base = of_iomap(svsp->dev->of_node, 0); 2882 2547 if (IS_ERR_OR_NULL(svsp->base)) { 2883 - dev_err(svsp->dev, "cannot find svs register base\n"); 2884 - ret = -EINVAL; 2548 + ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n"); 2885 2549 goto svs_probe_clk_disable; 2886 2550 } 2887 2551 2888 2552 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, 2889 2553 IRQF_ONESHOT, svsp_data->name, svsp); 2890 2554 if (ret) { 2891 - dev_err(svsp->dev, "register irq(%d) failed: %d\n", 2892 - svsp_irq, ret); 2555 + dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq); 2893 2556 goto svs_probe_iounmap; 2894 2557 } 2895 2558 2896 2559 ret = svs_start(svsp); 2897 2560 if (ret) { 2898 - dev_err(svsp->dev, "svs start fail: %d\n", ret); 2561 + dev_err_probe(svsp->dev, ret, "svs start fail\n"); 2899 2562 goto svs_probe_iounmap; 2900 2563 } 2901 2564 2902 2565 #ifdef CONFIG_DEBUG_FS 2903 2566 ret = svs_create_debug_cmds(svsp); 2904 2567 if (ret) { 2905 - dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); 2568 + dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n"); 2906 2569 goto svs_probe_iounmap; 2907 2570 } 2908 2571 #endif ··· 2908 2577 2909 2578 svs_probe_iounmap: 2910 2579 iounmap(svsp->base); 2911 - 2912 2580 svs_probe_clk_disable: 2913 2581 clk_disable_unprepare(svsp->main_clk); 2914 - 2915 2582 svs_probe_free_tefuse: 2916 - if (!IS_ERR_OR_NULL(svsp->tefuse)) 2917 - kfree(svsp->tefuse); 2918 - 2583 + kfree(svsp->tefuse); 2919 2584 svs_probe_free_efuse: 2920 - if (!IS_ERR_OR_NULL(svsp->efuse)) 2921 - kfree(svsp->efuse); 2922 - 2585 + kfree(svsp->efuse); 2923 2586 return ret; 2924 2587 } 2925 2588 ··· 2931 2606 module_platform_driver(svs_driver); 2932 2607 2933 2608 MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>"); 2609 + MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>"); 2934 2610 MODULE_DESCRIPTION("MediaTek SVS driver"); 2935 2611 MODULE_LICENSE("GPL");
+1
drivers/soc/microchip/Kconfig
··· 1 1 config POLARFIRE_SOC_SYS_CTRL 2 2 tristate "POLARFIRE_SOC_SYS_CTRL" 3 3 depends on POLARFIRE_SOC_MAILBOX 4 + depends on MTD 4 5 help 5 6 This driver adds support for the PolarFire SoC (MPFS) system controller. 6 7
+30 -3
drivers/soc/microchip/mpfs-sys-controller.c
··· 12 12 #include <linux/kref.h> 13 13 #include <linux/module.h> 14 14 #include <linux/jiffies.h> 15 + #include <linux/mtd/mtd.h> 16 + #include <linux/spi/spi.h> 15 17 #include <linux/interrupt.h> 16 18 #include <linux/of.h> 17 19 #include <linux/mailbox_client.h> ··· 32 30 struct mbox_client client; 33 31 struct mbox_chan *chan; 34 32 struct completion c; 33 + struct mtd_info *flash; 35 34 struct kref consumers; 36 35 }; 37 36 ··· 66 63 */ 67 64 if (!wait_for_completion_timeout(&sys_controller->c, timeout)) { 68 65 ret = -EBADMSG; 69 - dev_warn(sys_controller->client.dev, "MPFS sys controller service failed\n"); 66 + dev_warn(sys_controller->client.dev, 67 + "MPFS sys controller service failed with status: %d\n", 68 + msg->response->resp_status); 70 69 } else { 71 70 ret = 0; 72 71 } ··· 104 99 kref_put(&sys_controller->consumers, mpfs_sys_controller_delete); 105 100 } 106 101 102 + struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_client) 103 + { 104 + return mpfs_client->flash; 105 + } 106 + EXPORT_SYMBOL(mpfs_sys_controller_get_flash); 107 + 107 108 static struct platform_device subdevs[] = { 108 109 { 109 110 .name = "mpfs-rng", ··· 118 107 { 119 108 .name = "mpfs-generic-service", 120 109 .id = -1, 121 - } 110 + }, 111 + { 112 + .name = "mpfs-auto-update", 113 + .id = -1, 114 + }, 122 115 }; 123 116 124 117 static int mpfs_sys_controller_probe(struct platform_device *pdev) 125 118 { 126 119 struct device *dev = &pdev->dev; 127 120 struct mpfs_sys_controller *sys_controller; 121 + struct device_node *np; 128 122 int i, ret; 129 123 130 124 sys_controller = kzalloc(sizeof(*sys_controller), GFP_KERNEL); 131 125 if (!sys_controller) 132 126 return -ENOMEM; 133 127 128 + np = of_parse_phandle(dev->of_node, "microchip,bitstream-flash", 0); 129 + if (!np) 130 + goto no_flash; 131 + 132 + sys_controller->flash = of_get_mtd_device_by_node(np); 133 + of_node_put(np); 134 + if (IS_ERR(sys_controller->flash)) 135 + return dev_err_probe(dev, PTR_ERR(sys_controller->flash), "Failed to get flash\n"); 136 + 137 + no_flash: 134 138 sys_controller->client.dev = dev; 135 139 sys_controller->client.rx_callback = mpfs_sys_controller_rx_callback; 136 140 sys_controller->client.tx_block = 1U; ··· 164 138 165 139 platform_set_drvdata(pdev, sys_controller); 166 140 167 - dev_info(&pdev->dev, "Registered MPFS system controller\n"); 168 141 169 142 for (i = 0; i < ARRAY_SIZE(subdevs); i++) { 170 143 subdevs[i].dev.parent = dev; 171 144 if (platform_device_register(&subdevs[i])) 172 145 dev_warn(dev, "Error registering sub device %s\n", subdevs[i].name); 173 146 } 147 + 148 + dev_info(&pdev->dev, "Registered MPFS system controller\n"); 174 149 175 150 return 0; 176 151 }
+13
drivers/soc/qcom/Kconfig
··· 77 77 select QCOM_QMI_HELPERS 78 78 depends on NET 79 79 80 + config QCOM_PMIC_PDCHARGER_ULOG 81 + tristate "Qualcomm PMIC PDCharger ULOG driver" 82 + depends on RPMSG 83 + depends on EVENT_TRACING 84 + help 85 + The Qualcomm PMIC PDCharger ULOG driver provides access to logs of 86 + the ADSP firmware PDCharger module in charge of Battery and Power 87 + Delivery on modern systems. 88 + 89 + Say yes here to support PDCharger ULOG event tracing on modern 90 + Qualcomm platforms. 91 + 80 92 config QCOM_PMIC_GLINK 81 93 tristate "Qualcomm PMIC GLINK driver" 82 94 depends on RPMSG ··· 221 209 tristate "Qualcomm Technologies, Inc. (QTI) Sleep stats driver" 222 210 depends on (ARCH_QCOM && DEBUG_FS) || COMPILE_TEST 223 211 depends on QCOM_SMEM 212 + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n 224 213 help 225 214 Qualcomm Technologies, Inc. (QTI) Sleep stats driver to read 226 215 the shared memory exported by the remote processor related to
+2
drivers/soc/qcom/Makefile
··· 9 9 obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o 10 10 obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o 11 11 obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink_altmode.o 12 + obj-$(CONFIG_QCOM_PMIC_PDCHARGER_ULOG) += pmic_pdcharger_ulog.o 13 + CFLAGS_pmic_pdcharger_ulog.o := -I$(src) 12 14 obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o 13 15 qmi_helpers-y += qmi_encdec.o qmi_interface.o 14 16 obj-$(CONFIG_QCOM_RAMP_CTRL) += ramp_controller.o
+101 -6
drivers/soc/qcom/llcc-qcom.c
··· 47 47 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 48 48 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 49 49 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 50 - #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_8 * n) 50 + #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n) 51 51 52 52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 53 53 #define LLCC_TRP_PCB_ACT 0x21f04 ··· 92 92 * @write_scid_en: Bit enables write cache support for a given scid. 93 93 * @write_scid_cacheable_en: Enables write cache cacheable support for a 94 94 * given scid (not supported on v2 or older hardware). 95 + * @stale_en: Bit enables stale. 96 + * @stale_cap_en: Bit enables stale only if current scid is over-cap. 97 + * @mru_uncap_en: Roll-over on reserved cache ways if current scid is 98 + * under-cap. 99 + * @mru_rollover: Roll-over on reserved cache ways. 100 + * @alloc_oneway_en: Allways allocate one way on over-cap even if there's no 101 + * same-scid lines for replacement. 102 + * @ovcap_en: Once current scid is over-capacity, allocate other over-cap SCID. 103 + * @ovcap_prio: Once current scid is over-capacity, allocate other low priority 104 + * over-cap scid. Depends on corresponding bit being set in 105 + * ovcap_en. 106 + * @vict_prio: When current scid is under-capacity, allocate over other 107 + * lower-than victim priority-line threshold scid. 95 108 */ 96 109 struct llcc_slice_config { 97 110 u32 usecase_id; ··· 375 362 {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 376 363 }; 377 364 365 + static const struct llcc_slice_config sm8650_data[] = { 366 + {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}, 367 + {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 368 + {LLCC_AUDIO, 6, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 369 + {LLCC_MDMHPGRW, 25, 1024, 3, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 370 + {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 371 + {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 372 + {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 373 + {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, 374 + {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 375 + {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 376 + {LLCC_MDMHPFX, 24, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 377 + {LLCC_MDMPNG, 27, 1024, 0, 1, 0x000000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 378 + {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 379 + {LLCC_CVP, 8, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 380 + {LLCC_MODPE, 29, 128, 1, 1, 0xF00000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, 381 + {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 382 + {LLCC_CAMEXP0, 4, 256, 3, 1, 0xF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 383 + {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 384 + {LLCC_CMPTHCP, 17, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 385 + {LLCC_LCPDARE, 30, 128, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, 386 + {LLCC_AENPU, 3, 3072, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 387 + {LLCC_ISLAND1, 12, 5888, 7, 1, 0x0, 0x7FFFFF, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 388 + {LLCC_DISP_WB, 23, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 389 + {LLCC_VIDVSP, 28, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 390 + }; 391 + 378 392 static const struct llcc_slice_config qdu1000_data_2ch[] = { 379 393 { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 380 394 { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, ··· 430 390 { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 431 391 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 }, 432 392 { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 393 + }; 394 + 395 + static const struct llcc_slice_config x1e80100_data[] = { 396 + {LLCC_CPUSS, 1, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 397 + {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 398 + {LLCC_AUDIO, 6, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 399 + {LLCC_CMPT, 10, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 400 + {LLCC_GPUHTW, 11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 401 + {LLCC_GPU, 9, 4096, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, 402 + {LLCC_MMUHWT, 18, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 403 + {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 404 + {LLCC_CVP, 8, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 405 + {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 406 + {LLCC_CAMEXP1, 7, 3072, 2, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 407 + {LLCC_LCPDARE, 30, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 408 + {LLCC_AENPU, 3, 3072, 1, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 409 + {LLCC_ISLAND1, 12, 512, 7, 1, 0x1, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 410 + {LLCC_ISLAND2, 13, 512, 7, 1, 0x2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 411 + {LLCC_ISLAND3, 14, 512, 7, 1, 0x3, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 412 + {LLCC_ISLAND4, 15, 512, 7, 1, 0x4, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 413 + {LLCC_CAMEXP2, 19, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 414 + {LLCC_CAMEXP3, 20, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 415 + {LLCC_CAMEXP4, 21, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 433 416 }; 434 417 435 418 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { ··· 673 610 }, 674 611 }; 675 612 613 + static const struct qcom_llcc_config sm8650_cfg[] = { 614 + { 615 + .sct_data = sm8650_data, 616 + .size = ARRAY_SIZE(sm8650_data), 617 + .need_llcc_cfg = true, 618 + .reg_offset = llcc_v2_1_reg_offset, 619 + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 620 + }, 621 + }; 622 + 623 + static const struct qcom_llcc_config x1e80100_cfg[] = { 624 + { 625 + .sct_data = x1e80100_data, 626 + .size = ARRAY_SIZE(x1e80100_data), 627 + .need_llcc_cfg = true, 628 + .reg_offset = llcc_v2_1_reg_offset, 629 + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 630 + }, 631 + }; 632 + 676 633 static const struct qcom_sct_config qdu1000_cfgs = { 677 634 .llcc_config = qdu1000_cfg, 678 635 .num_config = ARRAY_SIZE(qdu1000_cfg), ··· 758 675 .num_config = ARRAY_SIZE(sm8550_cfg), 759 676 }; 760 677 678 + static const struct qcom_sct_config sm8650_cfgs = { 679 + .llcc_config = sm8650_cfg, 680 + .num_config = ARRAY_SIZE(sm8650_cfg), 681 + }; 682 + 683 + static const struct qcom_sct_config x1e80100_cfgs = { 684 + .llcc_config = x1e80100_cfg, 685 + .num_config = ARRAY_SIZE(x1e80100_cfg), 686 + }; 687 + 761 688 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 762 689 763 690 /** ··· 808 715 EXPORT_SYMBOL_GPL(llcc_slice_getd); 809 716 810 717 /** 811 - * llcc_slice_putd - llcc slice descritpor 718 + * llcc_slice_putd - llcc slice descriptor 812 719 * @desc: Pointer to llcc slice descriptor 813 720 */ 814 721 void llcc_slice_putd(struct llcc_slice_desc *desc) ··· 1034 941 u32 disable_cap_alloc, retain_pc; 1035 942 1036 943 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 1037 - ret = regmap_write(drv_data->bcast_regmap, 1038 - LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 944 + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC, 945 + BIT(config->slice_id), disable_cap_alloc); 1039 946 if (ret) 1040 947 return ret; 1041 948 1042 949 if (drv_data->version < LLCC_VERSION_4_1_0_0) { 1043 950 retain_pc = config->retain_on_pc << config->slice_id; 1044 - ret = regmap_write(drv_data->bcast_regmap, 1045 - LLCC_TRP_PCB_ACT, retain_pc); 951 + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_PCB_ACT, 952 + BIT(config->slice_id), retain_pc); 1046 953 if (ret) 1047 954 return ret; 1048 955 } ··· 1342 1249 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs }, 1343 1250 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs }, 1344 1251 { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs }, 1252 + { .compatible = "qcom,sm8650-llcc", .data = &sm8650_cfgs }, 1253 + { .compatible = "qcom,x1e80100-llcc", .data = &x1e80100_cfgs }, 1345 1254 { } 1346 1255 }; 1347 1256 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
+12 -12
drivers/soc/qcom/pmic_glink.c
··· 18 18 PMIC_GLINK_CLIENT_UCSI, 19 19 }; 20 20 21 - #define PMIC_GLINK_CLIENT_DEFAULT (BIT(PMIC_GLINK_CLIENT_BATT) | \ 22 - BIT(PMIC_GLINK_CLIENT_ALTMODE)) 23 - 24 21 struct pmic_glink { 25 22 struct device *dev; 26 23 struct pdr_handle *pdr; ··· 260 263 mutex_init(&pg->state_lock); 261 264 262 265 match_data = (unsigned long *)of_device_get_match_data(&pdev->dev); 263 - if (match_data) 264 - pg->client_mask = *match_data; 265 - else 266 - pg->client_mask = PMIC_GLINK_CLIENT_DEFAULT; 266 + if (!match_data) 267 + return -EINVAL; 268 + 269 + pg->client_mask = *match_data; 267 270 268 271 if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) { 269 272 ret = pmic_glink_add_aux_device(pg, &pg->ucsi_aux, "ucsi"); ··· 333 336 mutex_unlock(&__pmic_glink_lock); 334 337 } 335 338 339 + static const unsigned long pmic_glink_sc8180x_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | 340 + BIT(PMIC_GLINK_CLIENT_ALTMODE); 341 + 336 342 static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | 337 343 BIT(PMIC_GLINK_CLIENT_ALTMODE) | 338 344 BIT(PMIC_GLINK_CLIENT_UCSI); 339 345 340 346 static const struct of_device_id pmic_glink_of_match[] = { 341 - { .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, 342 - { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, 343 - { .compatible = "qcom,pmic-glink" }, 347 + { .compatible = "qcom,sc8180x-pmic-glink", .data = &pmic_glink_sc8180x_client_mask }, 348 + { .compatible = "qcom,sc8280xp-pmic-glink", .data = &pmic_glink_sc8180x_client_mask }, 349 + { .compatible = "qcom,pmic-glink", .data = &pmic_glink_sm8450_client_mask }, 344 350 {} 345 351 }; 346 352 MODULE_DEVICE_TABLE(of, pmic_glink_of_match); ··· 363 363 register_rpmsg_driver(&pmic_glink_rpmsg_driver); 364 364 365 365 return 0; 366 - }; 366 + } 367 367 module_init(pmic_glink_init); 368 368 369 369 static void pmic_glink_exit(void) 370 370 { 371 371 unregister_rpmsg_driver(&pmic_glink_rpmsg_driver); 372 372 platform_driver_unregister(&pmic_glink_driver); 373 - }; 373 + } 374 374 module_exit(pmic_glink_exit); 375 375 376 376 MODULE_DESCRIPTION("Qualcomm PMIC GLINK driver");
+166
drivers/soc/qcom/pmic_pdcharger_ulog.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) 2019-2022, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2023, Linaro Ltd 5 + */ 6 + #include <linux/of_device.h> 7 + #include <linux/module.h> 8 + #include <linux/platform_device.h> 9 + #include <linux/rpmsg.h> 10 + #include <linux/slab.h> 11 + #include <linux/soc/qcom/pdr.h> 12 + #include <linux/debugfs.h> 13 + 14 + #define CREATE_TRACE_POINTS 15 + #include "pmic_pdcharger_ulog.h" 16 + 17 + #define MSG_OWNER_CHG_ULOG 32778 18 + #define MSG_TYPE_REQ_RESP 1 19 + 20 + #define GET_CHG_ULOG_REQ 0x18 21 + #define SET_CHG_ULOG_PROP_REQ 0x19 22 + 23 + #define LOG_DEFAULT_TIME_MS 1000 24 + 25 + #define MAX_ULOG_SIZE 8192 26 + 27 + struct pmic_pdcharger_ulog_hdr { 28 + __le32 owner; 29 + __le32 type; 30 + __le32 opcode; 31 + }; 32 + 33 + struct pmic_pdcharger_ulog { 34 + struct rpmsg_device *rpdev; 35 + struct delayed_work ulog_work; 36 + }; 37 + 38 + struct get_ulog_req_msg { 39 + struct pmic_pdcharger_ulog_hdr hdr; 40 + u32 log_size; 41 + }; 42 + 43 + struct get_ulog_resp_msg { 44 + struct pmic_pdcharger_ulog_hdr hdr; 45 + u8 buf[MAX_ULOG_SIZE]; 46 + }; 47 + 48 + static int pmic_pdcharger_ulog_write_async(struct pmic_pdcharger_ulog *pg, void *data, size_t len) 49 + { 50 + return rpmsg_send(pg->rpdev->ept, data, len); 51 + } 52 + 53 + static int pmic_pdcharger_ulog_request(struct pmic_pdcharger_ulog *pg) 54 + { 55 + struct get_ulog_req_msg req_msg = { 56 + .hdr = { 57 + .owner = cpu_to_le32(MSG_OWNER_CHG_ULOG), 58 + .type = cpu_to_le32(MSG_TYPE_REQ_RESP), 59 + .opcode = cpu_to_le32(GET_CHG_ULOG_REQ) 60 + }, 61 + .log_size = MAX_ULOG_SIZE 62 + }; 63 + 64 + return pmic_pdcharger_ulog_write_async(pg, &req_msg, sizeof(req_msg)); 65 + } 66 + 67 + static void pmic_pdcharger_ulog_work(struct work_struct *work) 68 + { 69 + struct pmic_pdcharger_ulog *pg = container_of(work, struct pmic_pdcharger_ulog, 70 + ulog_work.work); 71 + int rc; 72 + 73 + rc = pmic_pdcharger_ulog_request(pg); 74 + if (rc) { 75 + dev_err(&pg->rpdev->dev, "Error requesting ulog, rc=%d\n", rc); 76 + return; 77 + } 78 + } 79 + 80 + static void pmic_pdcharger_ulog_handle_message(struct pmic_pdcharger_ulog *pg, 81 + struct get_ulog_resp_msg *resp_msg, 82 + size_t len) 83 + { 84 + char *token, *buf = resp_msg->buf; 85 + 86 + if (len != sizeof(*resp_msg)) { 87 + dev_err(&pg->rpdev->dev, "Expected data length: %zu, received: %zu\n", 88 + sizeof(*resp_msg), len); 89 + return; 90 + } 91 + 92 + buf[MAX_ULOG_SIZE - 1] = '\0'; 93 + 94 + do { 95 + token = strsep((char **)&buf, "\n"); 96 + if (token && strlen(token)) 97 + trace_pmic_pdcharger_ulog_msg(token); 98 + } while (token); 99 + } 100 + 101 + static int pmic_pdcharger_ulog_rpmsg_callback(struct rpmsg_device *rpdev, void *data, 102 + int len, void *priv, u32 addr) 103 + { 104 + struct pmic_pdcharger_ulog *pg = dev_get_drvdata(&rpdev->dev); 105 + struct pmic_pdcharger_ulog_hdr *hdr = data; 106 + u32 opcode; 107 + 108 + opcode = le32_to_cpu(hdr->opcode); 109 + 110 + switch (opcode) { 111 + case GET_CHG_ULOG_REQ: 112 + schedule_delayed_work(&pg->ulog_work, msecs_to_jiffies(LOG_DEFAULT_TIME_MS)); 113 + pmic_pdcharger_ulog_handle_message(pg, data, len); 114 + break; 115 + default: 116 + dev_err(&pg->rpdev->dev, "Unknown opcode %u\n", opcode); 117 + break; 118 + } 119 + 120 + return 0; 121 + } 122 + 123 + static int pmic_pdcharger_ulog_rpmsg_probe(struct rpmsg_device *rpdev) 124 + { 125 + struct pmic_pdcharger_ulog *pg; 126 + struct device *dev = &rpdev->dev; 127 + 128 + pg = devm_kzalloc(dev, sizeof(*pg), GFP_KERNEL); 129 + if (!pg) 130 + return -ENOMEM; 131 + 132 + pg->rpdev = rpdev; 133 + INIT_DELAYED_WORK(&pg->ulog_work, pmic_pdcharger_ulog_work); 134 + 135 + dev_set_drvdata(dev, pg); 136 + 137 + pmic_pdcharger_ulog_request(pg); 138 + 139 + return 0; 140 + } 141 + 142 + static void pmic_pdcharger_ulog_rpmsg_remove(struct rpmsg_device *rpdev) 143 + { 144 + struct pmic_pdcharger_ulog *pg = dev_get_drvdata(&rpdev->dev); 145 + 146 + cancel_delayed_work_sync(&pg->ulog_work); 147 + } 148 + 149 + static const struct rpmsg_device_id pmic_pdcharger_ulog_rpmsg_id_match[] = { 150 + { "PMIC_LOGS_ADSP_APPS" }, 151 + {} 152 + }; 153 + 154 + static struct rpmsg_driver pmic_pdcharger_ulog_rpmsg_driver = { 155 + .probe = pmic_pdcharger_ulog_rpmsg_probe, 156 + .remove = pmic_pdcharger_ulog_rpmsg_remove, 157 + .callback = pmic_pdcharger_ulog_rpmsg_callback, 158 + .id_table = pmic_pdcharger_ulog_rpmsg_id_match, 159 + .drv = { 160 + .name = "qcom_pmic_pdcharger_ulog_rpmsg", 161 + }, 162 + }; 163 + 164 + module_rpmsg_driver(pmic_pdcharger_ulog_rpmsg_driver); 165 + MODULE_DESCRIPTION("Qualcomm PMIC ChargerPD ULOG driver"); 166 + MODULE_LICENSE("GPL");
+36
drivers/soc/qcom/pmic_pdcharger_ulog.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (c) 2023, Linaro Ltd 4 + */ 5 + 6 + #undef TRACE_SYSTEM 7 + #define TRACE_SYSTEM pmic_pdcharger_ulog 8 + 9 + #if !defined(_TRACE_PMIC_PDCHARGER_ULOG_H) || defined(TRACE_HEADER_MULTI_READ) 10 + #define _TRACE_PMIC_PDCHARGER_ULOG_H 11 + 12 + #include <linux/tracepoint.h> 13 + 14 + TRACE_EVENT(pmic_pdcharger_ulog_msg, 15 + TP_PROTO(char *msg), 16 + TP_ARGS(msg), 17 + TP_STRUCT__entry( 18 + __string(msg, msg) 19 + ), 20 + TP_fast_assign( 21 + __assign_str(msg, msg); 22 + ), 23 + TP_printk("%s", __get_str(msg)) 24 + ); 25 + 26 + #endif /* _TRACE_PMIC_PDCHARGER_ULOG_H */ 27 + 28 + /* This part must be outside protection */ 29 + 30 + #undef TRACE_INCLUDE_PATH 31 + #define TRACE_INCLUDE_PATH . 32 + 33 + #undef TRACE_INCLUDE_FILE 34 + #define TRACE_INCLUDE_FILE pmic_pdcharger_ulog 35 + 36 + #include <trace/define_trace.h>
+12 -1
drivers/soc/qcom/socinfo.c
··· 51 51 #define SMEM_IMAGE_TABLE_ADSP_INDEX 12 52 52 #define SMEM_IMAGE_TABLE_CNSS_INDEX 13 53 53 #define SMEM_IMAGE_TABLE_VIDEO_INDEX 14 54 + #define SMEM_IMAGE_TABLE_DSPS_INDEX 15 55 + #define SMEM_IMAGE_TABLE_CDSP_INDEX 16 56 + #define SMEM_IMAGE_TABLE_CDSP1_INDEX 19 57 + #define SMEM_IMAGE_TABLE_GPDSP_INDEX 20 58 + #define SMEM_IMAGE_TABLE_GPDSP1_INDEX 21 54 59 #define SMEM_IMAGE_VERSION_TABLE 469 55 60 56 61 /* ··· 70 65 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm", 71 66 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz", 72 67 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video", 68 + [SMEM_IMAGE_TABLE_DSPS_INDEX] = "dsps", 69 + [SMEM_IMAGE_TABLE_CDSP_INDEX] = "cdsp", 70 + [SMEM_IMAGE_TABLE_CDSP1_INDEX] = "cdsp1", 71 + [SMEM_IMAGE_TABLE_GPDSP_INDEX] = "gpdsp", 72 + [SMEM_IMAGE_TABLE_GPDSP1_INDEX] = "gpdsp1", 73 73 }; 74 74 75 75 static const char *const pmic_models[] = { ··· 103 93 [22] = "PM8821", 104 94 [23] = "PM8038", 105 95 [24] = "PM8005/PM8922", 106 - [25] = "PM8917", 96 + [25] = "PM8917/PM8937", 107 97 [26] = "PM660L", 108 98 [27] = "PM660", 109 99 [30] = "PM8150", ··· 427 417 { qcom_board_id(SA8775P) }, 428 418 { qcom_board_id(QRU1000) }, 429 419 { qcom_board_id(QDU1000) }, 420 + { qcom_board_id(SM8650) }, 430 421 { qcom_board_id(SM4450) }, 431 422 { qcom_board_id(QDU1010) }, 432 423 { qcom_board_id(QRU1032) },
+1
drivers/soc/renesas/Kconfig
··· 340 340 config ARCH_R9A07G043 341 341 bool "RISC-V Platform support for RZ/Five" 342 342 depends on NONPORTABLE 343 + depends on !DMA_DIRECT_REMAP 343 344 depends on RISCV_ALTERNATIVE 344 345 depends on !RISCV_ISA_ZICBOM 345 346 depends on RISCV_SBI
-4
drivers/soc/renesas/renesas-soc.c
··· 486 486 return -ENOMEM; 487 487 } 488 488 489 - np = of_find_node_by_path("/"); 490 - of_property_read_string(np, "model", &soc_dev_attr->machine); 491 - of_node_put(np); 492 - 493 489 soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL); 494 490 soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL); 495 491
+1
drivers/soc/samsung/exynos-chipid.c
··· 59 59 { "EXYNOS7885", 0xE7885000 }, 60 60 { "EXYNOS850", 0xE3830000 }, 61 61 { "EXYNOSAUTOV9", 0xAAA80000 }, 62 + { "EXYNOSAUTOV920", 0x0A920000 }, 62 63 }; 63 64 64 65 static const char *product_id_to_soc_id(unsigned int product_id)
-10
drivers/soc/sifive/Kconfig
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - 3 - if ARCH_SIFIVE || ARCH_STARFIVE 4 - 5 - config SIFIVE_CCACHE 6 - bool "Sifive Composable Cache controller" 7 - help 8 - Support for the composable cache controller on SiFive platforms. 9 - 10 - endif
-3
drivers/soc/sifive/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - 3 - obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
+60 -2
drivers/soc/sifive/sifive_ccache.c drivers/cache/sifive_ccache.c
··· 8 8 9 9 #define pr_fmt(fmt) "CCACHE: " fmt 10 10 11 + #include <linux/align.h> 11 12 #include <linux/debugfs.h> 12 13 #include <linux/interrupt.h> 13 14 #include <linux/of_irq.h> 14 15 #include <linux/of_address.h> 15 16 #include <linux/device.h> 16 17 #include <linux/bitfield.h> 18 + #include <asm/cacheflush.h> 17 19 #include <asm/cacheinfo.h> 20 + #include <asm/dma-noncoherent.h> 18 21 #include <soc/sifive/sifive_ccache.h> 19 22 20 23 #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 ··· 42 39 #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) 43 40 #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) 44 41 42 + #define SIFIVE_CCACHE_FLUSH64 0x200 43 + #define SIFIVE_CCACHE_FLUSH32 0x240 44 + 45 45 #define SIFIVE_CCACHE_WAYENABLE 0x08 46 46 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 47 47 48 48 #define SIFIVE_CCACHE_MAX_ECCINTR 4 49 + #define SIFIVE_CCACHE_LINE_SIZE 64 49 50 50 51 static void __iomem *ccache_base; 51 52 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; ··· 61 54 DATA_CORR, 62 55 DATA_UNCORR, 63 56 DIR_UNCORR, 57 + }; 58 + 59 + enum { 60 + QUIRK_NONSTANDARD_CACHE_OPS = BIT(0), 61 + QUIRK_BROKEN_DATA_UNCORR = BIT(1), 64 62 }; 65 63 66 64 #ifdef CONFIG_DEBUG_FS ··· 118 106 static const struct of_device_id sifive_ccache_ids[] = { 119 107 { .compatible = "sifive,fu540-c000-ccache" }, 120 108 { .compatible = "sifive,fu740-c000-ccache" }, 109 + { .compatible = "starfive,jh7100-ccache", 110 + .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) }, 121 111 { .compatible = "sifive,ccache0" }, 122 112 { /* end of table */ } 123 113 }; ··· 137 123 return atomic_notifier_chain_unregister(&ccache_err_chain, nb); 138 124 } 139 125 EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); 126 + 127 + #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS 128 + static void ccache_flush_range(phys_addr_t start, size_t len) 129 + { 130 + phys_addr_t end = start + len; 131 + phys_addr_t line; 132 + 133 + if (!len) 134 + return; 135 + 136 + mb(); 137 + for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end; 138 + line += SIFIVE_CCACHE_LINE_SIZE) { 139 + #ifdef CONFIG_32BIT 140 + writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); 141 + #else 142 + writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64); 143 + #endif 144 + mb(); 145 + } 146 + } 147 + 148 + static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = { 149 + .wback = &ccache_flush_range, 150 + .inv = &ccache_flush_range, 151 + .wback_inv = &ccache_flush_range, 152 + }; 153 + #endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */ 140 154 141 155 static int ccache_largest_wayenabled(void) 142 156 { ··· 252 210 struct device_node *np; 253 211 struct resource res; 254 212 int i, rc, intr_num; 213 + const struct of_device_id *match; 214 + unsigned long quirks; 255 215 256 - np = of_find_matching_node(NULL, sifive_ccache_ids); 216 + np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match); 257 217 if (!np) 258 218 return -ENODEV; 219 + 220 + quirks = (uintptr_t)match->data; 259 221 260 222 if (of_address_to_resource(np, 0, &res)) { 261 223 rc = -ENODEV; ··· 286 240 287 241 for (i = 0; i < intr_num; i++) { 288 242 g_irq[i] = irq_of_parse_and_map(np, i); 243 + 244 + if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR)) 245 + continue; 246 + 289 247 rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", 290 248 NULL); 291 249 if (rc) { ··· 298 248 } 299 249 } 300 250 of_node_put(np); 251 + 252 + #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS 253 + if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) { 254 + riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE; 255 + riscv_noncoherent_supported(); 256 + riscv_noncoherent_register_cache_ops(&ccache_mgmt_ops); 257 + } 258 + #endif 301 259 302 260 ccache_config_read(); 303 261 ··· 327 269 return rc; 328 270 } 329 271 330 - device_initcall(sifive_ccache_init); 272 + arch_initcall(sifive_ccache_init);
+58 -17
drivers/soc/ti/k3-socinfo.c
··· 33 33 34 34 #define CTRLMMR_WKUP_JTAGID_MFG_TI 0x17 35 35 36 + #define JTAG_ID_PARTNO_AM65X 0xBB5A 37 + #define JTAG_ID_PARTNO_J721E 0xBB64 38 + #define JTAG_ID_PARTNO_J7200 0xBB6D 39 + #define JTAG_ID_PARTNO_AM64X 0xBB38 40 + #define JTAG_ID_PARTNO_J721S2 0xBB75 41 + #define JTAG_ID_PARTNO_AM62X 0xBB7E 42 + #define JTAG_ID_PARTNO_J784S4 0xBB80 43 + #define JTAG_ID_PARTNO_AM62AX 0xBB8D 44 + #define JTAG_ID_PARTNO_AM62PX 0xBB9D 45 + #define JTAG_ID_PARTNO_J722S 0xBBA0 46 + 36 47 static const struct k3_soc_id { 37 48 unsigned int id; 38 49 const char *family_name; 39 50 } k3_soc_ids[] = { 40 - { 0xBB5A, "AM65X" }, 41 - { 0xBB64, "J721E" }, 42 - { 0xBB6D, "J7200" }, 43 - { 0xBB38, "AM64X" }, 44 - { 0xBB75, "J721S2"}, 45 - { 0xBB7E, "AM62X" }, 46 - { 0xBB80, "J784S4" }, 47 - { 0xBB8D, "AM62AX" }, 48 - { 0xBB9D, "AM62PX" }, 51 + { JTAG_ID_PARTNO_AM65X, "AM65X" }, 52 + { JTAG_ID_PARTNO_J721E, "J721E" }, 53 + { JTAG_ID_PARTNO_J7200, "J7200" }, 54 + { JTAG_ID_PARTNO_AM64X, "AM64X" }, 55 + { JTAG_ID_PARTNO_J721S2, "J721S2"}, 56 + { JTAG_ID_PARTNO_AM62X, "AM62X" }, 57 + { JTAG_ID_PARTNO_J784S4, "J784S4" }, 58 + { JTAG_ID_PARTNO_AM62AX, "AM62AX" }, 59 + { JTAG_ID_PARTNO_AM62PX, "AM62PX" }, 60 + { JTAG_ID_PARTNO_J722S, "J722S" }, 61 + }; 62 + 63 + static const char * const j721e_rev_string_map[] = { 64 + "1.0", "1.1", 49 65 }; 50 66 51 67 static int ··· 76 60 return 0; 77 61 } 78 62 63 + return -ENODEV; 64 + } 65 + 66 + static int 67 + k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant, 68 + struct soc_device_attribute *soc_dev_attr) 69 + { 70 + switch (partno) { 71 + case JTAG_ID_PARTNO_J721E: 72 + if (variant >= ARRAY_SIZE(j721e_rev_string_map)) 73 + goto err_unknown_variant; 74 + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", 75 + j721e_rev_string_map[variant]); 76 + break; 77 + default: 78 + variant++; 79 + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%x.0", 80 + variant); 81 + } 82 + 83 + if (!soc_dev_attr->revision) 84 + return -ENOMEM; 85 + 86 + return 0; 87 + 88 + err_unknown_variant: 79 89 return -ENODEV; 80 90 } 81 91 ··· 136 94 137 95 variant = (jtag_id & CTRLMMR_WKUP_JTAGID_VARIANT_MASK) >> 138 96 CTRLMMR_WKUP_JTAGID_VARIANT_SHIFT; 139 - variant++; 140 97 141 98 partno_id = (jtag_id & CTRLMMR_WKUP_JTAGID_PARTNO_MASK) >> 142 99 CTRLMMR_WKUP_JTAGID_PARTNO_SHIFT; ··· 144 103 if (!soc_dev_attr) 145 104 return -ENOMEM; 146 105 147 - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%x.0", variant); 148 - if (!soc_dev_attr->revision) { 149 - ret = -ENOMEM; 150 - goto err; 151 - } 152 - 153 106 ret = k3_chipinfo_partno_to_names(partno_id, soc_dev_attr); 154 107 if (ret) { 155 108 dev_err(dev, "Unknown SoC JTAGID[0x%08X]: %d\n", jtag_id, ret); 156 - goto err_free_rev; 109 + goto err; 110 + } 111 + 112 + ret = k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr); 113 + if (ret) { 114 + dev_err(dev, "Unknown SoC SR[0x%08X]: %d\n", jtag_id, ret); 115 + goto err; 157 116 } 158 117 159 118 node = of_find_node_by_path("/");
+5 -2
drivers/soc/xilinx/xlnx_event_manager.c
··· 477 477 } 478 478 } 479 479 if (!is_callback_found) 480 - pr_warn("Didn't find any registered callback for 0x%x 0x%x\n", 480 + pr_warn("Unhandled SGI node 0x%x event 0x%x. Expected with Xen hypervisor\n", 481 481 payload[1], payload[2]); 482 482 } 483 483 ··· 555 555 static int xlnx_event_init_sgi(struct platform_device *pdev) 556 556 { 557 557 int ret = 0; 558 - int cpu = smp_processor_id(); 558 + int cpu; 559 559 /* 560 560 * IRQ related structures are used for the following: 561 561 * for each SGI interrupt ensure its mapped by GIC IRQ domain ··· 592 592 sgi_fwspec.param[0] = sgi_num; 593 593 virq_sgi = irq_create_fwspec_mapping(&sgi_fwspec); 594 594 595 + cpu = get_cpu(); 595 596 per_cpu(cpu_number1, cpu) = cpu; 596 597 ret = request_percpu_irq(virq_sgi, xlnx_event_handler, "xlnx_event_mgmt", 597 598 &cpu_number1); 599 + put_cpu(); 600 + 598 601 WARN_ON(ret); 599 602 if (ret) { 600 603 irq_dispose_mapping(virq_sgi);
+8 -8
drivers/soc/xilinx/zynqmp_power.c
··· 83 83 pm_suspend(PM_SUSPEND_MEM); 84 84 break; 85 85 default: 86 - pr_err("%s Unsupported InitSuspendCb reason " 87 - "code %d\n", __func__, payload[1]); 86 + pr_err("%s Unsupported InitSuspendCb reason code %d\n", 87 + __func__, payload[1]); 88 88 } 89 + } else { 90 + pr_err("%s() Unsupported Callback %d\n", __func__, payload[0]); 89 91 } 90 92 91 93 return IRQ_HANDLED; ··· 254 252 dev_name(&pdev->dev), 255 253 &pdev->dev); 256 254 if (ret) { 257 - dev_err(&pdev->dev, "devm_request_threaded_irq '%d' " 258 - "failed with %d\n", irq, ret); 255 + dev_err(&pdev->dev, "devm_request_threaded_irq '%d' failed with %d\n", 256 + irq, ret); 259 257 return ret; 260 258 } 261 259 } else { ··· 277 275 return 0; 278 276 } 279 277 280 - static int zynqmp_pm_remove(struct platform_device *pdev) 278 + static void zynqmp_pm_remove(struct platform_device *pdev) 281 279 { 282 280 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr); 283 281 if (event_registered) ··· 285 283 286 284 if (!rx_chan) 287 285 mbox_free_channel(rx_chan); 288 - 289 - return 0; 290 286 } 291 287 292 288 static const struct of_device_id pm_of_match[] = { ··· 295 295 296 296 static struct platform_driver zynqmp_pm_platform_driver = { 297 297 .probe = zynqmp_pm_probe, 298 - .remove = zynqmp_pm_remove, 298 + .remove_new = zynqmp_pm_remove, 299 299 .driver = { 300 300 .name = "zynqmp_power", 301 301 .of_match_table = pm_of_match,
+154 -9
drivers/tee/optee/call.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 - * Copyright (c) 2015-2021, Linaro Limited 3 + * Copyright (c) 2015-2021, 2023 Linaro Limited 4 4 */ 5 5 #include <linux/device.h> 6 6 #include <linux/err.h> ··· 39 39 DECLARE_BITMAP(map, MAX_ARG_COUNT_PER_ENTRY); 40 40 }; 41 41 42 - void optee_cq_wait_init(struct optee_call_queue *cq, 43 - struct optee_call_waiter *w) 42 + void optee_cq_init(struct optee_call_queue *cq, int thread_count) 44 43 { 44 + mutex_init(&cq->mutex); 45 + INIT_LIST_HEAD(&cq->waiters); 46 + 47 + /* 48 + * If cq->total_thread_count is 0 then we're not trying to keep 49 + * track of how many free threads we have, instead we're relying on 50 + * the secure world to tell us when we're out of thread and have to 51 + * wait for another thread to become available. 52 + */ 53 + cq->total_thread_count = thread_count; 54 + cq->free_thread_count = thread_count; 55 + } 56 + 57 + void optee_cq_wait_init(struct optee_call_queue *cq, 58 + struct optee_call_waiter *w, bool sys_thread) 59 + { 60 + unsigned int free_thread_threshold; 61 + bool need_wait = false; 62 + 63 + memset(w, 0, sizeof(*w)); 64 + 45 65 /* 46 66 * We're preparing to make a call to secure world. In case we can't 47 67 * allocate a thread in secure world we'll end up waiting in ··· 80 60 */ 81 61 init_completion(&w->c); 82 62 list_add_tail(&w->list_node, &cq->waiters); 63 + w->sys_thread = sys_thread; 64 + 65 + if (cq->total_thread_count) { 66 + if (sys_thread || !cq->sys_thread_req_count) 67 + free_thread_threshold = 0; 68 + else 69 + free_thread_threshold = 1; 70 + 71 + if (cq->free_thread_count > free_thread_threshold) 72 + cq->free_thread_count--; 73 + else 74 + need_wait = true; 75 + } 83 76 84 77 mutex_unlock(&cq->mutex); 78 + 79 + while (need_wait) { 80 + optee_cq_wait_for_completion(cq, w); 81 + mutex_lock(&cq->mutex); 82 + 83 + if (sys_thread || !cq->sys_thread_req_count) 84 + free_thread_threshold = 0; 85 + else 86 + free_thread_threshold = 1; 87 + 88 + if (cq->free_thread_count > free_thread_threshold) { 89 + cq->free_thread_count--; 90 + need_wait = false; 91 + } 92 + 93 + mutex_unlock(&cq->mutex); 94 + } 85 95 } 86 96 87 97 void optee_cq_wait_for_completion(struct optee_call_queue *cq, ··· 132 82 static void optee_cq_complete_one(struct optee_call_queue *cq) 133 83 { 134 84 struct optee_call_waiter *w; 85 + 86 + /* Wake a waiting system session if any, prior to a normal session */ 87 + list_for_each_entry(w, &cq->waiters, list_node) { 88 + if (w->sys_thread && !completion_done(&w->c)) { 89 + complete(&w->c); 90 + return; 91 + } 92 + } 135 93 136 94 list_for_each_entry(w, &cq->waiters, list_node) { 137 95 if (!completion_done(&w->c)) { ··· 162 104 /* Get out of the list */ 163 105 list_del(&w->list_node); 164 106 107 + cq->free_thread_count++; 108 + 165 109 /* Wake up one eventual waiting task */ 166 110 optee_cq_complete_one(cq); 167 111 ··· 176 116 if (completion_done(&w->c)) 177 117 optee_cq_complete_one(cq); 178 118 119 + mutex_unlock(&cq->mutex); 120 + } 121 + 122 + /* Count registered system sessions to reserved a system thread or not */ 123 + static bool optee_cq_incr_sys_thread_count(struct optee_call_queue *cq) 124 + { 125 + if (cq->total_thread_count <= 1) 126 + return false; 127 + 128 + mutex_lock(&cq->mutex); 129 + cq->sys_thread_req_count++; 130 + mutex_unlock(&cq->mutex); 131 + 132 + return true; 133 + } 134 + 135 + static void optee_cq_decr_sys_thread_count(struct optee_call_queue *cq) 136 + { 137 + mutex_lock(&cq->mutex); 138 + cq->sys_thread_req_count--; 139 + /* If there's someone waiting, let it resume */ 140 + optee_cq_complete_one(cq); 179 141 mutex_unlock(&cq->mutex); 180 142 } 181 143 ··· 410 328 goto out; 411 329 } 412 330 413 - if (optee->ops->do_call_with_arg(ctx, shm, offs)) { 331 + if (optee->ops->do_call_with_arg(ctx, shm, offs, 332 + sess->use_sys_thread)) { 414 333 msg_arg->ret = TEEC_ERROR_COMMUNICATION; 415 334 msg_arg->ret_origin = TEEC_ORIGIN_COMMS; 416 335 } ··· 443 360 return rc; 444 361 } 445 362 446 - int optee_close_session_helper(struct tee_context *ctx, u32 session) 363 + int optee_system_session(struct tee_context *ctx, u32 session) 364 + { 365 + struct optee *optee = tee_get_drvdata(ctx->teedev); 366 + struct optee_context_data *ctxdata = ctx->data; 367 + struct optee_session *sess; 368 + int rc = -EINVAL; 369 + 370 + mutex_lock(&ctxdata->mutex); 371 + 372 + sess = find_session(ctxdata, session); 373 + if (sess && (sess->use_sys_thread || 374 + optee_cq_incr_sys_thread_count(&optee->call_queue))) { 375 + sess->use_sys_thread = true; 376 + rc = 0; 377 + } 378 + 379 + mutex_unlock(&ctxdata->mutex); 380 + 381 + return rc; 382 + } 383 + 384 + int optee_close_session_helper(struct tee_context *ctx, u32 session, 385 + bool system_thread) 447 386 { 448 387 struct optee *optee = tee_get_drvdata(ctx->teedev); 449 388 struct optee_shm_arg_entry *entry; ··· 479 374 480 375 msg_arg->cmd = OPTEE_MSG_CMD_CLOSE_SESSION; 481 376 msg_arg->session = session; 482 - optee->ops->do_call_with_arg(ctx, shm, offs); 377 + optee->ops->do_call_with_arg(ctx, shm, offs, system_thread); 483 378 484 379 optee_free_msg_arg(ctx, entry, offs); 380 + 381 + if (system_thread) 382 + optee_cq_decr_sys_thread_count(&optee->call_queue); 485 383 486 384 return 0; 487 385 } ··· 493 385 { 494 386 struct optee_context_data *ctxdata = ctx->data; 495 387 struct optee_session *sess; 388 + bool system_thread; 496 389 497 390 /* Check that the session is valid and remove it from the list */ 498 391 mutex_lock(&ctxdata->mutex); ··· 503 394 mutex_unlock(&ctxdata->mutex); 504 395 if (!sess) 505 396 return -EINVAL; 397 + system_thread = sess->use_sys_thread; 506 398 kfree(sess); 507 399 508 - return optee_close_session_helper(ctx, session); 400 + return optee_close_session_helper(ctx, session, system_thread); 509 401 } 510 402 511 403 int optee_invoke_func(struct tee_context *ctx, struct tee_ioctl_invoke_arg *arg, ··· 518 408 struct optee_msg_arg *msg_arg; 519 409 struct optee_session *sess; 520 410 struct tee_shm *shm; 411 + bool system_thread; 521 412 u_int offs; 522 413 int rc; 523 414 524 415 /* Check that the session is valid */ 525 416 mutex_lock(&ctxdata->mutex); 526 417 sess = find_session(ctxdata, arg->session); 418 + if (sess) 419 + system_thread = sess->use_sys_thread; 527 420 mutex_unlock(&ctxdata->mutex); 528 421 if (!sess) 529 422 return -EINVAL; ··· 545 432 if (rc) 546 433 goto out; 547 434 548 - if (optee->ops->do_call_with_arg(ctx, shm, offs)) { 435 + if (optee->ops->do_call_with_arg(ctx, shm, offs, system_thread)) { 549 436 msg_arg->ret = TEEC_ERROR_COMMUNICATION; 550 437 msg_arg->ret_origin = TEEC_ORIGIN_COMMS; 551 438 } ··· 570 457 struct optee_shm_arg_entry *entry; 571 458 struct optee_msg_arg *msg_arg; 572 459 struct optee_session *sess; 460 + bool system_thread; 573 461 struct tee_shm *shm; 574 462 u_int offs; 575 463 576 464 /* Check that the session is valid */ 577 465 mutex_lock(&ctxdata->mutex); 578 466 sess = find_session(ctxdata, session); 467 + if (sess) 468 + system_thread = sess->use_sys_thread; 579 469 mutex_unlock(&ctxdata->mutex); 580 470 if (!sess) 581 471 return -EINVAL; ··· 590 474 msg_arg->cmd = OPTEE_MSG_CMD_CANCEL; 591 475 msg_arg->session = session; 592 476 msg_arg->cancel_id = cancel_id; 593 - optee->ops->do_call_with_arg(ctx, shm, offs); 477 + optee->ops->do_call_with_arg(ctx, shm, offs, system_thread); 594 478 595 479 optee_free_msg_arg(ctx, entry, offs); 596 480 return 0; ··· 639 523 mmap_read_unlock(mm); 640 524 641 525 return rc; 526 + } 527 + 528 + static int simple_call_with_arg(struct tee_context *ctx, u32 cmd) 529 + { 530 + struct optee *optee = tee_get_drvdata(ctx->teedev); 531 + struct optee_shm_arg_entry *entry; 532 + struct optee_msg_arg *msg_arg; 533 + struct tee_shm *shm; 534 + u_int offs; 535 + 536 + msg_arg = optee_get_msg_arg(ctx, 0, &entry, &shm, &offs); 537 + if (IS_ERR(msg_arg)) 538 + return PTR_ERR(msg_arg); 539 + 540 + msg_arg->cmd = cmd; 541 + optee->ops->do_call_with_arg(ctx, shm, offs, false); 542 + 543 + optee_free_msg_arg(ctx, entry, offs); 544 + return 0; 545 + } 546 + 547 + int optee_do_bottom_half(struct tee_context *ctx) 548 + { 549 + return simple_call_with_arg(ctx, OPTEE_MSG_CMD_DO_BOTTOM_HALF); 550 + } 551 + 552 + int optee_stop_async_notif(struct tee_context *ctx) 553 + { 554 + return simple_call_with_arg(ctx, OPTEE_MSG_CMD_STOP_ASYNC_NOTIF); 642 555 }
+30 -36
drivers/tee/optee/core.c
··· 15 15 #include <linux/string.h> 16 16 #include <linux/tee_drv.h> 17 17 #include <linux/types.h> 18 - #include <linux/workqueue.h> 19 18 #include "optee_private.h" 20 19 21 20 int optee_pool_op_alloc_helper(struct tee_shm_pool *pool, struct tee_shm *shm, ··· 25 26 size_t num_pages, 26 27 unsigned long start)) 27 28 { 28 - unsigned int order = get_order(size); 29 - struct page *page; 29 + size_t nr_pages = roundup(size, PAGE_SIZE) / PAGE_SIZE; 30 + struct page **pages; 31 + unsigned int i; 30 32 int rc = 0; 31 33 32 34 /* 33 35 * Ignore alignment since this is already going to be page aligned 34 36 * and there's no need for any larger alignment. 35 37 */ 36 - page = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); 37 - if (!page) 38 + shm->kaddr = alloc_pages_exact(nr_pages * PAGE_SIZE, 39 + GFP_KERNEL | __GFP_ZERO); 40 + if (!shm->kaddr) 38 41 return -ENOMEM; 39 42 40 - shm->kaddr = page_address(page); 41 - shm->paddr = page_to_phys(page); 42 - shm->size = PAGE_SIZE << order; 43 + shm->paddr = virt_to_phys(shm->kaddr); 44 + shm->size = nr_pages * PAGE_SIZE; 45 + 46 + pages = kcalloc(nr_pages, sizeof(*pages), GFP_KERNEL); 47 + if (!pages) { 48 + rc = -ENOMEM; 49 + goto err; 50 + } 51 + 52 + for (i = 0; i < nr_pages; i++) 53 + pages[i] = virt_to_page((u8 *)shm->kaddr + i * PAGE_SIZE); 54 + 55 + shm->pages = pages; 56 + shm->num_pages = nr_pages; 43 57 44 58 if (shm_register) { 45 - unsigned int nr_pages = 1 << order, i; 46 - struct page **pages; 47 - 48 - pages = kcalloc(nr_pages, sizeof(*pages), GFP_KERNEL); 49 - if (!pages) { 50 - rc = -ENOMEM; 51 - goto err; 52 - } 53 - 54 - for (i = 0; i < nr_pages; i++) 55 - pages[i] = page + i; 56 - 57 59 rc = shm_register(shm->ctx, shm, pages, nr_pages, 58 60 (unsigned long)shm->kaddr); 59 - kfree(pages); 60 61 if (rc) 61 62 goto err; 62 63 } 63 64 64 65 return 0; 65 - 66 66 err: 67 - free_pages((unsigned long)shm->kaddr, order); 67 + free_pages_exact(shm->kaddr, shm->size); 68 + shm->kaddr = NULL; 68 69 return rc; 69 70 } 70 71 ··· 74 75 { 75 76 if (shm_unregister) 76 77 shm_unregister(shm->ctx, shm); 77 - free_pages((unsigned long)shm->kaddr, get_order(shm->size)); 78 + free_pages_exact(shm->kaddr, shm->size); 78 79 shm->kaddr = NULL; 80 + kfree(shm->pages); 81 + shm->pages = NULL; 79 82 } 80 83 81 84 static void optee_bus_scan(struct work_struct *work) ··· 111 110 112 111 if (!optee->scan_bus_done) { 113 112 INIT_WORK(&optee->scan_bus_work, optee_bus_scan); 114 - optee->scan_bus_wq = create_workqueue("optee_bus_scan"); 115 - if (!optee->scan_bus_wq) { 116 - kfree(ctxdata); 117 - return -ECHILD; 118 - } 119 - queue_work(optee->scan_bus_wq, &optee->scan_bus_work); 113 + schedule_work(&optee->scan_bus_work); 120 114 optee->scan_bus_done = true; 121 115 } 122 116 } ··· 125 129 126 130 static void optee_release_helper(struct tee_context *ctx, 127 131 int (*close_session)(struct tee_context *ctx, 128 - u32 session)) 132 + u32 session, 133 + bool system_thread)) 129 134 { 130 135 struct optee_context_data *ctxdata = ctx->data; 131 136 struct optee_session *sess; ··· 138 141 list_for_each_entry_safe(sess, sess_tmp, &ctxdata->sess_list, 139 142 list_node) { 140 143 list_del(&sess->list_node); 141 - close_session(ctx, sess->session_id); 144 + close_session(ctx, sess->session_id, sess->use_sys_thread); 142 145 kfree(sess); 143 146 } 144 147 kfree(ctxdata); ··· 155 158 struct optee *optee = tee_get_drvdata(ctx->teedev); 156 159 157 160 optee_release_helper(ctx, optee_close_session_helper); 158 - if (optee->scan_bus_wq) { 159 - destroy_workqueue(optee->scan_bus_wq); 160 - optee->scan_bus_wq = NULL; 161 - } 161 + 162 162 optee_supp_release(&optee->supp); 163 163 } 164 164
+98 -9
drivers/tee/optee/ffa_abi.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 - * Copyright (c) 2021, Linaro Limited 3 + * Copyright (c) 2021, 2023 Linaro Limited 4 4 */ 5 5 6 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ··· 528 528 529 529 static int optee_ffa_yielding_call(struct tee_context *ctx, 530 530 struct ffa_send_direct_data *data, 531 - struct optee_msg_arg *rpc_arg) 531 + struct optee_msg_arg *rpc_arg, 532 + bool system_thread) 532 533 { 533 534 struct optee *optee = tee_get_drvdata(ctx->teedev); 534 535 struct ffa_device *ffa_dev = optee->ffa.ffa_dev; ··· 542 541 int rc; 543 542 544 543 /* Initialize waiter */ 545 - optee_cq_wait_init(&optee->call_queue, &w); 544 + optee_cq_wait_init(&optee->call_queue, &w, system_thread); 546 545 while (true) { 547 546 rc = msg_ops->sync_send_receive(ffa_dev, data); 548 547 if (rc) ··· 605 604 * @ctx: calling context 606 605 * @shm: shared memory holding the message to pass to secure world 607 606 * @offs: offset of the message in @shm 607 + * @system_thread: true if caller requests TEE system thread support 608 608 * 609 609 * Does a FF-A call to OP-TEE in secure world and handles eventual resulting 610 610 * Remote Procedure Calls (RPC) from OP-TEE. ··· 614 612 */ 615 613 616 614 static int optee_ffa_do_call_with_arg(struct tee_context *ctx, 617 - struct tee_shm *shm, u_int offs) 615 + struct tee_shm *shm, u_int offs, 616 + bool system_thread) 618 617 { 619 618 struct ffa_send_direct_data data = { 620 619 .data0 = OPTEE_FFA_YIELDING_CALL_WITH_ARG, ··· 645 642 if (IS_ERR(rpc_arg)) 646 643 return PTR_ERR(rpc_arg); 647 644 648 - return optee_ffa_yielding_call(ctx, &data, rpc_arg); 645 + return optee_ffa_yielding_call(ctx, &data, rpc_arg, system_thread); 649 646 } 650 647 651 648 /* ··· 695 692 static bool optee_ffa_exchange_caps(struct ffa_device *ffa_dev, 696 693 const struct ffa_ops *ops, 697 694 u32 *sec_caps, 698 - unsigned int *rpc_param_count) 695 + unsigned int *rpc_param_count, 696 + unsigned int *max_notif_value) 699 697 { 700 698 struct ffa_send_direct_data data = { OPTEE_FFA_EXCHANGE_CAPABILITIES }; 701 699 int rc; ··· 713 709 714 710 *rpc_param_count = (u8)data.data1; 715 711 *sec_caps = data.data2; 712 + if (data.data3) 713 + *max_notif_value = data.data3; 714 + else 715 + *max_notif_value = OPTEE_DEFAULT_MAX_NOTIF_VALUE; 716 716 717 717 return true; 718 + } 719 + 720 + static void notif_callback(int notify_id, void *cb_data) 721 + { 722 + struct optee *optee = cb_data; 723 + 724 + if (notify_id == optee->ffa.bottom_half_value) 725 + optee_do_bottom_half(optee->ctx); 726 + else 727 + optee_notif_send(optee, notify_id); 728 + } 729 + 730 + static int enable_async_notif(struct optee *optee) 731 + { 732 + struct ffa_device *ffa_dev = optee->ffa.ffa_dev; 733 + struct ffa_send_direct_data data = { 734 + .data0 = OPTEE_FFA_ENABLE_ASYNC_NOTIF, 735 + .data1 = optee->ffa.bottom_half_value, 736 + }; 737 + int rc; 738 + 739 + rc = ffa_dev->ops->msg_ops->sync_send_receive(ffa_dev, &data); 740 + if (rc) 741 + return rc; 742 + return data.data0; 718 743 } 719 744 720 745 static void optee_ffa_get_version(struct tee_device *teedev, ··· 808 775 static void optee_ffa_remove(struct ffa_device *ffa_dev) 809 776 { 810 777 struct optee *optee = ffa_dev_get_drvdata(ffa_dev); 778 + u32 bottom_half_id = optee->ffa.bottom_half_value; 811 779 780 + if (bottom_half_id != U32_MAX) 781 + ffa_dev->ops->notifier_ops->notify_relinquish(ffa_dev, 782 + bottom_half_id); 812 783 optee_remove_common(optee); 813 784 814 785 mutex_destroy(&optee->ffa.mutex); ··· 821 784 kfree(optee); 822 785 } 823 786 787 + static int optee_ffa_async_notif_init(struct ffa_device *ffa_dev, 788 + struct optee *optee) 789 + { 790 + bool is_per_vcpu = false; 791 + u32 notif_id = 0; 792 + int rc; 793 + 794 + while (true) { 795 + rc = ffa_dev->ops->notifier_ops->notify_request(ffa_dev, 796 + is_per_vcpu, 797 + notif_callback, 798 + optee, 799 + notif_id); 800 + if (!rc) 801 + break; 802 + /* 803 + * -EACCES means that the notification ID was 804 + * already bound, try the next one as long as we 805 + * haven't reached the max. Any other error is a 806 + * permanent error, so skip asynchronous 807 + * notifications in that case. 808 + */ 809 + if (rc != -EACCES) 810 + return rc; 811 + notif_id++; 812 + if (notif_id >= OPTEE_FFA_MAX_ASYNC_NOTIF_VALUE) 813 + return rc; 814 + } 815 + optee->ffa.bottom_half_value = notif_id; 816 + 817 + rc = enable_async_notif(optee); 818 + if (rc < 0) { 819 + ffa_dev->ops->notifier_ops->notify_relinquish(ffa_dev, 820 + notif_id); 821 + optee->ffa.bottom_half_value = U32_MAX; 822 + } 823 + 824 + return rc; 825 + } 826 + 824 827 static int optee_ffa_probe(struct ffa_device *ffa_dev) 825 828 { 829 + const struct ffa_notifier_ops *notif_ops; 826 830 const struct ffa_ops *ffa_ops; 831 + unsigned int max_notif_value; 827 832 unsigned int rpc_param_count; 828 833 struct tee_shm_pool *pool; 829 834 struct tee_device *teedev; ··· 876 797 int rc; 877 798 878 799 ffa_ops = ffa_dev->ops; 800 + notif_ops = ffa_ops->notifier_ops; 879 801 880 802 if (!optee_ffa_api_is_compatbile(ffa_dev, ffa_ops)) 881 803 return -EINVAL; 882 804 883 805 if (!optee_ffa_exchange_caps(ffa_dev, ffa_ops, &sec_caps, 884 - &rpc_param_count)) 806 + &rpc_param_count, &max_notif_value)) 885 807 return -EINVAL; 886 808 if (sec_caps & OPTEE_FFA_SEC_CAP_ARG_OFFSET) 887 809 arg_cache_flags |= OPTEE_SHM_ARG_SHARED; ··· 900 820 901 821 optee->ops = &optee_ffa_ops; 902 822 optee->ffa.ffa_dev = ffa_dev; 823 + optee->ffa.bottom_half_value = U32_MAX; 903 824 optee->rpc_param_count = rpc_param_count; 904 825 905 826 teedev = tee_device_alloc(&optee_ffa_clnt_desc, NULL, optee->pool, ··· 931 850 if (rc) 932 851 goto err_unreg_supp_teedev; 933 852 mutex_init(&optee->ffa.mutex); 934 - mutex_init(&optee->call_queue.mutex); 935 - INIT_LIST_HEAD(&optee->call_queue.waiters); 853 + optee_cq_init(&optee->call_queue, 0); 936 854 optee_supp_init(&optee->supp); 937 855 optee_shm_arg_cache_init(optee, arg_cache_flags); 938 856 ffa_dev_set_drvdata(ffa_dev, optee); ··· 944 864 rc = optee_notif_init(optee, OPTEE_DEFAULT_MAX_NOTIF_VALUE); 945 865 if (rc) 946 866 goto err_close_ctx; 867 + if (sec_caps & OPTEE_FFA_SEC_CAP_ASYNC_NOTIF) { 868 + rc = optee_ffa_async_notif_init(ffa_dev, optee); 869 + if (rc < 0) 870 + pr_err("Failed to initialize async notifications: %d", 871 + rc); 872 + } 947 873 948 874 rc = optee_enumerate_devices(PTA_CMD_GET_DEVICES); 949 875 if (rc) ··· 960 874 961 875 err_unregister_devices: 962 876 optee_unregister_devices(); 877 + if (optee->ffa.bottom_half_value != U32_MAX) 878 + notif_ops->notify_relinquish(ffa_dev, 879 + optee->ffa.bottom_half_value); 963 880 optee_notif_uninit(optee); 964 881 err_close_ctx: 965 882 teedev_close_context(ctx);
+24 -4
drivers/tee/optee/optee_ffa.h
··· 1 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 2 /* 3 - * Copyright (c) 2019-2021, Linaro Limited 3 + * Copyright (c) 2019-2021, 2023 Linaro Limited 4 4 */ 5 5 6 6 /* ··· 73 73 * 74 74 * Call register usage: 75 75 * w3: Service ID, OPTEE_FFA_EXCHANGE_CAPABILITIES 76 - * w4-w7: Note used (MBZ) 76 + * w4-w7: Not used (MBZ) 77 77 * 78 78 * Return register usage: 79 79 * w3: Error code, 0 on success ··· 82 82 * OPTEE_FFA_YIELDING_CALL_WITH_ARG. 83 83 * Bit[31:8]: Reserved (MBZ) 84 84 * w5: Bitfield of secure world capabilities OPTEE_FFA_SEC_CAP_* below, 85 - * unused bits MBZ. 86 - * w6-w7: Not used (MBZ) 85 + * w6: The maximum secure world notification number 86 + * w7: Not used (MBZ) 87 87 */ 88 88 /* 89 89 * Secure world supports giving an offset into the argument shared memory 90 90 * object, see also OPTEE_FFA_YIELDING_CALL_WITH_ARG 91 91 */ 92 92 #define OPTEE_FFA_SEC_CAP_ARG_OFFSET BIT(0) 93 + /* OP-TEE supports asynchronous notification via FF-A */ 94 + #define OPTEE_FFA_SEC_CAP_ASYNC_NOTIF BIT(1) 93 95 94 96 #define OPTEE_FFA_EXCHANGE_CAPABILITIES OPTEE_FFA_BLOCKING_CALL(2) 95 97 ··· 109 107 * w4-w7: Note used (MBZ) 110 108 */ 111 109 #define OPTEE_FFA_UNREGISTER_SHM OPTEE_FFA_BLOCKING_CALL(3) 110 + 111 + /* 112 + * Inform OP-TEE that the normal world is able to receive asynchronous 113 + * notifications. 114 + * 115 + * Call register usage: 116 + * w3: Service ID, OPTEE_FFA_ENABLE_ASYNC_NOTIF 117 + * w4: Notification value to request bottom half processing, should be 118 + * less than OPTEE_FFA_MAX_ASYNC_NOTIF_VALUE. 119 + * w5-w7: Not used (MBZ) 120 + * 121 + * Return register usage: 122 + * w3: Error code, 0 on success 123 + * w4-w7: Note used (MBZ) 124 + */ 125 + #define OPTEE_FFA_ENABLE_ASYNC_NOTIF OPTEE_FFA_BLOCKING_CALL(5) 126 + 127 + #define OPTEE_FFA_MAX_ASYNC_NOTIF_VALUE 64 112 128 113 129 /* 114 130 * Call with struct optee_msg_arg as argument in the supplied shared memory
+33 -7
drivers/tee/optee/optee_private.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 /* 3 - * Copyright (c) 2015-2021, Linaro Limited 3 + * Copyright (c) 2015-2021, 2023 Linaro Limited 4 4 */ 5 5 6 6 #ifndef OPTEE_PRIVATE_H ··· 40 40 unsigned long, unsigned long, 41 41 struct arm_smccc_res *); 42 42 43 + /* 44 + * struct optee_call_waiter - TEE entry may need to wait for a free TEE thread 45 + * @list_node Reference in waiters list 46 + * @c Waiting completion reference 47 + * @sys_thread True if waiter belongs to a system thread 48 + */ 43 49 struct optee_call_waiter { 44 50 struct list_head list_node; 45 51 struct completion c; 52 + bool sys_thread; 46 53 }; 47 54 55 + /* 56 + * struct optee_call_queue - OP-TEE call queue management 57 + * @mutex Serializes access to this struct 58 + * @waiters List of threads waiting to enter OP-TEE 59 + * @total_thread_count Overall number of thread context in OP-TEE or 0 60 + * @free_thread_count Number of threads context free in OP-TEE 61 + * @sys_thread_req_count Number of registered system thread sessions 62 + */ 48 63 struct optee_call_queue { 49 64 /* Serializes access to this struct */ 50 65 struct mutex mutex; 51 66 struct list_head waiters; 67 + int total_thread_count; 68 + int free_thread_count; 69 + int sys_thread_req_count; 52 70 }; 53 71 54 72 struct optee_notif { ··· 147 129 * struct optee_ffa_data - FFA communication struct 148 130 * @ffa_dev FFA device, contains the destination id, the id of 149 131 * OP-TEE in secure world 150 - * @ffa_ops FFA operations 132 + * @bottom_half_value Notification ID used for bottom half signalling or 133 + * U32_MAX if unused 151 134 * @mutex Serializes access to @global_ids 152 135 * @global_ids FF-A shared memory global handle translation 153 136 */ 154 137 struct optee_ffa { 155 138 struct ffa_device *ffa_dev; 139 + u32 bottom_half_value; 156 140 /* Serializes access to @global_ids */ 157 141 struct mutex mutex; 158 142 struct rhashtable global_ids; ··· 174 154 */ 175 155 struct optee_ops { 176 156 int (*do_call_with_arg)(struct tee_context *ctx, 177 - struct tee_shm *shm_arg, u_int offs); 157 + struct tee_shm *shm_arg, u_int offs, 158 + bool system_thread); 178 159 int (*to_msg_param)(struct optee *optee, 179 160 struct optee_msg_param *msg_params, 180 161 size_t num_params, const struct tee_param *params); ··· 199 178 * @pool: shared memory pool 200 179 * @rpc_param_count: If > 0 number of RPC parameters to make room for 201 180 * @scan_bus_done flag if device registation was already done. 202 - * @scan_bus_wq workqueue to scan optee bus and register optee drivers 203 181 * @scan_bus_work workq to scan optee bus and register optee drivers 204 182 */ 205 183 struct optee { ··· 217 197 struct tee_shm_pool *pool; 218 198 unsigned int rpc_param_count; 219 199 bool scan_bus_done; 220 - struct workqueue_struct *scan_bus_wq; 221 200 struct work_struct scan_bus_work; 222 201 }; 223 202 224 203 struct optee_session { 225 204 struct list_head list_node; 226 205 u32 session_id; 206 + bool use_sys_thread; 227 207 }; 228 208 229 209 struct optee_context_data { ··· 270 250 int optee_open_session(struct tee_context *ctx, 271 251 struct tee_ioctl_open_session_arg *arg, 272 252 struct tee_param *param); 273 - int optee_close_session_helper(struct tee_context *ctx, u32 session); 253 + int optee_system_session(struct tee_context *ctx, u32 session); 254 + int optee_close_session_helper(struct tee_context *ctx, u32 session, 255 + bool system_thread); 274 256 int optee_close_session(struct tee_context *ctx, u32 session); 275 257 int optee_invoke_func(struct tee_context *ctx, struct tee_ioctl_invoke_arg *arg, 276 258 struct tee_param *param); ··· 320 298 mp->u.value.c = p->u.value.c; 321 299 } 322 300 301 + void optee_cq_init(struct optee_call_queue *cq, int thread_count); 323 302 void optee_cq_wait_init(struct optee_call_queue *cq, 324 - struct optee_call_waiter *w); 303 + struct optee_call_waiter *w, bool sys_thread); 325 304 void optee_cq_wait_for_completion(struct optee_call_queue *cq, 326 305 struct optee_call_waiter *w); 327 306 void optee_cq_wait_final(struct optee_call_queue *cq, ··· 345 322 void optee_rpc_cmd_free_suppl(struct tee_context *ctx, struct tee_shm *shm); 346 323 void optee_rpc_cmd(struct tee_context *ctx, struct optee *optee, 347 324 struct optee_msg_arg *arg); 325 + 326 + int optee_do_bottom_half(struct tee_context *ctx); 327 + int optee_stop_async_notif(struct tee_context *ctx); 348 328 349 329 /* 350 330 * Small helpers
+48 -64
drivers/tee/optee/smc_abi.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 - * Copyright (c) 2015-2021, Linaro Limited 3 + * Copyright (c) 2015-2021, 2023 Linaro Limited 4 4 * Copyright (c) 2016, EPAM Systems 5 5 */ 6 6 ··· 283 283 struct optee_call_waiter w; 284 284 285 285 /* We need to retry until secure world isn't busy. */ 286 - optee_cq_wait_init(&optee->call_queue, &w); 286 + optee_cq_wait_init(&optee->call_queue, &w, false); 287 287 while (true) { 288 288 struct arm_smccc_res res; 289 289 ··· 308 308 struct optee_call_waiter w; 309 309 310 310 /* We need to retry until secure world isn't busy. */ 311 - optee_cq_wait_init(&optee->call_queue, &w); 311 + optee_cq_wait_init(&optee->call_queue, &w, false); 312 312 while (true) { 313 313 union { 314 314 struct arm_smccc_res smccc; ··· 507 507 msg_arg->params->u.tmem.buf_ptr = virt_to_phys(pages_list) | 508 508 (tee_shm_get_page_offset(shm) & (OPTEE_MSG_NONCONTIG_PAGE_SIZE - 1)); 509 509 510 - if (optee->ops->do_call_with_arg(ctx, shm_arg, 0) || 510 + if (optee->ops->do_call_with_arg(ctx, shm_arg, 0, false) || 511 511 msg_arg->ret != TEEC_SUCCESS) 512 512 rc = -EINVAL; 513 513 ··· 550 550 msg_arg->params[0].attr = OPTEE_MSG_ATTR_TYPE_RMEM_INPUT; 551 551 msg_arg->params[0].u.rmem.shm_ref = (unsigned long)shm; 552 552 553 - if (optee->ops->do_call_with_arg(ctx, shm_arg, 0) || 553 + if (optee->ops->do_call_with_arg(ctx, shm_arg, 0, false) || 554 554 msg_arg->ret != TEEC_SUCCESS) 555 555 rc = -EINVAL; 556 556 out: ··· 678 678 struct optee_msg_arg *arg, 679 679 struct optee_call_ctx *call_ctx) 680 680 { 681 - phys_addr_t pa; 682 681 struct tee_shm *shm; 683 682 size_t sz; 684 683 size_t n; 684 + struct page **pages; 685 + size_t page_count; 685 686 686 687 arg->ret_origin = TEEC_ORIGIN_COMMS; 687 688 ··· 717 716 return; 718 717 } 719 718 720 - if (tee_shm_get_pa(shm, 0, &pa)) { 721 - arg->ret = TEEC_ERROR_BAD_PARAMETERS; 722 - goto bad; 723 - } 724 - 725 - sz = tee_shm_get_size(shm); 726 - 727 - if (tee_shm_is_dynamic(shm)) { 728 - struct page **pages; 719 + /* 720 + * If there are pages it's dynamically allocated shared memory (not 721 + * from the reserved shared memory pool) and needs to be 722 + * registered. 723 + */ 724 + pages = tee_shm_get_pages(shm, &page_count); 725 + if (pages) { 729 726 u64 *pages_list; 730 - size_t page_num; 731 727 732 - pages = tee_shm_get_pages(shm, &page_num); 733 - if (!pages || !page_num) { 734 - arg->ret = TEEC_ERROR_OUT_OF_MEMORY; 735 - goto bad; 736 - } 737 - 738 - pages_list = optee_allocate_pages_list(page_num); 728 + pages_list = optee_allocate_pages_list(page_count); 739 729 if (!pages_list) { 740 730 arg->ret = TEEC_ERROR_OUT_OF_MEMORY; 741 731 goto bad; 742 732 } 743 733 744 734 call_ctx->pages_list = pages_list; 745 - call_ctx->num_entries = page_num; 735 + call_ctx->num_entries = page_count; 746 736 747 737 arg->params[0].attr = OPTEE_MSG_ATTR_TYPE_TMEM_OUTPUT | 748 738 OPTEE_MSG_ATTR_NONCONTIG; ··· 744 752 arg->params[0].u.tmem.buf_ptr = virt_to_phys(pages_list) | 745 753 (tee_shm_get_page_offset(shm) & 746 754 (OPTEE_MSG_NONCONTIG_PAGE_SIZE - 1)); 747 - arg->params[0].u.tmem.size = tee_shm_get_size(shm); 748 - arg->params[0].u.tmem.shm_ref = (unsigned long)shm; 749 755 750 - optee_fill_pages_list(pages_list, pages, page_num, 756 + optee_fill_pages_list(pages_list, pages, page_count, 751 757 tee_shm_get_page_offset(shm)); 752 758 } else { 759 + phys_addr_t pa; 760 + 761 + if (tee_shm_get_pa(shm, 0, &pa)) { 762 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 763 + goto bad; 764 + } 765 + 753 766 arg->params[0].attr = OPTEE_MSG_ATTR_TYPE_TMEM_OUTPUT; 754 767 arg->params[0].u.tmem.buf_ptr = pa; 755 - arg->params[0].u.tmem.size = sz; 756 - arg->params[0].u.tmem.shm_ref = (unsigned long)shm; 757 768 } 769 + arg->params[0].u.tmem.size = tee_shm_get_size(shm); 770 + arg->params[0].u.tmem.shm_ref = (unsigned long)shm; 758 771 759 772 arg->ret = TEEC_SUCCESS; 760 773 return; ··· 803 806 /** 804 807 * optee_handle_rpc() - handle RPC from secure world 805 808 * @ctx: context doing the RPC 809 + * @rpc_arg: pointer to RPC arguments if any, or NULL if none 806 810 * @param: value of registers for the RPC 807 811 * @call_ctx: call context. Preserved during one OP-TEE invocation 808 812 * ··· 876 878 * @ctx: calling context 877 879 * @shm: shared memory holding the message to pass to secure world 878 880 * @offs: offset of the message in @shm 881 + * @system_thread: true if caller requests TEE system thread support 879 882 * 880 883 * Does and SMC to OP-TEE in secure world and handles eventual resulting 881 884 * Remote Procedure Calls (RPC) from OP-TEE. ··· 884 885 * Returns return code from secure world, 0 is OK 885 886 */ 886 887 static int optee_smc_do_call_with_arg(struct tee_context *ctx, 887 - struct tee_shm *shm, u_int offs) 888 + struct tee_shm *shm, u_int offs, 889 + bool system_thread) 888 890 { 889 891 struct optee *optee = tee_get_drvdata(ctx->teedev); 890 892 struct optee_call_waiter w; ··· 926 926 reg_pair_from_64(&param.a1, &param.a2, parg); 927 927 } 928 928 /* Initialize waiter */ 929 - optee_cq_wait_init(&optee->call_queue, &w); 929 + optee_cq_wait_init(&optee->call_queue, &w, system_thread); 930 930 while (true) { 931 931 struct arm_smccc_res res; 932 932 ··· 963 963 optee_cq_wait_final(&optee->call_queue, &w); 964 964 965 965 return rc; 966 - } 967 - 968 - static int simple_call_with_arg(struct tee_context *ctx, u32 cmd) 969 - { 970 - struct optee_shm_arg_entry *entry; 971 - struct optee_msg_arg *msg_arg; 972 - struct tee_shm *shm; 973 - u_int offs; 974 - 975 - msg_arg = optee_get_msg_arg(ctx, 0, &entry, &shm, &offs); 976 - if (IS_ERR(msg_arg)) 977 - return PTR_ERR(msg_arg); 978 - 979 - msg_arg->cmd = cmd; 980 - optee_smc_do_call_with_arg(ctx, shm, offs); 981 - 982 - optee_free_msg_arg(ctx, entry, offs); 983 - return 0; 984 - } 985 - 986 - static int optee_smc_do_bottom_half(struct tee_context *ctx) 987 - { 988 - return simple_call_with_arg(ctx, OPTEE_MSG_CMD_DO_BOTTOM_HALF); 989 - } 990 - 991 - static int optee_smc_stop_async_notif(struct tee_context *ctx) 992 - { 993 - return simple_call_with_arg(ctx, OPTEE_MSG_CMD_STOP_ASYNC_NOTIF); 994 966 } 995 967 996 968 /* ··· 1020 1048 { 1021 1049 struct optee *optee = dev_id; 1022 1050 1023 - optee_smc_do_bottom_half(optee->ctx); 1051 + optee_do_bottom_half(optee->ctx); 1024 1052 1025 1053 return IRQ_HANDLED; 1026 1054 } ··· 1058 1086 notif_pcpu_work); 1059 1087 struct optee *optee = container_of(optee_smc, struct optee, smc); 1060 1088 1061 - optee_smc_do_bottom_half(optee->ctx); 1089 + optee_do_bottom_half(optee->ctx); 1062 1090 } 1063 1091 1064 1092 static int init_pcpu_irq(struct optee *optee, u_int irq) ··· 1130 1158 static void optee_smc_notif_uninit_irq(struct optee *optee) 1131 1159 { 1132 1160 if (optee->smc.sec_caps & OPTEE_SMC_SEC_CAP_ASYNC_NOTIF) { 1133 - optee_smc_stop_async_notif(optee->ctx); 1161 + optee_stop_async_notif(optee->ctx); 1134 1162 if (optee->smc.notif_irq) { 1135 1163 if (irq_is_percpu_devid(optee->smc.notif_irq)) 1136 1164 uninit_pcpu_irq(optee); ··· 1182 1210 .release = optee_release, 1183 1211 .open_session = optee_open_session, 1184 1212 .close_session = optee_close_session, 1213 + .system_session = optee_system_session, 1185 1214 .invoke_func = optee_invoke_func, 1186 1215 .cancel_req = optee_cancel_req, 1187 1216 .shm_register = optee_shm_register, ··· 1328 1355 *rpc_param_count = 0; 1329 1356 1330 1357 return true; 1358 + } 1359 + 1360 + static unsigned int optee_msg_get_thread_count(optee_invoke_fn *invoke_fn) 1361 + { 1362 + struct arm_smccc_res res; 1363 + 1364 + invoke_fn(OPTEE_SMC_GET_THREAD_COUNT, 0, 0, 0, 0, 0, 0, 0, &res); 1365 + if (res.a0) 1366 + return 0; 1367 + return res.a1; 1331 1368 } 1332 1369 1333 1370 static struct tee_shm_pool * ··· 1592 1609 struct optee *optee = NULL; 1593 1610 void *memremaped_shm = NULL; 1594 1611 unsigned int rpc_param_count; 1612 + unsigned int thread_count; 1595 1613 struct tee_device *teedev; 1596 1614 struct tee_context *ctx; 1597 1615 u32 max_notif_value; ··· 1620 1636 return -EINVAL; 1621 1637 } 1622 1638 1639 + thread_count = optee_msg_get_thread_count(invoke_fn); 1623 1640 if (!optee_msg_exchange_capabilities(invoke_fn, &sec_caps, 1624 1641 &max_notif_value, 1625 1642 &rpc_param_count)) { ··· 1710 1725 if (rc) 1711 1726 goto err_unreg_supp_teedev; 1712 1727 1713 - mutex_init(&optee->call_queue.mutex); 1714 - INIT_LIST_HEAD(&optee->call_queue.waiters); 1728 + optee_cq_init(&optee->call_queue, thread_count); 1715 1729 optee_supp_init(&optee->supp); 1716 1730 optee->smc.memremaped_shm = memremaped_shm; 1717 1731 optee->pool = pool;
+8
drivers/tee/tee_core.c
··· 1173 1173 } 1174 1174 EXPORT_SYMBOL_GPL(tee_client_close_session); 1175 1175 1176 + int tee_client_system_session(struct tee_context *ctx, u32 session) 1177 + { 1178 + if (!ctx->teedev->desc->ops->system_session) 1179 + return -EINVAL; 1180 + return ctx->teedev->desc->ops->system_session(ctx, session); 1181 + } 1182 + EXPORT_SYMBOL_GPL(tee_client_system_session); 1183 + 1176 1184 int tee_client_invoke_func(struct tee_context *ctx, 1177 1185 struct tee_ioctl_invoke_arg *arg, 1178 1186 struct tee_param *param)
+42 -36
drivers/tee/tee_shm.c
··· 22 22 put_page(pages[n]); 23 23 } 24 24 25 - static int shm_get_kernel_pages(unsigned long start, size_t page_count, 26 - struct page **pages) 25 + static void shm_get_kernel_pages(struct page **pages, size_t page_count) 27 26 { 28 - struct page *page; 29 27 size_t n; 30 28 31 - if (WARN_ON_ONCE(is_vmalloc_addr((void *)start) || 32 - is_kmap_addr((void *)start))) 33 - return -EINVAL; 34 - 35 - page = virt_to_page((void *)start); 36 - for (n = 0; n < page_count; n++) { 37 - pages[n] = page + n; 29 + for (n = 0; n < page_count; n++) 38 30 get_page(pages[n]); 39 - } 40 - 41 - return page_count; 42 31 } 43 32 44 33 static void release_registered_pages(struct tee_shm *shm) ··· 203 214 EXPORT_SYMBOL_GPL(tee_shm_alloc_priv_buf); 204 215 205 216 static struct tee_shm * 206 - register_shm_helper(struct tee_context *ctx, unsigned long addr, 207 - size_t length, u32 flags, int id) 217 + register_shm_helper(struct tee_context *ctx, struct iov_iter *iter, u32 flags, 218 + int id) 208 219 { 209 220 struct tee_device *teedev = ctx->teedev; 210 221 struct tee_shm *shm; 211 - unsigned long start; 212 - size_t num_pages; 222 + unsigned long start, addr; 223 + size_t num_pages, off; 224 + ssize_t len; 213 225 void *ret; 214 226 int rc; 215 227 ··· 235 245 shm->flags = flags; 236 246 shm->ctx = ctx; 237 247 shm->id = id; 238 - addr = untagged_addr(addr); 248 + addr = untagged_addr((unsigned long)iter_iov_addr(iter)); 239 249 start = rounddown(addr, PAGE_SIZE); 240 - shm->offset = addr - start; 241 - shm->size = length; 242 - num_pages = (roundup(addr + length, PAGE_SIZE) - start) / PAGE_SIZE; 250 + num_pages = iov_iter_npages(iter, INT_MAX); 251 + if (!num_pages) { 252 + ret = ERR_PTR(-ENOMEM); 253 + goto err_ctx_put; 254 + } 255 + 243 256 shm->pages = kcalloc(num_pages, sizeof(*shm->pages), GFP_KERNEL); 244 257 if (!shm->pages) { 245 258 ret = ERR_PTR(-ENOMEM); 246 259 goto err_free_shm; 247 260 } 248 261 249 - if (flags & TEE_SHM_USER_MAPPED) 250 - rc = pin_user_pages_fast(start, num_pages, FOLL_WRITE, 251 - shm->pages); 252 - else 253 - rc = shm_get_kernel_pages(start, num_pages, shm->pages); 254 - if (rc > 0) 255 - shm->num_pages = rc; 256 - if (rc != num_pages) { 257 - if (rc >= 0) 258 - rc = -ENOMEM; 259 - ret = ERR_PTR(rc); 260 - goto err_put_shm_pages; 262 + len = iov_iter_extract_pages(iter, &shm->pages, LONG_MAX, num_pages, 0, 263 + &off); 264 + if (unlikely(len <= 0)) { 265 + ret = len ? ERR_PTR(len) : ERR_PTR(-ENOMEM); 266 + goto err_free_shm_pages; 261 267 } 268 + 269 + /* 270 + * iov_iter_extract_kvec_pages does not get reference on the pages, 271 + * get a reference on them. 272 + */ 273 + if (iov_iter_is_kvec(iter)) 274 + shm_get_kernel_pages(shm->pages, num_pages); 275 + 276 + shm->offset = off; 277 + shm->size = len; 278 + shm->num_pages = num_pages; 262 279 263 280 rc = teedev->desc->ops->shm_register(ctx, shm, shm->pages, 264 281 shm->num_pages, start); ··· 276 279 277 280 return shm; 278 281 err_put_shm_pages: 279 - if (flags & TEE_SHM_USER_MAPPED) 282 + if (!iov_iter_is_kvec(iter)) 280 283 unpin_user_pages(shm->pages, shm->num_pages); 281 284 else 282 285 shm_put_kernel_pages(shm->pages, shm->num_pages); 286 + err_free_shm_pages: 283 287 kfree(shm->pages); 284 288 err_free_shm: 285 289 kfree(shm); ··· 305 307 u32 flags = TEE_SHM_USER_MAPPED | TEE_SHM_DYNAMIC; 306 308 struct tee_device *teedev = ctx->teedev; 307 309 struct tee_shm *shm; 310 + struct iov_iter iter; 308 311 void *ret; 309 312 int id; 310 313 ··· 318 319 if (id < 0) 319 320 return ERR_PTR(id); 320 321 321 - shm = register_shm_helper(ctx, addr, length, flags, id); 322 + iov_iter_ubuf(&iter, ITER_DEST, (void __user *)addr, length); 323 + shm = register_shm_helper(ctx, &iter, flags, id); 322 324 if (IS_ERR(shm)) { 323 325 mutex_lock(&teedev->mutex); 324 326 idr_remove(&teedev->idr, id); ··· 352 352 void *addr, size_t length) 353 353 { 354 354 u32 flags = TEE_SHM_DYNAMIC; 355 + struct kvec kvec; 356 + struct iov_iter iter; 355 357 356 - return register_shm_helper(ctx, (unsigned long)addr, length, flags, -1); 358 + kvec.iov_base = addr; 359 + kvec.iov_len = length; 360 + iov_iter_kvec(&iter, ITER_DEST, &kvec, 1, length); 361 + 362 + return register_shm_helper(ctx, &iter, flags, -1); 357 363 } 358 364 EXPORT_SYMBOL_GPL(tee_shm_register_kernel_buf); 359 365
+16
drivers/tty/serial/samsung_tty.c
··· 2492 2492 .fifosize = { 256, 64, 64, 64 }, 2493 2493 }; 2494 2494 2495 + /* 2496 + * Common drv_data struct for platforms that specify samsung,uart-fifosize in 2497 + * device tree. 2498 + */ 2499 + static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = { 2500 + EXYNOS_COMMON_SERIAL_DRV_DATA(), 2501 + .fifosize = { 0 }, 2502 + }; 2503 + 2495 2504 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) 2496 2505 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) 2497 2506 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) 2507 + #define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) 2498 2508 2499 2509 #else 2500 2510 #define EXYNOS4210_SERIAL_DRV_DATA NULL 2501 2511 #define EXYNOS5433_SERIAL_DRV_DATA NULL 2502 2512 #define EXYNOS850_SERIAL_DRV_DATA NULL 2513 + #define EXYNOS_FIFOSZDT_DRV_DATA NULL 2503 2514 #endif 2504 2515 2505 2516 #ifdef CONFIG_ARCH_APPLE ··· 2594 2583 }, { 2595 2584 .name = "artpec8-uart", 2596 2585 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, 2586 + }, { 2587 + .name = "gs101-uart", 2588 + .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, 2597 2589 }, 2598 2590 { }, 2599 2591 }; ··· 2618 2604 .data = EXYNOS850_SERIAL_DRV_DATA }, 2619 2605 { .compatible = "axis,artpec8-uart", 2620 2606 .data = ARTPEC8_SERIAL_DRV_DATA }, 2607 + { .compatible = "google,gs101-uart", 2608 + .data = EXYNOS_FIFOSZDT_DRV_DATA }, 2621 2609 {}, 2622 2610 }; 2623 2611 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
+3
drivers/usb/typec/ucsi/ucsi.c
··· 578 578 u64 command; 579 579 int ret; 580 580 581 + if (ucsi->quirks & UCSI_NO_PARTNER_PDOS) 582 + return 0; 583 + 581 584 command = UCSI_COMMAND(UCSI_GET_PDOS) | UCSI_CONNECTOR_NUMBER(con->num); 582 585 command |= UCSI_GET_PDOS_PARTNER_PDO(is_partner); 583 586 command |= UCSI_GET_PDOS_PDO_OFFSET(offset);
+3
drivers/usb/typec/ucsi/ucsi.h
··· 317 317 #define EVENT_PENDING 0 318 318 #define COMMAND_PENDING 1 319 319 #define ACK_PENDING 2 320 + 321 + unsigned long quirks; 322 + #define UCSI_NO_PARTNER_PDOS BIT(0) /* Don't read partner's PDOs */ 320 323 }; 321 324 322 325 #define UCSI_MAX_SVID 5
+13
drivers/usb/typec/ucsi/ucsi_glink.c
··· 6 6 #include <linux/auxiliary_bus.h> 7 7 #include <linux/module.h> 8 8 #include <linux/mutex.h> 9 + #include <linux/of_device.h> 9 10 #include <linux/property.h> 10 11 #include <linux/soc/qcom/pdr.h> 11 12 #include <linux/usb/typec_mux.h> ··· 297 296 mutex_unlock(&ucsi->lock); 298 297 } 299 298 299 + static const struct of_device_id pmic_glink_ucsi_of_quirks[] = { 300 + { .compatible = "qcom,sc8180x-pmic-glink", .data = (void *)UCSI_NO_PARTNER_PDOS, }, 301 + { .compatible = "qcom,sc8280xp-pmic-glink", .data = (void *)UCSI_NO_PARTNER_PDOS, }, 302 + { .compatible = "qcom,sm8350-pmic-glink", .data = (void *)UCSI_NO_PARTNER_PDOS, }, 303 + {} 304 + }; 305 + 300 306 static int pmic_glink_ucsi_probe(struct auxiliary_device *adev, 301 307 const struct auxiliary_device_id *id) 302 308 { 303 309 struct pmic_glink_ucsi *ucsi; 304 310 struct device *dev = &adev->dev; 311 + const struct of_device_id *match; 305 312 struct fwnode_handle *fwnode; 306 313 int ret; 307 314 ··· 335 326 ret = devm_add_action_or_reset(dev, pmic_glink_ucsi_destroy, ucsi); 336 327 if (ret) 337 328 return ret; 329 + 330 + match = of_match_device(pmic_glink_ucsi_of_quirks, dev->parent); 331 + if (match) 332 + ucsi->ucsi->quirks = (unsigned long)match->data; 338 333 339 334 ucsi_set_drvdata(ucsi->ucsi, ucsi); 340 335
+73 -12
drivers/watchdog/s3c2410_wdt.c
··· 9 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> 10 10 */ 11 11 12 + #include <linux/bits.h> 12 13 #include <linux/module.h> 13 14 #include <linux/moduleparam.h> 14 15 #include <linux/types.h> ··· 35 34 36 35 #define S3C2410_WTCNT_MAXCNT 0xffff 37 36 38 - #define S3C2410_WTCON_RSTEN (1 << 0) 39 - #define S3C2410_WTCON_INTEN (1 << 2) 40 - #define S3C2410_WTCON_ENABLE (1 << 5) 37 + #define S3C2410_WTCON_RSTEN BIT(0) 38 + #define S3C2410_WTCON_INTEN BIT(2) 39 + #define S3C2410_WTCON_ENABLE BIT(5) 40 + #define S3C2410_WTCON_DBGACK_MASK BIT(16) 41 41 42 42 #define S3C2410_WTCON_DIV16 (0 << 3) 43 43 #define S3C2410_WTCON_DIV32 (1 << 3) ··· 68 66 #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 69 67 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 70 68 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 69 + 70 + #define GS_CLUSTER0_NONCPU_OUT 0x1220 71 + #define GS_CLUSTER1_NONCPU_OUT 0x1420 72 + #define GS_CLUSTER0_NONCPU_INT_EN 0x1244 73 + #define GS_CLUSTER1_NONCPU_INT_EN 0x1444 74 + #define GS_CLUSTER2_NONCPU_INT_EN 0x1644 75 + #define GS_RST_STAT_REG_OFFSET 0x3B44 71 76 72 77 /** 73 78 * DOC: Quirk flags for different Samsung watchdog IP-cores ··· 109 100 * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) 110 101 * with "watchdog counter enable" bit. That bit should be set to make watchdog 111 102 * counter running. 103 + * 104 + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the 105 + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. 106 + * Debug mode is determined by the DBGACK CPU signal. 112 107 */ 113 - #define QUIRK_HAS_WTCLRINT_REG (1 << 0) 114 - #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) 115 - #define QUIRK_HAS_PMU_RST_STAT (1 << 2) 116 - #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) 117 - #define QUIRK_HAS_PMU_CNT_EN (1 << 4) 108 + #define QUIRK_HAS_WTCLRINT_REG BIT(0) 109 + #define QUIRK_HAS_PMU_MASK_RESET BIT(1) 110 + #define QUIRK_HAS_PMU_RST_STAT BIT(2) 111 + #define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3) 112 + #define QUIRK_HAS_PMU_CNT_EN BIT(4) 113 + #define QUIRK_HAS_DBGACK_BIT BIT(5) 118 114 119 115 /* These quirks require that we have a PMU register map */ 120 116 #define QUIRKS_HAVE_PMUREG \ ··· 277 263 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 278 264 }; 279 265 266 + static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { 267 + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, 268 + .mask_bit = 2, 269 + .mask_reset_inv = true, 270 + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, 271 + .rst_stat_bit = 0, 272 + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, 273 + .cnt_en_bit = 8, 274 + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | 275 + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | 276 + QUIRK_HAS_DBGACK_BIT, 277 + }; 278 + 279 + static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { 280 + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, 281 + .mask_bit = 2, 282 + .mask_reset_inv = true, 283 + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, 284 + .rst_stat_bit = 1, 285 + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, 286 + .cnt_en_bit = 7, 287 + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | 288 + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | 289 + QUIRK_HAS_DBGACK_BIT, 290 + }; 291 + 280 292 static const struct of_device_id s3c2410_wdt_match[] = { 293 + { .compatible = "google,gs101-wdt", 294 + .data = &drv_data_gs101_cl0 }, 281 295 { .compatible = "samsung,s3c2410-wdt", 282 296 .data = &drv_data_s3c2410 }, 283 297 { .compatible = "samsung,s3c6410-wdt", ··· 415 373 } 416 374 417 375 return 0; 376 + } 377 + 378 + /* Disable watchdog outputs if CPU is in debug mode */ 379 + static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) 380 + { 381 + unsigned long wtcon; 382 + 383 + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) 384 + return; 385 + 386 + wtcon = readl(wdt->reg_base + S3C2410_WTCON); 387 + wtcon |= S3C2410_WTCON_DBGACK_MASK; 388 + writel(wtcon, wdt->reg_base + S3C2410_WTCON); 418 389 } 419 390 420 391 static int s3c2410wdt_keepalive(struct watchdog_device *wdd) ··· 642 587 #ifdef CONFIG_OF 643 588 /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ 644 589 if (variant == &drv_data_exynos850_cl0 || 645 - variant == &drv_data_exynosautov9_cl0) { 590 + variant == &drv_data_exynosautov9_cl0 || 591 + variant == &drv_data_gs101_cl0) { 646 592 u32 index; 647 593 int err; 648 594 ··· 656 600 case 0: 657 601 break; 658 602 case 1: 659 - variant = (variant == &drv_data_exynos850_cl0) ? 660 - &drv_data_exynos850_cl1 : 661 - &drv_data_exynosautov9_cl1; 603 + if (variant == &drv_data_exynos850_cl0) 604 + variant = &drv_data_exynos850_cl1; 605 + else if (variant == &drv_data_exynosautov9_cl0) 606 + variant = &drv_data_exynosautov9_cl1; 607 + else if (variant == &drv_data_gs101_cl0) 608 + variant = &drv_data_gs101_cl1; 662 609 break; 663 610 default: 664 611 return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index); ··· 758 699 759 700 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); 760 701 wdt->wdt_device.parent = dev; 702 + 703 + s3c2410wdt_mask_dbgack(wdt); 761 704 762 705 /* 763 706 * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
+1
include/dt-bindings/arm/qcom,ids.h
··· 255 255 #define QCOM_ID_SA8775P 534 256 256 #define QCOM_ID_QRU1000 539 257 257 #define QCOM_ID_QDU1000 545 258 + #define QCOM_ID_SM8650 557 258 259 #define QCOM_ID_SM4450 568 259 260 #define QCOM_ID_QDU1010 587 260 261 #define QCOM_ID_QRU1032 588
+74 -74
include/dt-bindings/clock/google,gs101.h
··· 59 59 #define CLK_MOUT_CMU_HSI0_BUS 45 60 60 #define CLK_MOUT_CMU_HSI0_DPGTC 46 61 61 #define CLK_MOUT_CMU_HSI0_USB31DRD 47 62 - #define CLK_MOUT_CMU_HSI0_USBDPDGB 48 62 + #define CLK_MOUT_CMU_HSI0_USBDPDBG 48 63 63 #define CLK_MOUT_CMU_HSI1_BUS 49 64 64 #define CLK_MOUT_CMU_HSI1_PCIE 50 65 65 #define CLK_MOUT_CMU_HSI2_BUS 51 ··· 166 166 #define CLK_DOUT_CMU_SHARED3_DIV2 150 167 167 168 168 /* CMU_TOP Gates */ 169 - #define CLK_GOUT_BUS0_BOOST 151 170 - #define CLK_GOUT_BUS1_BOOST 152 171 - #define CLK_GOUT_BUS2_BOOST 153 172 - #define CLK_GOUT_CORE_BOOST 154 173 - #define CLK_GOUT_CPUCL0_BOOST 155 174 - #define CLK_GOUT_CPUCL1_BOOST 156 175 - #define CLK_GOUT_CPUCL2_BOOST 157 176 - #define CLK_GOUT_MIF_BOOST 158 177 - #define CLK_GOUT_MIF_SWITCH 159 178 - #define CLK_GOUT_BO_BUS 160 179 - #define CLK_GOUT_BUS0_BUS 161 180 - #define CLK_GOUT_BUS1_BUS 162 181 - #define CLK_GOUT_BUS2_BUS 163 182 - #define CLK_GOUT_CIS_CLK0 164 183 - #define CLK_GOUT_CIS_CLK1 165 184 - #define CLK_GOUT_CIS_CLK2 167 185 - #define CLK_GOUT_CIS_CLK3 168 186 - #define CLK_GOUT_CIS_CLK4 169 187 - #define CLK_GOUT_CIS_CLK5 170 188 - #define CLK_GOUT_CIS_CLK6 171 189 - #define CLK_GOUT_CIS_CLK7 172 190 - #define CLK_GOUT_CMU_BOOST 173 191 - #define CLK_GOUT_CORE_BUS 174 192 - #define CLK_GOUT_CPUCL0_DBG 175 193 - #define CLK_GOUT_CPUCL0_SWITCH 176 194 - #define CLK_GOUT_CPUCL1_SWITCH 177 195 - #define CLK_GOUT_CPUCL2_SWITCH 178 196 - #define CLK_GOUT_CSIS_BUS 179 197 - #define CLK_GOUT_DISP_BUS 180 198 - #define CLK_GOUT_DNS_BUS 181 199 - #define CLK_GOUT_DPU_BUS 182 200 - #define CLK_GOUT_EH_BUS 183 201 - #define CLK_GOUT_G2D_G2D 184 202 - #define CLK_GOUT_G2D_MSCL 185 203 - #define CLK_GOUT_G3AA_G3AA 186 204 - #define CLK_GOUT_G3D_BUSD 187 205 - #define CLK_GOUT_G3D_GLB 188 206 - #define CLK_GOUT_G3D_SWITCH 189 207 - #define CLK_GOUT_GDC_GDC0 190 208 - #define CLK_GOUT_GDC_GDC1 191 209 - #define CLK_GOUT_GDC_SCSC 192 210 - #define CLK_GOUT_CMU_HPM 193 211 - #define CLK_GOUT_HSI0_BUS 194 212 - #define CLK_GOUT_HSI0_DPGTC 195 213 - #define CLK_GOUT_HSI0_USB31DRD 196 214 - #define CLK_GOUT_HSI0_USBDPDGB 197 215 - #define CLK_GOUT_HSI1_BUS 198 216 - #define CLK_GOUT_HSI1_PCIE 199 217 - #define CLK_GOUT_HSI2_BUS 200 218 - #define CLK_GOUT_HSI2_MMC_CARD 201 219 - #define CLK_GOUT_HSI2_PCIE 202 220 - #define CLK_GOUT_HSI2_UFS_EMBD 203 221 - #define CLK_GOUT_IPP_BUS 204 222 - #define CLK_GOUT_ITP_BUS 205 223 - #define CLK_GOUT_MCSC_ITSC 206 224 - #define CLK_GOUT_MCSC_MCSC 207 225 - #define CLK_GOUT_MFC_MFC 208 226 - #define CLK_GOUT_MIF_BUSP 209 227 - #define CLK_GOUT_MISC_BUS 210 228 - #define CLK_GOUT_MISC_SSS 211 229 - #define CLK_GOUT_PDP_BUS 212 230 - #define CLK_GOUT_PDP_VRA 213 231 - #define CLK_GOUT_G3AA 214 232 - #define CLK_GOUT_PERIC0_BUS 215 233 - #define CLK_GOUT_PERIC0_IP 216 234 - #define CLK_GOUT_PERIC1_BUS 217 235 - #define CLK_GOUT_PERIC1_IP 218 236 - #define CLK_GOUT_TNR_BUS 219 237 - #define CLK_GOUT_TOP_CMUREF 220 238 - #define CLK_GOUT_TPU_BUS 221 239 - #define CLK_GOUT_TPU_TPU 222 240 - #define CLK_GOUT_TPU_TPUCTL 223 241 - #define CLK_GOUT_TPU_UART 224 169 + #define CLK_GOUT_CMU_BUS0_BOOST 151 170 + #define CLK_GOUT_CMU_BUS1_BOOST 152 171 + #define CLK_GOUT_CMU_BUS2_BOOST 153 172 + #define CLK_GOUT_CMU_CORE_BOOST 154 173 + #define CLK_GOUT_CMU_CPUCL0_BOOST 155 174 + #define CLK_GOUT_CMU_CPUCL1_BOOST 156 175 + #define CLK_GOUT_CMU_CPUCL2_BOOST 157 176 + #define CLK_GOUT_CMU_MIF_BOOST 158 177 + #define CLK_GOUT_CMU_MIF_SWITCH 159 178 + #define CLK_GOUT_CMU_BO_BUS 160 179 + #define CLK_GOUT_CMU_BUS0_BUS 161 180 + #define CLK_GOUT_CMU_BUS1_BUS 162 181 + #define CLK_GOUT_CMU_BUS2_BUS 163 182 + #define CLK_GOUT_CMU_CIS_CLK0 164 183 + #define CLK_GOUT_CMU_CIS_CLK1 165 184 + #define CLK_GOUT_CMU_CIS_CLK2 166 185 + #define CLK_GOUT_CMU_CIS_CLK3 167 186 + #define CLK_GOUT_CMU_CIS_CLK4 168 187 + #define CLK_GOUT_CMU_CIS_CLK5 169 188 + #define CLK_GOUT_CMU_CIS_CLK6 170 189 + #define CLK_GOUT_CMU_CIS_CLK7 171 190 + #define CLK_GOUT_CMU_CMU_BOOST 172 191 + #define CLK_GOUT_CMU_CORE_BUS 173 192 + #define CLK_GOUT_CMU_CPUCL0_DBG 174 193 + #define CLK_GOUT_CMU_CPUCL0_SWITCH 175 194 + #define CLK_GOUT_CMU_CPUCL1_SWITCH 176 195 + #define CLK_GOUT_CMU_CPUCL2_SWITCH 177 196 + #define CLK_GOUT_CMU_CSIS_BUS 178 197 + #define CLK_GOUT_CMU_DISP_BUS 179 198 + #define CLK_GOUT_CMU_DNS_BUS 180 199 + #define CLK_GOUT_CMU_DPU_BUS 181 200 + #define CLK_GOUT_CMU_EH_BUS 182 201 + #define CLK_GOUT_CMU_G2D_G2D 183 202 + #define CLK_GOUT_CMU_G2D_MSCL 184 203 + #define CLK_GOUT_CMU_G3AA_G3AA 185 204 + #define CLK_GOUT_CMU_G3D_BUSD 186 205 + #define CLK_GOUT_CMU_G3D_GLB 187 206 + #define CLK_GOUT_CMU_G3D_SWITCH 188 207 + #define CLK_GOUT_CMU_GDC_GDC0 189 208 + #define CLK_GOUT_CMU_GDC_GDC1 190 209 + #define CLK_GOUT_CMU_GDC_SCSC 191 210 + #define CLK_GOUT_CMU_HPM 192 211 + #define CLK_GOUT_CMU_HSI0_BUS 193 212 + #define CLK_GOUT_CMU_HSI0_DPGTC 194 213 + #define CLK_GOUT_CMU_HSI0_USB31DRD 195 214 + #define CLK_GOUT_CMU_HSI0_USBDPDBG 196 215 + #define CLK_GOUT_CMU_HSI1_BUS 197 216 + #define CLK_GOUT_CMU_HSI1_PCIE 198 217 + #define CLK_GOUT_CMU_HSI2_BUS 199 218 + #define CLK_GOUT_CMU_HSI2_MMC_CARD 200 219 + #define CLK_GOUT_CMU_HSI2_PCIE 201 220 + #define CLK_GOUT_CMU_HSI2_UFS_EMBD 202 221 + #define CLK_GOUT_CMU_IPP_BUS 203 222 + #define CLK_GOUT_CMU_ITP_BUS 204 223 + #define CLK_GOUT_CMU_MCSC_ITSC 205 224 + #define CLK_GOUT_CMU_MCSC_MCSC 206 225 + #define CLK_GOUT_CMU_MFC_MFC 207 226 + #define CLK_GOUT_CMU_MIF_BUSP 208 227 + #define CLK_GOUT_CMU_MISC_BUS 209 228 + #define CLK_GOUT_CMU_MISC_SSS 210 229 + #define CLK_GOUT_CMU_PDP_BUS 211 230 + #define CLK_GOUT_CMU_PDP_VRA 212 231 + #define CLK_GOUT_CMU_G3AA 213 232 + #define CLK_GOUT_CMU_PERIC0_BUS 214 233 + #define CLK_GOUT_CMU_PERIC0_IP 215 234 + #define CLK_GOUT_CMU_PERIC1_BUS 216 235 + #define CLK_GOUT_CMU_PERIC1_IP 217 236 + #define CLK_GOUT_CMU_TNR_BUS 218 237 + #define CLK_GOUT_CMU_TOP_CMUREF 219 238 + #define CLK_GOUT_CMU_TPU_BUS 220 239 + #define CLK_GOUT_CMU_TPU_TPU 221 240 + #define CLK_GOUT_CMU_TPU_TPUCTL 222 241 + #define CLK_GOUT_CMU_TPU_UART 223 242 242 243 243 /* CMU_APM */ 244 244 #define CLK_MOUT_APM_FUNC 1
+119
include/dt-bindings/reset/amlogic,c3-reset.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 + /* 3 + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H 7 + #define _DT_BINDINGS_AMLOGIC_C3_RESET_H 8 + 9 + /* RESET0 */ 10 + /* 0-3 */ 11 + #define RESET_USBCTRL 4 12 + /* 5-7 */ 13 + #define RESET_USBPHY20 8 14 + /* 9 */ 15 + #define RESET_USB2DRD 10 16 + #define RESET_MIPI_DSI_HOST 11 17 + #define RESET_MIPI_DSI_PHY 12 18 + /* 13-20 */ 19 + #define RESET_GE2D 21 20 + #define RESET_DWAP 22 21 + /* 23-31 */ 22 + 23 + /* RESET1 */ 24 + #define RESET_AUDIO 32 25 + /* 33-34 */ 26 + #define RESET_DDRAPB 35 27 + #define RESET_DDR 36 28 + #define RESET_DOS_CAPB3 37 29 + #define RESET_DOS 38 30 + /* 39-46 */ 31 + #define RESET_NNA 47 32 + #define RESET_ETHERNET 48 33 + #define RESET_ISP 49 34 + #define RESET_VC9000E_APB 50 35 + #define RESET_VC9000E_A 51 36 + /* 52 */ 37 + #define RESET_VC9000E_CORE 53 38 + /* 54-63 */ 39 + 40 + /* RESET2 */ 41 + #define RESET_ABUS_ARB 64 42 + #define RESET_IRCTRL 65 43 + /* 66 */ 44 + #define RESET_TEMP_PII 67 45 + /* 68-72 */ 46 + #define RESET_SPICC_0 73 47 + #define RESET_SPICC_1 74 48 + #define RESET_RSA 75 49 + 50 + /* 76-79 */ 51 + #define RESET_MSR_CLK 80 52 + #define RESET_SPIFC 81 53 + #define RESET_SAR_ADC 82 54 + /* 83-87 */ 55 + #define RESET_ACODEC 88 56 + /* 89-90 */ 57 + #define RESET_WATCHDOG 91 58 + /* 92-95 */ 59 + 60 + /* RESET3 */ 61 + #define RESET_ISP_NIC_GPV 96 62 + #define RESET_ISP_NIC_MAIN 97 63 + #define RESET_ISP_NIC_VCLK 98 64 + #define RESET_ISP_NIC_VOUT 99 65 + #define RESET_ISP_NIC_ALL 100 66 + #define RESET_VOUT 101 67 + #define RESET_VOUT_VENC 102 68 + /* 103 */ 69 + #define RESET_CVE_NIC_GPV 104 70 + #define RESET_CVE_NIC_MAIN 105 71 + #define RESET_CVE_NIC_GE2D 106 72 + #define RESET_CVE_NIC_DW 106 73 + #define RESET_CVE_NIC_CVE 108 74 + #define RESET_CVE_NIC_ALL 109 75 + #define RESET_CVE 110 76 + /* 112-127 */ 77 + 78 + /* RESET4 */ 79 + #define RESET_RTC 128 80 + #define RESET_PWM_AB 129 81 + #define RESET_PWM_CD 130 82 + #define RESET_PWM_EF 131 83 + #define RESET_PWM_GH 132 84 + #define RESET_PWM_IJ 133 85 + #define RESET_PWM_KL 134 86 + #define RESET_PWM_MN 135 87 + /* 136-137 */ 88 + #define RESET_UART_A 138 89 + #define RESET_UART_B 139 90 + #define RESET_UART_C 140 91 + #define RESET_UART_D 141 92 + #define RESET_UART_E 142 93 + #define RESET_UART_F 143 94 + #define RESET_I2C_S_A 144 95 + #define RESET_I2C_M_A 145 96 + #define RESET_I2C_M_B 146 97 + #define RESET_I2C_M_C 147 98 + #define RESET_I2C_M_D 148 99 + /* 149-151 */ 100 + #define RESET_SD_EMMC_A 152 101 + #define RESET_SD_EMMC_B 153 102 + #define RESET_SD_EMMC_C 154 103 + 104 + /* RESET5 */ 105 + /* 160-172 */ 106 + #define RESET_BRG_NIC_NNA 173 107 + #define RESET_BRG_MUX_NIC_MAIN 174 108 + #define RESET_BRG_AO_NIC_ALL 175 109 + /* 176-183 */ 110 + #define RESET_BRG_NIC_VAPB 184 111 + #define RESET_BRG_NIC_SDIO_B 185 112 + #define RESET_BRG_NIC_SDIO_A 186 113 + #define RESET_BRG_NIC_EMMC 187 114 + #define RESET_BRG_NIC_DSU 188 115 + #define RESET_BRG_NIC_SYSCLK 189 116 + #define RESET_BRG_NIC_MAIN 190 117 + #define RESET_BRG_NIC_ALL 191 118 + 119 + #endif
-19
include/linux/apple-mailbox.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 - /* 3 - * Apple mailbox message format 4 - * 5 - * Copyright (C) 2021 The Asahi Linux Contributors 6 - */ 7 - 8 - #ifndef _LINUX_APPLE_MAILBOX_H_ 9 - #define _LINUX_APPLE_MAILBOX_H_ 10 - 11 - #include <linux/types.h> 12 - 13 - /* encodes a single 96bit message sent over the single channel */ 14 - struct apple_mbox_msg { 15 - u64 msg0; 16 - u32 msg1; 17 - }; 18 - 19 - #endif
-18
include/linux/soc/apple/rtkit.h
··· 161 161 struct completion *completion, bool atomic); 162 162 163 163 /* 164 - * Send a message to the given endpoint and wait until it has been submitted 165 - * to the hardware FIFO. 166 - * Will return zero on success and a negative error code on failure 167 - * (e.g. -ETIME when the message couldn't be written within the given 168 - * timeout) 169 - * 170 - * @rtk: RTKit reference 171 - * @ep: target endpoint 172 - * @message: message to be sent 173 - * @timeout: timeout in milliseconds to allow the message transmission 174 - * to be completed 175 - * @atomic: if set to true this function can be called from atomic 176 - * context. 177 - */ 178 - int apple_rtkit_send_message_wait(struct apple_rtkit *rtk, u8 ep, u64 message, 179 - unsigned long timeout, bool atomic); 180 - 181 - /* 182 164 * Process incoming messages in atomic context. 183 165 * This only guarantees that messages arrive as far as the recv_message_early 184 166 * callback; drivers expecting to handle incoming messages synchronously
+8
include/linux/soc/mediatek/mtk-mmsys.h
··· 62 62 DDP_COMPONENT_OVL_2L1, 63 63 DDP_COMPONENT_OVL_2L2, 64 64 DDP_COMPONENT_OVL1, 65 + DDP_COMPONENT_PADDING0, 66 + DDP_COMPONENT_PADDING1, 67 + DDP_COMPONENT_PADDING2, 68 + DDP_COMPONENT_PADDING3, 69 + DDP_COMPONENT_PADDING4, 70 + DDP_COMPONENT_PADDING5, 71 + DDP_COMPONENT_PADDING6, 72 + DDP_COMPONENT_PADDING7, 65 73 DDP_COMPONENT_POSTMASK0, 66 74 DDP_COMPONENT_PWM0, 67 75 DDP_COMPONENT_PWM1,
+16
include/linux/tee_drv.h
··· 84 84 * @release: release this open file 85 85 * @open_session: open a new session 86 86 * @close_session: close a session 87 + * @system_session: declare session as a system session 87 88 * @invoke_func: invoke a trusted function 88 89 * @cancel_req: request cancel of an ongoing invoke or open 89 90 * @supp_recv: called for supplicant to get a command ··· 101 100 struct tee_ioctl_open_session_arg *arg, 102 101 struct tee_param *param); 103 102 int (*close_session)(struct tee_context *ctx, u32 session); 103 + int (*system_session)(struct tee_context *ctx, u32 session); 104 104 int (*invoke_func)(struct tee_context *ctx, 105 105 struct tee_ioctl_invoke_arg *arg, 106 106 struct tee_param *param); ··· 430 428 * valid after this function has returned. 431 429 */ 432 430 int tee_client_close_session(struct tee_context *ctx, u32 session); 431 + 432 + /** 433 + * tee_client_system_session() - Declare session as a system session 434 + * @ctx: TEE Context 435 + * @session: Session id 436 + * 437 + * This function requests TEE to provision an entry context ready to use for 438 + * that session only. The provisioned entry context is used for command 439 + * invocation and session closure, not for command cancelling requests. 440 + * TEE releases the provisioned context upon session closure. 441 + * 442 + * Return < 0 on error else 0 if an entry context has been provisioned. 443 + */ 444 + int tee_client_system_session(struct tee_context *ctx, u32 session); 433 445 434 446 /** 435 447 * tee_client_invoke_func() - Invoke a function in a Trusted Application
+26 -1
include/soc/fsl/qe/qmc.h
··· 9 9 #ifndef __SOC_FSL_QMC_H__ 10 10 #define __SOC_FSL_QMC_H__ 11 11 12 + #include <linux/bits.h> 12 13 #include <linux/types.h> 13 14 14 15 struct device_node; ··· 17 16 struct qmc_chan; 18 17 19 18 struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char *phandle_name); 19 + struct qmc_chan *qmc_chan_get_bychild(struct device_node *np); 20 20 void qmc_chan_put(struct qmc_chan *chan); 21 21 struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev, struct device_node *np, 22 22 const char *phandle_name); 23 + struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, struct device_node *np); 23 24 24 25 enum qmc_mode { 25 26 QMC_TRANSPARENT, ··· 39 36 }; 40 37 41 38 int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info); 39 + 40 + struct qmc_chan_ts_info { 41 + u64 rx_ts_mask_avail; 42 + u64 tx_ts_mask_avail; 43 + u64 rx_ts_mask; 44 + u64 tx_ts_mask; 45 + }; 46 + 47 + int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info); 48 + int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info); 42 49 43 50 struct qmc_chan_param { 44 51 enum qmc_mode mode; ··· 69 56 int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, 70 57 void (*complete)(void *context), void *context); 71 58 59 + /* Flags available (ORed) for read complete() flags parameter in HDLC mode. 60 + * No flags are available in transparent mode and the read complete() flags 61 + * parameter has no meaning in transparent mode. 62 + */ 63 + #define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */ 64 + #define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */ 65 + #define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */ 66 + #define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not multiple of 8) */ 67 + #define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seven consecutive ones) */ 68 + #define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */ 69 + 72 70 int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, 73 - void (*complete)(void *context, size_t length), 71 + void (*complete)(void *context, size_t length, 72 + unsigned int flags), 74 73 void *context); 75 74 76 75 #define QMC_CHAN_READ (1<<0)
+2
include/soc/microchip/mpfs.h
··· 38 38 39 39 struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev); 40 40 41 + struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_client); 42 + 41 43 #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ 42 44 43 45 #if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
+1
include/soc/tegra/mc.h
··· 162 162 */ 163 163 int (*probe)(struct tegra_mc *mc); 164 164 void (*remove)(struct tegra_mc *mc); 165 + int (*resume)(struct tegra_mc *mc); 165 166 irqreturn_t (*handle_irq)(int irq, void *data); 166 167 int (*probe_device)(struct tegra_mc *mc, struct device *dev); 167 168 };
+1 -1
sound/soc/fsl/fsl_qmc_audio.c
··· 99 99 snd_pcm_period_elapsed(prtd->substream); 100 100 } 101 101 102 - static void qmc_audio_pcm_read_complete(void *context, size_t length) 102 + static void qmc_audio_pcm_read_complete(void *context, size_t length, unsigned int flags) 103 103 { 104 104 struct qmc_dai_prtd *prtd = context; 105 105 int ret;