+6 -2

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 1176 1176 * queue fence. 1177 1177 */ 1178 1178 struct xarray userq_xa; 1179 1179 + /** 1180 1180 + * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1181 1181 + * Key: doorbell_index (unique global identifier for the queue) 1182 1182 + * Value: struct amdgpu_usermode_queue 1183 1183 + */ 1184 1184 + struct xarray userq_doorbell_xa; 1179 1185 1180 1186 /* df */ 1181 1187 struct amdgpu_df df; ··· 1315 1309 */ 1316 1310 bool apu_prefer_gtt; 1317 1311 1318 1318 - struct list_head userq_mgr_list; 1319 1319 - struct mutex userq_mutex; 1320 1312 bool userq_halt_for_enforce_isolation; 1321 1313 struct amdgpu_uid *uid_info; 1322 1314

-1

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

reviewed

··· 507 507 pm_runtime_get_sync(adev_to_drm(adev)->dev); 508 508 /* Just fire off a uevent and let userspace tell us what to do */ 509 509 drm_helper_hpd_irq_event(adev_to_drm(adev)); 510 510 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 511 510 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 512 511 } 513 512 }

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

reviewed

··· 103 103 { 104 104 uint8_t __iomem *bios = NULL; 105 105 resource_size_t vram_base; 106 106 - resource_size_t size = 256 * 1024; /* ??? */ 106 106 + u32 size = 256U * 1024U; /* ??? */ 107 107 108 108 if (!(adev->flags & AMD_IS_APU)) 109 109 if (amdgpu_device_need_post(adev)) ··· 126 126 */ 127 127 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 128 128 if (amdgpu_virt_get_dynamic_data_info(adev, 129 129 - AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, adev->bios, (uint64_t *)&size)) { 129 129 + AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, adev->bios, &size)) { 130 130 amdgpu_bios_release(adev); 131 131 return false; 132 132 }

+4 -12

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

reviewed

··· 734 734 735 735 amdgpu_connector_update_scratch_regs(connector, ret); 736 736 737 737 - if (!drm_kms_helper_is_poll_worker()) { 738 738 - pm_runtime_mark_last_busy(connector->dev->dev); 737 737 + if (!drm_kms_helper_is_poll_worker()) 739 738 pm_runtime_put_autosuspend(connector->dev->dev); 740 740 - } 741 739 742 740 return ret; 743 741 } ··· 917 919 amdgpu_connector_update_scratch_regs(connector, ret); 918 920 919 921 out: 920 920 - if (!drm_kms_helper_is_poll_worker()) { 921 921 - pm_runtime_mark_last_busy(connector->dev->dev); 922 922 + if (!drm_kms_helper_is_poll_worker()) 922 923 pm_runtime_put_autosuspend(connector->dev->dev); 923 923 - } 924 924 925 925 return ret; 926 926 } ··· 1142 1146 amdgpu_connector_update_scratch_regs(connector, ret); 1143 1147 1144 1148 exit: 1145 1145 - if (!drm_kms_helper_is_poll_worker()) { 1146 1146 - pm_runtime_mark_last_busy(connector->dev->dev); 1149 1149 + if (!drm_kms_helper_is_poll_worker()) 1147 1150 pm_runtime_put_autosuspend(connector->dev->dev); 1148 1148 - } 1149 1151 1150 1152 return ret; 1151 1153 } ··· 1480 1486 1481 1487 amdgpu_connector_update_scratch_regs(connector, ret); 1482 1488 out: 1483 1483 - if (!drm_kms_helper_is_poll_worker()) { 1484 1484 - pm_runtime_mark_last_busy(connector->dev->dev); 1489 1489 + if (!drm_kms_helper_is_poll_worker()) 1485 1490 pm_runtime_put_autosuspend(connector->dev->dev); 1486 1486 - } 1487 1491 1488 1492 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1489 1493 connector->connector_type == DRM_MODE_CONNECTOR_eDP)

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: MIT 2 2 /* 3 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 4 *

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 */ 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 /* 3 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 4 *

-25

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

reviewed

··· 129 129 if (use_bank) { 130 130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || 131 131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { 132 132 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 133 132 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 134 133 amdgpu_virt_disable_access_debugfs(adev); 135 134 return -EINVAL; ··· 178 179 if (pm_pg_lock) 179 180 mutex_unlock(&adev->pm.mutex); 180 181 181 181 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 182 182 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 183 183 184 184 amdgpu_virt_disable_access_debugfs(adev); ··· 253 255 if (rd->id.use_grbm) { 254 256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || 255 257 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) { 256 256 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 257 258 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 258 259 amdgpu_virt_disable_access_debugfs(adev); 259 260 mutex_unlock(&rd->lock); ··· 307 310 308 311 mutex_unlock(&rd->lock); 309 312 310 310 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 311 313 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 312 314 313 315 amdgpu_virt_disable_access_debugfs(adev); ··· 442 446 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, rd->id.xcc_id); 443 447 mutex_unlock(&adev->grbm_idx_mutex); 444 448 445 445 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 446 449 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 447 450 448 451 if (!x) { ··· 552 557 553 558 r = result; 554 559 out: 555 555 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 556 560 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 557 561 amdgpu_virt_disable_access_debugfs(adev); 558 562 return r; ··· 611 617 612 618 r = result; 613 619 out: 614 614 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 615 620 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 616 621 amdgpu_virt_disable_access_debugfs(adev); 617 622 return r; ··· 669 676 670 677 r = result; 671 678 out: 672 672 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 673 679 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 674 680 amdgpu_virt_disable_access_debugfs(adev); 675 681 return r; ··· 728 736 729 737 r = result; 730 738 out: 731 731 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 732 739 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 733 740 amdgpu_virt_disable_access_debugfs(adev); 734 741 return r; ··· 786 795 787 796 r = result; 788 797 out: 789 789 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 790 798 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 791 799 amdgpu_virt_disable_access_debugfs(adev); 792 800 return r; ··· 845 855 846 856 r = result; 847 857 out: 848 848 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 849 858 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 850 859 amdgpu_virt_disable_access_debugfs(adev); 851 860 return r; ··· 992 1003 993 1004 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); 994 1005 995 995 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 996 1006 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 997 1007 998 1008 if (r) { ··· 1082 1094 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0); 1083 1095 mutex_unlock(&adev->grbm_idx_mutex); 1084 1096 1085 1085 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1086 1097 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1087 1098 1088 1099 if (!x) { ··· 1179 1192 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0); 1180 1193 mutex_unlock(&adev->grbm_idx_mutex); 1181 1194 1182 1182 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1183 1195 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1184 1196 1185 1197 while (size) { ··· 1252 1266 1253 1267 r = result; 1254 1268 out: 1255 1255 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1256 1269 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1257 1270 1258 1271 return r; ··· 1300 1315 1301 1316 r = result; 1302 1317 out: 1303 1303 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1304 1318 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1305 1319 1306 1320 return r; ··· 1349 1365 1350 1366 r = result; 1351 1367 out: 1352 1352 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1353 1368 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1354 1369 1355 1370 return r; ··· 1397 1414 1398 1415 r = result; 1399 1416 out: 1400 1400 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1401 1417 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1402 1418 1403 1419 return r; ··· 1442 1460 1443 1461 r = result; 1444 1462 out: 1445 1445 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1446 1463 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1447 1464 1448 1465 return r; ··· 1482 1501 1483 1502 r = result; 1484 1503 out: 1485 1485 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1486 1504 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1487 1505 1488 1506 return r; ··· 1681 1701 1682 1702 up_write(&adev->reset_domain->sem); 1683 1703 1684 1684 - pm_runtime_mark_last_busy(dev->dev); 1685 1704 pm_runtime_put_autosuspend(dev->dev); 1686 1705 1687 1706 return 0; ··· 1700 1721 1701 1722 *val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM); 1702 1723 1703 1703 - pm_runtime_mark_last_busy(dev->dev); 1704 1724 pm_runtime_put_autosuspend(dev->dev); 1705 1725 1706 1726 return 0; ··· 1720 1742 1721 1743 *val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT); 1722 1744 1723 1723 - pm_runtime_mark_last_busy(dev->dev); 1724 1745 pm_runtime_put_autosuspend(dev->dev); 1725 1746 1726 1747 return 0; ··· 1739 1762 1740 1763 r = amdgpu_benchmark(adev, val); 1741 1764 1742 1742 - pm_runtime_mark_last_busy(dev->dev); 1743 1765 pm_runtime_put_autosuspend(dev->dev); 1744 1766 1745 1767 return r; ··· 1990 2014 ret = -EINVAL; 1991 2015 1992 2016 out: 1993 1993 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1994 2017 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1995 2018 1996 2019 return ret;

+1 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 4215 4215 #else 4216 4216 return false; 4217 4217 #endif 4218 4218 - case CHIP_BONAIRE: 4219 4218 case CHIP_KAVERI: 4220 4219 case CHIP_KABINI: 4221 4220 case CHIP_MULLINS: ··· 4557 4558 mutex_init(&adev->gfx.userq_sch_mutex); 4558 4559 mutex_init(&adev->gfx.workload_profile_mutex); 4559 4560 mutex_init(&adev->vcn.workload_profile_mutex); 4560 4560 - mutex_init(&adev->userq_mutex); 4561 4561 4562 4562 amdgpu_device_init_apu_flags(adev); 4563 4563 ··· 4584 4586 4585 4587 INIT_LIST_HEAD(&adev->pm.od_kobj_list); 4586 4588 4587 4587 - INIT_LIST_HEAD(&adev->userq_mgr_list); 4589 4589 + xa_init(&adev->userq_doorbell_xa); 4588 4590 4589 4591 INIT_DELAYED_WORK(&adev->delayed_init_work, 4590 4592 amdgpu_device_delayed_init_work_handler);

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

reviewed

··· 311 311 */ 312 312 if (amdgpu_virt_get_dynamic_data_info(adev, 313 313 AMD_SRIOV_MSG_IPD_TABLE_ID, binary, 314 314 - (uint64_t *)&adev->discovery.size)) { 314 314 + &adev->discovery.size)) { 315 315 dev_err(adev->dev, 316 316 "failed to read discovery info from dynamic critical region."); 317 317 ret = -EINVAL;

+59 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

reviewed

··· 332 332 if (crtc->enabled) 333 333 active = true; 334 334 335 335 - pm_runtime_mark_last_busy(dev->dev); 336 336 - 337 335 adev = drm_to_adev(dev); 338 336 /* if we have active crtcs and we don't have a power ref, 339 337 * take the current one ··· 1363 1365 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 1364 1366 }; 1365 1367 1368 1368 + /** 1369 1369 + * DOC: property for adaptive backlight modulation 1370 1370 + * 1371 1371 + * The 'adaptive backlight modulation' property is used for the compositor to 1372 1372 + * directly control the adaptive backlight modulation power savings feature 1373 1373 + * that is part of DCN hardware. 1374 1374 + * 1375 1375 + * The property will be attached specifically to eDP panels that support it. 1376 1376 + * 1377 1377 + * The property is by default set to 'sysfs' to allow the sysfs file 'panel_power_savings' 1378 1378 + * to be able to control it. 1379 1379 + * If set to 'off' the compositor will ensure it stays off. 1380 1380 + * The other values 'min', 'bias min', 'bias max', and 'max' will control the 1381 1381 + * intensity of the power savings. 1382 1382 + * 1383 1383 + * Modifying this value can have implications on color accuracy, so tread 1384 1384 + * carefully. 1385 1385 + */ 1386 1386 + static int amdgpu_display_setup_abm_prop(struct amdgpu_device *adev) 1387 1387 + { 1388 1388 + const struct drm_prop_enum_list props[] = { 1389 1389 + { ABM_SYSFS_CONTROL, "sysfs" }, 1390 1390 + { ABM_LEVEL_OFF, "off" }, 1391 1391 + { ABM_LEVEL_MIN, "min" }, 1392 1392 + { ABM_LEVEL_BIAS_MIN, "bias min" }, 1393 1393 + { ABM_LEVEL_BIAS_MAX, "bias max" }, 1394 1394 + { ABM_LEVEL_MAX, "max" }, 1395 1395 + }; 1396 1396 + struct drm_property *prop; 1397 1397 + int i; 1398 1398 + 1399 1399 + if (!adev->dc_enabled) 1400 1400 + return 0; 1401 1401 + 1402 1402 + prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_ENUM, 1403 1403 + "adaptive backlight modulation", 1404 1404 + 6); 1405 1405 + if (!prop) 1406 1406 + return -ENOMEM; 1407 1407 + 1408 1408 + for (i = 0; i < ARRAY_SIZE(props); i++) { 1409 1409 + int ret; 1410 1410 + 1411 1411 + ret = drm_property_add_enum(prop, props[i].type, 1412 1412 + props[i].name); 1413 1413 + 1414 1414 + if (ret) { 1415 1415 + drm_property_destroy(adev_to_drm(adev), prop); 1416 1416 + 1417 1417 + return ret; 1418 1418 + } 1419 1419 + } 1420 1420 + 1421 1421 + adev->mode_info.abm_level_property = prop; 1422 1422 + 1423 1423 + return 0; 1424 1424 + } 1425 1425 + 1366 1426 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 1367 1427 { 1368 1428 int sz; ··· 1467 1411 "dither", 1468 1412 amdgpu_dither_enum_list, sz); 1469 1413 1470 1470 - return 0; 1414 1414 + return amdgpu_display_setup_abm_prop(adev); 1471 1415 } 1472 1416 1473 1417 void amdgpu_display_update_priority(struct amdgpu_device *adev)

+7

drivers/gpu/drm/amd/amdgpu/amdgpu_display.h

reviewed

··· 55 55 int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, 56 56 struct drm_scanout_buffer *sb); 57 57 58 58 + #define ABM_SYSFS_CONTROL -1 59 59 + #define ABM_LEVEL_OFF 0 60 60 + #define ABM_LEVEL_MIN 1 61 61 + #define ABM_LEVEL_BIAS_MIN 2 62 62 + #define ABM_LEVEL_BIAS_MAX 3 63 63 + #define ABM_LEVEL_MAX 4 64 64 + 58 65 #endif

+1 -19

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

reviewed

··· 2228 2228 adev->pdev->bus->number, i); 2229 2229 if (p) { 2230 2230 pm_runtime_get_sync(&p->dev); 2231 2231 - pm_runtime_mark_last_busy(&p->dev); 2232 2231 pm_runtime_put_autosuspend(&p->dev); 2233 2232 pci_dev_put(p); 2234 2233 } ··· 2473 2474 2474 2475 pm_runtime_allow(ddev->dev); 2475 2476 2476 2476 - pm_runtime_mark_last_busy(ddev->dev); 2477 2477 pm_runtime_put_autosuspend(ddev->dev); 2478 2478 2479 2479 pci_wake_from_d3(pdev, TRUE); ··· 2770 2772 struct pci_dev *pdev = to_pci_dev(dev); 2771 2773 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2772 2774 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2773 2773 - struct amdgpu_usermode_queue *queue; 2774 2774 - struct amdgpu_userq_mgr *uqm, *tmp; 2775 2775 - int queue_id; 2776 2776 - int ret = 0; 2777 2775 2778 2778 - mutex_lock(&adev->userq_mutex); 2779 2779 - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 2780 2780 - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 2781 2781 - ret = -EBUSY; 2782 2782 - goto done; 2783 2783 - } 2784 2784 - } 2785 2785 - done: 2786 2786 - mutex_unlock(&adev->userq_mutex); 2787 2787 - 2788 2788 - return ret; 2776 2776 + return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2789 2777 } 2790 2778 2791 2779 static int amdgpu_pmops_runtime_suspend(struct device *dev) ··· 2918 2934 2919 2935 ret = amdgpu_runtime_idle_check_userq(dev); 2920 2936 done: 2921 2921 - pm_runtime_mark_last_busy(dev); 2922 2937 pm_runtime_autosuspend(dev); 2923 2938 return ret; 2924 2939 } ··· 2953 2970 2954 2971 ret = drm_ioctl(filp, cmd, arg); 2955 2972 2956 2956 - pm_runtime_mark_last_busy(dev->dev); 2957 2973 out: 2958 2974 pm_runtime_put_autosuspend(dev->dev); 2959 2975 return ret;

-2

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

reviewed

··· 250 250 drv->signalled_wptr = am_fence->wptr; 251 251 dma_fence_signal(fence); 252 252 dma_fence_put(fence); 253 253 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 254 253 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 255 254 } while (last_seq != seq); 256 255 ··· 927 928 928 929 *val = atomic_read(&adev->reset_domain->reset_res); 929 930 930 930 - pm_runtime_mark_last_busy(dev->dev); 931 931 pm_runtime_put_autosuspend(dev->dev); 932 932 933 933 return 0;

-1

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

reviewed

··· 1670 1670 1671 1671 ret = amdgpu_gfx_run_cleaner_shader(adev, value); 1672 1672 1673 1673 - pm_runtime_mark_last_busy(ddev->dev); 1674 1673 pm_runtime_put_autosuspend(ddev->dev); 1675 1674 1676 1675 if (ret)

+4 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c

reviewed

··· 221 221 222 222 out_free_pfns: 223 223 kvfree(pfns); 224 224 + hmm_range->hmm_pfns = NULL; 224 225 out_free_range: 225 226 if (r == -EBUSY) 226 227 r = -EAGAIN; ··· 287 286 if (!range) 288 287 return; 289 288 290 290 - kvfree(range->hmm_range.hmm_pfns); 289 289 + if (range->hmm_range.hmm_pfns) 290 290 + kvfree(range->hmm_range.hmm_pfns); 291 291 + 291 292 amdgpu_bo_unref(&range->bo); 292 293 kfree(range); 293 294 }

-2

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

reviewed

··· 1471 1471 kfree(fpriv); 1472 1472 1473 1473 out_suspend: 1474 1474 - pm_runtime_mark_last_busy(dev->dev); 1475 1474 pm_put: 1476 1475 pm_runtime_put_autosuspend(dev->dev); 1477 1476 ··· 1538 1539 kfree(fpriv); 1539 1540 file_priv->driver_priv = NULL; 1540 1541 1541 1541 - pm_runtime_mark_last_busy(dev->dev); 1542 1542 pm_runtime_put_autosuspend(dev->dev); 1543 1543 } 1544 1544

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

reviewed

··· 326 326 struct drm_property *audio_property; 327 327 /* FMT dithering */ 328 328 struct drm_property *dither_property; 329 329 + /* Adaptive Backlight Modulation (power feature) */ 330 330 + struct drm_property *abm_level_property; 329 331 /* hardcoded DFP edid from BIOS */ 330 332 const struct drm_edid *bios_hardcoded_edid; 331 333

-1

drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c

reviewed

··· 101 101 } 102 102 103 103 amdgpu_gfx_off_ctrl(adev, true); 104 104 - pm_runtime_mark_last_busy(dev->dev); 105 104 pm_runtime_put_autosuspend(dev->dev); 106 105 107 106 return size;

+53 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

reviewed

··· 612 612 return size; 613 613 } 614 614 615 615 + static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev); 616 616 + 615 617 /** 616 618 * DOC: AMDGPU RAS debugfs EEPROM table reset interface 617 619 * ··· 637 635 struct amdgpu_device *adev = 638 636 (struct amdgpu_device *)file_inode(f)->i_private; 639 637 int ret; 638 638 + 639 639 + if (amdgpu_uniras_enabled(adev)) { 640 640 + ret = amdgpu_uniras_clear_badpages_info(adev); 641 641 + return ret ? ret : size; 642 642 + } 640 643 641 644 ret = amdgpu_ras_eeprom_reset_table( 642 645 &(amdgpu_ras_get_context(adev)->eeprom_control)); ··· 1550 1543 return ret; 1551 1544 } 1552 1545 1546 1546 + static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev) 1547 1547 + { 1548 1548 + struct ras_cmd_dev_handle req = {0}; 1549 1549 + int ret; 1550 1550 + 1551 1551 + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CLEAR_BAD_PAGE_INFO, 1552 1552 + &req, sizeof(req), NULL, 0); 1553 1553 + if (ret) { 1554 1554 + dev_err(adev->dev, "Failed to clear bad pages info, ret: %d\n", ret); 1555 1555 + return ret; 1556 1556 + } 1557 1557 + 1558 1558 + return 0; 1559 1559 + } 1560 1560 + 1553 1561 static int amdgpu_uniras_query_block_ecc(struct amdgpu_device *adev, 1554 1562 struct ras_query_if *info) 1555 1563 { ··· 1950 1928 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features); 1951 1929 } 1952 1930 1931 1931 + static bool amdgpu_ras_get_version_info(struct amdgpu_device *adev, u32 *major, 1932 1932 + u32 *minor, u32 *rev) 1933 1933 + { 1934 1934 + int i; 1935 1935 + 1936 1936 + if (!adev || !major || !minor || !rev || !amdgpu_uniras_enabled(adev)) 1937 1937 + return false; 1938 1938 + 1939 1939 + for (i = 0; i < adev->num_ip_blocks; i++) { 1940 1940 + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_RAS) { 1941 1941 + *major = adev->ip_blocks[i].version->major; 1942 1942 + *minor = adev->ip_blocks[i].version->minor; 1943 1943 + *rev = adev->ip_blocks[i].version->rev; 1944 1944 + return true; 1945 1945 + } 1946 1946 + } 1947 1947 + 1948 1948 + return false; 1949 1949 + } 1950 1950 + 1953 1951 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev, 1954 1952 struct device_attribute *attr, char *buf) 1955 1953 { 1956 1954 struct amdgpu_ras *con = 1957 1955 container_of(attr, struct amdgpu_ras, version_attr); 1958 1958 - return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version); 1956 1956 + u32 major, minor, rev; 1957 1957 + ssize_t size = 0; 1958 1958 + 1959 1959 + size += sysfs_emit_at(buf, size, "table version: 0x%x\n", 1960 1960 + con->eeprom_control.tbl_hdr.version); 1961 1961 + 1962 1962 + if (amdgpu_ras_get_version_info(con->adev, &major, &minor, &rev)) 1963 1963 + size += sysfs_emit_at(buf, size, "ras version: %u.%u.%u\n", 1964 1964 + major, minor, rev); 1965 1965 + 1966 1966 + return size; 1959 1967 } 1960 1968 1961 1969 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev, ··· 4151 4099 atomic_set(&con->ras_ue_count, ue_count); 4152 4100 } 4153 4101 4154 4154 - pm_runtime_mark_last_busy(dev->dev); 4155 4102 Out: 4156 4103 pm_runtime_put_autosuspend(dev->dev); 4157 4104 }

-1

drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c

reviewed

··· 159 159 dev_err(adev->dev, "Invalid input: %s\n", str); 160 160 } 161 161 162 162 - pm_runtime_mark_last_busy(dev->dev); 163 162 pm_runtime_put_autosuspend(dev->dev); 164 163 165 164 return size;

+76 -78

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c

reviewed

··· 30 30 #include "amdgpu_vm.h" 31 31 #include "amdgpu_userq.h" 32 32 #include "amdgpu_hmm.h" 33 33 + #include "amdgpu_reset.h" 33 34 #include "amdgpu_userq_fence.h" 34 35 35 36 u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) ··· 160 159 r = -EINVAL; 161 160 goto err; 162 161 } 163 163 - amdgpu_userq_buffer_va_list_del(mapping, va_cursor); 164 162 dev_dbg(adev->dev, "delete the userq:%p va:%llx\n", 165 163 queue, va_cursor->gpu_addr); 164 164 + amdgpu_userq_buffer_va_list_del(mapping, va_cursor); 166 165 } 167 166 err: 168 167 amdgpu_bo_unreserve(queue->vm->root.bo); ··· 279 278 struct amdgpu_device *adev = uq_mgr->adev; 280 279 const struct amdgpu_userq_funcs *uq_funcs = adev->userq_funcs[queue->queue_type]; 281 280 281 281 + /* Wait for mode-1 reset to complete */ 282 282 + down_read(&adev->reset_domain->sem); 283 283 + 282 284 /* Drop the userq reference. */ 283 285 amdgpu_userq_buffer_vas_list_cleanup(adev, queue); 284 286 uq_funcs->mqd_destroy(uq_mgr, queue); 285 287 amdgpu_userq_fence_driver_free(queue); 286 286 - idr_remove(&uq_mgr->userq_idr, queue_id); 288 288 + /* Use interrupt-safe locking since IRQ handlers may access these XArrays */ 289 289 + xa_erase_irq(&uq_mgr->userq_mgr_xa, (unsigned long)queue_id); 290 290 + xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index); 291 291 + queue->userq_mgr = NULL; 287 292 list_del(&queue->userq_va_list); 288 293 kfree(queue); 294 294 + 295 295 + up_read(&adev->reset_domain->sem); 289 296 } 290 297 291 298 static struct amdgpu_usermode_queue * 292 299 amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid) 293 300 { 294 294 - return idr_find(&uq_mgr->userq_idr, qid); 301 301 + return xa_load(&uq_mgr->userq_mgr_xa, qid); 295 302 } 296 303 297 304 void ··· 488 479 amdgpu_userq_cleanup(uq_mgr, queue, queue_id); 489 480 mutex_unlock(&uq_mgr->userq_mutex); 490 481 491 491 - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 492 482 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 493 483 494 484 return r; ··· 559 551 struct amdgpu_db_info db_info; 560 552 char *queue_name; 561 553 bool skip_map_queue; 554 554 + u32 qid; 562 555 uint64_t index; 563 563 - int qid, r = 0; 556 556 + int r = 0; 564 557 int priority = 565 558 (args->in.flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK) >> 566 559 AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT; ··· 584 575 * 585 576 * This will also make sure we have a valid eviction fence ready to be used. 586 577 */ 587 587 - mutex_lock(&adev->userq_mutex); 588 578 amdgpu_userq_ensure_ev_fence(&fpriv->userq_mgr, &fpriv->evf_mgr); 589 579 590 580 uq_funcs = adev->userq_funcs[args->in.ip_type]; ··· 646 638 goto unlock; 647 639 } 648 640 649 649 - qid = idr_alloc(&uq_mgr->userq_idr, queue, 1, AMDGPU_MAX_USERQ_COUNT, GFP_KERNEL); 650 650 - if (qid < 0) { 641 641 + /* Wait for mode-1 reset to complete */ 642 642 + down_read(&adev->reset_domain->sem); 643 643 + r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); 644 644 + if (r) { 645 645 + kfree(queue); 646 646 + up_read(&adev->reset_domain->sem); 647 647 + goto unlock; 648 648 + } 649 649 + 650 650 + r = xa_alloc(&uq_mgr->userq_mgr_xa, &qid, queue, XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); 651 651 + if (r) { 651 652 drm_file_err(uq_mgr->file, "Failed to allocate a queue id\n"); 652 653 amdgpu_userq_fence_driver_free(queue); 653 654 uq_funcs->mqd_destroy(uq_mgr, queue); 654 655 kfree(queue); 655 656 r = -ENOMEM; 657 657 + up_read(&adev->reset_domain->sem); 656 658 goto unlock; 657 659 } 660 660 + up_read(&adev->reset_domain->sem); 661 661 + queue->userq_mgr = uq_mgr; 658 662 659 663 /* don't map the queue if scheduling is halted */ 660 664 if (adev->userq_halt_for_enforce_isolation && ··· 679 659 r = amdgpu_userq_map_helper(uq_mgr, queue); 680 660 if (r) { 681 661 drm_file_err(uq_mgr->file, "Failed to map Queue\n"); 682 682 - idr_remove(&uq_mgr->userq_idr, qid); 662 662 + xa_erase(&uq_mgr->userq_mgr_xa, qid); 683 663 amdgpu_userq_fence_driver_free(queue); 684 664 uq_funcs->mqd_destroy(uq_mgr, queue); 685 665 kfree(queue); ··· 704 684 705 685 unlock: 706 686 mutex_unlock(&uq_mgr->userq_mutex); 707 707 - mutex_unlock(&adev->userq_mutex); 708 687 709 688 return r; 710 689 } ··· 801 782 amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) 802 783 { 803 784 struct amdgpu_usermode_queue *queue; 804 804 - int queue_id; 785 785 + unsigned long queue_id; 805 786 int ret = 0, r; 806 787 807 788 /* Resume all the queues for this process */ 808 808 - idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { 789 789 + xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { 809 790 810 791 if (!amdgpu_userq_buffer_vas_mapped(queue)) { 811 792 drm_file_err(uq_mgr->file, ··· 1042 1023 amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) 1043 1024 { 1044 1025 struct amdgpu_usermode_queue *queue; 1045 1045 - int queue_id; 1026 1026 + unsigned long queue_id; 1046 1027 int ret = 0, r; 1047 1028 1048 1029 /* Try to unmap all the queues in this process ctx */ 1049 1049 - idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { 1030 1030 + xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { 1050 1031 r = amdgpu_userq_preempt_helper(uq_mgr, queue); 1051 1032 if (r) 1052 1033 ret = r; ··· 1061 1042 amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) 1062 1043 { 1063 1044 struct amdgpu_usermode_queue *queue; 1064 1064 - int queue_id, ret; 1045 1045 + unsigned long queue_id; 1046 1046 + int ret; 1065 1047 1066 1066 - idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { 1048 1048 + xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { 1067 1049 struct dma_fence *f = queue->last_fence; 1068 1050 1069 1051 if (!f || dma_fence_is_signaled(f)) ··· 1117 1097 struct amdgpu_device *adev) 1118 1098 { 1119 1099 mutex_init(&userq_mgr->userq_mutex); 1120 1120 - idr_init_base(&userq_mgr->userq_idr, 1); 1100 1100 + xa_init_flags(&userq_mgr->userq_mgr_xa, XA_FLAGS_ALLOC); 1121 1101 userq_mgr->adev = adev; 1122 1102 userq_mgr->file = file_priv; 1123 1123 - 1124 1124 - mutex_lock(&adev->userq_mutex); 1125 1125 - list_add(&userq_mgr->list, &adev->userq_mgr_list); 1126 1126 - mutex_unlock(&adev->userq_mutex); 1127 1103 1128 1104 INIT_DELAYED_WORK(&userq_mgr->resume_work, amdgpu_userq_restore_worker); 1129 1105 return 0; ··· 1127 1111 1128 1112 void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) 1129 1113 { 1130 1130 - struct amdgpu_device *adev = userq_mgr->adev; 1131 1114 struct amdgpu_usermode_queue *queue; 1132 1132 - struct amdgpu_userq_mgr *uqm, *tmp; 1133 1133 - uint32_t queue_id; 1115 1115 + unsigned long queue_id; 1134 1116 1135 1117 cancel_delayed_work_sync(&userq_mgr->resume_work); 1136 1118 1137 1137 - mutex_lock(&adev->userq_mutex); 1138 1119 mutex_lock(&userq_mgr->userq_mutex); 1139 1139 - idr_for_each_entry(&userq_mgr->userq_idr, queue, queue_id) { 1120 1120 + xa_for_each(&userq_mgr->userq_mgr_xa, queue_id, queue) { 1140 1121 amdgpu_userq_wait_for_last_fence(userq_mgr, queue); 1141 1122 amdgpu_userq_unmap_helper(userq_mgr, queue); 1142 1123 amdgpu_userq_cleanup(userq_mgr, queue, queue_id); 1143 1124 } 1144 1125 1145 1145 - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 1146 1146 - if (uqm == userq_mgr) { 1147 1147 - list_del(&uqm->list); 1148 1148 - break; 1149 1149 - } 1150 1150 - } 1151 1151 - idr_destroy(&userq_mgr->userq_idr); 1126 1126 + xa_destroy(&userq_mgr->userq_mgr_xa); 1152 1127 mutex_unlock(&userq_mgr->userq_mutex); 1153 1153 - mutex_unlock(&adev->userq_mutex); 1154 1128 mutex_destroy(&userq_mgr->userq_mutex); 1155 1129 } 1156 1130 ··· 1148 1142 { 1149 1143 u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1150 1144 struct amdgpu_usermode_queue *queue; 1151 1151 - struct amdgpu_userq_mgr *uqm, *tmp; 1152 1152 - int queue_id; 1145 1145 + struct amdgpu_userq_mgr *uqm; 1146 1146 + unsigned long queue_id; 1153 1147 int r; 1154 1148 1155 1149 if (!ip_mask) 1156 1150 return 0; 1157 1151 1158 1158 - guard(mutex)(&adev->userq_mutex); 1159 1159 - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 1152 1152 + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 1153 1153 + uqm = queue->userq_mgr; 1160 1154 cancel_delayed_work_sync(&uqm->resume_work); 1161 1155 guard(mutex)(&uqm->userq_mutex); 1162 1162 - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 1163 1163 - if (adev->in_s0ix) 1164 1164 - r = amdgpu_userq_preempt_helper(uqm, queue); 1165 1165 - else 1166 1166 - r = amdgpu_userq_unmap_helper(uqm, queue); 1167 1167 - if (r) 1168 1168 - return r; 1169 1169 - } 1156 1156 + if (adev->in_s0ix) 1157 1157 + r = amdgpu_userq_preempt_helper(uqm, queue); 1158 1158 + else 1159 1159 + r = amdgpu_userq_unmap_helper(uqm, queue); 1160 1160 + if (r) 1161 1161 + return r; 1170 1162 } 1171 1163 return 0; 1172 1164 } ··· 1173 1169 { 1174 1170 u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1175 1171 struct amdgpu_usermode_queue *queue; 1176 1176 - struct amdgpu_userq_mgr *uqm, *tmp; 1177 1177 - int queue_id; 1172 1172 + struct amdgpu_userq_mgr *uqm; 1173 1173 + unsigned long queue_id; 1178 1174 int r; 1179 1175 1180 1176 if (!ip_mask) 1181 1177 return 0; 1182 1178 1183 1183 - guard(mutex)(&adev->userq_mutex); 1184 1184 - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 1179 1179 + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 1180 1180 + uqm = queue->userq_mgr; 1185 1181 guard(mutex)(&uqm->userq_mutex); 1186 1186 - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 1187 1187 - if (adev->in_s0ix) 1188 1188 - r = amdgpu_userq_restore_helper(uqm, queue); 1189 1189 - else 1190 1190 - r = amdgpu_userq_map_helper(uqm, queue); 1191 1191 - if (r) 1192 1192 - return r; 1193 1193 - } 1182 1182 + if (adev->in_s0ix) 1183 1183 + r = amdgpu_userq_restore_helper(uqm, queue); 1184 1184 + else 1185 1185 + r = amdgpu_userq_map_helper(uqm, queue); 1186 1186 + if (r) 1187 1187 + return r; 1194 1188 } 1195 1189 1196 1190 return 0; ··· 1199 1197 { 1200 1198 u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1201 1199 struct amdgpu_usermode_queue *queue; 1202 1202 - struct amdgpu_userq_mgr *uqm, *tmp; 1203 1203 - int queue_id; 1200 1200 + struct amdgpu_userq_mgr *uqm; 1201 1201 + unsigned long queue_id; 1204 1202 int ret = 0, r; 1205 1203 1206 1204 /* only need to stop gfx/compute */ 1207 1205 if (!(ip_mask & ((1 << AMDGPU_HW_IP_GFX) | (1 << AMDGPU_HW_IP_COMPUTE)))) 1208 1206 return 0; 1209 1207 1210 1210 - mutex_lock(&adev->userq_mutex); 1211 1208 if (adev->userq_halt_for_enforce_isolation) 1212 1209 dev_warn(adev->dev, "userq scheduling already stopped!\n"); 1213 1210 adev->userq_halt_for_enforce_isolation = true; 1214 1214 - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 1211 1211 + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 1212 1212 + uqm = queue->userq_mgr; 1215 1213 cancel_delayed_work_sync(&uqm->resume_work); 1216 1214 mutex_lock(&uqm->userq_mutex); 1217 1217 - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 1218 1218 - if (((queue->queue_type == AMDGPU_HW_IP_GFX) || 1219 1219 - (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && 1220 1220 - (queue->xcp_id == idx)) { 1221 1221 - r = amdgpu_userq_preempt_helper(uqm, queue); 1222 1222 - if (r) 1223 1223 - ret = r; 1224 1224 - } 1215 1215 + if (((queue->queue_type == AMDGPU_HW_IP_GFX) || 1216 1216 + (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && 1217 1217 + (queue->xcp_id == idx)) { 1218 1218 + r = amdgpu_userq_preempt_helper(uqm, queue); 1219 1219 + if (r) 1220 1220 + ret = r; 1225 1221 } 1226 1222 mutex_unlock(&uqm->userq_mutex); 1227 1223 } 1228 1228 - mutex_unlock(&adev->userq_mutex); 1224 1224 + 1229 1225 return ret; 1230 1226 } 1231 1227 ··· 1232 1232 { 1233 1233 u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1234 1234 struct amdgpu_usermode_queue *queue; 1235 1235 - struct amdgpu_userq_mgr *uqm, *tmp; 1236 1236 - int queue_id; 1235 1235 + struct amdgpu_userq_mgr *uqm; 1236 1236 + unsigned long queue_id; 1237 1237 int ret = 0, r; 1238 1238 1239 1239 /* only need to stop gfx/compute */ 1240 1240 if (!(ip_mask & ((1 << AMDGPU_HW_IP_GFX) | (1 << AMDGPU_HW_IP_COMPUTE)))) 1241 1241 return 0; 1242 1242 1243 1243 - mutex_lock(&adev->userq_mutex); 1244 1243 if (!adev->userq_halt_for_enforce_isolation) 1245 1244 dev_warn(adev->dev, "userq scheduling already started!\n"); 1246 1245 adev->userq_halt_for_enforce_isolation = false; 1247 1247 - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 1246 1246 + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 1247 1247 + uqm = queue->userq_mgr; 1248 1248 mutex_lock(&uqm->userq_mutex); 1249 1249 - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 1250 1249 if (((queue->queue_type == AMDGPU_HW_IP_GFX) || 1251 1250 (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && 1252 1251 (queue->xcp_id == idx)) { ··· 1253 1254 if (r) 1254 1255 ret = r; 1255 1256 } 1256 1256 - } 1257 1257 mutex_unlock(&uqm->userq_mutex); 1258 1258 } 1259 1259 - mutex_unlock(&adev->userq_mutex); 1259 1259 + 1260 1260 return ret; 1261 1261 } 1262 1262

+6 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h

reviewed

··· 96 96 97 97 /* Usermode queues for gfx */ 98 98 struct amdgpu_userq_mgr { 99 99 - struct idr userq_idr; 99 99 + /** 100 100 + * @userq_mgr_xa: Per-process user queue map (queue ID → queue) 101 101 + * Key: queue_id (unique ID within the process's userq manager) 102 102 + * Value: struct amdgpu_usermode_queue 103 103 + */ 104 104 + struct xarray userq_mgr_xa; 100 105 struct mutex userq_mutex; 101 106 struct amdgpu_device *adev; 102 107 struct delayed_work resume_work; 103 103 - struct list_head list; 104 108 struct drm_file *file; 105 109 }; 106 110

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c

reviewed

··· 537 537 } 538 538 539 539 /* Retrieve the user queue */ 540 540 - queue = idr_find(&userq_mgr->userq_idr, args->queue_id); 540 540 + queue = xa_load(&userq_mgr->userq_mgr_xa, args->queue_id); 541 541 if (!queue) { 542 542 r = -ENOENT; 543 543 goto put_gobj_write; ··· 899 899 */ 900 900 num_fences = dma_fence_dedup_array(fences, num_fences); 901 901 902 902 - waitq = idr_find(&userq_mgr->userq_idr, wait_info->waitq_id); 902 902 + waitq = xa_load(&userq_mgr->userq_mgr_xa, wait_info->waitq_id); 903 903 if (!waitq) { 904 904 r = -EINVAL; 905 905 goto free_fences;

+6 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

reviewed

··· 937 937 int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) 938 938 { 939 939 struct amd_sriov_msg_init_data_header *init_data_hdr = NULL; 940 940 - uint32_t init_hdr_offset = adev->virt.init_data_header.offset; 941 941 - uint32_t init_hdr_size = adev->virt.init_data_header.size_kb << 10; 942 942 - uint64_t vram_size; 940 940 + u64 init_hdr_offset = adev->virt.init_data_header.offset; 941 941 + u64 init_hdr_size = (u64)adev->virt.init_data_header.size_kb << 10; /* KB → bytes */ 942 942 + u64 vram_size; 943 943 + u64 end; 943 944 int r = 0; 944 945 uint8_t checksum = 0; 945 946 ··· 958 957 return -EINVAL; 959 958 vram_size <<= 20; 960 959 961 961 - if ((init_hdr_offset + init_hdr_size) > vram_size) { 960 960 + if (check_add_overflow(init_hdr_offset, init_hdr_size, &end) || end > vram_size) { 962 961 dev_err(adev->dev, "init_data_header exceeds VRAM size, exiting\n"); 963 962 return -EINVAL; 964 963 } ··· 1102 1101 } 1103 1102 1104 1103 int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, 1105 1105 - int data_id, uint8_t *binary, uint64_t *size) 1104 1104 + int data_id, uint8_t *binary, u32 *size) 1106 1105 { 1107 1106 uint32_t data_offset = 0; 1108 1107 uint32_t data_size = 0;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

reviewed

··· 443 443 444 444 int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); 445 445 int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, 446 446 - int data_id, uint8_t *binary, uint64_t *size); 446 446 + int data_id, uint8_t *binary, u32 *size); 447 447 448 448 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 449 449 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);

+30 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

reviewed

··· 322 322 return 0; 323 323 } 324 324 325 325 + static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev) 326 326 + { 327 327 + switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 328 328 + case IP_VERSION(6, 1, 1): 329 329 + return adev->pm.fw_version < 0x0a640500; 330 330 + default: 331 331 + return false; 332 332 + } 333 333 + } 334 334 + 335 335 + static int vpe_get_dpm_level(struct amdgpu_device *adev) 336 336 + { 337 337 + struct amdgpu_vpe *vpe = &adev->vpe; 338 338 + 339 339 + if (!adev->pm.dpm_enabled) 340 340 + return 0; 341 341 + 342 342 + return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv)); 343 343 + } 344 344 + 325 345 static void vpe_idle_work_handler(struct work_struct *work) 326 346 { 327 347 struct amdgpu_device *adev = ··· 349 329 unsigned int fences = 0; 350 330 351 331 fences += amdgpu_fence_count_emitted(&adev->vpe.ring); 332 332 + if (fences) 333 333 + goto reschedule; 352 334 353 353 - if (fences == 0) 354 354 - amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 355 355 - else 356 356 - schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 335 335 + if (vpe_need_dpm0_at_power_down(adev) && vpe_get_dpm_level(adev) != 0) 336 336 + goto reschedule; 337 337 + 338 338 + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 339 339 + return; 340 340 + 341 341 + reschedule: 342 342 + schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 357 343 } 358 344 359 345 static int vpe_common_init(struct amdgpu_vpe *vpe)

+1 -1

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: MIT 2 2 /* 3 3 * Copyright 2018 Advanced Micro Devices, Inc. 4 4 *

+4

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

reviewed

··· 1843 1843 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1844 1844 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1845 1845 1846 1846 + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && 1847 1847 + adev->rev_id == 0x3) 1848 1848 + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1849 1849 + 1846 1850 if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { 1847 1851 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 1848 1852 adev->gmc.vram_vendor = vram_info & 0xF;

+24 -17

drivers/gpu/drm/amd/amdgpu/mes_userqueue.c

reviewed

··· 205 205 int db_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); 206 206 struct mes_detect_and_reset_queue_input input; 207 207 struct amdgpu_usermode_queue *queue; 208 208 - struct amdgpu_userq_mgr *uqm, *tmp; 209 208 unsigned int hung_db_num = 0; 210 210 - int queue_id, r, i; 209 209 + unsigned long queue_id; 211 210 u32 db_array[8]; 211 211 + int r, i; 212 212 213 213 if (db_array_size > 8) { 214 214 dev_err(adev->dev, "DB array size (%d vs 8) too small\n", ··· 227 227 if (r) { 228 228 dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); 229 229 } else if (hung_db_num) { 230 230 - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 231 231 - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 232 232 - if (queue->queue_type == queue_type) { 233 233 - for (i = 0; i < hung_db_num; i++) { 234 234 - if (queue->doorbell_index == db_array[i]) { 235 235 - queue->state = AMDGPU_USERQ_STATE_HUNG; 236 236 - atomic_inc(&adev->gpu_reset_counter); 237 237 - amdgpu_userq_fence_driver_force_completion(queue); 238 238 - drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 239 239 - } 230 230 + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 231 231 + if (queue->queue_type == queue_type) { 232 232 + for (i = 0; i < hung_db_num; i++) { 233 233 + if (queue->doorbell_index == db_array[i]) { 234 234 + queue->state = AMDGPU_USERQ_STATE_HUNG; 235 235 + atomic_inc(&adev->gpu_reset_counter); 236 236 + amdgpu_userq_fence_driver_force_completion(queue); 237 237 + drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 240 238 } 241 239 } 242 240 } ··· 252 254 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 253 255 struct drm_amdgpu_userq_in *mqd_user = args_in; 254 256 struct amdgpu_mqd_prop *userq_props; 255 255 - struct amdgpu_gfx_shadow_info shadow_info; 256 257 int r; 257 258 258 259 /* Structure to initialize MQD for userqueue using generic MQD init function */ ··· 277 280 userq_props->doorbell_index = queue->doorbell_index; 278 281 userq_props->fence_address = queue->fence_drv->gpu_addr; 279 282 280 280 - if (adev->gfx.funcs->get_gfx_shadow_info) 281 281 - adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 282 283 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 283 284 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 284 285 ··· 294 299 } 295 300 296 301 r = amdgpu_userq_input_va_validate(queue, compute_mqd->eop_va, 297 297 - max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE)); 302 302 + 2048); 298 303 if (r) 299 304 goto free_mqd; 300 305 ··· 307 312 kfree(compute_mqd); 308 313 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 309 314 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 315 315 + struct amdgpu_gfx_shadow_info shadow_info; 316 316 + 317 317 + if (adev->gfx.funcs->get_gfx_shadow_info) { 318 318 + adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 319 319 + } else { 320 320 + r = -EINVAL; 321 321 + goto free_mqd; 322 322 + } 310 323 311 324 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 312 325 DRM_ERROR("Invalid GFX MQD\n"); ··· 338 335 shadow_info.shadow_size); 339 336 if (r) 340 337 goto free_mqd; 338 338 + r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->csa_va, 339 339 + shadow_info.csa_size); 340 340 + if (r) 341 341 + goto free_mqd; 341 342 342 343 kfree(mqd_gfx_v11); 343 344 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { ··· 360 353 goto free_mqd; 361 354 } 362 355 r = amdgpu_userq_input_va_validate(queue, mqd_sdma_v11->csa_va, 363 363 - shadow_info.csa_size); 356 356 + 32); 364 357 if (r) 365 358 goto free_mqd; 366 359

+13 -11

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

reviewed

··· 41 41 42 42 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) 43 43 { 44 44 - u32 tmp; 44 44 + u32 rev_id; 45 45 46 46 - tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); 47 47 - /* If it is VF or subrevision holds a non-zero value, that should be used */ 48 48 - if (tmp || amdgpu_sriov_vf(adev)) 49 49 - return tmp; 46 46 + /* 47 47 + * fetch the sub-revision field from the IP-discovery table 48 48 + * (returns zero if the table entry is not populated). 49 49 + */ 50 50 + if (amdgpu_sriov_vf(adev)) { 51 51 + rev_id = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); 52 52 + } else { 53 53 + rev_id = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 54 54 + rev_id = REG_GET_FIELD(rev_id, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, 55 55 + STRAP_ATI_REV_ID_DEV0_F0); 56 56 + } 50 57 51 51 - /* If discovery subrev is not updated, use register version */ 52 52 - tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 53 53 - tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, 54 54 - STRAP_ATI_REV_ID_DEV0_F0); 55 55 - 56 56 - return tmp; 58 58 + return rev_id; 57 59 } 58 60 59 61 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)

+6 -3

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

reviewed

··· 1897 1897 1898 1898 static int stop_cpsch(struct device_queue_manager *dqm) 1899 1899 { 1900 1900 + int ret = 0; 1901 1901 + 1900 1902 dqm_lock(dqm); 1901 1903 if (!dqm->sched_running) { 1902 1904 dqm_unlock(dqm); ··· 1906 1904 } 1907 1905 1908 1906 if (!dqm->dev->kfd->shared_resources.enable_mes) 1909 1909 - unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 1907 1907 + ret = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 1908 1908 + 0, USE_DEFAULT_GRACE_PERIOD, false); 1910 1909 else 1911 1911 - remove_all_kfd_queues_mes(dqm); 1910 1910 + ret = remove_all_kfd_queues_mes(dqm); 1912 1911 1913 1912 dqm->sched_running = false; 1914 1913 ··· 1923 1920 dqm->detect_hang_info = NULL; 1924 1921 dqm_unlock(dqm); 1925 1922 1926 1926 - return 0; 1923 1923 + return ret; 1927 1924 } 1928 1925 1929 1926 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,

+8 -4

drivers/gpu/drm/amd/amdkfd/kfd_process.c

reviewed

··· 1083 1083 * for auto suspend 1084 1084 */ 1085 1085 if (pdd->runtime_inuse) { 1086 1086 - pm_runtime_mark_last_busy(adev_to_drm(pdd->dev->adev)->dev); 1087 1086 pm_runtime_put_autosuspend(adev_to_drm(pdd->dev->adev)->dev); 1088 1087 pdd->runtime_inuse = false; 1089 1088 } ··· 1161 1162 release_work); 1162 1163 struct dma_fence *ef; 1163 1164 1164 1164 - kfd_process_dequeue_from_all_devices(p); 1165 1165 - pqm_uninit(&p->pqm); 1166 1166 - 1167 1165 /* 1168 1166 * If GPU in reset, user queues may still running, wait for reset complete. 1169 1167 */ ··· 1221 1225 1222 1226 cancel_delayed_work_sync(&p->eviction_work); 1223 1227 cancel_delayed_work_sync(&p->restore_work); 1228 1228 + 1229 1229 + /* 1230 1230 + * Dequeue and destroy user queues, it is not safe for GPU to access 1231 1231 + * system memory after mmu release notifier callback returns because 1232 1232 + * exit_mmap free process memory afterwards. 1233 1233 + */ 1234 1234 + kfd_process_dequeue_from_all_devices(p); 1235 1235 + pqm_uninit(&p->pqm); 1224 1236 1225 1237 for (i = 0; i < p->n_pdds; i++) { 1226 1238 struct kfd_process_device *pdd = p->pdds[i];

+9 -5

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

reviewed

··· 1738 1738 1739 1739 WRITE_ONCE(p->svms.faulting_task, current); 1740 1740 range = amdgpu_hmm_range_alloc(NULL); 1741 1741 - r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, 1742 1742 - readonly, owner, 1743 1743 - range); 1741 1741 + if (likely(range)) 1742 1742 + r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, 1743 1743 + readonly, owner, range); 1744 1744 + else 1745 1745 + r = -ENOMEM; 1744 1746 WRITE_ONCE(p->svms.faulting_task, NULL); 1745 1747 if (r) { 1746 1748 amdgpu_hmm_range_free(range); 1749 1749 + range = NULL; 1747 1750 pr_debug("failed %d to get svm range pages\n", r); 1748 1751 } 1749 1752 } else { ··· 1764 1761 svm_range_lock(prange); 1765 1762 1766 1763 /* Free backing memory of hmm_range if it was initialized 1767 1767 - * Overrride return value to TRY AGAIN only if prior returns 1764 1764 + * Override return value to TRY AGAIN only if prior returns 1768 1765 * were successful 1769 1766 */ 1770 1767 if (range && !amdgpu_hmm_range_valid(range) && !r) { ··· 1772 1769 r = -EAGAIN; 1773 1770 } 1774 1771 /* Free the hmm range */ 1775 1775 - amdgpu_hmm_range_free(range); 1772 1772 + if (range) 1773 1773 + amdgpu_hmm_range_free(range); 1776 1774 1777 1775 1778 1776 if (!r && !list_empty(&prange->child_list)) {

+175 -39

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

reviewed

··· 3853 3853 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3854 3854 aconnector->connector_id, aconnector->dc_sink, sink); 3855 3855 3856 3856 - guard(mutex)(&dev->mode_config.mutex); 3856 3856 + /* When polling, DRM has already locked the mutex for us. */ 3857 3857 + if (!drm_kms_helper_is_poll_worker()) 3858 3858 + mutex_lock(&dev->mode_config.mutex); 3857 3859 3858 3860 /* 3859 3861 * 1. Update status of the drm connector ··· 3918 3916 } 3919 3917 3920 3918 update_subconnector_property(aconnector); 3919 3919 + 3920 3920 + /* When polling, the mutex will be unlocked for us by DRM. */ 3921 3921 + if (!drm_kms_helper_is_poll_worker()) 3922 3922 + mutex_unlock(&dev->mode_config.mutex); 3921 3923 } 3922 3924 3923 3925 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) ··· 5206 5200 static void setup_backlight_device(struct amdgpu_display_manager *dm, 5207 5201 struct amdgpu_dm_connector *aconnector) 5208 5202 { 5203 5203 + struct amdgpu_dm_backlight_caps *caps; 5209 5204 struct dc_link *link = aconnector->dc_link; 5210 5205 int bl_idx = dm->num_of_edps; 5211 5206 ··· 5226 5219 dm->num_of_edps++; 5227 5220 5228 5221 update_connector_ext_caps(aconnector); 5222 5222 + caps = &dm->backlight_caps[aconnector->bl_idx]; 5223 5223 + 5224 5224 + /* Only offer ABM property when non-OLED and user didn't turn off by module parameter */ 5225 5225 + if (!caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) 5226 5226 + drm_object_attach_property(&aconnector->base.base, 5227 5227 + dm->adev->mode_info.abm_level_property, 5228 5228 + ABM_SYSFS_CONTROL); 5229 5229 } 5230 5230 5231 5231 static void amdgpu_set_panel_orientation(struct drm_connector *connector); ··· 7232 7218 return stream; 7233 7219 } 7234 7220 7221 7221 + /** 7222 7222 + * amdgpu_dm_connector_poll() - Poll a connector to see if it's connected to a display 7223 7223 + * 7224 7224 + * Used for connectors that don't support HPD (hotplug detection) 7225 7225 + * to periodically checked whether the connector is connected to a display. 7226 7226 + */ 7227 7227 + static enum drm_connector_status 7228 7228 + amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) 7229 7229 + { 7230 7230 + struct drm_connector *connector = &aconnector->base; 7231 7231 + struct drm_device *dev = connector->dev; 7232 7232 + struct amdgpu_device *adev = drm_to_adev(dev); 7233 7233 + struct dc_link *link = aconnector->dc_link; 7234 7234 + enum dc_connection_type conn_type = dc_connection_none; 7235 7235 + enum drm_connector_status status = connector_status_disconnected; 7236 7236 + 7237 7237 + /* When we determined the connection using DAC load detection, 7238 7238 + * do NOT poll the connector do detect disconnect because 7239 7239 + * that would run DAC load detection again which can cause 7240 7240 + * visible visual glitches. 7241 7241 + * 7242 7242 + * Only allow to poll such a connector again when forcing. 7243 7243 + */ 7244 7244 + if (!force && link->local_sink && link->type == dc_connection_dac_load) 7245 7245 + return connector->status; 7246 7246 + 7247 7247 + mutex_lock(&aconnector->hpd_lock); 7248 7248 + 7249 7249 + if (dc_link_detect_connection_type(aconnector->dc_link, &conn_type) && 7250 7250 + conn_type != dc_connection_none) { 7251 7251 + mutex_lock(&adev->dm.dc_lock); 7252 7252 + 7253 7253 + /* Only call full link detection when a sink isn't created yet, 7254 7254 + * ie. just when the display is plugged in, otherwise we risk flickering. 7255 7255 + */ 7256 7256 + if (link->local_sink || 7257 7257 + dc_link_detect(link, DETECT_REASON_HPD)) 7258 7258 + status = connector_status_connected; 7259 7259 + 7260 7260 + mutex_unlock(&adev->dm.dc_lock); 7261 7261 + } 7262 7262 + 7263 7263 + if (connector->status != status) { 7264 7264 + if (status == connector_status_disconnected) { 7265 7265 + if (link->local_sink) 7266 7266 + dc_sink_release(link->local_sink); 7267 7267 + 7268 7268 + link->local_sink = NULL; 7269 7269 + link->dpcd_sink_count = 0; 7270 7270 + link->type = dc_connection_none; 7271 7271 + } 7272 7272 + 7273 7273 + amdgpu_dm_update_connector_after_detect(aconnector); 7274 7274 + } 7275 7275 + 7276 7276 + mutex_unlock(&aconnector->hpd_lock); 7277 7277 + return status; 7278 7278 + } 7279 7279 + 7280 7280 + /** 7281 7281 + * amdgpu_dm_connector_detect() - Detect whether a DRM connector is connected to a display 7282 7282 + * 7283 7283 + * A connector is considered connected when it has a sink that is not NULL. 7284 7284 + * For connectors that support HPD (hotplug detection), the connection is 7285 7285 + * handled in the HPD interrupt. 7286 7286 + * For connectors that may not support HPD, such as analog connectors, 7287 7287 + * DRM will call this function repeatedly to poll them. 7288 7288 + * 7289 7289 + * Notes: 7290 7290 + * 1. This interface is NOT called in context of HPD irq. 7291 7291 + * 2. This interface *is called* in context of user-mode ioctl. Which 7292 7292 + * makes it a bad place for *any* MST-related activity. 7293 7293 + */ 7235 7294 static enum drm_connector_status 7236 7295 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 7237 7296 { 7238 7238 - bool connected; 7239 7297 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7240 7240 - 7241 7241 - /* 7242 7242 - * Notes: 7243 7243 - * 1. This interface is NOT called in context of HPD irq. 7244 7244 - * 2. This interface *is called* in context of user-mode ioctl. Which 7245 7245 - * makes it a bad place for *any* MST-related activity. 7246 7246 - */ 7247 7247 - 7248 7248 - if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 7249 7249 - !aconnector->fake_enable) 7250 7250 - connected = (aconnector->dc_sink != NULL); 7251 7251 - else 7252 7252 - connected = (aconnector->base.force == DRM_FORCE_ON || 7253 7253 - aconnector->base.force == DRM_FORCE_ON_DIGITAL); 7254 7298 7255 7299 update_subconnector_property(aconnector); 7256 7300 7257 7257 - return (connected ? connector_status_connected : 7301 7301 + if (aconnector->base.force == DRM_FORCE_ON || 7302 7302 + aconnector->base.force == DRM_FORCE_ON_DIGITAL) 7303 7303 + return connector_status_connected; 7304 7304 + else if (aconnector->base.force == DRM_FORCE_OFF) 7305 7305 + return connector_status_disconnected; 7306 7306 + 7307 7307 + /* Poll analog connectors and only when either 7308 7308 + * disconnected or connected to an analog display. 7309 7309 + */ 7310 7310 + if (drm_kms_helper_is_poll_worker() && 7311 7311 + dc_connector_supports_analog(aconnector->dc_link->link_id.id) && 7312 7312 + (!aconnector->dc_sink || aconnector->dc_sink->edid_caps.analog)) 7313 7313 + return amdgpu_dm_connector_poll(aconnector, force); 7314 7314 + 7315 7315 + return (aconnector->dc_sink ? connector_status_connected : 7258 7316 connector_status_disconnected); 7259 7317 } 7260 7318 ··· 7377 7291 } else if (property == adev->mode_info.underscan_property) { 7378 7292 dm_new_state->underscan_enable = val; 7379 7293 ret = 0; 7294 7294 + } else if (property == adev->mode_info.abm_level_property) { 7295 7295 + switch (val) { 7296 7296 + case ABM_SYSFS_CONTROL: 7297 7297 + dm_new_state->abm_sysfs_forbidden = false; 7298 7298 + break; 7299 7299 + case ABM_LEVEL_OFF: 7300 7300 + dm_new_state->abm_sysfs_forbidden = true; 7301 7301 + dm_new_state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 7302 7302 + break; 7303 7303 + default: 7304 7304 + dm_new_state->abm_sysfs_forbidden = true; 7305 7305 + dm_new_state->abm_level = val; 7306 7306 + }; 7307 7307 + ret = 0; 7380 7308 } 7381 7309 7382 7310 return ret; ··· 7432 7332 ret = 0; 7433 7333 } else if (property == adev->mode_info.underscan_property) { 7434 7334 *val = dm_state->underscan_enable; 7335 7335 + ret = 0; 7336 7336 + } else if (property == adev->mode_info.abm_level_property) { 7337 7337 + if (!dm_state->abm_sysfs_forbidden) 7338 7338 + *val = ABM_SYSFS_CONTROL; 7339 7339 + else 7340 7340 + *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? 7341 7341 + dm_state->abm_level : 0; 7435 7342 ret = 0; 7436 7343 } 7437 7344 ··· 7492 7385 return -EINVAL; 7493 7386 7494 7387 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 7495 7495 - to_dm_connector_state(connector->state)->abm_level = val ?: 7496 7496 - ABM_LEVEL_IMMEDIATE_DISABLE; 7388 7388 + if (to_dm_connector_state(connector->state)->abm_sysfs_forbidden) 7389 7389 + ret = -EBUSY; 7390 7390 + else 7391 7391 + to_dm_connector_state(connector->state)->abm_level = val ?: 7392 7392 + ABM_LEVEL_IMMEDIATE_DISABLE; 7497 7393 drm_modeset_unlock(&dev->mode_config.connection_mutex); 7394 7394 + 7395 7395 + if (ret) 7396 7396 + return ret; 7498 7397 7499 7398 drm_kms_helper_hotplug_event(dev); 7500 7399 ··· 8341 8228 return 0; 8342 8229 } 8343 8230 8344 8344 - static int to_drm_connector_type(enum signal_type st) 8231 8231 + static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) 8345 8232 { 8346 8233 switch (st) { 8347 8234 case SIGNAL_TYPE_HDMI_TYPE_A: ··· 8357 8244 return DRM_MODE_CONNECTOR_DisplayPort; 8358 8245 case SIGNAL_TYPE_DVI_DUAL_LINK: 8359 8246 case SIGNAL_TYPE_DVI_SINGLE_LINK: 8247 8247 + if (connector_id == CONNECTOR_ID_SINGLE_LINK_DVII || 8248 8248 + connector_id == CONNECTOR_ID_DUAL_LINK_DVII) 8249 8249 + return DRM_MODE_CONNECTOR_DVII; 8250 8250 + 8360 8251 return DRM_MODE_CONNECTOR_DVID; 8361 8252 case SIGNAL_TYPE_VIRTUAL: 8362 8253 return DRM_MODE_CONNECTOR_VIRTUAL; ··· 8412 8295 8413 8296 static struct drm_display_mode * 8414 8297 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 8415 8415 - char *name, 8298 8298 + const char *name, 8416 8299 int hdisplay, int vdisplay) 8417 8300 { 8418 8301 struct drm_device *dev = encoder->dev; ··· 8434 8317 8435 8318 } 8436 8319 8320 8320 + static const struct amdgpu_dm_mode_size { 8321 8321 + char name[DRM_DISPLAY_MODE_LEN]; 8322 8322 + int w; 8323 8323 + int h; 8324 8324 + } common_modes[] = { 8325 8325 + { "640x480", 640, 480}, 8326 8326 + { "800x600", 800, 600}, 8327 8327 + { "1024x768", 1024, 768}, 8328 8328 + { "1280x720", 1280, 720}, 8329 8329 + { "1280x800", 1280, 800}, 8330 8330 + {"1280x1024", 1280, 1024}, 8331 8331 + { "1440x900", 1440, 900}, 8332 8332 + {"1680x1050", 1680, 1050}, 8333 8333 + {"1600x1200", 1600, 1200}, 8334 8334 + {"1920x1080", 1920, 1080}, 8335 8335 + {"1920x1200", 1920, 1200} 8336 8336 + }; 8337 8337 + 8437 8338 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 8438 8339 struct drm_connector *connector) 8439 8340 { ··· 8462 8327 to_amdgpu_dm_connector(connector); 8463 8328 int i; 8464 8329 int n; 8465 8465 - struct mode_size { 8466 8466 - char name[DRM_DISPLAY_MODE_LEN]; 8467 8467 - int w; 8468 8468 - int h; 8469 8469 - } common_modes[] = { 8470 8470 - { "640x480", 640, 480}, 8471 8471 - { "800x600", 800, 600}, 8472 8472 - { "1024x768", 1024, 768}, 8473 8473 - { "1280x720", 1280, 720}, 8474 8474 - { "1280x800", 1280, 800}, 8475 8475 - {"1280x1024", 1280, 1024}, 8476 8476 - { "1440x900", 1440, 900}, 8477 8477 - {"1680x1050", 1680, 1050}, 8478 8478 - {"1600x1200", 1600, 1200}, 8479 8479 - {"1920x1080", 1920, 1080}, 8480 8480 - {"1920x1200", 1920, 1200} 8481 8481 - }; 8482 8330 8483 8331 if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && 8484 8332 (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) ··· 8662 8544 if (!(amdgpu_freesync_vid_mode && drm_edid)) 8663 8545 return; 8664 8546 8547 8547 + if (!amdgpu_dm_connector->dc_sink || amdgpu_dm_connector->dc_sink->edid_caps.analog || 8548 8548 + !dc_supports_vrr(amdgpu_dm_connector->dc_sink->ctx->dce_version)) 8549 8549 + return; 8550 8550 + 8665 8551 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 8666 8552 amdgpu_dm_connector->num_modes += 8667 8553 add_fs_modes(amdgpu_dm_connector); ··· 8689 8567 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 8690 8568 amdgpu_dm_connector->num_modes += 8691 8569 drm_add_modes_noedid(connector, 1920, 1080); 8570 8570 + 8571 8571 + if (amdgpu_dm_connector->dc_sink->edid_caps.analog) { 8572 8572 + /* Analog monitor connected by DAC load detection. 8573 8573 + * Add common modes. It will be up to the user to select one that works. 8574 8574 + */ 8575 8575 + for (int i = 0; i < ARRAY_SIZE(common_modes); i++) 8576 8576 + amdgpu_dm_connector->num_modes += drm_add_modes_noedid( 8577 8577 + connector, common_modes[i].w, common_modes[i].h); 8578 8578 + } 8692 8579 } else { 8693 8580 amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); 8694 8581 if (encoder) ··· 8765 8634 break; 8766 8635 case DRM_MODE_CONNECTOR_DVID: 8767 8636 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8637 8637 + break; 8638 8638 + case DRM_MODE_CONNECTOR_DVII: 8639 8639 + case DRM_MODE_CONNECTOR_VGA: 8640 8640 + aconnector->base.polled = 8641 8641 + DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 8768 8642 break; 8769 8643 default: 8770 8644 break; ··· 8972 8836 goto out_free; 8973 8837 } 8974 8838 8975 8975 - connector_type = to_drm_connector_type(link->connector_signal); 8839 8839 + connector_type = to_drm_connector_type(link->connector_signal, link->link_id.id); 8976 8840 8977 8841 res = drm_connector_init_with_ddc( 8978 8842 dm->ddev,

+1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

reviewed

··· 993 993 bool underscan_enable; 994 994 bool freesync_capable; 995 995 bool update_hdcp; 996 996 + bool abm_sysfs_forbidden; 996 997 uint8_t abm_level; 997 998 int vcpi_slots; 998 999 uint64_t pbn;

+18 -3

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

reviewed

··· 248 248 struct vblank_control_work *vblank_work = 249 249 container_of(work, struct vblank_control_work, work); 250 250 struct amdgpu_display_manager *dm = vblank_work->dm; 251 251 + struct amdgpu_device *adev = drm_to_adev(dm->ddev); 252 252 + int r; 251 253 252 254 mutex_lock(&dm->dc_lock); 253 255 ··· 279 277 280 278 if (dm->active_vblank_irq_count == 0) { 281 279 dc_post_update_surfaces_to_stream(dm->dc); 280 280 + 281 281 + r = amdgpu_dpm_pause_power_profile(adev, true); 282 282 + if (r) 283 283 + dev_warn(adev->dev, "failed to set default power profile mode\n"); 284 284 + 282 285 dc_allow_idle_optimizations(dm->dc, true); 286 286 + 287 287 + r = amdgpu_dpm_pause_power_profile(adev, false); 288 288 + if (r) 289 289 + dev_warn(adev->dev, "failed to restore the power profile mode\n"); 283 290 } 284 291 285 292 mutex_unlock(&dm->dc_lock); ··· 308 297 int irq_type; 309 298 int rc = 0; 310 299 311 311 - if (acrtc->otg_inst == -1) 312 312 - goto skip; 300 300 + if (enable && !acrtc->base.enabled) { 301 301 + drm_dbg_vbl(crtc->dev, 302 302 + "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n", 303 303 + acrtc->crtc_id, acrtc->base.enabled); 304 304 + return -EINVAL; 305 305 + } 313 306 314 307 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 315 308 ··· 398 383 return rc; 399 384 } 400 385 #endif 401 401 - skip: 386 386 + 402 387 if (amdgpu_in_reset(adev)) 403 388 return 0; 404 389

+3 -2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

reviewed

··· 759 759 int max_param_num = 11; 760 760 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 761 761 bool disable_hpd = false; 762 762 + bool supports_hpd = link->irq_source_hpd != DC_IRQ_SOURCE_INVALID; 762 763 bool valid_test_pattern = false; 763 764 uint8_t param_nums = 0; 764 765 /* init with default 80bit custom pattern */ ··· 851 850 * because it might have been disabled after a test pattern was set. 852 851 * AUX depends on HPD * sequence dependent, do not move! 853 852 */ 854 854 - if (!disable_hpd) 853 853 + if (supports_hpd && !disable_hpd) 855 854 dc_link_enable_hpd(link); 856 855 857 856 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; ··· 889 888 * Need disable interrupt to avoid SW driver disable DP output. This is 890 889 * done after the test pattern is set. 891 890 */ 892 892 - if (valid_test_pattern && disable_hpd) 891 891 + if (valid_test_pattern && supports_hpd && disable_hpd) 893 892 dc_link_disable_hpd(link); 894 893 895 894 kfree(wr_buf);

+2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

reviewed

··· 83 83 edid_caps->panel_patch.remove_sink_ext_caps = true; 84 84 break; 85 85 case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154): 86 86 + case drm_edid_encode_panel_id('S', 'D', 'C', 0x4171): 86 87 drm_dbg_driver(dev, "Disabling VSC on monitor with panel id %X\n", panel_id); 87 88 edid_caps->panel_patch.disable_colorimetry = true; 88 89 break; ··· 131 130 edid_caps->serial_number = edid_buf->serial; 132 131 edid_caps->manufacture_week = edid_buf->mfg_week; 133 132 edid_caps->manufacture_year = edid_buf->mfg_year; 133 133 + edid_caps->analog = !(edid_buf->input & DRM_EDID_INPUT_DIGITAL); 134 134 135 135 drm_edid_get_monitor_name(edid_buf, 136 136 edid_caps->display_name,

+17

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

reviewed

··· 476 476 477 477 void amdgpu_dm_irq_suspend(struct amdgpu_device *adev) 478 478 { 479 479 + struct drm_device *dev = adev_to_drm(adev); 479 480 int src; 480 481 struct list_head *hnd_list_h; 481 482 struct list_head *hnd_list_l; ··· 513 512 } 514 513 515 514 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); 515 515 + 516 516 + if (dev->mode_config.poll_enabled) 517 517 + drm_kms_helper_poll_disable(dev); 516 518 } 517 519 518 520 void amdgpu_dm_irq_resume_early(struct amdgpu_device *adev) ··· 541 537 542 538 void amdgpu_dm_irq_resume_late(struct amdgpu_device *adev) 543 539 { 540 540 + struct drm_device *dev = adev_to_drm(adev); 544 541 int src; 545 542 struct list_head *hnd_list_h, *hnd_list_l; 546 543 unsigned long irq_table_flags; ··· 562 557 } 563 558 564 559 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); 560 560 + 561 561 + if (dev->mode_config.poll_enabled) 562 562 + drm_kms_helper_poll_enable(dev); 565 563 } 566 564 567 565 /* ··· 901 893 struct drm_connector_list_iter iter; 902 894 int irq_type; 903 895 int i; 896 896 + bool use_polling = false; 904 897 905 898 /* First, clear all hpd and hpdrx interrupts */ 906 899 for (i = DC_IRQ_SOURCE_HPD1; i <= DC_IRQ_SOURCE_HPD6RX; i++) { ··· 914 905 drm_for_each_connector_iter(connector, &iter) { 915 906 struct amdgpu_dm_connector *amdgpu_dm_connector; 916 907 const struct dc_link *dc_link; 908 908 + 909 909 + use_polling |= connector->polled != DRM_CONNECTOR_POLL_HPD; 917 910 918 911 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 919 912 continue; ··· 958 947 } 959 948 } 960 949 drm_connector_list_iter_end(&iter); 950 950 + 951 951 + if (use_polling) 952 952 + drm_kms_helper_poll_init(dev); 961 953 } 962 954 963 955 /** ··· 1011 997 } 1012 998 } 1013 999 drm_connector_list_iter_end(&iter); 1000 1000 + 1001 1001 + if (dev->mode_config.poll_enabled) 1002 1002 + drm_kms_helper_poll_fini(dev); 1014 1003 }

+1 -1

drivers/gpu/drm/amd/display/dc/Makefile

reviewed

··· 36 36 DC_LIBS += dcn301 37 37 DC_LIBS += dcn31 38 38 DC_LIBS += dml 39 39 - DC_LIBS += dml2 39 39 + DC_LIBS += dml2_0 40 40 DC_LIBS += soc_and_ip_translator 41 41 endif 42 42

+89 -6

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

reviewed

··· 67 67 ATOM_OBJECT *object); 68 68 static struct device_id device_type_from_device_id(uint16_t device_id); 69 69 static uint32_t signal_to_ss_id(enum as_signal_type signal); 70 70 - static uint32_t get_support_mask_for_device_id(struct device_id device_id); 70 70 + static uint32_t get_support_mask_for_device_id( 71 71 + enum dal_device_type device_type, 72 72 + uint32_t enum_id); 71 73 static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record( 72 74 struct bios_parser *bp, 73 75 ATOM_OBJECT *object); ··· 443 441 le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10; 444 442 info->pll_info.max_output_pxl_clk_pll_frequency = 445 443 le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10; 444 444 + info->max_pixel_clock = le16_to_cpu(firmware_info->usMaxPixelClock) * 10; 446 445 447 446 if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support) 448 447 /* Since there is no information on the SS, report conservative ··· 500 497 info->external_clock_source_frequency_for_dp = 501 498 le16_to_cpu(firmwareInfo->usUniphyDPModeExtClkFreq) * 10; 502 499 info->min_allowed_bl_level = firmwareInfo->ucMinAllowedBL_Level; 500 500 + info->max_pixel_clock = le16_to_cpu(firmwareInfo->usMaxPixelClock) * 10; 503 501 504 502 /* There should be only one entry in the SS info table for Memory Clock 505 503 */ ··· 740 736 return bp->cmd_tbl.transmitter_control(bp, cntl); 741 737 } 742 738 739 739 + static enum bp_result bios_parser_select_crtc_source( 740 740 + struct dc_bios *dcb, 741 741 + struct bp_crtc_source_select *bp_params) 742 742 + { 743 743 + struct bios_parser *bp = BP_FROM_DCB(dcb); 744 744 + 745 745 + if (!bp->cmd_tbl.select_crtc_source) 746 746 + return BP_RESULT_FAILURE; 747 747 + 748 748 + return bp->cmd_tbl.select_crtc_source(bp, bp_params); 749 749 + } 750 750 + 743 751 static enum bp_result bios_parser_encoder_control( 744 752 struct dc_bios *dcb, 745 753 struct bp_encoder_control *cntl) 746 754 { 747 755 struct bios_parser *bp = BP_FROM_DCB(dcb); 748 756 757 757 + if (cntl->engine_id == ENGINE_ID_DACA) { 758 758 + if (!bp->cmd_tbl.dac1_encoder_control) 759 759 + return BP_RESULT_FAILURE; 760 760 + 761 761 + return bp->cmd_tbl.dac1_encoder_control( 762 762 + bp, cntl->action == ENCODER_CONTROL_ENABLE, 763 763 + cntl->pixel_clock, ATOM_DAC1_PS2); 764 764 + } else if (cntl->engine_id == ENGINE_ID_DACB) { 765 765 + if (!bp->cmd_tbl.dac2_encoder_control) 766 766 + return BP_RESULT_FAILURE; 767 767 + 768 768 + return bp->cmd_tbl.dac2_encoder_control( 769 769 + bp, cntl->action == ENCODER_CONTROL_ENABLE, 770 770 + cntl->pixel_clock, ATOM_DAC1_PS2); 771 771 + } 772 772 + 749 773 if (!bp->cmd_tbl.dig_encoder_control) 750 774 return BP_RESULT_FAILURE; 751 775 752 776 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 777 777 + } 778 778 + 779 779 + static enum bp_result bios_parser_dac_load_detection( 780 780 + struct dc_bios *dcb, 781 781 + enum engine_id engine_id, 782 782 + enum dal_device_type device_type, 783 783 + uint32_t enum_id) 784 784 + { 785 785 + struct bios_parser *bp = BP_FROM_DCB(dcb); 786 786 + struct dc_context *ctx = dcb->ctx; 787 787 + struct bp_load_detection_parameters bp_params = {0}; 788 788 + enum bp_result bp_result; 789 789 + uint32_t bios_0_scratch; 790 790 + uint32_t device_id_mask = 0; 791 791 + 792 792 + bp_params.engine_id = engine_id; 793 793 + bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id); 794 794 + 795 795 + if (engine_id != ENGINE_ID_DACA && 796 796 + engine_id != ENGINE_ID_DACB) 797 797 + return BP_RESULT_UNSUPPORTED; 798 798 + 799 799 + if (!bp->cmd_tbl.dac_load_detection) 800 800 + return BP_RESULT_UNSUPPORTED; 801 801 + 802 802 + if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) 803 803 + device_id_mask = ATOM_S0_CRT1_MASK; 804 804 + else if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) 805 805 + device_id_mask = ATOM_S0_CRT2_MASK; 806 806 + else 807 807 + return BP_RESULT_UNSUPPORTED; 808 808 + 809 809 + /* BIOS will write the detected devices to BIOS_SCRATCH_0, clear corresponding bit */ 810 810 + bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); 811 811 + bios_0_scratch &= ~device_id_mask; 812 812 + dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch); 813 813 + 814 814 + bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); 815 815 + 816 816 + if (bp_result != BP_RESULT_OK) 817 817 + return bp_result; 818 818 + 819 819 + bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); 820 820 + 821 821 + if (bios_0_scratch & device_id_mask) 822 822 + return BP_RESULT_OK; 823 823 + 824 824 + return BP_RESULT_FAILURE; 753 825 } 754 826 755 827 static enum bp_result bios_parser_adjust_pixel_clock( ··· 938 858 { 939 859 struct bios_parser *bp = BP_FROM_DCB(dcb); 940 860 941 941 - uint32_t mask = get_support_mask_for_device_id(id); 861 861 + uint32_t mask = get_support_mask_for_device_id(id.device_type, id.enum_id); 942 862 943 863 return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0; 944 864 } ··· 2229 2149 return clk_id_ss; 2230 2150 } 2231 2151 2232 2232 - static uint32_t get_support_mask_for_device_id(struct device_id device_id) 2152 2152 + static uint32_t get_support_mask_for_device_id( 2153 2153 + enum dal_device_type device_type, 2154 2154 + uint32_t enum_id) 2233 2155 { 2234 2234 - enum dal_device_type device_type = device_id.device_type; 2235 2235 - uint32_t enum_id = device_id.enum_id; 2236 2236 - 2237 2156 switch (device_type) { 2238 2157 case DEVICE_TYPE_LCD: 2239 2158 switch (enum_id) { ··· 2908 2829 .is_device_id_supported = bios_parser_is_device_id_supported, 2909 2830 2910 2831 /* COMMANDS */ 2832 2832 + .select_crtc_source = bios_parser_select_crtc_source, 2833 2833 + 2911 2834 .encoder_control = bios_parser_encoder_control, 2835 2835 + 2836 2836 + .dac_load_detection = bios_parser_dac_load_detection, 2912 2837 2913 2838 .transmitter_control = bios_parser_transmitter_control, 2914 2839

+286

drivers/gpu/drm/amd/display/dc/bios/command_table.c

reviewed

··· 52 52 static void init_set_pixel_clock(struct bios_parser *bp); 53 53 static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp); 54 54 static void init_adjust_display_pll(struct bios_parser *bp); 55 55 + static void init_select_crtc_source(struct bios_parser *bp); 55 56 static void init_dac_encoder_control(struct bios_parser *bp); 57 57 + static void init_dac_load_detection(struct bios_parser *bp); 56 58 static void init_dac_output_control(struct bios_parser *bp); 57 59 static void init_set_crtc_timing(struct bios_parser *bp); 58 60 static void init_enable_crtc(struct bios_parser *bp); ··· 71 69 init_set_pixel_clock(bp); 72 70 init_enable_spread_spectrum_on_ppll(bp); 73 71 init_adjust_display_pll(bp); 72 72 + init_select_crtc_source(bp); 74 73 init_dac_encoder_control(bp); 74 74 + init_dac_load_detection(bp); 75 75 init_dac_output_control(bp); 76 76 init_set_crtc_timing(bp); 77 77 init_enable_crtc(bp); ··· 1616 1612 /******************************************************************************* 1617 1613 ******************************************************************************** 1618 1614 ** 1615 1615 + ** SELECT CRTC SOURCE 1616 1616 + ** 1617 1617 + ******************************************************************************** 1618 1618 + *******************************************************************************/ 1619 1619 + 1620 1620 + static enum bp_result select_crtc_source_v1( 1621 1621 + struct bios_parser *bp, 1622 1622 + struct bp_crtc_source_select *bp_params); 1623 1623 + static enum bp_result select_crtc_source_v2( 1624 1624 + struct bios_parser *bp, 1625 1625 + struct bp_crtc_source_select *bp_params); 1626 1626 + static enum bp_result select_crtc_source_v3( 1627 1627 + struct bios_parser *bp, 1628 1628 + struct bp_crtc_source_select *bp_params); 1629 1629 + 1630 1630 + static void init_select_crtc_source(struct bios_parser *bp) 1631 1631 + { 1632 1632 + switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) { 1633 1633 + case 1: 1634 1634 + bp->cmd_tbl.select_crtc_source = select_crtc_source_v1; 1635 1635 + break; 1636 1636 + case 2: 1637 1637 + bp->cmd_tbl.select_crtc_source = select_crtc_source_v2; 1638 1638 + break; 1639 1639 + case 3: 1640 1640 + bp->cmd_tbl.select_crtc_source = select_crtc_source_v3; 1641 1641 + break; 1642 1642 + default: 1643 1643 + bp->cmd_tbl.select_crtc_source = NULL; 1644 1644 + break; 1645 1645 + } 1646 1646 + } 1647 1647 + 1648 1648 + static enum bp_result select_crtc_source_v1( 1649 1649 + struct bios_parser *bp, 1650 1650 + struct bp_crtc_source_select *bp_params) 1651 1651 + { 1652 1652 + enum bp_result result = BP_RESULT_FAILURE; 1653 1653 + SELECT_CRTC_SOURCE_PS_ALLOCATION params; 1654 1654 + 1655 1655 + if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &params.ucCRTC)) 1656 1656 + return BP_RESULT_BADINPUT; 1657 1657 + 1658 1658 + switch (bp_params->engine_id) { 1659 1659 + case ENGINE_ID_DACA: 1660 1660 + params.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1661 1661 + break; 1662 1662 + case ENGINE_ID_DACB: 1663 1663 + params.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1664 1664 + break; 1665 1665 + default: 1666 1666 + return BP_RESULT_BADINPUT; 1667 1667 + } 1668 1668 + 1669 1669 + if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) 1670 1670 + result = BP_RESULT_OK; 1671 1671 + 1672 1672 + return result; 1673 1673 + } 1674 1674 + 1675 1675 + static bool select_crtc_source_v2_encoder_id( 1676 1676 + enum engine_id engine_id, uint8_t *out_encoder_id) 1677 1677 + { 1678 1678 + uint8_t encoder_id = 0; 1679 1679 + 1680 1680 + switch (engine_id) { 1681 1681 + case ENGINE_ID_DIGA: 1682 1682 + encoder_id = ASIC_INT_DIG1_ENCODER_ID; 1683 1683 + break; 1684 1684 + case ENGINE_ID_DIGB: 1685 1685 + encoder_id = ASIC_INT_DIG2_ENCODER_ID; 1686 1686 + break; 1687 1687 + case ENGINE_ID_DIGC: 1688 1688 + encoder_id = ASIC_INT_DIG3_ENCODER_ID; 1689 1689 + break; 1690 1690 + case ENGINE_ID_DIGD: 1691 1691 + encoder_id = ASIC_INT_DIG4_ENCODER_ID; 1692 1692 + break; 1693 1693 + case ENGINE_ID_DIGE: 1694 1694 + encoder_id = ASIC_INT_DIG5_ENCODER_ID; 1695 1695 + break; 1696 1696 + case ENGINE_ID_DIGF: 1697 1697 + encoder_id = ASIC_INT_DIG6_ENCODER_ID; 1698 1698 + break; 1699 1699 + case ENGINE_ID_DIGG: 1700 1700 + encoder_id = ASIC_INT_DIG7_ENCODER_ID; 1701 1701 + break; 1702 1702 + case ENGINE_ID_DACA: 1703 1703 + encoder_id = ASIC_INT_DAC1_ENCODER_ID; 1704 1704 + break; 1705 1705 + case ENGINE_ID_DACB: 1706 1706 + encoder_id = ASIC_INT_DAC2_ENCODER_ID; 1707 1707 + break; 1708 1708 + default: 1709 1709 + return false; 1710 1710 + } 1711 1711 + 1712 1712 + *out_encoder_id = encoder_id; 1713 1713 + return true; 1714 1714 + } 1715 1715 + 1716 1716 + static bool select_crtc_source_v2_encoder_mode( 1717 1717 + enum signal_type signal_type, uint8_t *out_encoder_mode) 1718 1718 + { 1719 1719 + uint8_t encoder_mode = 0; 1720 1720 + 1721 1721 + switch (signal_type) { 1722 1722 + case SIGNAL_TYPE_DVI_SINGLE_LINK: 1723 1723 + case SIGNAL_TYPE_DVI_DUAL_LINK: 1724 1724 + encoder_mode = ATOM_ENCODER_MODE_DVI; 1725 1725 + break; 1726 1726 + case SIGNAL_TYPE_HDMI_TYPE_A: 1727 1727 + encoder_mode = ATOM_ENCODER_MODE_HDMI; 1728 1728 + break; 1729 1729 + case SIGNAL_TYPE_LVDS: 1730 1730 + encoder_mode = ATOM_ENCODER_MODE_LVDS; 1731 1731 + break; 1732 1732 + case SIGNAL_TYPE_RGB: 1733 1733 + encoder_mode = ATOM_ENCODER_MODE_CRT; 1734 1734 + break; 1735 1735 + case SIGNAL_TYPE_DISPLAY_PORT: 1736 1736 + encoder_mode = ATOM_ENCODER_MODE_DP; 1737 1737 + break; 1738 1738 + case SIGNAL_TYPE_DISPLAY_PORT_MST: 1739 1739 + encoder_mode = ATOM_ENCODER_MODE_DP_MST; 1740 1740 + break; 1741 1741 + case SIGNAL_TYPE_EDP: 1742 1742 + encoder_mode = ATOM_ENCODER_MODE_DP; 1743 1743 + break; 1744 1744 + default: 1745 1745 + return false; 1746 1746 + } 1747 1747 + 1748 1748 + *out_encoder_mode = encoder_mode; 1749 1749 + return true; 1750 1750 + } 1751 1751 + 1752 1752 + static enum bp_result select_crtc_source_v2( 1753 1753 + struct bios_parser *bp, 1754 1754 + struct bp_crtc_source_select *bp_params) 1755 1755 + { 1756 1756 + enum bp_result result = BP_RESULT_FAILURE; 1757 1757 + SELECT_CRTC_SOURCE_PARAMETERS_V3 params; 1758 1758 + 1759 1759 + if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &params.ucCRTC)) 1760 1760 + return BP_RESULT_BADINPUT; 1761 1761 + 1762 1762 + if (!select_crtc_source_v2_encoder_id( 1763 1763 + bp_params->engine_id, 1764 1764 + &params.ucEncoderID)) 1765 1765 + return BP_RESULT_BADINPUT; 1766 1766 + if (!select_crtc_source_v2_encoder_mode( 1767 1767 + bp_params->sink_signal, 1768 1768 + &params.ucEncodeMode)) 1769 1769 + return BP_RESULT_BADINPUT; 1770 1770 + 1771 1771 + if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) 1772 1772 + result = BP_RESULT_OK; 1773 1773 + 1774 1774 + return result; 1775 1775 + } 1776 1776 + 1777 1777 + static enum bp_result select_crtc_source_v3( 1778 1778 + struct bios_parser *bp, 1779 1779 + struct bp_crtc_source_select *bp_params) 1780 1780 + { 1781 1781 + enum bp_result result = BP_RESULT_FAILURE; 1782 1782 + SELECT_CRTC_SOURCE_PARAMETERS_V3 params; 1783 1783 + 1784 1784 + if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &params.ucCRTC)) 1785 1785 + return BP_RESULT_BADINPUT; 1786 1786 + 1787 1787 + if (!select_crtc_source_v2_encoder_id( 1788 1788 + bp_params->engine_id, 1789 1789 + &params.ucEncoderID)) 1790 1790 + return BP_RESULT_BADINPUT; 1791 1791 + if (!select_crtc_source_v2_encoder_mode( 1792 1792 + bp_params->sink_signal, 1793 1793 + &params.ucEncodeMode)) 1794 1794 + return BP_RESULT_BADINPUT; 1795 1795 + 1796 1796 + params.ucDstBpc = bp_params->bit_depth; 1797 1797 + 1798 1798 + if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) 1799 1799 + result = BP_RESULT_OK; 1800 1800 + 1801 1801 + return result; 1802 1802 + } 1803 1803 + 1804 1804 + /******************************************************************************* 1805 1805 + ******************************************************************************** 1806 1806 + ** 1619 1807 ** DAC ENCODER CONTROL 1620 1808 ** 1621 1809 ******************************************************************************** ··· 1899 1703 dac_standard); 1900 1704 1901 1705 if (EXEC_BIOS_CMD_TABLE(DAC2EncoderControl, params)) 1706 1706 + result = BP_RESULT_OK; 1707 1707 + 1708 1708 + return result; 1709 1709 + } 1710 1710 + 1711 1711 + /******************************************************************************* 1712 1712 + ******************************************************************************** 1713 1713 + ** 1714 1714 + ** DAC LOAD DETECTION 1715 1715 + ** 1716 1716 + ******************************************************************************** 1717 1717 + *******************************************************************************/ 1718 1718 + 1719 1719 + static enum bp_result dac_load_detection_v1( 1720 1720 + struct bios_parser *bp, 1721 1721 + struct bp_load_detection_parameters *bp_params); 1722 1722 + 1723 1723 + static enum bp_result dac_load_detection_v3( 1724 1724 + struct bios_parser *bp, 1725 1725 + struct bp_load_detection_parameters *bp_params); 1726 1726 + 1727 1727 + static void init_dac_load_detection(struct bios_parser *bp) 1728 1728 + { 1729 1729 + switch (BIOS_CMD_TABLE_PARA_REVISION(DAC_LoadDetection)) { 1730 1730 + case 1: 1731 1731 + case 2: 1732 1732 + bp->cmd_tbl.dac_load_detection = dac_load_detection_v1; 1733 1733 + break; 1734 1734 + case 3: 1735 1735 + default: 1736 1736 + bp->cmd_tbl.dac_load_detection = dac_load_detection_v3; 1737 1737 + break; 1738 1738 + } 1739 1739 + } 1740 1740 + 1741 1741 + static void dac_load_detect_prepare_params( 1742 1742 + struct _DAC_LOAD_DETECTION_PS_ALLOCATION *params, 1743 1743 + enum engine_id engine_id, 1744 1744 + uint16_t device_id, 1745 1745 + uint8_t misc) 1746 1746 + { 1747 1747 + uint8_t dac_type = ENGINE_ID_DACA; 1748 1748 + 1749 1749 + if (engine_id == ENGINE_ID_DACB) 1750 1750 + dac_type = ATOM_DAC_B; 1751 1751 + 1752 1752 + params->sDacload.usDeviceID = cpu_to_le16(device_id); 1753 1753 + params->sDacload.ucDacType = dac_type; 1754 1754 + params->sDacload.ucMisc = misc; 1755 1755 + } 1756 1756 + 1757 1757 + static enum bp_result dac_load_detection_v1( 1758 1758 + struct bios_parser *bp, 1759 1759 + struct bp_load_detection_parameters *bp_params) 1760 1760 + { 1761 1761 + enum bp_result result = BP_RESULT_FAILURE; 1762 1762 + DAC_LOAD_DETECTION_PS_ALLOCATION params; 1763 1763 + 1764 1764 + dac_load_detect_prepare_params( 1765 1765 + &params, 1766 1766 + bp_params->engine_id, 1767 1767 + bp_params->device_id, 1768 1768 + 0); 1769 1769 + 1770 1770 + if (EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params)) 1771 1771 + result = BP_RESULT_OK; 1772 1772 + 1773 1773 + return result; 1774 1774 + } 1775 1775 + 1776 1776 + static enum bp_result dac_load_detection_v3( 1777 1777 + struct bios_parser *bp, 1778 1778 + struct bp_load_detection_parameters *bp_params) 1779 1779 + { 1780 1780 + enum bp_result result = BP_RESULT_FAILURE; 1781 1781 + DAC_LOAD_DETECTION_PS_ALLOCATION params; 1782 1782 + 1783 1783 + uint8_t misc = 0; 1784 1784 + 1785 1785 + if (bp_params->device_id == ATOM_DEVICE_CV_SUPPORT || 1786 1786 + bp_params->device_id == ATOM_DEVICE_TV1_SUPPORT) 1787 1787 + misc = DAC_LOAD_MISC_YPrPb; 1788 1788 + 1789 1789 + dac_load_detect_prepare_params( 1790 1790 + &params, 1791 1791 + bp_params->engine_id, 1792 1792 + bp_params->device_id, 1793 1793 + misc); 1794 1794 + 1795 1795 + if (EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params)) 1902 1796 result = BP_RESULT_OK; 1903 1797 1904 1798 return result;

+6

drivers/gpu/drm/amd/display/dc/bios/command_table.h

reviewed

··· 52 52 enum bp_result (*adjust_display_pll)( 53 53 struct bios_parser *bp, 54 54 struct bp_adjust_pixel_clock_parameters *bp_params); 55 55 + enum bp_result (*select_crtc_source)( 56 56 + struct bios_parser *bp, 57 57 + struct bp_crtc_source_select *bp_params); 55 58 enum bp_result (*dac1_encoder_control)( 56 59 struct bios_parser *bp, 57 60 bool enable, ··· 71 68 enum bp_result (*dac2_output_control)( 72 69 struct bios_parser *bp, 73 70 bool enable); 71 71 + enum bp_result (*dac_load_detection)( 72 72 + struct bios_parser *bp, 73 73 + struct bp_load_detection_parameters *bp_params); 74 74 enum bp_result (*set_crtc_timing)( 75 75 struct bios_parser *bp, 76 76 struct bp_hw_crtc_timing_parameters *bp_params);

+85 -2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

reviewed

··· 40 40 #include "dm_helpers.h" 41 41 42 42 #include "dc_dmub_srv.h" 43 43 - 43 43 + #include "reg_helper.h" 44 44 #include "logger_types.h" 45 45 #undef DC_LOGGER 46 46 #define DC_LOGGER \ ··· 48 48 49 49 #include "link_service.h" 50 50 51 51 + #define MAX_INSTANCE 7 52 52 + #define MAX_SEGMENT 8 53 53 + 54 54 + struct IP_BASE_INSTANCE { 55 55 + unsigned int segment[MAX_SEGMENT]; 56 56 + }; 57 57 + 58 58 + struct IP_BASE { 59 59 + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 60 60 + }; 61 61 + 62 62 + static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, 63 63 + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } }, 64 64 + { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } }, 65 65 + { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } }, 66 66 + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } }, 67 67 + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } } } }; 68 68 + 69 69 + #define regCLK1_CLK0_CURRENT_CNT 0x0314 70 70 + #define regCLK1_CLK0_CURRENT_CNT_BASE_IDX 0 71 71 + #define regCLK1_CLK1_CURRENT_CNT 0x0315 72 72 + #define regCLK1_CLK1_CURRENT_CNT_BASE_IDX 0 73 73 + #define regCLK1_CLK2_CURRENT_CNT 0x0316 74 74 + #define regCLK1_CLK2_CURRENT_CNT_BASE_IDX 0 75 75 + #define regCLK1_CLK3_CURRENT_CNT 0x0317 76 76 + #define regCLK1_CLK3_CURRENT_CNT_BASE_IDX 0 77 77 + #define regCLK1_CLK4_CURRENT_CNT 0x0318 78 78 + #define regCLK1_CLK4_CURRENT_CNT_BASE_IDX 0 79 79 + #define regCLK1_CLK5_CURRENT_CNT 0x0319 80 80 + #define regCLK1_CLK5_CURRENT_CNT_BASE_IDX 0 81 81 + 51 82 #define TO_CLK_MGR_DCN315(clk_mgr)\ 52 83 container_of(clk_mgr, struct clk_mgr_dcn315, base) 84 84 + 85 85 + #define REG(reg_name) \ 86 86 + (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 53 87 54 88 #define UNSUPPORTED_DCFCLK 10000000 55 89 #define MIN_DPP_DISP_CLK 100000 ··· 279 245 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 280 246 } 281 247 248 248 + static void dcn315_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base) 249 249 + { 250 250 + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 251 251 + 252 252 + // read dtbclk 253 253 + internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT); 254 254 + 255 255 + // read dcfclk 256 256 + internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); 257 257 + 258 258 + // read dppclk 259 259 + internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); 260 260 + 261 261 + // read dprefclk 262 262 + internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); 263 263 + 264 264 + // read dispclk 265 265 + internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); 266 266 + } 267 267 + 282 268 static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 283 269 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 284 270 { 271 271 + struct dcn35_clk_internal internal = {0}; 272 272 + 273 273 + dcn315_dump_clk_registers_internal(&internal, clk_mgr_base); 274 274 + 275 275 + regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 276 276 + regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; 277 277 + regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; 278 278 + regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 279 279 + regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; 285 280 return; 286 281 } 287 282 ··· 657 594 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 658 595 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 659 596 .update_clocks = dcn315_update_clocks, 660 660 - .init_clocks = dcn31_init_clocks, 597 597 + .init_clocks = dcn315_init_clocks, 661 598 .enable_pme_wa = dcn315_enable_pme_wa, 662 599 .are_clock_states_equal = dcn31_are_clock_states_equal, 663 600 .notify_wm_ranges = dcn315_notify_wm_ranges 664 601 }; 665 602 extern struct clk_mgr_funcs dcn3_fpga_funcs; 603 603 + 604 604 + void dcn315_init_clocks(struct clk_mgr *clk_mgr) 605 605 + { 606 606 + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); 607 607 + uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; 608 608 + struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr_int); 609 609 + struct clk_log_info log_info = {0}; 610 610 + 611 611 + memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 612 612 + // Assumption is that boot state always supports pstate 613 613 + clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk 614 614 + clk_mgr->clks.p_state_change_support = true; 615 615 + clk_mgr->clks.prev_p_state_change_support = true; 616 616 + clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; 617 617 + clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; 618 618 + 619 619 + dcn315_dump_clk_registers(&clk_mgr->boot_snapshot, &clk_mgr_dcn315->base.base, &log_info); 620 620 + clk_mgr->clks.dispclk_khz = clk_mgr->boot_snapshot.dispclk * 1000; 621 621 + } 666 622 667 623 void dcn315_clk_mgr_construct( 668 624 struct dc_context *ctx, ··· 743 661 /* Saved clocks configured at boot for debug purposes */ 744 662 dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, 745 663 &clk_mgr->base.base, &log_info); 664 664 + clk_mgr->base.base.clks.dispclk_khz = clk_mgr->base.base.boot_snapshot.dispclk * 1000; 746 665 747 666 clk_mgr->base.base.dprefclk_khz = 600000; 748 667 clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);

+1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

reviewed

··· 44 44 struct pp_smu_funcs *pp_smu, 45 45 struct dccg *dccg); 46 46 47 47 + void dcn315_init_clocks(struct clk_mgr *clk_mgr); 47 48 void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); 48 49 49 50 #endif //__DCN315_CLK_MGR_H__

+118 -102

drivers/gpu/drm/amd/display/dc/core/dc.c

reviewed

··· 83 83 #include "hw_sequencer_private.h" 84 84 85 85 #if defined(CONFIG_DRM_AMD_DC_FP) 86 86 - #include "dml2/dml2_internal_types.h" 86 86 + #include "dml2_0/dml2_internal_types.h" 87 87 #include "soc_and_ip_translator.h" 88 88 #endif 89 89 ··· 148 148 149 149 /* Private functions */ 150 150 151 151 - static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new) 151 151 + static inline void elevate_update_type( 152 152 + struct surface_update_descriptor *descriptor, 153 153 + enum surface_update_type new_type, 154 154 + enum dc_lock_descriptor new_locks 155 155 + ) 152 156 { 153 153 - if (new > *original) 154 154 - *original = new; 157 157 + if (new_type > descriptor->update_type) 158 158 + descriptor->update_type = new_type; 159 159 + 160 160 + descriptor->lock_descriptor |= new_locks; 155 161 } 156 162 157 163 static void destroy_links(struct dc *dc) ··· 499 493 1, 500 494 *adjust); 501 495 stream->adjust.timing_adjust_pending = false; 496 496 + 497 497 + if (dc->hwss.notify_cursor_offload_drr_update) 498 498 + dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); 499 499 + 502 500 return true; 503 501 } 504 502 } 505 505 - 506 506 - if (dc->hwss.notify_cursor_offload_drr_update) 507 507 - dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); 508 503 509 504 return false; 510 505 } ··· 1154 1147 /* set i2c speed if not done by the respective dcnxxx__resource.c */ 1155 1148 if (dc->caps.i2c_speed_in_khz_hdcp == 0) 1156 1149 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz; 1157 1157 - if (dc->caps.max_optimizable_video_width == 0) 1158 1158 - dc->caps.max_optimizable_video_width = 5120; 1150 1150 + if (dc->check_config.max_optimizable_video_width == 0) 1151 1151 + dc->check_config.max_optimizable_video_width = 5120; 1159 1152 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); 1160 1153 if (!dc->clk_mgr) 1161 1154 goto fail; ··· 2662 2655 return false; 2663 2656 } 2664 2657 2665 2665 - static enum surface_update_type get_plane_info_update_type(const struct dc *dc, const struct dc_surface_update *u) 2658 2658 + static struct surface_update_descriptor get_plane_info_update_type(const struct dc_surface_update *u) 2666 2659 { 2667 2660 union surface_update_flags *update_flags = &u->surface->update_flags; 2668 2668 - enum surface_update_type update_type = UPDATE_TYPE_FAST; 2661 2661 + struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; 2669 2662 2670 2663 if (!u->plane_info) 2671 2671 - return UPDATE_TYPE_FAST; 2664 2664 + return update_type; 2665 2665 + 2666 2666 + elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_PLANE); 2672 2667 2673 2668 if (u->plane_info->color_space != u->surface->color_space) { 2674 2669 update_flags->bits.color_space_change = 1; 2675 2675 - elevate_update_type(&update_type, UPDATE_TYPE_MED); 2670 2670 + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2676 2671 } 2677 2672 2678 2673 if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) { 2679 2674 update_flags->bits.horizontal_mirror_change = 1; 2680 2680 - elevate_update_type(&update_type, UPDATE_TYPE_MED); 2675 2675 + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2681 2676 } 2682 2677 2683 2678 if (u->plane_info->rotation != u->surface->rotation) { 2684 2679 update_flags->bits.rotation_change = 1; 2685 2685 - elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2680 2680 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2686 2681 } 2687 2682 2688 2683 if (u->plane_info->format != u->surface->format) { 2689 2684 update_flags->bits.pixel_format_change = 1; 2690 2690 - elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2685 2685 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2691 2686 } 2692 2687 2693 2688 if (u->plane_info->stereo_format != u->surface->stereo_format) { 2694 2689 update_flags->bits.stereo_format_change = 1; 2695 2695 - elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2690 2690 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2696 2691 } 2697 2692 2698 2693 if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) { 2699 2694 update_flags->bits.per_pixel_alpha_change = 1; 2700 2700 - elevate_update_type(&update_type, UPDATE_TYPE_MED); 2695 2695 + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2701 2696 } 2702 2697 2703 2698 if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) { 2704 2699 update_flags->bits.global_alpha_change = 1; 2705 2705 - elevate_update_type(&update_type, UPDATE_TYPE_MED); 2700 2700 + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2706 2701 } 2707 2702 2708 2703 if (u->plane_info->dcc.enable != u->surface->dcc.enable ··· 2716 2707 * recalculate stutter period. 2717 2708 */ 2718 2709 update_flags->bits.dcc_change = 1; 2719 2719 - elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2710 2710 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2720 2711 } 2721 2712 2722 2713 if (resource_pixel_format_to_bpp(u->plane_info->format) != ··· 2725 2716 * and DML calculation 2726 2717 */ 2727 2718 update_flags->bits.bpp_change = 1; 2728 2728 - elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2719 2719 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2729 2720 } 2730 2721 2731 2722 if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch 2732 2723 || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) { 2733 2724 update_flags->bits.plane_size_change = 1; 2734 2734 - elevate_update_type(&update_type, UPDATE_TYPE_MED); 2725 2725 + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2735 2726 } 2736 2727 2737 2728 const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; 2738 2729 2739 2730 if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { 2740 2731 update_flags->bits.swizzle_change = 1; 2741 2741 - elevate_update_type(&update_type, UPDATE_TYPE_MED); 2732 2732 + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2742 2733 2743 2734 switch (tiling->gfxversion) { 2744 2735 case DcGfxVersion9: 2745 2736 case DcGfxVersion10: 2746 2737 case DcGfxVersion11: 2747 2738 if (tiling->gfx9.swizzle != DC_SW_LINEAR) { 2748 2748 - elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2739 2739 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2749 2740 update_flags->bits.bandwidth_change = 1; 2750 2741 } 2751 2742 break; 2752 2743 case DcGfxAddr3: 2753 2744 if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { 2754 2754 - elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2745 2745 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2755 2746 update_flags->bits.bandwidth_change = 1; 2756 2747 } 2757 2748 break; ··· 2767 2758 return update_type; 2768 2759 } 2769 2760 2770 2770 - static enum surface_update_type get_scaling_info_update_type( 2771 2771 - const struct dc *dc, 2761 2761 + static struct surface_update_descriptor get_scaling_info_update_type( 2762 2762 + const struct dc_check_config *check_config, 2772 2763 const struct dc_surface_update *u) 2773 2764 { 2774 2765 union surface_update_flags *update_flags = &u->surface->update_flags; 2766 2766 + struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; 2775 2767 2776 2768 if (!u->scaling_info) 2777 2777 - return UPDATE_TYPE_FAST; 2769 2769 + return update_type; 2770 2770 + 2771 2771 + elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_PLANE); 2778 2772 2779 2773 if (u->scaling_info->src_rect.width != u->surface->src_rect.width 2780 2774 || u->scaling_info->src_rect.height != u->surface->src_rect.height ··· 2801 2789 /* Making dst rect smaller requires a bandwidth change */ 2802 2790 update_flags->bits.bandwidth_change = 1; 2803 2791 2804 2804 - if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width && 2792 2792 + if (u->scaling_info->src_rect.width > check_config->max_optimizable_video_width && 2805 2793 (u->scaling_info->clip_rect.width > u->surface->clip_rect.width || 2806 2794 u->scaling_info->clip_rect.height > u->surface->clip_rect.height)) 2807 2795 /* Changing clip size of a large surface may result in MPC slice count change */ ··· 2820 2808 if (update_flags->bits.clock_change 2821 2809 || update_flags->bits.bandwidth_change 2822 2810 || update_flags->bits.scaling_change) 2823 2823 - return UPDATE_TYPE_FULL; 2811 2811 + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2824 2812 2825 2813 if (update_flags->bits.position_change) 2826 2826 - return UPDATE_TYPE_MED; 2814 2814 + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2827 2815 2828 2828 - return UPDATE_TYPE_FAST; 2816 2816 + return update_type; 2829 2817 } 2830 2818 2831 2831 - static enum surface_update_type det_surface_update(const struct dc *dc, 2832 2832 - const struct dc_surface_update *u) 2819 2819 + static struct surface_update_descriptor det_surface_update( 2820 2820 + const struct dc_check_config *check_config, 2821 2821 + struct dc_surface_update *u) 2833 2822 { 2834 2834 - enum surface_update_type type; 2835 2835 - enum surface_update_type overall_type = UPDATE_TYPE_FAST; 2823 2823 + struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; 2836 2824 union surface_update_flags *update_flags = &u->surface->update_flags; 2837 2825 2838 2826 if (u->surface->force_full_update) { 2839 2827 update_flags->raw = 0xFFFFFFFF; 2840 2840 - return UPDATE_TYPE_FULL; 2828 2828 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2829 2829 + return overall_type; 2841 2830 } 2842 2831 2843 2832 update_flags->raw = 0; // Reset all flags 2844 2833 2845 2845 - type = get_plane_info_update_type(dc, u); 2846 2846 - elevate_update_type(&overall_type, type); 2834 2834 + struct surface_update_descriptor inner_type = get_plane_info_update_type(u); 2847 2835 2848 2848 - type = get_scaling_info_update_type(dc, u); 2849 2849 - elevate_update_type(&overall_type, type); 2836 2836 + elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); 2837 2837 + 2838 2838 + inner_type = get_scaling_info_update_type(check_config, u); 2839 2839 + elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); 2850 2840 2851 2841 if (u->flip_addr) { 2852 2842 update_flags->bits.addr_update = 1; 2853 2843 if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) { 2854 2844 update_flags->bits.tmz_changed = 1; 2855 2855 - elevate_update_type(&overall_type, UPDATE_TYPE_FULL); 2845 2845 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2856 2846 } 2857 2847 } 2858 2848 if (u->in_transfer_func) ··· 2890 2876 if (u->hdr_mult.value) 2891 2877 if (u->hdr_mult.value != u->surface->hdr_mult.value) { 2892 2878 update_flags->bits.hdr_mult = 1; 2893 2893 - elevate_update_type(&overall_type, UPDATE_TYPE_MED); 2879 2879 + // TODO: Should be fast? 2880 2880 + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2894 2881 } 2895 2882 2896 2883 if (u->sdr_white_level_nits) 2897 2884 if (u->sdr_white_level_nits != u->surface->sdr_white_level_nits) { 2898 2885 update_flags->bits.sdr_white_level_nits = 1; 2899 2899 - elevate_update_type(&overall_type, UPDATE_TYPE_FULL); 2886 2886 + // TODO: Should be fast? 2887 2887 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2900 2888 } 2901 2889 2902 2890 if (u->cm2_params) { ··· 2912 2896 update_flags->bits.mcm_transfer_function_enable_change = 1; 2913 2897 } 2914 2898 if (update_flags->bits.in_transfer_func_change) { 2915 2915 - type = UPDATE_TYPE_MED; 2916 2916 - elevate_update_type(&overall_type, type); 2899 2899 + // TODO: Fast? 2900 2900 + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); 2917 2901 } 2918 2902 2919 2903 if (update_flags->bits.lut_3d && 2920 2904 u->surface->mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { 2921 2921 - type = UPDATE_TYPE_FULL; 2922 2922 - elevate_update_type(&overall_type, type); 2905 2905 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2923 2906 } 2924 2907 if (update_flags->bits.mcm_transfer_function_enable_change) { 2925 2925 - type = UPDATE_TYPE_FULL; 2926 2926 - elevate_update_type(&overall_type, type); 2908 2908 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2927 2909 } 2928 2910 2929 2929 - if (dc->debug.enable_legacy_fast_update && 2911 2911 + if (check_config->enable_legacy_fast_update && 2930 2912 (update_flags->bits.gamma_change || 2931 2913 update_flags->bits.gamut_remap_change || 2932 2914 update_flags->bits.input_csc_change || 2933 2915 update_flags->bits.coeff_reduction_change)) { 2934 2934 - type = UPDATE_TYPE_FULL; 2935 2935 - elevate_update_type(&overall_type, type); 2916 2916 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2936 2917 } 2937 2918 return overall_type; 2938 2919 } ··· 2957 2944 } 2958 2945 } 2959 2946 2960 2960 - static enum surface_update_type check_update_surfaces_for_stream( 2961 2961 - struct dc *dc, 2947 2947 + static struct surface_update_descriptor check_update_surfaces_for_stream( 2948 2948 + const struct dc_check_config *check_config, 2962 2949 struct dc_surface_update *updates, 2963 2950 int surface_count, 2964 2964 - struct dc_stream_update *stream_update, 2965 2965 - const struct dc_stream_status *stream_status) 2951 2951 + struct dc_stream_update *stream_update) 2966 2952 { 2967 2967 - int i; 2968 2968 - enum surface_update_type overall_type = UPDATE_TYPE_FAST; 2953 2953 + struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; 2969 2954 2970 2955 if (stream_update && stream_update->pending_test_pattern) { 2971 2971 - overall_type = UPDATE_TYPE_FULL; 2956 2956 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2972 2957 } 2973 2958 2974 2959 if (stream_update && stream_update->hw_cursor_req) { 2975 2975 - overall_type = UPDATE_TYPE_FULL; 2960 2960 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 2976 2961 } 2977 2962 2978 2963 /* some stream updates require passive update */ 2979 2964 if (stream_update) { 2980 2965 union stream_update_flags *su_flags = &stream_update->stream->update_flags; 2981 2966 2967 2967 + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); 2968 2968 + 2982 2969 if ((stream_update->src.height != 0 && stream_update->src.width != 0) || 2983 2970 (stream_update->dst.height != 0 && stream_update->dst.width != 0) || 2984 2971 stream_update->integer_scaling_update) 2985 2972 su_flags->bits.scaling = 1; 2986 2973 2987 2987 - if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func) 2974 2974 + if (check_config->enable_legacy_fast_update && stream_update->out_transfer_func) 2988 2975 su_flags->bits.out_tf = 1; 2989 2976 2990 2977 if (stream_update->abm_level) ··· 3020 3007 su_flags->bits.out_csc = 1; 3021 3008 3022 3009 if (su_flags->raw != 0) 3023 3023 - overall_type = UPDATE_TYPE_FULL; 3010 3010 + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); 3024 3011 3025 3012 if (stream_update->output_csc_transform) 3026 3013 su_flags->bits.out_csc = 1; ··· 3028 3015 /* Output transfer function changes do not require bandwidth recalculation, 3029 3016 * so don't trigger a full update 3030 3017 */ 3031 3031 - if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func) 3018 3018 + if (!check_config->enable_legacy_fast_update && stream_update->out_transfer_func) 3032 3019 su_flags->bits.out_tf = 1; 3033 3020 } 3034 3021 3035 3035 - for (i = 0 ; i < surface_count; i++) { 3036 3036 - enum surface_update_type type = 3037 3037 - det_surface_update(dc, &updates[i]); 3022 3022 + for (int i = 0 ; i < surface_count; i++) { 3023 3023 + struct surface_update_descriptor inner_type = 3024 3024 + det_surface_update(check_config, &updates[i]); 3038 3025 3039 3039 - elevate_update_type(&overall_type, type); 3026 3026 + elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); 3040 3027 } 3041 3028 3042 3029 return overall_type; ··· 3047 3034 * 3048 3035 * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types 3049 3036 */ 3050 3050 - enum surface_update_type dc_check_update_surfaces_for_stream( 3051 3051 - struct dc *dc, 3037 3037 + struct surface_update_descriptor dc_check_update_surfaces_for_stream( 3038 3038 + const struct dc_check_config *check_config, 3052 3039 struct dc_surface_update *updates, 3053 3040 int surface_count, 3054 3054 - struct dc_stream_update *stream_update, 3055 3055 - const struct dc_stream_status *stream_status) 3041 3041 + struct dc_stream_update *stream_update) 3056 3042 { 3057 3057 - int i; 3058 3058 - enum surface_update_type type; 3059 3059 - 3060 3043 if (stream_update) 3061 3044 stream_update->stream->update_flags.raw = 0; 3062 3062 - for (i = 0; i < surface_count; i++) 3045 3045 + for (size_t i = 0; i < surface_count; i++) 3063 3046 updates[i].surface->update_flags.raw = 0; 3064 3047 3065 3065 - type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); 3066 3066 - return type; 3048 3048 + return check_update_surfaces_for_stream(check_config, updates, surface_count, stream_update); 3067 3049 } 3068 3050 3069 3051 static struct dc_stream_status *stream_get_status( ··· 3427 3419 } 3428 3420 } 3429 3421 3430 3430 - static bool full_update_required_weak(struct dc *dc, 3431 3431 - struct dc_surface_update *srf_updates, 3422 3422 + static bool full_update_required_weak( 3423 3423 + const struct dc *dc, 3424 3424 + const struct dc_surface_update *srf_updates, 3432 3425 int surface_count, 3433 3433 - struct dc_stream_update *stream_update, 3434 3434 - struct dc_stream_state *stream); 3426 3426 + const struct dc_stream_update *stream_update, 3427 3427 + const struct dc_stream_state *stream); 3435 3428 3436 3429 /** 3437 3430 * update_planes_and_stream_state() - The function takes planes and stream ··· 3480 3471 3481 3472 context = dc->current_state; 3482 3473 update_type = dc_check_update_surfaces_for_stream( 3483 3483 - dc, srf_updates, surface_count, stream_update, stream_status); 3484 3484 - 3474 3474 + &dc->check_config, srf_updates, surface_count, stream_update).update_type; 3485 3475 if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) 3486 3476 update_type = UPDATE_TYPE_FULL; 3487 3477 ··· 5016 5008 } 5017 5009 } 5018 5010 5019 5019 - static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count) 5011 5011 + static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count) 5020 5012 { 5021 5013 int i; 5022 5014 ··· 5057 5049 return false; 5058 5050 } 5059 5051 5060 5060 - static bool full_update_required_weak(struct dc *dc, 5061 5061 - struct dc_surface_update *srf_updates, 5052 5052 + static bool full_update_required_weak( 5053 5053 + const struct dc *dc, 5054 5054 + const struct dc_surface_update *srf_updates, 5062 5055 int surface_count, 5063 5063 - struct dc_stream_update *stream_update, 5064 5064 - struct dc_stream_state *stream) 5056 5056 + const struct dc_stream_update *stream_update, 5057 5057 + const struct dc_stream_state *stream) 5065 5058 { 5066 5059 const struct dc_state *context = dc->current_state; 5067 5060 if (srf_updates) ··· 5071 5062 return true; 5072 5063 5073 5064 if (stream) { 5074 5074 - const struct dc_stream_status *stream_status = dc_stream_get_status(stream); 5065 5065 + const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream); 5075 5066 if (stream_status == NULL || stream_status->plane_count != surface_count) 5076 5067 return true; 5077 5068 } ··· 5084 5075 return false; 5085 5076 } 5086 5077 5087 5087 - static bool full_update_required(struct dc *dc, 5088 5088 - struct dc_surface_update *srf_updates, 5078 5078 + static bool full_update_required( 5079 5079 + const struct dc *dc, 5080 5080 + const struct dc_surface_update *srf_updates, 5089 5081 int surface_count, 5090 5090 - struct dc_stream_update *stream_update, 5091 5091 - struct dc_stream_state *stream) 5082 5082 + const struct dc_stream_update *stream_update, 5083 5083 + const struct dc_stream_state *stream) 5092 5084 { 5093 5085 if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) 5094 5086 return true; ··· 5149 5139 return false; 5150 5140 } 5151 5141 5152 5152 - static bool fast_update_only(struct dc *dc, 5153 5153 - struct dc_fast_update *fast_update, 5154 5154 - struct dc_surface_update *srf_updates, 5142 5142 + static bool fast_update_only( 5143 5143 + const struct dc *dc, 5144 5144 + const struct dc_fast_update *fast_update, 5145 5145 + const struct dc_surface_update *srf_updates, 5155 5146 int surface_count, 5156 5156 - struct dc_stream_update *stream_update, 5157 5157 - struct dc_stream_state *stream) 5147 5147 + const struct dc_stream_update *stream_update, 5148 5148 + const struct dc_stream_state *stream) 5158 5149 { 5159 5150 return fast_updates_exist(fast_update, surface_count) 5160 5151 && !full_update_required(dc, srf_updates, surface_count, stream_update, stream); ··· 5218 5207 commit_minimal_transition_state_in_dc_update(dc, context, stream, 5219 5208 srf_updates, surface_count); 5220 5209 5221 5221 - if (is_fast_update_only && !dc->debug.enable_legacy_fast_update) { 5210 5210 + if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) { 5222 5211 commit_planes_for_stream_fast(dc, 5223 5212 srf_updates, 5224 5213 surface_count, ··· 5261 5250 stream_update); 5262 5251 if (fast_update_only(dc, fast_update, srf_updates, surface_count, 5263 5252 stream_update, stream) && 5264 5264 - !dc->debug.enable_legacy_fast_update) 5253 5253 + !dc->check_config.enable_legacy_fast_update) 5265 5254 commit_planes_for_stream_fast(dc, 5266 5255 srf_updates, 5267 5256 surface_count, ··· 6387 6376 return false; 6388 6377 } 6389 6378 6390 6390 - bool dc_can_clear_cursor_limit(struct dc *dc) 6379 6379 + bool dc_can_clear_cursor_limit(const struct dc *dc) 6391 6380 { 6392 6381 uint32_t i; 6393 6382 ··· 6415 6404 dc_exit_ips_for_hw_access(dc); 6416 6405 if (dc->hwss.get_underflow_debug_data) 6417 6406 dc->hwss.get_underflow_debug_data(dc, tg, out_data); 6407 6407 + } 6408 6408 + 6409 6409 + void dc_log_preos_dmcub_info(const struct dc *dc) 6410 6410 + { 6411 6411 + dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv); 6418 6412 }

+2 -2

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

reviewed

··· 522 522 struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc) 523 523 { 524 524 struct link_encoder *link_enc = NULL; 525 525 - enum engine_id encs_assigned[MAX_DIG_LINK_ENCODERS]; 525 525 + enum engine_id encs_assigned[MAX_LINK_ENCODERS]; 526 526 int i; 527 527 528 528 - for (i = 0; i < MAX_DIG_LINK_ENCODERS; i++) 528 528 + for (i = 0; i < MAX_LINK_ENCODERS; i++) 529 529 encs_assigned[i] = ENGINE_ID_UNKNOWN; 530 530 531 531 /* Add assigned encoders to list. */

+42 -11

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

reviewed

··· 95 95 #define DC_LOGGER \ 96 96 dc->ctx->logger 97 97 #define DC_LOGGER_INIT(logger) 98 98 - #include "dml2/dml2_wrapper.h" 98 98 + #include "dml2_0/dml2_wrapper.h" 99 99 100 100 #define UNABLE_TO_SPLIT -1 101 101 ··· 444 444 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 445 445 if (pool->stream_enc[i] == NULL) 446 446 DC_ERR("DC: failed to create stream_encoder!\n"); 447 447 + pool->stream_enc_count++; 448 448 + } 449 449 + 450 450 + for (i = 0; i < caps->num_analog_stream_encoder; i++) { 451 451 + pool->stream_enc[caps->num_stream_encoder + i] = 452 452 + create_funcs->create_stream_encoder(ENGINE_ID_DACA + i, ctx); 453 453 + if (pool->stream_enc[caps->num_stream_encoder + i] == NULL) 454 454 + DC_ERR("DC: failed to create analog stream_encoder %d!\n", i); 447 455 pool->stream_enc_count++; 448 456 } 449 457 } ··· 2698 2690 } 2699 2691 2700 2692 static inline int find_free_dio_link_enc(const struct resource_context *res_ctx, 2701 2701 - const struct dc_link *link, const struct resource_pool *pool) 2693 2693 + const struct dc_link *link, const struct resource_pool *pool, struct dc_stream_state *stream) 2702 2694 { 2703 2703 - int i; 2695 2695 + int i, j = -1; 2696 2696 + int stream_enc_inst = -1; 2704 2697 int enc_count = pool->dig_link_enc_count; 2705 2698 2706 2706 - /* for dpia, check preferred encoder first and then the next one */ 2707 2707 - for (i = 0; i < enc_count; i++) 2708 2708 - if (res_ctx->dio_link_enc_ref_cnts[(link->dpia_preferred_eng_id + i) % enc_count] == 0) 2709 2709 - break; 2699 2699 + /* Find stream encoder instance for the stream */ 2700 2700 + if (stream) { 2701 2701 + for (i = 0; i < pool->pipe_count; i++) { 2702 2702 + if ((res_ctx->pipe_ctx[i].stream == stream) && 2703 2703 + (res_ctx->pipe_ctx[i].stream_res.stream_enc != NULL)) { 2704 2704 + stream_enc_inst = res_ctx->pipe_ctx[i].stream_res.stream_enc->id; 2705 2705 + break; 2706 2706 + } 2707 2707 + } 2708 2708 + } 2710 2709 2711 2711 - return (i >= 0 && i < enc_count) ? (link->dpia_preferred_eng_id + i) % enc_count : -1; 2710 2710 + /* Assign dpia preferred > stream enc instance > available */ 2711 2711 + for (i = 0; i < enc_count; i++) { 2712 2712 + if (res_ctx->dio_link_enc_ref_cnts[i] == 0) { 2713 2713 + if (j == -1) 2714 2714 + j = i; 2715 2715 + 2716 2716 + if (link->dpia_preferred_eng_id == i) { 2717 2717 + j = i; 2718 2718 + break; 2719 2719 + } 2720 2720 + 2721 2721 + if (stream_enc_inst == i) { 2722 2722 + j = stream_enc_inst; 2723 2723 + } 2724 2724 + } 2725 2725 + } 2726 2726 + return j; 2712 2727 } 2713 2728 2714 2729 static inline void acquire_dio_link_enc( ··· 2812 2781 retain_dio_link_enc(res_ctx, enc_index); 2813 2782 } else { 2814 2783 if (stream->link->is_dig_mapping_flexible) 2815 2815 - enc_index = find_free_dio_link_enc(res_ctx, stream->link, pool); 2784 2784 + enc_index = find_free_dio_link_enc(res_ctx, stream->link, pool, stream); 2816 2785 else { 2817 2786 int link_index = 0; 2818 2787 ··· 2822 2791 * one into the acquiring link. 2823 2792 */ 2824 2793 if (enc_index >= 0 && is_dio_enc_acquired_by_other_link(stream->link, enc_index, &link_index)) { 2825 2825 - int new_enc_index = find_free_dio_link_enc(res_ctx, dc->links[link_index], pool); 2794 2794 + int new_enc_index = find_free_dio_link_enc(res_ctx, dc->links[link_index], pool, stream); 2826 2795 2827 2796 if (new_enc_index >= 0) 2828 2797 swap_dio_link_enc_to_muxable_ctx(context, pool, new_enc_index, enc_index); ··· 5232 5201 enc_index = link->eng_id; 5233 5202 5234 5203 if (enc_index < 0) 5235 5235 - enc_index = find_free_dio_link_enc(res_ctx, link, pool); 5204 5204 + enc_index = find_free_dio_link_enc(res_ctx, link, pool, NULL); 5236 5205 5237 5206 if (enc_index >= 0) 5238 5207 link_enc = pool->link_encoders[enc_index];

+2 -2

drivers/gpu/drm/amd/display/dc/core/dc_state.c

reviewed

··· 35 35 #include "link_enc_cfg.h" 36 36 37 37 #if defined(CONFIG_DRM_AMD_DC_FP) 38 38 - #include "dml2/dml2_wrapper.h" 39 39 - #include "dml2/dml2_internal_types.h" 38 38 + #include "dml2_0/dml2_wrapper.h" 39 39 + #include "dml2_0/dml2_internal_types.h" 40 40 #endif 41 41 42 42 #define DC_LOGGER \

+8

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

reviewed

··· 224 224 return dc_state_get_stream_status(dc->current_state, stream); 225 225 } 226 226 227 227 + const struct dc_stream_status *dc_stream_get_status_const( 228 228 + const struct dc_stream_state *stream) 229 229 + { 230 230 + struct dc *dc = stream->ctx->dc; 231 231 + 232 232 + return dc_state_get_stream_status(dc->current_state, stream); 233 233 + } 234 234 + 227 235 void program_cursor_attributes( 228 236 struct dc *dc, 229 237 struct dc_stream_state *stream)

+44 -24

drivers/gpu/drm/amd/display/dc/dc.h

reviewed

··· 42 42 #include "inc/hw/dmcu.h" 43 43 #include "dml/display_mode_lib.h" 44 44 45 45 - #include "dml2/dml2_wrapper.h" 45 45 + #include "dml2_0/dml2_wrapper.h" 46 46 47 47 #include "dmub/inc/dmub_cmd.h" 48 48 ··· 54 54 struct aux_payload; 55 55 struct set_config_cmd_payload; 56 56 struct dmub_notification; 57 57 + struct dcn_hubbub_reg_state; 58 58 + struct dcn_hubp_reg_state; 59 59 + struct dcn_dpp_reg_state; 60 60 + struct dcn_mpc_reg_state; 61 61 + struct dcn_opp_reg_state; 62 62 + struct dcn_dsc_reg_state; 63 63 + struct dcn_optc_reg_state; 64 64 + struct dcn_dccg_reg_state; 57 65 58 58 - #define DC_VER "3.2.355" 66 66 + #define DC_VER "3.2.356" 59 67 60 68 /** 61 69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC ··· 286 278 bool sharpener_support; 287 279 }; 288 280 281 281 + struct dc_check_config { 282 282 + /** 283 283 + * max video plane width that can be safely assumed to be always 284 284 + * supported by single DPP pipe. 285 285 + */ 286 286 + unsigned int max_optimizable_video_width; 287 287 + bool enable_legacy_fast_update; 288 288 + }; 289 289 + 289 290 struct dc_caps { 290 291 uint32_t max_streams; 291 292 uint32_t max_links; ··· 310 293 unsigned int max_cursor_size; 311 294 unsigned int max_buffered_cursor_size; 312 295 unsigned int max_video_width; 313 313 - /* 314 314 - * max video plane width that can be safely assumed to be always 315 315 - * supported by single DPP pipe. 316 316 - */ 317 317 - unsigned int max_optimizable_video_width; 318 296 unsigned int min_horizontal_blanking_period; 319 297 int linear_pitch_alignment; 320 298 bool dcc_const_color; ··· 465 453 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 466 454 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 467 455 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 456 456 + }; 457 457 + 458 458 + enum dc_lock_descriptor { 459 459 + LOCK_DESCRIPTOR_NONE = 0x0, 460 460 + LOCK_DESCRIPTOR_STATE = 0x1, 461 461 + LOCK_DESCRIPTOR_LINK = 0x2, 462 462 + LOCK_DESCRIPTOR_STREAM = 0x4, 463 463 + LOCK_DESCRIPTOR_PLANE = 0x8, 464 464 + }; 465 465 + 466 466 + struct surface_update_descriptor { 467 467 + enum surface_update_type update_type; 468 468 + enum dc_lock_descriptor lock_descriptor; 468 469 }; 469 470 470 471 /* Forward declaration*/ ··· 1145 1120 uint32_t fpo_vactive_min_active_margin_us; 1146 1121 uint32_t fpo_vactive_max_blank_us; 1147 1122 bool enable_hpo_pg_support; 1148 1148 - bool enable_legacy_fast_update; 1149 1123 bool disable_dc_mode_overwrite; 1150 1124 bool replay_skip_crtc_disabled; 1151 1125 bool ignore_pg;/*do nothing, let pmfw control it*/ ··· 1176 1152 bool enable_ips_visual_confirm; 1177 1153 unsigned int sharpen_policy; 1178 1154 unsigned int scale_to_sharpness_policy; 1179 1179 - bool skip_full_updated_if_possible; 1180 1155 unsigned int enable_oled_edp_power_up_opt; 1181 1156 bool enable_hblank_borrow; 1182 1157 bool force_subvp_df_throttle; ··· 1726 1703 struct dc_debug_options debug; 1727 1704 struct dc_versions versions; 1728 1705 struct dc_caps caps; 1706 1706 + struct dc_check_config check_config; 1729 1707 struct dc_cap_funcs cap_funcs; 1730 1708 struct dc_config config; 1731 1709 struct dc_bounding_box_overrides bb_overrides; ··· 1855 1831 }; 1856 1832 1857 1833 struct dc_underflow_debug_data { 1858 1858 - uint32_t otg_inst; 1859 1859 - uint32_t otg_underflow; 1860 1860 - uint32_t h_position; 1861 1861 - uint32_t v_position; 1862 1862 - uint32_t otg_frame_count; 1863 1863 - struct dc_underflow_per_hubp_debug_data { 1864 1864 - uint32_t hubp_underflow; 1865 1865 - uint32_t hubp_in_blank; 1866 1866 - uint32_t hubp_readline; 1867 1867 - uint32_t det_config_error; 1868 1868 - } hubps[MAX_PIPES]; 1869 1869 - uint32_t curr_det_sizes[MAX_PIPES]; 1870 1870 - uint32_t target_det_sizes[MAX_PIPES]; 1871 1871 - uint32_t compbuf_config_error; 1834 1834 + struct dcn_hubbub_reg_state *hubbub_reg_state; 1835 1835 + struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 1836 1836 + struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 1837 1837 + struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 1838 1838 + struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 1839 1839 + struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 1840 1840 + struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 1841 1841 + struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 1872 1842 }; 1873 1843 1874 1844 /* ··· 2740 2722 2741 2723 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 2742 2724 2725 2725 + void dc_log_preos_dmcub_info(const struct dc *dc); 2726 2726 + 2743 2727 /* DSC Interfaces */ 2744 2728 #include "dc_dsc.h" 2745 2729 ··· 2757 2737 struct dc_stream_state *new_stream); 2758 2738 2759 2739 bool dc_is_cursor_limit_pending(struct dc *dc); 2760 2760 - bool dc_can_clear_cursor_limit(struct dc *dc); 2740 2740 + bool dc_can_clear_cursor_limit(const struct dc *dc); 2761 2741 2762 2742 /** 2763 2743 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data.

+9

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

reviewed

··· 91 91 struct device_id id); 92 92 /* COMMANDS */ 93 93 94 94 + enum bp_result (*select_crtc_source)( 95 95 + struct dc_bios *bios, 96 96 + struct bp_crtc_source_select *bp_params); 94 97 enum bp_result (*encoder_control)( 95 98 struct dc_bios *bios, 96 99 struct bp_encoder_control *cntl); 100 100 + enum bp_result (*dac_load_detection)( 101 101 + struct dc_bios *bios, 102 102 + enum engine_id engine_id, 103 103 + enum dal_device_type device_type, 104 104 + uint32_t enum_id); 97 105 enum bp_result (*transmitter_control)( 98 106 struct dc_bios *bios, 99 107 struct bp_transmitter_control *cntl); ··· 173 165 }; 174 166 175 167 struct bios_registers { 168 168 + uint32_t BIOS_SCRATCH_0; 176 169 uint32_t BIOS_SCRATCH_3; 177 170 uint32_t BIOS_SCRATCH_6; 178 171 };

+21

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

reviewed

··· 2344 2344 2345 2345 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 2346 2346 } 2347 2347 + 2348 2348 + void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv) 2349 2349 + { 2350 2350 + struct dmub_srv *dmub; 2351 2351 + 2352 2352 + if (!dc_dmub_srv || !dc_dmub_srv->dmub) 2353 2353 + return; 2354 2354 + 2355 2355 + dmub = dc_dmub_srv->dmub; 2356 2356 + 2357 2357 + if (dmub_srv_get_preos_info(dmub)) { 2358 2358 + DC_LOG_DEBUG("%s: PreOS DMCUB Info", __func__); 2359 2359 + DC_LOG_DEBUG("fw_version : 0x%08x", dmub->preos_info.fw_version); 2360 2360 + DC_LOG_DEBUG("boot_options : 0x%08x", dmub->preos_info.boot_options); 2361 2361 + DC_LOG_DEBUG("boot_status : 0x%08x", dmub->preos_info.boot_status); 2362 2362 + DC_LOG_DEBUG("trace_buffer_phy_addr : 0x%016llx", dmub->preos_info.trace_buffer_phy_addr); 2363 2363 + DC_LOG_DEBUG("trace_buffer_size_bytes : 0x%08x", dmub->preos_info.trace_buffer_size); 2364 2364 + DC_LOG_DEBUG("fb_base : 0x%016llx", dmub->preos_info.fb_base); 2365 2365 + DC_LOG_DEBUG("fb_offset : 0x%016llx", dmub->preos_info.fb_offset); 2366 2366 + } 2367 2367 + }

+7

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

reviewed

··· 367 367 * @dc - pointer to DC object 368 368 */ 369 369 void dc_dmub_srv_release_hw(const struct dc *dc); 370 370 + 371 371 + /** 372 372 + * dc_dmub_srv_log_preos_dmcub_info() - Logs preos dmcub fw info. 373 373 + * 374 374 + * @dc - pointer to DC object 375 375 + */ 376 376 + void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv); 370 377 #endif /* _DMUB_DC_SRV_H_ */

+5 -6

drivers/gpu/drm/amd/display/dc/dc_stream.h

reviewed

··· 473 473 /* Triggers multi-stream synchronization. */ 474 474 void dc_trigger_sync(struct dc *dc, struct dc_state *context); 475 475 476 476 - enum surface_update_type dc_check_update_surfaces_for_stream( 477 477 - struct dc *dc, 476 476 + struct surface_update_descriptor dc_check_update_surfaces_for_stream( 477 477 + const struct dc_check_config *check_config, 478 478 struct dc_surface_update *updates, 479 479 int surface_count, 480 480 - struct dc_stream_update *stream_update, 481 481 - const struct dc_stream_status *stream_status); 480 480 + struct dc_stream_update *stream_update); 482 481 483 482 /** 484 483 * Create a new default stream for the requested sink ··· 491 492 void dc_stream_retain(struct dc_stream_state *dc_stream); 492 493 void dc_stream_release(struct dc_stream_state *dc_stream); 493 494 494 494 - struct dc_stream_status *dc_stream_get_status( 495 495 - struct dc_stream_state *dc_stream); 495 495 + struct dc_stream_status *dc_stream_get_status(struct dc_stream_state *dc_stream); 496 496 + const struct dc_stream_status *dc_stream_get_status_const(const struct dc_stream_state *dc_stream); 496 497 497 498 /******************************************************************************* 498 499 * Cursor interfaces - To manages the cursor within a stream

+7 -1

drivers/gpu/drm/amd/display/dc/dc_types.h

reviewed

··· 185 185 unsigned int wait_after_dpcd_poweroff_ms; 186 186 }; 187 187 188 188 + /** 189 189 + * struct dc_edid_caps - Capabilities read from EDID. 190 190 + * @analog: Whether the monitor is analog. Used by DVI-I handling. 191 191 + */ 188 192 struct dc_edid_caps { 189 193 /* sink identification */ 190 194 uint16_t manufacturer_id; ··· 217 213 bool hdr_supported; 218 214 bool rr_capable; 219 215 bool scdc_present; 216 216 + bool analog; 220 217 221 218 struct dc_panel_patch panel_patch; 222 219 }; ··· 353 348 dc_connection_none, 354 349 dc_connection_single, 355 350 dc_connection_mst_branch, 356 356 - dc_connection_sst_branch 351 351 + dc_connection_sst_branch, 352 352 + dc_connection_dac_load 357 353 }; 358 354 359 355 struct dc_csc_adjustments {

+63 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

reviewed

··· 425 425 uint32_t SYMCLKD_CLOCK_ENABLE; \ 426 426 uint32_t SYMCLKE_CLOCK_ENABLE; \ 427 427 uint32_t DP_DTO_MODULO[MAX_PIPES]; \ 428 428 - uint32_t DP_DTO_PHASE[MAX_PIPES] 428 428 + uint32_t DP_DTO_PHASE[MAX_PIPES]; \ 429 429 + uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; \ 430 430 + uint32_t DCCG_AUDIO_DTO0_MODULE; \ 431 431 + uint32_t DCCG_AUDIO_DTO0_PHASE; \ 432 432 + uint32_t DCCG_AUDIO_DTO1_MODULE; \ 433 433 + uint32_t DCCG_AUDIO_DTO1_PHASE; \ 434 434 + uint32_t DCCG_CAC_STATUS; \ 435 435 + uint32_t DCCG_CAC_STATUS2; \ 436 436 + uint32_t DCCG_DISP_CNTL_REG; \ 437 437 + uint32_t DCCG_DS_CNTL; \ 438 438 + uint32_t DCCG_DS_DTO_INCR; \ 439 439 + uint32_t DCCG_DS_DTO_MODULO; \ 440 440 + uint32_t DCCG_DS_HW_CAL_INTERVAL; \ 441 441 + uint32_t DCCG_GTC_CNTL; \ 442 442 + uint32_t DCCG_GTC_CURRENT; \ 443 443 + uint32_t DCCG_GTC_DTO_INCR; \ 444 444 + uint32_t DCCG_GTC_DTO_MODULO; \ 445 445 + uint32_t DCCG_PERFMON_CNTL; \ 446 446 + uint32_t DCCG_PERFMON_CNTL2; \ 447 447 + uint32_t DCCG_SOFT_RESET; \ 448 448 + uint32_t DCCG_TEST_CLK_SEL; \ 449 449 + uint32_t DCCG_VSYNC_CNT_CTRL; \ 450 450 + uint32_t DCCG_VSYNC_CNT_INT_CTRL; \ 451 451 + uint32_t DCCG_VSYNC_OTG0_LATCH_VALUE; \ 452 452 + uint32_t DCCG_VSYNC_OTG1_LATCH_VALUE; \ 453 453 + uint32_t DCCG_VSYNC_OTG2_LATCH_VALUE; \ 454 454 + uint32_t DCCG_VSYNC_OTG3_LATCH_VALUE; \ 455 455 + uint32_t DCCG_VSYNC_OTG4_LATCH_VALUE; \ 456 456 + uint32_t DCCG_VSYNC_OTG5_LATCH_VALUE; \ 457 457 + uint32_t DISPCLK_CGTT_BLK_CTRL_REG; \ 458 458 + uint32_t DP_DTO_DBUF_EN; \ 459 459 + uint32_t DPIACLK_540M_DTO_MODULO; \ 460 460 + uint32_t DPIACLK_540M_DTO_PHASE; \ 461 461 + uint32_t DPIACLK_810M_DTO_MODULO; \ 462 462 + uint32_t DPIACLK_810M_DTO_PHASE; \ 463 463 + uint32_t DPIACLK_DTO_CNTL; \ 464 464 + uint32_t DPIASYMCLK_CNTL; \ 465 465 + uint32_t DPPCLK_CGTT_BLK_CTRL_REG; \ 466 466 + uint32_t DPREFCLK_CGTT_BLK_CTRL_REG; \ 467 467 + uint32_t DPREFCLK_CNTL; \ 468 468 + uint32_t DTBCLK_DTO_DBUF_EN; \ 469 469 + uint32_t FORCE_SYMCLK_DISABLE; \ 470 470 + uint32_t HDMICHARCLK0_CLOCK_CNTL; \ 471 471 + uint32_t MICROSECOND_TIME_BASE_DIV; \ 472 472 + uint32_t MILLISECOND_TIME_BASE_DIV; \ 473 473 + uint32_t OTG0_PHYPLL_PIXEL_RATE_CNTL; \ 474 474 + uint32_t OTG0_PIXEL_RATE_CNTL; \ 475 475 + uint32_t OTG1_PHYPLL_PIXEL_RATE_CNTL; \ 476 476 + uint32_t OTG1_PIXEL_RATE_CNTL; \ 477 477 + uint32_t OTG2_PHYPLL_PIXEL_RATE_CNTL; \ 478 478 + uint32_t OTG2_PIXEL_RATE_CNTL; \ 479 479 + uint32_t OTG3_PHYPLL_PIXEL_RATE_CNTL; \ 480 480 + uint32_t OTG3_PIXEL_RATE_CNTL; \ 481 481 + uint32_t PHYPLLA_PIXCLK_RESYNC_CNTL; \ 482 482 + uint32_t PHYPLLB_PIXCLK_RESYNC_CNTL; \ 483 483 + uint32_t PHYPLLC_PIXCLK_RESYNC_CNTL; \ 484 484 + uint32_t PHYPLLD_PIXCLK_RESYNC_CNTL; \ 485 485 + uint32_t PHYPLLE_PIXCLK_RESYNC_CNTL; \ 486 486 + uint32_t REFCLK_CGTT_BLK_CTRL_REG; \ 487 487 + uint32_t SOCCLK_CGTT_BLK_CTRL_REG; \ 488 488 + uint32_t SYMCLK_CGTT_BLK_CTRL_REG; \ 489 489 + uint32_t SYMCLK_PSP_CNTL 490 490 + 429 491 struct dccg_registers { 430 492 DCCG_REG_VARIABLE_LIST; 431 493 };

+123

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

reviewed

··· 709 709 OTG_DROP_PIXEL[otg_inst], 1); 710 710 } 711 711 712 712 + void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state) 713 713 + { 714 714 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 715 715 + 716 716 + dccg_reg_state->dc_mem_global_pwr_req_cntl = REG_READ(DC_MEM_GLOBAL_PWR_REQ_CNTL); 717 717 + dccg_reg_state->dccg_audio_dtbclk_dto_modulo = REG_READ(DCCG_AUDIO_DTBCLK_DTO_MODULO); 718 718 + dccg_reg_state->dccg_audio_dtbclk_dto_phase = REG_READ(DCCG_AUDIO_DTBCLK_DTO_PHASE); 719 719 + dccg_reg_state->dccg_audio_dto_source = REG_READ(DCCG_AUDIO_DTO_SOURCE); 720 720 + dccg_reg_state->dccg_audio_dto0_module = REG_READ(DCCG_AUDIO_DTO0_MODULE); 721 721 + dccg_reg_state->dccg_audio_dto0_phase = REG_READ(DCCG_AUDIO_DTO0_PHASE); 722 722 + dccg_reg_state->dccg_audio_dto1_module = REG_READ(DCCG_AUDIO_DTO1_MODULE); 723 723 + dccg_reg_state->dccg_audio_dto1_phase = REG_READ(DCCG_AUDIO_DTO1_PHASE); 724 724 + dccg_reg_state->dccg_cac_status = REG_READ(DCCG_CAC_STATUS); 725 725 + dccg_reg_state->dccg_cac_status2 = REG_READ(DCCG_CAC_STATUS2); 726 726 + dccg_reg_state->dccg_disp_cntl_reg = REG_READ(DCCG_DISP_CNTL_REG); 727 727 + dccg_reg_state->dccg_ds_cntl = REG_READ(DCCG_DS_CNTL); 728 728 + dccg_reg_state->dccg_ds_dto_incr = REG_READ(DCCG_DS_DTO_INCR); 729 729 + dccg_reg_state->dccg_ds_dto_modulo = REG_READ(DCCG_DS_DTO_MODULO); 730 730 + dccg_reg_state->dccg_ds_hw_cal_interval = REG_READ(DCCG_DS_HW_CAL_INTERVAL); 731 731 + dccg_reg_state->dccg_gate_disable_cntl = REG_READ(DCCG_GATE_DISABLE_CNTL); 732 732 + dccg_reg_state->dccg_gate_disable_cntl2 = REG_READ(DCCG_GATE_DISABLE_CNTL2); 733 733 + dccg_reg_state->dccg_gate_disable_cntl3 = REG_READ(DCCG_GATE_DISABLE_CNTL3); 734 734 + dccg_reg_state->dccg_gate_disable_cntl4 = REG_READ(DCCG_GATE_DISABLE_CNTL4); 735 735 + dccg_reg_state->dccg_gate_disable_cntl5 = REG_READ(DCCG_GATE_DISABLE_CNTL5); 736 736 + dccg_reg_state->dccg_gate_disable_cntl6 = REG_READ(DCCG_GATE_DISABLE_CNTL6); 737 737 + dccg_reg_state->dccg_global_fgcg_rep_cntl = REG_READ(DCCG_GLOBAL_FGCG_REP_CNTL); 738 738 + dccg_reg_state->dccg_gtc_cntl = REG_READ(DCCG_GTC_CNTL); 739 739 + dccg_reg_state->dccg_gtc_current = REG_READ(DCCG_GTC_CURRENT); 740 740 + dccg_reg_state->dccg_gtc_dto_incr = REG_READ(DCCG_GTC_DTO_INCR); 741 741 + dccg_reg_state->dccg_gtc_dto_modulo = REG_READ(DCCG_GTC_DTO_MODULO); 742 742 + dccg_reg_state->dccg_perfmon_cntl = REG_READ(DCCG_PERFMON_CNTL); 743 743 + dccg_reg_state->dccg_perfmon_cntl2 = REG_READ(DCCG_PERFMON_CNTL2); 744 744 + dccg_reg_state->dccg_soft_reset = REG_READ(DCCG_SOFT_RESET); 745 745 + dccg_reg_state->dccg_test_clk_sel = REG_READ(DCCG_TEST_CLK_SEL); 746 746 + dccg_reg_state->dccg_vsync_cnt_ctrl = REG_READ(DCCG_VSYNC_CNT_CTRL); 747 747 + dccg_reg_state->dccg_vsync_cnt_int_ctrl = REG_READ(DCCG_VSYNC_CNT_INT_CTRL); 748 748 + dccg_reg_state->dccg_vsync_otg0_latch_value = REG_READ(DCCG_VSYNC_OTG0_LATCH_VALUE); 749 749 + dccg_reg_state->dccg_vsync_otg1_latch_value = REG_READ(DCCG_VSYNC_OTG1_LATCH_VALUE); 750 750 + dccg_reg_state->dccg_vsync_otg2_latch_value = REG_READ(DCCG_VSYNC_OTG2_LATCH_VALUE); 751 751 + dccg_reg_state->dccg_vsync_otg3_latch_value = REG_READ(DCCG_VSYNC_OTG3_LATCH_VALUE); 752 752 + dccg_reg_state->dccg_vsync_otg4_latch_value = REG_READ(DCCG_VSYNC_OTG4_LATCH_VALUE); 753 753 + dccg_reg_state->dccg_vsync_otg5_latch_value = REG_READ(DCCG_VSYNC_OTG5_LATCH_VALUE); 754 754 + dccg_reg_state->dispclk_cgtt_blk_ctrl_reg = REG_READ(DISPCLK_CGTT_BLK_CTRL_REG); 755 755 + dccg_reg_state->dispclk_freq_change_cntl = REG_READ(DISPCLK_FREQ_CHANGE_CNTL); 756 756 + dccg_reg_state->dp_dto_dbuf_en = REG_READ(DP_DTO_DBUF_EN); 757 757 + dccg_reg_state->dp_dto0_modulo = REG_READ(DP_DTO_MODULO[0]); 758 758 + dccg_reg_state->dp_dto0_phase = REG_READ(DP_DTO_PHASE[0]); 759 759 + dccg_reg_state->dp_dto1_modulo = REG_READ(DP_DTO_MODULO[1]); 760 760 + dccg_reg_state->dp_dto1_phase = REG_READ(DP_DTO_PHASE[1]); 761 761 + dccg_reg_state->dp_dto2_modulo = REG_READ(DP_DTO_MODULO[2]); 762 762 + dccg_reg_state->dp_dto2_phase = REG_READ(DP_DTO_PHASE[2]); 763 763 + dccg_reg_state->dp_dto3_modulo = REG_READ(DP_DTO_MODULO[3]); 764 764 + dccg_reg_state->dp_dto3_phase = REG_READ(DP_DTO_PHASE[3]); 765 765 + dccg_reg_state->dpiaclk_540m_dto_modulo = REG_READ(DPIACLK_540M_DTO_MODULO); 766 766 + dccg_reg_state->dpiaclk_540m_dto_phase = REG_READ(DPIACLK_540M_DTO_PHASE); 767 767 + dccg_reg_state->dpiaclk_810m_dto_modulo = REG_READ(DPIACLK_810M_DTO_MODULO); 768 768 + dccg_reg_state->dpiaclk_810m_dto_phase = REG_READ(DPIACLK_810M_DTO_PHASE); 769 769 + dccg_reg_state->dpiaclk_dto_cntl = REG_READ(DPIACLK_DTO_CNTL); 770 770 + dccg_reg_state->dpiasymclk_cntl = REG_READ(DPIASYMCLK_CNTL); 771 771 + dccg_reg_state->dppclk_cgtt_blk_ctrl_reg = REG_READ(DPPCLK_CGTT_BLK_CTRL_REG); 772 772 + dccg_reg_state->dppclk_ctrl = REG_READ(DPPCLK_CTRL); 773 773 + dccg_reg_state->dppclk_dto_ctrl = REG_READ(DPPCLK_DTO_CTRL); 774 774 + dccg_reg_state->dppclk0_dto_param = REG_READ(DPPCLK_DTO_PARAM[0]); 775 775 + dccg_reg_state->dppclk1_dto_param = REG_READ(DPPCLK_DTO_PARAM[1]); 776 776 + dccg_reg_state->dppclk2_dto_param = REG_READ(DPPCLK_DTO_PARAM[2]); 777 777 + dccg_reg_state->dppclk3_dto_param = REG_READ(DPPCLK_DTO_PARAM[3]); 778 778 + dccg_reg_state->dprefclk_cgtt_blk_ctrl_reg = REG_READ(DPREFCLK_CGTT_BLK_CTRL_REG); 779 779 + dccg_reg_state->dprefclk_cntl = REG_READ(DPREFCLK_CNTL); 780 780 + dccg_reg_state->dpstreamclk_cntl = REG_READ(DPSTREAMCLK_CNTL); 781 781 + dccg_reg_state->dscclk_dto_ctrl = REG_READ(DSCCLK_DTO_CTRL); 782 782 + dccg_reg_state->dscclk0_dto_param = REG_READ(DSCCLK0_DTO_PARAM); 783 783 + dccg_reg_state->dscclk1_dto_param = REG_READ(DSCCLK1_DTO_PARAM); 784 784 + dccg_reg_state->dscclk2_dto_param = REG_READ(DSCCLK2_DTO_PARAM); 785 785 + dccg_reg_state->dscclk3_dto_param = REG_READ(DSCCLK3_DTO_PARAM); 786 786 + dccg_reg_state->dtbclk_dto_dbuf_en = REG_READ(DTBCLK_DTO_DBUF_EN); 787 787 + dccg_reg_state->dtbclk_dto0_modulo = REG_READ(DTBCLK_DTO_MODULO[0]); 788 788 + dccg_reg_state->dtbclk_dto0_phase = REG_READ(DTBCLK_DTO_PHASE[0]); 789 789 + dccg_reg_state->dtbclk_dto1_modulo = REG_READ(DTBCLK_DTO_MODULO[1]); 790 790 + dccg_reg_state->dtbclk_dto1_phase = REG_READ(DTBCLK_DTO_PHASE[1]); 791 791 + dccg_reg_state->dtbclk_dto2_modulo = REG_READ(DTBCLK_DTO_MODULO[2]); 792 792 + dccg_reg_state->dtbclk_dto2_phase = REG_READ(DTBCLK_DTO_PHASE[2]); 793 793 + dccg_reg_state->dtbclk_dto3_modulo = REG_READ(DTBCLK_DTO_MODULO[3]); 794 794 + dccg_reg_state->dtbclk_dto3_phase = REG_READ(DTBCLK_DTO_PHASE[3]); 795 795 + dccg_reg_state->dtbclk_p_cntl = REG_READ(DTBCLK_P_CNTL); 796 796 + dccg_reg_state->force_symclk_disable = REG_READ(FORCE_SYMCLK_DISABLE); 797 797 + dccg_reg_state->hdmicharclk0_clock_cntl = REG_READ(HDMICHARCLK0_CLOCK_CNTL); 798 798 + dccg_reg_state->hdmistreamclk_cntl = REG_READ(HDMISTREAMCLK_CNTL); 799 799 + dccg_reg_state->hdmistreamclk0_dto_param = REG_READ(HDMISTREAMCLK0_DTO_PARAM); 800 800 + dccg_reg_state->microsecond_time_base_div = REG_READ(MICROSECOND_TIME_BASE_DIV); 801 801 + dccg_reg_state->millisecond_time_base_div = REG_READ(MILLISECOND_TIME_BASE_DIV); 802 802 + dccg_reg_state->otg_pixel_rate_div = REG_READ(OTG_PIXEL_RATE_DIV); 803 803 + dccg_reg_state->otg0_phypll_pixel_rate_cntl = REG_READ(OTG0_PHYPLL_PIXEL_RATE_CNTL); 804 804 + dccg_reg_state->otg0_pixel_rate_cntl = REG_READ(OTG0_PIXEL_RATE_CNTL); 805 805 + dccg_reg_state->otg1_phypll_pixel_rate_cntl = REG_READ(OTG1_PHYPLL_PIXEL_RATE_CNTL); 806 806 + dccg_reg_state->otg1_pixel_rate_cntl = REG_READ(OTG1_PIXEL_RATE_CNTL); 807 807 + dccg_reg_state->otg2_phypll_pixel_rate_cntl = REG_READ(OTG2_PHYPLL_PIXEL_RATE_CNTL); 808 808 + dccg_reg_state->otg2_pixel_rate_cntl = REG_READ(OTG2_PIXEL_RATE_CNTL); 809 809 + dccg_reg_state->otg3_phypll_pixel_rate_cntl = REG_READ(OTG3_PHYPLL_PIXEL_RATE_CNTL); 810 810 + dccg_reg_state->otg3_pixel_rate_cntl = REG_READ(OTG3_PIXEL_RATE_CNTL); 811 811 + dccg_reg_state->phyasymclk_clock_cntl = REG_READ(PHYASYMCLK_CLOCK_CNTL); 812 812 + dccg_reg_state->phybsymclk_clock_cntl = REG_READ(PHYBSYMCLK_CLOCK_CNTL); 813 813 + dccg_reg_state->phycsymclk_clock_cntl = REG_READ(PHYCSYMCLK_CLOCK_CNTL); 814 814 + dccg_reg_state->phydsymclk_clock_cntl = REG_READ(PHYDSYMCLK_CLOCK_CNTL); 815 815 + dccg_reg_state->phyesymclk_clock_cntl = REG_READ(PHYESYMCLK_CLOCK_CNTL); 816 816 + dccg_reg_state->phyplla_pixclk_resync_cntl = REG_READ(PHYPLLA_PIXCLK_RESYNC_CNTL); 817 817 + dccg_reg_state->phypllb_pixclk_resync_cntl = REG_READ(PHYPLLB_PIXCLK_RESYNC_CNTL); 818 818 + dccg_reg_state->phypllc_pixclk_resync_cntl = REG_READ(PHYPLLC_PIXCLK_RESYNC_CNTL); 819 819 + dccg_reg_state->phyplld_pixclk_resync_cntl = REG_READ(PHYPLLD_PIXCLK_RESYNC_CNTL); 820 820 + dccg_reg_state->phyplle_pixclk_resync_cntl = REG_READ(PHYPLLE_PIXCLK_RESYNC_CNTL); 821 821 + dccg_reg_state->refclk_cgtt_blk_ctrl_reg = REG_READ(REFCLK_CGTT_BLK_CTRL_REG); 822 822 + dccg_reg_state->socclk_cgtt_blk_ctrl_reg = REG_READ(SOCCLK_CGTT_BLK_CTRL_REG); 823 823 + dccg_reg_state->symclk_cgtt_blk_ctrl_reg = REG_READ(SYMCLK_CGTT_BLK_CTRL_REG); 824 824 + dccg_reg_state->symclk_psp_cntl = REG_READ(SYMCLK_PSP_CNTL); 825 825 + dccg_reg_state->symclk32_le_cntl = REG_READ(SYMCLK32_LE_CNTL); 826 826 + dccg_reg_state->symclk32_se_cntl = REG_READ(SYMCLK32_SE_CNTL); 827 827 + dccg_reg_state->symclka_clock_enable = REG_READ(SYMCLKA_CLOCK_ENABLE); 828 828 + dccg_reg_state->symclkb_clock_enable = REG_READ(SYMCLKB_CLOCK_ENABLE); 829 829 + dccg_reg_state->symclkc_clock_enable = REG_READ(SYMCLKC_CLOCK_ENABLE); 830 830 + dccg_reg_state->symclkd_clock_enable = REG_READ(SYMCLKD_CLOCK_ENABLE); 831 831 + dccg_reg_state->symclke_clock_enable = REG_READ(SYMCLKE_CLOCK_ENABLE); 832 832 + } 833 833 + 712 834 static const struct dccg_funcs dccg31_funcs = { 713 835 .update_dpp_dto = dccg31_update_dpp_dto, 714 836 .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, ··· 849 727 .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, 850 728 .disable_dsc = dccg31_disable_dscclk, 851 729 .enable_dsc = dccg31_enable_dscclk, 730 730 + .dccg_read_reg_state = dccg31_read_reg_state, 852 731 }; 853 732 854 733 struct dccg *dccg31_create(

+2

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

reviewed

··· 236 236 237 237 void dccg31_enable_dscclk(struct dccg *dccg, int inst); 238 238 239 239 + void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); 240 240 + 239 241 #endif //__DCN31_DCCG_H__

+2 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

reviewed

··· 377 377 .get_pixel_rate_div = dccg314_get_pixel_rate_div, 378 378 .trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync, 379 379 .set_valid_pixel_rate = dccg314_set_valid_pixel_rate, 380 380 - .set_dtbclk_p_src = dccg314_set_dtbclk_p_src 380 380 + .set_dtbclk_p_src = dccg314_set_dtbclk_p_src, 381 381 + .dccg_read_reg_state = dccg31_read_reg_state 381 382 }; 382 383 383 384 struct dccg *dccg314_create(

+1 -2

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

reviewed

··· 74 74 SR(DCCG_GATE_DISABLE_CNTL3),\ 75 75 SR(HDMISTREAMCLK0_DTO_PARAM),\ 76 76 SR(OTG_PIXEL_RATE_DIV),\ 77 77 - SR(DTBCLK_P_CNTL),\ 78 78 - SR(DCCG_AUDIO_DTO_SOURCE) 77 77 + SR(DTBCLK_P_CNTL) 79 78 80 79 #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \ 81 80 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\

+1

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

reviewed

··· 2453 2453 .disable_symclk_se = dccg35_disable_symclk_se, 2454 2454 .set_dtbclk_p_src = dccg35_set_dtbclk_p_src, 2455 2455 .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, 2456 2456 + .dccg_read_reg_state = dccg31_read_reg_state, 2456 2457 }; 2457 2458 2458 2459 struct dccg *dccg35_create(

+3 -2

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

reviewed

··· 41 41 SR(SYMCLKA_CLOCK_ENABLE),\ 42 42 SR(SYMCLKB_CLOCK_ENABLE),\ 43 43 SR(SYMCLKC_CLOCK_ENABLE),\ 44 44 - SR(SYMCLKD_CLOCK_ENABLE),\ 45 45 - SR(SYMCLKE_CLOCK_ENABLE) 44 44 + SR(SYMCLKD_CLOCK_ENABLE), \ 45 45 + SR(SYMCLKE_CLOCK_ENABLE),\ 46 46 + SR(SYMCLK_PSP_CNTL) 46 47 47 48 #define DCCG_MASK_SH_LIST_DCN35(mask_sh) \ 48 49 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\

+1

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

reviewed

··· 886 886 .enable_symclk_se = dccg401_enable_symclk_se, 887 887 .disable_symclk_se = dccg401_disable_symclk_se, 888 888 .set_dtbclk_p_src = dccg401_set_dtbclk_p_src, 889 889 + .dccg_read_reg_state = dccg31_read_reg_state 889 890 }; 890 891 891 892 struct dccg *dccg401_create(

+85

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

reviewed

··· 302 302 if (ctx->dc->caps.psp_setup_panel_mode) 303 303 return; 304 304 305 305 + /* The code below is only applicable to encoders with a digital transmitter. */ 306 306 + if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) 307 307 + return; 308 308 + 305 309 ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); 306 310 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 307 311 ··· 808 804 return true; 809 805 } 810 806 807 807 + static bool dce110_link_encoder_validate_rgb_output( 808 808 + const struct dce110_link_encoder *enc110, 809 809 + const struct dc_crtc_timing *crtc_timing) 810 810 + { 811 811 + /* When the VBIOS doesn't specify any limits, use 400 MHz. 812 812 + * The value comes from amdgpu_atombios_get_clock_info. 813 813 + */ 814 814 + uint32_t max_pixel_clock_khz = 400000; 815 815 + 816 816 + if (enc110->base.ctx->dc_bios->fw_info_valid && 817 817 + enc110->base.ctx->dc_bios->fw_info.max_pixel_clock) { 818 818 + max_pixel_clock_khz = 819 819 + enc110->base.ctx->dc_bios->fw_info.max_pixel_clock; 820 820 + } 821 821 + 822 822 + if (crtc_timing->pix_clk_100hz > max_pixel_clock_khz * 10) 823 823 + return false; 824 824 + 825 825 + if (crtc_timing->display_color_depth != COLOR_DEPTH_888) 826 826 + return false; 827 827 + 828 828 + if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 829 829 + return false; 830 830 + 831 831 + return true; 832 832 + } 833 833 + 811 834 void dce110_link_encoder_construct( 812 835 struct dce110_link_encoder *enc110, 813 836 const struct encoder_init_data *init_data, ··· 855 824 enc110->base.connector = init_data->connector; 856 825 857 826 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 827 827 + enc110->base.analog_engine = init_data->analog_engine; 858 828 859 829 enc110->base.features = *enc_features; 860 830 ··· 878 846 SIGNAL_TYPE_DISPLAY_PORT_MST | 879 847 SIGNAL_TYPE_EDP | 880 848 SIGNAL_TYPE_HDMI_TYPE_A; 849 849 + 850 850 + if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || 851 851 + enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 852 852 + enc110->base.analog_engine != ENGINE_ID_UNKNOWN) 853 853 + enc110->base.output_signals |= SIGNAL_TYPE_RGB; 881 854 882 855 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 883 856 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. ··· 922 885 enc110->base.preferred_engine = ENGINE_ID_DIGG; 923 886 break; 924 887 default: 888 888 + if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { 889 889 + /* The connector is analog-only, ie. VGA */ 890 890 + enc110->base.preferred_engine = init_data->analog_engine; 891 891 + enc110->base.output_signals = SIGNAL_TYPE_RGB; 892 892 + enc110->base.transmitter = TRANSMITTER_UNKNOWN; 893 893 + break; 894 894 + } 925 895 ASSERT_CRITICAL(false); 926 896 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 927 897 } ··· 983 939 is_valid = dce110_link_encoder_validate_dp_output( 984 940 enc110, &stream->timing); 985 941 break; 942 942 + case SIGNAL_TYPE_RGB: 943 943 + is_valid = dce110_link_encoder_validate_rgb_output( 944 944 + enc110, &stream->timing); 945 945 + break; 986 946 case SIGNAL_TYPE_EDP: 987 947 case SIGNAL_TYPE_LVDS: 988 948 is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB; ··· 1016 968 cntl.lanes_number = LANE_COUNT_FOUR; 1017 969 cntl.coherent = false; 1018 970 cntl.hpd_sel = enc110->base.hpd_source; 971 971 + 972 972 + /* The code below is only applicable to encoders with a digital transmitter. */ 973 973 + if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) 974 974 + return; 1019 975 1020 976 if (enc110->base.connector.id == CONNECTOR_ID_EDP) 1021 977 cntl.signal = SIGNAL_TYPE_EDP; ··· 1085 1033 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1086 1034 /* DP MST */ 1087 1035 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 1036 1036 + break; 1037 1037 + case SIGNAL_TYPE_RGB: 1088 1038 break; 1089 1039 default: 1090 1040 ASSERT_CRITICAL(false); ··· 1335 1281 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1336 1282 struct bp_transmitter_control cntl = { 0 }; 1337 1283 enum bp_result result; 1284 1284 + 1285 1285 + switch (enc->analog_engine) { 1286 1286 + case ENGINE_ID_DACA: 1287 1287 + REG_UPDATE(DAC_ENABLE, DAC_ENABLE, 0); 1288 1288 + break; 1289 1289 + case ENGINE_ID_DACB: 1290 1290 + /* DACB doesn't seem to be present on DCE6+, 1291 1291 + * although there are references to it in the register file. 1292 1292 + */ 1293 1293 + DC_LOG_ERROR("%s DACB is unsupported\n", __func__); 1294 1294 + break; 1295 1295 + default: 1296 1296 + break; 1297 1297 + } 1298 1298 + 1299 1299 + /* The code below only applies to connectors that support digital signals. */ 1300 1300 + if (enc->transmitter == TRANSMITTER_UNKNOWN) 1301 1301 + return; 1338 1302 1339 1303 if (!dce110_is_dig_enabled(enc)) { 1340 1304 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ ··· 1798 1726 enc110->base.connector = init_data->connector; 1799 1727 1800 1728 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1729 1729 + enc110->base.analog_engine = init_data->analog_engine; 1801 1730 1802 1731 enc110->base.features = *enc_features; 1803 1732 ··· 1821 1748 SIGNAL_TYPE_DISPLAY_PORT_MST | 1822 1749 SIGNAL_TYPE_EDP | 1823 1750 SIGNAL_TYPE_HDMI_TYPE_A; 1751 1751 + 1752 1752 + if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || 1753 1753 + enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 1754 1754 + enc110->base.analog_engine != ENGINE_ID_UNKNOWN) 1755 1755 + enc110->base.output_signals |= SIGNAL_TYPE_RGB; 1824 1756 1825 1757 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 1826 1758 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. ··· 1865 1787 enc110->base.preferred_engine = ENGINE_ID_DIGG; 1866 1788 break; 1867 1789 default: 1790 1790 + if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { 1791 1791 + /* The connector is analog-only, ie. VGA */ 1792 1792 + enc110->base.preferred_engine = init_data->analog_engine; 1793 1793 + enc110->base.output_signals = SIGNAL_TYPE_RGB; 1794 1794 + enc110->base.transmitter = TRANSMITTER_UNKNOWN; 1795 1795 + break; 1796 1796 + } 1868 1797 ASSERT_CRITICAL(false); 1869 1798 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1870 1799 }

+9 -7

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

reviewed

··· 101 101 SRI(DP_SEC_CNTL, DP, id), \ 102 102 SRI(DP_VID_STREAM_CNTL, DP, id), \ 103 103 SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 104 104 - SRI(DP_SEC_CNTL1, DP, id) 104 104 + SRI(DP_SEC_CNTL1, DP, id), \ 105 105 + SR(DAC_ENABLE) 105 106 #endif 106 107 107 108 #define LE_DCE80_REG_LIST(id)\ 108 109 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 109 109 - LE_COMMON_REG_LIST_BASE(id) 110 110 + LE_COMMON_REG_LIST_BASE(id), \ 111 111 + SR(DAC_ENABLE) 110 112 111 113 #define LE_DCE100_REG_LIST(id)\ 112 114 LE_COMMON_REG_LIST_BASE(id), \ 113 115 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 114 116 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 115 115 - SR(DCI_MEM_PWR_STATUS) 117 117 + SR(DCI_MEM_PWR_STATUS), \ 118 118 + SR(DAC_ENABLE) 116 119 117 120 #define LE_DCE110_REG_LIST(id)\ 118 121 LE_COMMON_REG_LIST_BASE(id), \ ··· 184 181 uint32_t DP_DPHY_BS_SR_SWAP_CNTL; 185 182 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; 186 183 uint32_t DP_SEC_CNTL1; 184 184 + 185 185 + /* DAC registers */ 186 186 + uint32_t DAC_ENABLE; 187 187 }; 188 188 189 189 struct dce110_link_encoder { ··· 219 213 const struct dce110_link_encoder *enc110, 220 214 enum signal_type connector_signal, 221 215 enum signal_type signal, 222 222 - const struct dc_crtc_timing *crtc_timing); 223 223 - 224 224 - bool dce110_link_encoder_validate_rgb_output( 225 225 - const struct dce110_link_encoder *enc110, 226 216 const struct dc_crtc_timing *crtc_timing); 227 217 228 218 bool dce110_link_encoder_validate_dp_output(

+14

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

reviewed

··· 1567 1567 enc110->se_shift = se_shift; 1568 1568 enc110->se_mask = se_mask; 1569 1569 } 1570 1570 + 1571 1571 + static const struct stream_encoder_funcs dce110_an_str_enc_funcs = {0}; 1572 1572 + 1573 1573 + void dce110_analog_stream_encoder_construct( 1574 1574 + struct dce110_stream_encoder *enc110, 1575 1575 + struct dc_context *ctx, 1576 1576 + struct dc_bios *bp, 1577 1577 + enum engine_id eng_id) 1578 1578 + { 1579 1579 + enc110->base.funcs = &dce110_an_str_enc_funcs; 1580 1580 + enc110->base.ctx = ctx; 1581 1581 + enc110->base.id = eng_id; 1582 1582 + enc110->base.bp = bp; 1583 1583 + }

+5

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

reviewed

··· 708 708 const struct dce_stream_encoder_shift *se_shift, 709 709 const struct dce_stream_encoder_mask *se_mask); 710 710 711 711 + void dce110_analog_stream_encoder_construct( 712 712 + struct dce110_stream_encoder *enc110, 713 713 + struct dc_context *ctx, 714 714 + struct dc_bios *bp, 715 715 + enum engine_id eng_id); 711 716 712 717 void dce110_se_audio_mute_control( 713 718 struct stream_encoder *enc, bool mute);

-141

drivers/gpu/drm/amd/display/dc/dml2/Makefile

reviewed

··· 1 1 - # SPDX-License-Identifier: MIT */ 2 2 - # 3 3 - # Copyright 2023 Advanced Micro Devices, Inc. 4 4 - # 5 5 - # Permission is hereby granted, free of charge, to any person obtaining a 6 6 - # copy of this software and associated documentation files (the "Software"), 7 7 - # to deal in the Software without restriction, including without limitation 8 8 - # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 9 - # and/or sell copies of the Software, and to permit persons to whom the 10 10 - # Software is furnished to do so, subject to the following conditions: 11 11 - # 12 12 - # The above copyright notice and this permission notice shall be included in 13 13 - # all copies or substantial portions of the Software. 14 14 - # 15 15 - # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 16 - # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 17 - # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 18 - # THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 19 - # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 20 - # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 21 - # OTHER DEALINGS IN THE SOFTWARE. 22 22 - # 23 23 - # Authors: AMD 24 24 - # 25 25 - # Makefile for dml2. 26 26 - 27 27 - dml2_ccflags := $(CC_FLAGS_FPU) 28 28 - dml2_rcflags := $(CC_FLAGS_NO_FPU) 29 29 - 30 30 - ifneq ($(CONFIG_FRAME_WARN),0) 31 31 - ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) 32 32 - ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy) 33 33 - frame_warn_limit := 4096 34 34 - else 35 35 - frame_warn_limit := 3072 36 36 - endif 37 37 - else 38 38 - frame_warn_limit := 2048 39 39 - endif 40 40 - 41 41 - ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y) 42 42 - frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit) 43 43 - endif 44 44 - endif 45 45 - 46 46 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2 47 47 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_core 48 48 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_mcg/ 49 49 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_dpmm/ 50 50 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_pmo/ 51 51 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_standalone_libraries/ 52 52 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/inc 53 53 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/inc 54 54 - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/ 55 55 - 56 56 - CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) 57 57 - CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_util.o := $(dml2_ccflags) 58 58 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_wrapper.o := $(dml2_ccflags) 59 59 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_utils.o := $(dml2_ccflags) 60 60 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_policy.o := $(dml2_ccflags) 61 61 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_translation_helper.o := $(dml2_ccflags) 62 62 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_mall_phantom.o := $(dml2_ccflags) 63 63 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml_display_rq_dlg_calc.o := $(dml2_ccflags) 64 64 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_dc_resource_mgmt.o := $(dml2_ccflags) 65 65 - 66 66 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_rcflags) 67 67 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/display_mode_util.o := $(dml2_rcflags) 68 68 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_wrapper.o := $(dml2_rcflags) 69 69 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_utils.o := $(dml2_rcflags) 70 70 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_policy.o := $(dml2_rcflags) 71 71 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_translation_helper.o := $(dml2_rcflags) 72 72 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_mall_phantom.o := $(dml2_rcflags) 73 73 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml_display_rq_dlg_calc.o := $(dml2_rcflags) 74 74 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_dc_resource_mgmt.o := $(dml2_rcflags) 75 75 - 76 76 - DML2 = display_mode_core.o display_mode_util.o dml2_wrapper.o \ 77 77 - dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \ 78 78 - dml_display_rq_dlg_calc.o 79 79 - 80 80 - AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2/,$(DML2)) 81 81 - 82 82 - AMD_DISPLAY_FILES += $(AMD_DAL_DML2) 83 83 - 84 84 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags) 85 85 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) 86 86 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) 87 87 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags) 88 88 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags) 89 89 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags) 90 90 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) 91 91 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) 92 92 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) 93 93 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) 94 94 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) 95 95 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) 96 96 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags) 97 97 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags) 98 98 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml21_wrapper.o := $(dml2_ccflags) 99 99 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/dml21_translation_helper.o := $(dml2_ccflags) 100 100 - CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/dml21_utils.o := $(dml2_ccflags) 101 101 - 102 102 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags) 103 103 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) 104 104 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags) 105 105 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) 106 106 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags) 107 107 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags) 108 108 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) 109 109 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) 110 110 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) 111 111 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) 112 112 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) 113 113 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) 114 114 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags) 115 115 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags) 116 116 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml21_wrapper.o := $(dml2_rcflags) 117 117 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/dml21_translation_helper.o := $(dml2_rcflags) 118 118 - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/dml21_utils.o := $(dml2_rcflags) 119 119 - 120 120 - DML21 := src/dml2_top/dml2_top_interfaces.o 121 121 - DML21 += src/dml2_top/dml2_top_soc15.o 122 122 - DML21 += src/dml2_core/dml2_core_dcn4.o 123 123 - DML21 += src/dml2_core/dml2_core_utils.o 124 124 - DML21 += src/dml2_core/dml2_core_factory.o 125 125 - DML21 += src/dml2_core/dml2_core_dcn4_calcs.o 126 126 - DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o 127 127 - DML21 += src/dml2_dpmm/dml2_dpmm_factory.o 128 128 - DML21 += src/dml2_mcg/dml2_mcg_dcn4.o 129 129 - DML21 += src/dml2_mcg/dml2_mcg_factory.o 130 130 - DML21 += src/dml2_pmo/dml2_pmo_dcn3.o 131 131 - DML21 += src/dml2_pmo/dml2_pmo_factory.o 132 132 - DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o 133 133 - DML21 += src/dml2_standalone_libraries/lib_float_math.o 134 134 - DML21 += dml21_translation_helper.o 135 135 - DML21 += dml21_wrapper.o 136 136 - DML21 += dml21_utils.o 137 137 - 138 138 - AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2/dml21/,$(DML21)) 139 139 - 140 140 - AMD_DISPLAY_FILES += $(AMD_DAL_DML21) 141 141 -

+9 -9

drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h

reviewed

··· 53 53 typedef const char *const_pchar; 54 54 55 55 typedef struct rgba_struct { 56 56 - uint8 a; 57 57 - uint8 r; 58 58 - uint8 g; 59 59 - uint8 b; 56 56 + uint8 a; 57 57 + uint8 r; 58 58 + uint8 g; 59 59 + uint8 b; 60 60 } rgba_t; 61 61 62 62 typedef struct { 63 63 - uint8 blue; 64 64 - uint8 green; 65 65 - uint8 red; 66 66 - uint8 alpha; 63 63 + uint8 blue; 64 64 + uint8 green; 65 65 + uint8 red; 66 66 + uint8 alpha; 67 67 } gen_color_t; 68 68 69 69 typedef union { ··· 87 87 } uintfloat64; 88 88 89 89 #ifndef UNREFERENCED_PARAMETER 90 90 - #define UNREFERENCED_PARAMETER(x) x = x 90 90 + #define UNREFERENCED_PARAMETER(x) (x = x) 91 91 #endif 92 92 #endif 93 93

+2

drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

reviewed

··· 10205 10205 return (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[plane_idx] == dml_use_mall_pstate_change_phantom_pipe); 10206 10206 } 10207 10207 10208 10208 + 10208 10209 #define dml_get_per_surface_var_func(variable, type, interval_var) type dml_get_##variable(struct display_mode_lib_st *mode_lib, dml_uint_t surface_idx) \ 10209 10210 { \ 10210 10211 dml_uint_t plane_idx; \ ··· 10334 10333 dml_get_per_surface_var_func(dpte_bytes_per_row, dml_uint_t, mode_lib->mp.PixelPTEBytesPerRow); 10335 10334 dml_get_per_surface_var_func(meta_bytes_per_row, dml_uint_t, mode_lib->mp.MetaRowByte); 10336 10335 dml_get_per_surface_var_func(det_buffer_size_kbytes, dml_uint_t, mode_lib->ms.DETBufferSizeInKByte); 10336 10336 +

drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h

reviewed

+1 -2

drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h

reviewed

··· 274 274 dml_use_state_freq = 2 275 275 }; 276 276 277 277 - 278 277 struct soc_state_bounding_box_st { 279 278 dml_float_t socclk_mhz; 280 279 dml_float_t dscclk_mhz; ··· 1893 1894 struct CalculatePrefetchSchedule_params_st CalculatePrefetchSchedule_params; 1894 1895 }; 1895 1896 1896 1896 - /// @brief Represent the overall soc/ip environment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output 1897 1897 + /// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output 1897 1898 struct display_mode_lib_st { 1898 1899 dml_uint_t project; 1899 1900

+1 -1

drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h

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··· 52 52 #define __DML_VBA_DEBUG__ 53 53 #define __DML_VBA_ENABLE_INLINE_CHECK_ 0 54 54 #define __DML_VBA_MIN_VSTARTUP__ 9 //<brief At which vstartup the DML start to try if the mode can be supported 55 55 - #define __DML_ARB_TO_RET_DELAY__ 7 + 95 //<brief Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET) 55 55 + #define __DML_ARB_TO_RET_DELAY__ (7 + 95) //<brief Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET) 56 56 #define __DML_MIN_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation 57 57 #define __DML_MAX_VRATIO_PRE__ 4.0 //<brief Prefetch schedule max vratio 58 58 #define __DML_MAX_VRATIO_PRE_OTO__ 4.0 //<brief Prefetch schedule max vratio for one to one scheduling calculation for prefetch

drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c

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-2

drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h

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··· 30 30 #include "display_mode_core_structs.h" 31 31 #include "cmntypes.h" 32 32 33 33 - 34 33 #include "dml_assert.h" 35 34 #include "dml_logging.h" 36 35 ··· 70 71 __DML_DLL_EXPORT__ dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx); 71 72 __DML_DLL_EXPORT__ dml_uint_t dml_get_pipe_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t plane_idx); 72 73 __DML_DLL_EXPORT__ void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane); 73 73 - 74 74 75 75 #endif

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

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+1 -3

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

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··· 224 224 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 225 225 226 226 /* Populate stream, plane mappings and other fields in display config. */ 227 227 - DC_FP_START(); 228 227 result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 229 229 - DC_FP_END(); 230 228 if (!result) 231 229 return false; 232 230 ··· 279 281 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 280 282 281 283 mode_support->dml2_instance = dml_init->dml2_instance; 282 282 - DC_FP_START(); 283 284 dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 284 285 dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; 286 286 + DC_FP_START(); 285 287 is_supported = dml2_check_mode_supported(mode_support); 286 288 DC_FP_END(); 287 289 if (!is_supported)

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h

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-1

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h

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··· 2 2 // 3 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 4 5 5 - 6 5 #ifndef __DML_DML_DCN4_SOC_BB__ 7 6 #define __DML_DML_DCN4_SOC_BB__ 8 7

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml2_external_lib_deps.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_policy_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

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+1

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

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··· 28 28 .writeback_interface_buffer_size_kbytes = 90, 29 29 //Number of pipes after DCN Pipe harvesting 30 30 .max_num_dpp = 4, 31 31 + .max_num_opp = 4, 31 32 .max_num_otg = 4, 32 33 .max_num_wb = 1, 33 34 .max_dchub_pscl_bw_pix_per_clk = 4,

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h

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+26 -3

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

reviewed

··· 1303 1303 MinDSCBPP = 8; 1304 1304 MaxDSCBPP = 16; 1305 1305 } else { 1306 1306 + 1306 1307 if (Output == dml2_hdmi || Output == dml2_hdmifrl) { 1307 1308 NonDSCBPP0 = 24; 1308 1309 NonDSCBPP1 = 24; ··· 1321 1320 MaxDSCBPP = 16; 1322 1321 } 1323 1322 } 1323 1323 + 1324 1324 if (Output == dml2_dp2p0) { 1325 1325 MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128.0 / 132.0 * 383.0 / 384.0 * 65536.0 / 65540.0; 1326 1326 } else if (DSCEnable && Output == dml2_dp) { ··· 4049 4047 bool UseDSC, 4050 4048 unsigned int NumberOfDSCSlices, 4051 4049 unsigned int TotalNumberOfActiveDPP, 4050 4050 + unsigned int TotalNumberOfActiveOPP, 4052 4051 unsigned int MaxNumDPP, 4052 4052 + unsigned int MaxNumOPP, 4053 4053 double DISPCLKRequired, 4054 4054 unsigned int NumberOfDPPRequired, 4055 4055 unsigned int MaxHActiveForDSC, ··· 4067 4063 4068 4064 if (DISPCLKRequired > MaxDispclk) 4069 4065 return false; 4070 4070 - if ((TotalNumberOfActiveDPP + NumberOfDPPRequired) > MaxNumDPP) 4066 4066 + if ((TotalNumberOfActiveDPP + NumberOfDPPRequired) > MaxNumDPP || (TotalNumberOfActiveOPP + NumberOfDPPRequired) > MaxNumOPP) 4071 4067 return false; 4072 4068 if (are_odm_segments_symmetrical) { 4073 4069 if (HActive % (NumberOfDPPRequired * pixels_per_clock_cycle)) ··· 4113 4109 double MaxDispclk, 4114 4110 bool DSCEnable, 4115 4111 unsigned int TotalNumberOfActiveDPP, 4112 4112 + unsigned int TotalNumberOfActiveOPP, 4116 4113 unsigned int MaxNumDPP, 4114 4114 + unsigned int MaxNumOPP, 4117 4115 double PixelClock, 4118 4116 unsigned int NumberOfDSCSlices, 4119 4117 ··· 4185 4179 UseDSC, 4186 4180 NumberOfDSCSlices, 4187 4181 TotalNumberOfActiveDPP, 4182 4182 + TotalNumberOfActiveOPP, 4188 4183 MaxNumDPP, 4184 4184 + MaxNumOPP, 4189 4185 DISPCLKRequired, 4190 4186 NumberOfDPPRequired, 4191 4187 MaxHActiveForDSC, ··· 8366 8358 CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params); 8367 8359 8368 8360 mode_lib->ms.TotalNumberOfActiveDPP = 0; 8361 8361 + mode_lib->ms.TotalNumberOfActiveOPP = 0; 8369 8362 mode_lib->ms.support.TotalAvailablePipesSupport = true; 8370 8363 8371 8364 for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { ··· 8402 8393 mode_lib->ms.max_dispclk_freq_mhz, 8403 8394 false, // DSCEnable 8404 8395 mode_lib->ms.TotalNumberOfActiveDPP, 8396 8396 + mode_lib->ms.TotalNumberOfActiveOPP, 8405 8397 mode_lib->ip.max_num_dpp, 8398 8398 + mode_lib->ip.max_num_opp, 8406 8399 ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000), 8407 8400 mode_lib->ms.support.NumberOfDSCSlices[k], 8408 8401 ··· 8423 8412 mode_lib->ms.max_dispclk_freq_mhz, 8424 8413 true, // DSCEnable 8425 8414 mode_lib->ms.TotalNumberOfActiveDPP, 8415 8415 + mode_lib->ms.TotalNumberOfActiveOPP, 8426 8416 mode_lib->ip.max_num_dpp, 8417 8417 + mode_lib->ip.max_num_opp, 8427 8418 ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000), 8428 8419 mode_lib->ms.support.NumberOfDSCSlices[k], 8429 8420 ··· 8529 8516 for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { 8530 8517 mode_lib->ms.MPCCombine[k] = false; 8531 8518 mode_lib->ms.NoOfDPP[k] = 1; 8519 8519 + mode_lib->ms.NoOfOPP[k] = 1; 8532 8520 8533 8521 if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1) { 8534 8522 mode_lib->ms.MPCCombine[k] = false; 8535 8523 mode_lib->ms.NoOfDPP[k] = 4; 8524 8524 + mode_lib->ms.NoOfOPP[k] = 4; 8536 8525 } else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1) { 8537 8526 mode_lib->ms.MPCCombine[k] = false; 8538 8527 mode_lib->ms.NoOfDPP[k] = 3; 8528 8528 + mode_lib->ms.NoOfOPP[k] = 3; 8539 8529 } else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1) { 8540 8530 mode_lib->ms.MPCCombine[k] = false; 8541 8531 mode_lib->ms.NoOfDPP[k] = 2; 8532 8532 + mode_lib->ms.NoOfOPP[k] = 2; 8542 8533 } else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 2) { 8543 8534 mode_lib->ms.MPCCombine[k] = true; 8544 8535 mode_lib->ms.NoOfDPP[k] = 2; 8545 8545 - mode_lib->ms.TotalNumberOfActiveDPP++; 8546 8536 } else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 1) { 8547 8537 mode_lib->ms.MPCCombine[k] = false; 8548 8538 mode_lib->ms.NoOfDPP[k] = 1; ··· 8556 8540 if ((mode_lib->ms.MinDPPCLKUsingSingleDPP[k] > mode_lib->ms.max_dppclk_freq_mhz) || !mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k]) { 8557 8541 mode_lib->ms.MPCCombine[k] = true; 8558 8542 mode_lib->ms.NoOfDPP[k] = 2; 8559 8559 - mode_lib->ms.TotalNumberOfActiveDPP++; 8560 8543 } 8561 8544 } 8562 8545 #if defined(__DML_VBA_DEBUG__) ··· 8563 8548 #endif 8564 8549 } 8565 8550 8551 8551 + mode_lib->ms.TotalNumberOfActiveDPP = 0; 8552 8552 + mode_lib->ms.TotalNumberOfActiveOPP = 0; 8553 8553 + for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { 8554 8554 + mode_lib->ms.TotalNumberOfActiveDPP += mode_lib->ms.NoOfDPP[k]; 8555 8555 + mode_lib->ms.TotalNumberOfActiveOPP += mode_lib->ms.NoOfOPP[k]; 8556 8556 + } 8566 8557 if (mode_lib->ms.TotalNumberOfActiveDPP > (unsigned int)mode_lib->ip.max_num_dpp) 8558 8558 + mode_lib->ms.support.TotalAvailablePipesSupport = false; 8559 8559 + if (mode_lib->ms.TotalNumberOfActiveOPP > (unsigned int)mode_lib->ip.max_num_opp) 8567 8560 mode_lib->ms.support.TotalAvailablePipesSupport = false; 8568 8561 8569 8562

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h

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+3

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h

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··· 36 36 unsigned int max_line_buffer_lines; 37 37 unsigned int writeback_interface_buffer_size_kbytes; 38 38 unsigned int max_num_dpp; 39 39 + unsigned int max_num_opp; 39 40 unsigned int max_num_otg; 40 41 unsigned int TDLUT_33cube_count; 41 42 unsigned int max_num_wb; ··· 571 570 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 572 571 unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; 573 572 unsigned int NoOfDPP[DML2_MAX_PLANES]; 573 573 + unsigned int NoOfOPP[DML2_MAX_PLANES]; 574 574 bool MPCCombine[DML2_MAX_PLANES]; 575 575 double dcfclk_deepsleep; 576 576 double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES]; ··· 582 580 bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES]; 583 581 bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES]; 584 582 unsigned int TotalNumberOfActiveDPP; 583 583 + unsigned int TotalNumberOfActiveOPP; 585 584 unsigned int TotalNumberOfSingleDPPSurfaces; 586 585 unsigned int TotalNumberOfDCCActiveDPP; 587 586 unsigned int Total3dlutActive;

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_legacy.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_legacy.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_debug.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h

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drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

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drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

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drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h

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drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h

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+1 -1

drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

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··· 23 23 * Authors: AMD 24 24 * 25 25 */ 26 26 - 26 26 + 27 27 #ifndef __DML2_INTERNAL_TYPES_H__ 28 28 #define __DML2_INTERNAL_TYPES_H__ 29 29

+1

drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

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··· 24 24 * 25 25 */ 26 26 27 27 + 27 28 #include "dml2_dc_types.h" 28 29 #include "dml2_internal_types.h" 29 30 #include "dml2_utils.h"

drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h

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drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c

reviewed

drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h

reviewed

+3

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

reviewed

··· 301 301 out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0; 302 302 break; 303 303 304 304 + 304 305 case dml_project_dcn401: 305 306 out->pct_ideal_fabric_bw_after_urgent = 76; //67; 306 307 out->max_avg_sdp_bw_use_normal_percent = 75; //80; ··· 425 424 p->in_states->state_array[1].dcfclk_mhz = 1434.0; 426 425 p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock; 427 426 break; 427 427 + 428 428 + 428 429 case dml_project_dcn401: 429 430 p->in_states->num_states = 2; 430 431 transactions_per_mem_clock = 16;

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

reviewed

drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

reviewed

drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

reviewed

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

reviewed

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

reviewed

drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h

reviewed

+1

drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h

reviewed

··· 31 31 */ 32 32 #include "os_types.h" 33 33 #include "cmntypes.h" 34 34 +

drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

reviewed

drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h

reviewed

+1

drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h

reviewed

··· 23 23 * Authors: AMD 24 24 * 25 25 */ 26 26 + 26 27 #ifndef __DML_LOGGING_H__ 27 28 #define __DML_LOGGING_H__ 28 29

+140

drivers/gpu/drm/amd/display/dc/dml2_0/Makefile

reviewed

··· 1 1 + # SPDX-License-Identifier: MIT */ 2 2 + # 3 3 + # Copyright 2023 Advanced Micro Devices, Inc. 4 4 + # 5 5 + # Permission is hereby granted, free of charge, to any person obtaining a 6 6 + # copy of this software and associated documentation files (the "Software"), 7 7 + # to deal in the Software without restriction, including without limitation 8 8 + # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 9 + # and/or sell copies of the Software, and to permit persons to whom the 10 10 + # Software is furnished to do so, subject to the following conditions: 11 11 + # 12 12 + # The above copyright notice and this permission notice shall be included in 13 13 + # all copies or substantial portions of the Software. 14 14 + # 15 15 + # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 16 + # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 17 + # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 18 + # THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 19 + # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 20 + # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 21 + # OTHER DEALINGS IN THE SOFTWARE. 22 22 + # 23 23 + # Authors: AMD 24 24 + # 25 25 + # Makefile for dml2. 26 26 + 27 27 + dml2_ccflags := $(CC_FLAGS_FPU) 28 28 + dml2_rcflags := $(CC_FLAGS_NO_FPU) 29 29 + 30 30 + ifneq ($(CONFIG_FRAME_WARN),0) 31 31 + ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) 32 32 + ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy) 33 33 + frame_warn_limit := 4096 34 34 + else 35 35 + frame_warn_limit := 3072 36 36 + endif 37 37 + else 38 38 + frame_warn_limit := 2056 39 39 + endif 40 40 + 41 41 + ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y) 42 42 + frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit) 43 43 + endif 44 44 + endif 45 45 + 46 46 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0 47 47 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_core 48 48 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_mcg/ 49 49 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_dpmm/ 50 50 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_pmo/ 51 51 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/ 52 52 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/inc 53 53 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/inc 54 54 + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/ 55 55 + 56 56 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) 57 57 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_ccflags) 58 58 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_ccflags) 59 59 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_ccflags) 60 60 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_ccflags) 61 61 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_ccflags) 62 62 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_ccflags) 63 63 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_ccflags) 64 64 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_ccflags) 65 65 + 66 66 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_rcflags) 67 67 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_rcflags) 68 68 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_rcflags) 69 69 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_rcflags) 70 70 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_rcflags) 71 71 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_rcflags) 72 72 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_rcflags) 73 73 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_rcflags) 74 74 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_rcflags) 75 75 + 76 76 + DML2 = display_mode_core.o display_mode_util.o dml2_wrapper.o \ 77 77 + dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \ 78 78 + dml_display_rq_dlg_calc.o 79 79 + 80 80 + AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2)) 81 81 + 82 82 + AMD_DISPLAY_FILES += $(AMD_DAL_DML2) 83 83 + 84 84 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags) 85 85 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) 86 86 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) 87 87 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags) 88 88 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags) 89 89 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags) 90 90 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) 91 91 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) 92 92 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) 93 93 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) 94 94 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) 95 95 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) 96 96 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags) 97 97 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags) 98 98 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_ccflags) 99 99 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_ccflags) 100 100 + CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_ccflags) 101 101 + 102 102 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags) 103 103 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) 104 104 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags) 105 105 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) 106 106 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags) 107 107 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags) 108 108 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) 109 109 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) 110 110 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) 111 111 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) 112 112 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) 113 113 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) 114 114 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags) 115 115 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags) 116 116 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_rcflags) 117 117 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_rcflags) 118 118 + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_rcflags) 119 119 + 120 120 + DML21 := src/dml2_top/dml2_top_interfaces.o 121 121 + DML21 += src/dml2_top/dml2_top_soc15.o 122 122 + DML21 += src/dml2_core/dml2_core_dcn4.o 123 123 + DML21 += src/dml2_core/dml2_core_utils.o 124 124 + DML21 += src/dml2_core/dml2_core_factory.o 125 125 + DML21 += src/dml2_core/dml2_core_dcn4_calcs.o 126 126 + DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o 127 127 + DML21 += src/dml2_dpmm/dml2_dpmm_factory.o 128 128 + DML21 += src/dml2_mcg/dml2_mcg_dcn4.o 129 129 + DML21 += src/dml2_mcg/dml2_mcg_factory.o 130 130 + DML21 += src/dml2_pmo/dml2_pmo_dcn3.o 131 131 + DML21 += src/dml2_pmo/dml2_pmo_factory.o 132 132 + DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o 133 133 + DML21 += src/dml2_standalone_libraries/lib_float_math.o 134 134 + DML21 += dml21_translation_helper.o 135 135 + DML21 += dml21_wrapper.o 136 136 + DML21 += dml21_utils.o 137 137 + 138 138 + AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2_0/dml21/,$(DML21)) 139 139 + 140 140 + AMD_DISPLAY_FILES += $(AMD_DAL_DML21)

+2 -2

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

reviewed

··· 1348 1348 uint32_t CURSOR0_COLOR1; \ 1349 1349 uint32_t DPP_CONTROL; \ 1350 1350 uint32_t CM_HDR_MULT_COEF; \ 1351 1351 - uint32_t CURSOR0_FP_SCALE_BIAS; 1351 1351 + uint32_t CURSOR0_FP_SCALE_BIAS; \ 1352 1352 + uint32_t OBUF_CONTROL; 1352 1353 1353 1354 struct dcn_dpp_registers { 1354 1355 DPP_COMMON_REG_VARIABLE_LIST ··· 1450 1449 1451 1450 void dpp1_set_degamma_pwl(struct dpp *dpp_base, 1452 1451 const struct pwl_params *params); 1453 1453 - 1454 1452 1455 1453 void dpp_read_state(struct dpp *dpp_base, 1456 1454 struct dcn_dpp_state *s);

+16 -3

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

reviewed

··· 84 84 } 85 85 } 86 86 87 87 + void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state) 88 88 + { 89 89 + struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 90 90 + 91 91 + dpp_reg_state->recout_start = REG_READ(RECOUT_START); 92 92 + dpp_reg_state->recout_size = REG_READ(RECOUT_SIZE); 93 93 + dpp_reg_state->scl_horz_filter_scale_ratio = REG_READ(SCL_HORZ_FILTER_SCALE_RATIO); 94 94 + dpp_reg_state->scl_vert_filter_scale_ratio = REG_READ(SCL_VERT_FILTER_SCALE_RATIO); 95 95 + dpp_reg_state->scl_mode = REG_READ(SCL_MODE); 96 96 + dpp_reg_state->cm_control = REG_READ(CM_CONTROL); 97 97 + dpp_reg_state->dpp_control = REG_READ(DPP_CONTROL); 98 98 + dpp_reg_state->dscl_control = REG_READ(DSCL_CONTROL); 99 99 + dpp_reg_state->obuf_control = REG_READ(OBUF_CONTROL); 100 100 + dpp_reg_state->mpc_size = REG_READ(MPC_SIZE); 101 101 + } 102 102 + 87 103 /*program post scaler scs block in dpp CM*/ 88 104 void dpp3_program_post_csc( 89 105 struct dpp *dpp_base, ··· 598 582 dpp_base->ctx->dc->optimized_required = true; 599 583 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; 600 584 } 601 601 - } else { 602 602 - REG_SET(CM_MEM_PWR_CTRL, 0, 603 603 - BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1); 604 585 } 605 586 } 606 587

+2

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

reviewed

··· 594 594 void dpp30_read_state(struct dpp *dpp_base, 595 595 struct dcn_dpp_state *s); 596 596 597 597 + void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state); 598 598 + 597 599 bool dpp3_get_optimal_number_of_taps( 598 600 struct dpp *dpp, 599 601 struct scaler_data *scl_data,

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

reviewed

··· 134 134 .dpp_dppclk_control = dpp1_dppclk_control, 135 135 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, 136 136 .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap, 137 137 + .dpp_read_reg_state = dpp30_read_reg_state, 137 138 }; 138 139 139 140

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

reviewed

··· 95 95 static struct dpp_funcs dcn35_dpp_funcs = { 96 96 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, 97 97 .dpp_read_state = dpp30_read_state, 98 98 + .dpp_read_reg_state = dpp30_read_reg_state, 98 99 .dpp_reset = dpp_reset, 99 100 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 100 101 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

reviewed

··· 248 248 .set_optional_cursor_attributes = dpp401_set_optional_cursor_attributes, 249 249 .dpp_dppclk_control = dpp1_dppclk_control, 250 250 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, 251 251 + .dpp_read_reg_state = dpp30_read_reg_state, 251 252 .set_cursor_matrix = dpp401_set_cursor_matrix, 252 253 }; 253 254

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

reviewed

··· 141 141 } 142 142 143 143 dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; 144 144 + dpp_base->att.cur0_ctl.bits.cur0_enable = cur_en; 144 145 } 145 146 146 147 void dpp401_set_optional_cursor_attributes(

+8

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

reviewed

··· 35 35 static const struct dsc_funcs dcn20_dsc_funcs = { 36 36 .dsc_get_enc_caps = dsc2_get_enc_caps, 37 37 .dsc_read_state = dsc2_read_state, 38 38 + .dsc_read_reg_state = dsc2_read_reg_state, 38 39 .dsc_validate_stream = dsc2_validate_stream, 39 40 .dsc_set_config = dsc2_set_config, 40 41 .dsc_get_packed_pps = dsc2_get_packed_pps, ··· 156 155 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); 157 156 } 158 157 158 158 + void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state) 159 159 + { 160 160 + struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 161 161 + 162 162 + dccg_reg_state->dsc_top_control = REG_READ(DSC_TOP_CONTROL); 163 163 + dccg_reg_state->dscc_interrupt_control_status = REG_READ(DSCC_INTERRUPT_CONTROL_STATUS); 164 164 + } 159 165 160 166 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 161 167 {

+1

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

reviewed

··· 606 606 uint8_t *dsc_packed_pps); 607 607 608 608 void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 609 609 + void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state); 609 610 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 610 611 void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 611 612 struct dsc_optc_config *dsc_optc_cfg);

+1

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

reviewed

··· 32 32 static const struct dsc_funcs dcn35_dsc_funcs = { 33 33 .dsc_get_enc_caps = dsc2_get_enc_caps, 34 34 .dsc_read_state = dsc2_read_state, 35 35 + .dsc_read_reg_state = dsc2_read_reg_state, 35 36 .dsc_validate_stream = dsc2_validate_stream, 36 37 .dsc_set_config = dsc2_set_config, 37 38 .dsc_get_packed_pps = dsc2_get_packed_pps,

+1

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

reviewed

··· 26 26 .dsc_disconnect = dsc401_disconnect, 27 27 .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear, 28 28 .dsc_get_single_enc_caps = dsc401_get_single_enc_caps, 29 29 + .dsc_read_reg_state = dsc2_read_reg_state 29 30 }; 30 31 31 32 /* Macro definitios for REG_SET macros*/

+5

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

reviewed

··· 66 66 uint32_t dsc_opp_source; 67 67 }; 68 68 69 69 + struct dcn_dsc_reg_state { 70 70 + uint32_t dsc_top_control; 71 71 + uint32_t dscc_interrupt_control_status; 72 72 + }; 69 73 70 74 /* DSC encoder capabilities 71 75 * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps. ··· 104 100 struct dsc_funcs { 105 101 void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 106 102 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 103 103 + void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state); 107 104 bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 108 105 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 109 106 struct dsc_optc_config *dsc_optc_cfg);

+7 -26

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

reviewed

··· 440 440 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg); 441 441 } 442 442 443 443 - void hubbub3_get_det_sizes(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes) 443 443 + void hubbub3_read_reg_state(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state) 444 444 { 445 445 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 446 446 447 447 - REG_GET_2(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, &curr_det_sizes[0], 448 448 - DET0_SIZE, &target_det_sizes[0]); 449 449 - 450 450 - REG_GET_2(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, &curr_det_sizes[1], 451 451 - DET1_SIZE, &target_det_sizes[1]); 452 452 - 453 453 - REG_GET_2(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, &curr_det_sizes[2], 454 454 - DET2_SIZE, &target_det_sizes[2]); 455 455 - 456 456 - REG_GET_2(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, &curr_det_sizes[3], 457 457 - DET3_SIZE, &target_det_sizes[3]); 458 458 - 459 459 - } 460 460 - 461 461 - uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub) 462 462 - { 463 463 - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 464 464 - uint32_t compbuf_config_error = 0; 465 465 - 466 466 - REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, 467 467 - &compbuf_config_error); 468 468 - 469 469 - return compbuf_config_error; 447 447 + hubbub_reg_state->det0_ctrl = REG_READ(DCHUBBUB_DET0_CTRL); 448 448 + hubbub_reg_state->det1_ctrl = REG_READ(DCHUBBUB_DET1_CTRL); 449 449 + hubbub_reg_state->det2_ctrl = REG_READ(DCHUBBUB_DET2_CTRL); 450 450 + hubbub_reg_state->det3_ctrl = REG_READ(DCHUBBUB_DET3_CTRL); 451 451 + hubbub_reg_state->compbuf_ctrl = REG_READ(DCHUBBUB_COMPBUF_CTRL); 470 452 } 471 453 472 454 static const struct hubbub_funcs hubbub30_funcs = { ··· 468 486 .force_pstate_change_control = hubbub3_force_pstate_change_control, 469 487 .init_watermarks = hubbub3_init_watermarks, 470 488 .hubbub_read_state = hubbub2_read_state, 471 471 - .get_det_sizes = hubbub3_get_det_sizes, 472 472 - .compbuf_config_error = hubbub3_compbuf_config_error, 489 489 + .hubbub_read_reg_state = hubbub3_read_reg_state 473 490 }; 474 491 475 492 void hubbub3_construct(struct dcn20_hubbub *hubbub3,

+1 -5

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h

reviewed

··· 133 133 134 134 void hubbub3_init_watermarks(struct hubbub *hubbub); 135 135 136 136 - void hubbub3_get_det_sizes(struct hubbub *hubbub, 137 137 - uint32_t *curr_det_sizes, 138 138 - uint32_t *target_det_sizes); 139 139 - 140 140 - uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub); 136 136 + void hubbub3_read_reg_state(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state); 141 137 142 138 #endif

+1 -2

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

reviewed

··· 1071 1071 .program_compbuf_size = dcn31_program_compbuf_size, 1072 1072 .init_crb = dcn31_init_crb, 1073 1073 .hubbub_read_state = hubbub2_read_state, 1074 1074 - .get_det_sizes = hubbub3_get_det_sizes, 1075 1075 - .compbuf_config_error = hubbub3_compbuf_config_error, 1074 1074 + .hubbub_read_reg_state = hubbub3_read_reg_state 1076 1075 }; 1077 1076 1078 1077 void hubbub31_construct(struct dcn20_hubbub *hubbub31,

+1 -2

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

reviewed

··· 1037 1037 .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, 1038 1038 .set_request_limit = hubbub32_set_request_limit, 1039 1039 .get_mall_en = hubbub32_get_mall_en, 1040 1040 - .get_det_sizes = hubbub3_get_det_sizes, 1041 1041 - .compbuf_config_error = hubbub3_compbuf_config_error, 1040 1040 + .hubbub_read_reg_state = hubbub3_read_reg_state 1042 1041 }; 1043 1042 1044 1043 void hubbub32_construct(struct dcn20_hubbub *hubbub2,

+1 -2

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

reviewed

··· 589 589 .hubbub_read_state = hubbub2_read_state, 590 590 .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, 591 591 .dchubbub_init = hubbub35_init, 592 592 - .get_det_sizes = hubbub3_get_det_sizes, 593 593 - .compbuf_config_error = hubbub3_compbuf_config_error, 592 592 + .hubbub_read_reg_state = hubbub3_read_reg_state 594 593 }; 595 594 596 595 void hubbub35_construct(struct dcn20_hubbub *hubbub2,

+1 -2

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

reviewed

··· 1247 1247 .program_compbuf_segments = dcn401_program_compbuf_segments, 1248 1248 .wait_for_det_update = dcn401_wait_for_det_update, 1249 1249 .program_arbiter = dcn401_program_arbiter, 1250 1250 - .get_det_sizes = hubbub3_get_det_sizes, 1251 1251 - .compbuf_config_error = hubbub3_compbuf_config_error, 1250 1250 + .hubbub_read_reg_state = hubbub3_read_reg_state 1252 1251 }; 1253 1252 1254 1253 void hubbub401_construct(struct dcn20_hubbub *hubbub2,

+133 -3

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

reviewed

··· 105 105 SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ 106 106 SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ 107 107 SRI(HUBP_CLK_CNTL, HUBP, id),\ 108 108 - SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id) 108 108 + SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id),\ 109 109 + SRI(HUBP_MEASURE_WIN_CTRL_DCFCLK, HUBP, id),\ 110 110 + SRI(HUBP_MEASURE_WIN_CTRL_DPPCLK, HUBP, id) 109 111 110 112 /* Register address initialization macro for ASICs with VM */ 111 113 #define HUBP_REG_LIST_DCN_VM(id)\ ··· 253 251 uint32_t CURSOR_HOT_SPOT; \ 254 252 uint32_t CURSOR_DST_OFFSET; \ 255 253 uint32_t HUBP_CLK_CNTL; \ 256 256 - uint32_t HUBPRET_READ_LINE_VALUE 254 254 + uint32_t HUBPRET_READ_LINE_VALUE; \ 255 255 + uint32_t HUBP_MEASURE_WIN_CTRL_DCFCLK; \ 256 256 + uint32_t HUBP_MEASURE_WIN_CTRL_DPPCLK; \ 257 257 + uint32_t HUBPRET_INTERRUPT; \ 258 258 + uint32_t HUBPRET_MEM_PWR_CTRL; \ 259 259 + uint32_t HUBPRET_MEM_PWR_STATUS; \ 260 260 + uint32_t HUBPRET_READ_LINE_CTRL0; \ 261 261 + uint32_t HUBPRET_READ_LINE_CTRL1; \ 262 262 + uint32_t HUBPRET_READ_LINE0; \ 263 263 + uint32_t HUBPRET_READ_LINE1; \ 264 264 + uint32_t HUBPREQ_MEM_PWR_CTRL; \ 265 265 + uint32_t HUBPREQ_MEM_PWR_STATUS 266 266 + 257 267 258 268 #define HUBP_SF(reg_name, field_name, post_fix)\ 259 269 .field_name = reg_name ## __ ## field_name ## post_fix ··· 702 688 uint32_t lut_fl_mode; 703 689 uint32_t lut_fl_format; 704 690 }; 691 691 + struct dcn_hubp_reg_state { 692 692 + uint32_t hubp_cntl; 693 693 + uint32_t mall_config; 694 694 + uint32_t mall_sub_vp; 695 695 + uint32_t hubp_req_size_config; 696 696 + uint32_t hubp_req_size_config_c; 697 697 + uint32_t vmpg_config; 698 698 + uint32_t addr_config; 699 699 + uint32_t pri_viewport_dimension; 700 700 + uint32_t pri_viewport_dimension_c; 701 701 + uint32_t pri_viewport_start; 702 702 + uint32_t pri_viewport_start_c; 703 703 + uint32_t sec_viewport_dimension; 704 704 + uint32_t sec_viewport_dimension_c; 705 705 + uint32_t sec_viewport_start; 706 706 + uint32_t sec_viewport_start_c; 707 707 + uint32_t surface_config; 708 708 + uint32_t tiling_config; 709 709 + uint32_t clk_cntl; 710 710 + uint32_t mall_status; 711 711 + uint32_t measure_win_ctrl_dcfclk; 712 712 + uint32_t measure_win_ctrl_dppclk; 713 713 + 714 714 + uint32_t blank_offset_0; 715 715 + uint32_t blank_offset_1; 716 716 + uint32_t cursor_settings; 717 717 + uint32_t dcn_cur0_ttu_cntl0; 718 718 + uint32_t dcn_cur0_ttu_cntl1; 719 719 + uint32_t dcn_cur1_ttu_cntl0; 720 720 + uint32_t dcn_cur1_ttu_cntl1; 721 721 + uint32_t dcn_dmdat_vm_cntl; 722 722 + uint32_t dcn_expansion_mode; 723 723 + uint32_t dcn_global_ttu_cntl; 724 724 + uint32_t dcn_surf0_ttu_cntl0; 725 725 + uint32_t dcn_surf0_ttu_cntl1; 726 726 + uint32_t dcn_surf1_ttu_cntl0; 727 727 + uint32_t dcn_surf1_ttu_cntl1; 728 728 + uint32_t dcn_ttu_qos_wm; 729 729 + uint32_t dcn_vm_mx_l1_tlb_cntl; 730 730 + uint32_t dcn_vm_system_aperture_high_addr; 731 731 + uint32_t dcn_vm_system_aperture_low_addr; 732 732 + uint32_t dcsurf_flip_control; 733 733 + uint32_t dcsurf_flip_control2; 734 734 + uint32_t dcsurf_primary_meta_surface_address; 735 735 + uint32_t dcsurf_primary_meta_surface_address_c; 736 736 + uint32_t dcsurf_primary_meta_surface_address_high; 737 737 + uint32_t dcsurf_primary_meta_surface_address_high_c; 738 738 + uint32_t dcsurf_primary_surface_address; 739 739 + uint32_t dcsurf_primary_surface_address_c; 740 740 + uint32_t dcsurf_primary_surface_address_high; 741 741 + uint32_t dcsurf_primary_surface_address_high_c; 742 742 + uint32_t dcsurf_secondary_meta_surface_address; 743 743 + uint32_t dcsurf_secondary_meta_surface_address_c; 744 744 + uint32_t dcsurf_secondary_meta_surface_address_high; 745 745 + uint32_t dcsurf_secondary_meta_surface_address_high_c; 746 746 + uint32_t dcsurf_secondary_surface_address; 747 747 + uint32_t dcsurf_secondary_surface_address_c; 748 748 + uint32_t dcsurf_secondary_surface_address_high; 749 749 + uint32_t dcsurf_secondary_surface_address_high_c; 750 750 + uint32_t dcsurf_surface_control; 751 751 + uint32_t dcsurf_surface_earliest_inuse; 752 752 + uint32_t dcsurf_surface_earliest_inuse_c; 753 753 + uint32_t dcsurf_surface_earliest_inuse_high; 754 754 + uint32_t dcsurf_surface_earliest_inuse_high_c; 755 755 + uint32_t dcsurf_surface_flip_interrupt; 756 756 + uint32_t dcsurf_surface_inuse; 757 757 + uint32_t dcsurf_surface_inuse_c; 758 758 + uint32_t dcsurf_surface_inuse_high; 759 759 + uint32_t dcsurf_surface_inuse_high_c; 760 760 + uint32_t dcsurf_surface_pitch; 761 761 + uint32_t dcsurf_surface_pitch_c; 762 762 + uint32_t dst_after_scaler; 763 763 + uint32_t dst_dimensions; 764 764 + uint32_t dst_y_delta_drq_limit; 765 765 + uint32_t flip_parameters_0; 766 766 + uint32_t flip_parameters_1; 767 767 + uint32_t flip_parameters_2; 768 768 + uint32_t flip_parameters_3; 769 769 + uint32_t flip_parameters_4; 770 770 + uint32_t flip_parameters_5; 771 771 + uint32_t flip_parameters_6; 772 772 + uint32_t hubpreq_mem_pwr_ctrl; 773 773 + uint32_t hubpreq_mem_pwr_status; 774 774 + uint32_t nom_parameters_0; 775 775 + uint32_t nom_parameters_1; 776 776 + uint32_t nom_parameters_2; 777 777 + uint32_t nom_parameters_3; 778 778 + uint32_t nom_parameters_4; 779 779 + uint32_t nom_parameters_5; 780 780 + uint32_t nom_parameters_6; 781 781 + uint32_t nom_parameters_7; 782 782 + uint32_t per_line_delivery; 783 783 + uint32_t per_line_delivery_pre; 784 784 + uint32_t prefetch_settings; 785 785 + uint32_t prefetch_settings_c; 786 786 + uint32_t ref_freq_to_pix_freq; 787 787 + uint32_t uclk_pstate_force; 788 788 + uint32_t vblank_parameters_0; 789 789 + uint32_t vblank_parameters_1; 790 790 + uint32_t vblank_parameters_2; 791 791 + uint32_t vblank_parameters_3; 792 792 + uint32_t vblank_parameters_4; 793 793 + uint32_t vblank_parameters_5; 794 794 + uint32_t vblank_parameters_6; 795 795 + uint32_t vmid_settings_0; 796 796 + 797 797 + uint32_t hubpret_control; 798 798 + uint32_t hubpret_interrupt; 799 799 + uint32_t hubpret_mem_pwr_ctrl; 800 800 + uint32_t hubpret_mem_pwr_status; 801 801 + uint32_t hubpret_read_line_ctrl0; 802 802 + uint32_t hubpret_read_line_ctrl1; 803 803 + uint32_t hubpret_read_line_status; 804 804 + uint32_t hubpret_read_line_value; 805 805 + uint32_t hubpret_read_line0; 806 806 + uint32_t hubpret_read_line1; 807 807 + }; 705 808 706 809 struct dcn_hubp_state { 707 810 struct _vcs_dpi_display_dlg_regs_st dlg_attr; ··· 849 718 uint32_t hubp_cntl; 850 719 uint32_t flip_control; 851 720 }; 852 852 - 853 721 struct dcn10_hubp { 854 722 struct hubp base; 855 723 struct dcn_hubp_state state;

+6 -2

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

reviewed

··· 145 145 uint32_t FLIP_PARAMETERS_2;\ 146 146 uint32_t DCN_CUR1_TTU_CNTL0;\ 147 147 uint32_t DCN_CUR1_TTU_CNTL1;\ 148 148 - uint32_t VMID_SETTINGS_0 148 148 + uint32_t VMID_SETTINGS_0;\ 149 149 + uint32_t DST_Y_DELTA_DRQ_LIMIT 149 150 150 151 /*shared with dcn3.x*/ 151 152 #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ ··· 177 176 uint32_t HUBP_3DLUT_CONTROL;\ 178 177 uint32_t HUBP_3DLUT_DLG_PARAM;\ 179 178 uint32_t DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE;\ 180 180 - uint32_t DCHUBP_MCACHEID_CONFIG 179 179 + uint32_t DCHUBP_MCACHEID_CONFIG;\ 180 180 + uint32_t DCHUBP_MALL_SUB_VP;\ 181 181 + uint32_t DCHUBP_ADDR_CONFIG;\ 182 182 + uint32_t HUBP_MALL_STATUS 181 183 182 184 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 183 185 DCN_HUBP_REG_FIELD_BASE_LIST(type); \

+121 -26

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

reviewed

··· 476 476 477 477 } 478 478 479 479 + void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state) 480 480 + { 481 481 + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 482 482 + 483 483 + reg_state->hubp_cntl = REG_READ(DCHUBP_CNTL); 484 484 + reg_state->mall_config = REG_READ(DCHUBP_MALL_CONFIG); 485 485 + reg_state->mall_sub_vp = REG_READ(DCHUBP_MALL_SUB_VP); 486 486 + reg_state->hubp_req_size_config = REG_READ(DCHUBP_REQ_SIZE_CONFIG); 487 487 + reg_state->hubp_req_size_config_c = REG_READ(DCHUBP_REQ_SIZE_CONFIG_C); 488 488 + reg_state->vmpg_config = REG_READ(DCHUBP_VMPG_CONFIG); 489 489 + reg_state->addr_config = REG_READ(DCSURF_ADDR_CONFIG); 490 490 + reg_state->pri_viewport_dimension = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION); 491 491 + reg_state->pri_viewport_dimension_c = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION_C); 492 492 + reg_state->pri_viewport_start = REG_READ(DCSURF_PRI_VIEWPORT_START); 493 493 + reg_state->pri_viewport_start_c = REG_READ(DCSURF_PRI_VIEWPORT_START_C); 494 494 + reg_state->sec_viewport_dimension = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION); 495 495 + reg_state->sec_viewport_dimension_c = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION_C); 496 496 + reg_state->sec_viewport_start = REG_READ(DCSURF_SEC_VIEWPORT_START); 497 497 + reg_state->sec_viewport_start_c = REG_READ(DCSURF_SEC_VIEWPORT_START_C); 498 498 + reg_state->surface_config = REG_READ(DCSURF_SURFACE_CONFIG); 499 499 + reg_state->tiling_config = REG_READ(DCSURF_TILING_CONFIG); 500 500 + reg_state->clk_cntl = REG_READ(HUBP_CLK_CNTL); 501 501 + reg_state->mall_status = REG_READ(HUBP_MALL_STATUS); 502 502 + reg_state->measure_win_ctrl_dcfclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DCFCLK); 503 503 + reg_state->measure_win_ctrl_dppclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DPPCLK); 504 504 + 505 505 + reg_state->blank_offset_0 = REG_READ(BLANK_OFFSET_0); 506 506 + reg_state->blank_offset_1 = REG_READ(BLANK_OFFSET_1); 507 507 + reg_state->cursor_settings = REG_READ(CURSOR_SETTINGS); 508 508 + reg_state->dcn_cur0_ttu_cntl0 = REG_READ(DCN_CUR0_TTU_CNTL0); 509 509 + reg_state->dcn_cur0_ttu_cntl1 = REG_READ(DCN_CUR0_TTU_CNTL1); 510 510 + reg_state->dcn_cur1_ttu_cntl0 = REG_READ(DCN_CUR1_TTU_CNTL0); 511 511 + reg_state->dcn_cur1_ttu_cntl1 = REG_READ(DCN_CUR1_TTU_CNTL1); 512 512 + reg_state->dcn_dmdat_vm_cntl = REG_READ(DCN_DMDATA_VM_CNTL); 513 513 + reg_state->dcn_expansion_mode = REG_READ(DCN_EXPANSION_MODE); 514 514 + reg_state->dcn_global_ttu_cntl = REG_READ(DCN_GLOBAL_TTU_CNTL); 515 515 + reg_state->dcn_surf0_ttu_cntl0 = REG_READ(DCN_SURF0_TTU_CNTL0); 516 516 + reg_state->dcn_surf0_ttu_cntl1 = REG_READ(DCN_SURF0_TTU_CNTL1); 517 517 + reg_state->dcn_surf1_ttu_cntl0 = REG_READ(DCN_SURF1_TTU_CNTL0); 518 518 + reg_state->dcn_surf1_ttu_cntl1 = REG_READ(DCN_SURF1_TTU_CNTL1); 519 519 + reg_state->dcn_ttu_qos_wm = REG_READ(DCN_TTU_QOS_WM); 520 520 + reg_state->dcn_vm_mx_l1_tlb_cntl = REG_READ(DCN_VM_MX_L1_TLB_CNTL); 521 521 + reg_state->dcn_vm_system_aperture_high_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR); 522 522 + reg_state->dcn_vm_system_aperture_low_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_LOW_ADDR); 523 523 + reg_state->dcsurf_flip_control = REG_READ(DCSURF_FLIP_CONTROL); 524 524 + reg_state->dcsurf_flip_control2 = REG_READ(DCSURF_FLIP_CONTROL2); 525 525 + reg_state->dcsurf_primary_meta_surface_address = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS); 526 526 + reg_state->dcsurf_primary_meta_surface_address_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); 527 527 + reg_state->dcsurf_primary_meta_surface_address_high = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); 528 528 + reg_state->dcsurf_primary_meta_surface_address_high_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); 529 529 + reg_state->dcsurf_primary_surface_address = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS); 530 530 + reg_state->dcsurf_primary_surface_address_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_C); 531 531 + reg_state->dcsurf_primary_surface_address_high = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); 532 532 + reg_state->dcsurf_primary_surface_address_high_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); 533 533 + reg_state->dcsurf_secondary_meta_surface_address = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS); 534 534 + reg_state->dcsurf_secondary_meta_surface_address_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C); 535 535 + reg_state->dcsurf_secondary_meta_surface_address_high = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); 536 536 + reg_state->dcsurf_secondary_meta_surface_address_high_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C); 537 537 + reg_state->dcsurf_secondary_surface_address = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS); 538 538 + reg_state->dcsurf_secondary_surface_address_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_C); 539 539 + reg_state->dcsurf_secondary_surface_address_high = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); 540 540 + reg_state->dcsurf_secondary_surface_address_high_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C); 541 541 + reg_state->dcsurf_surface_control = REG_READ(DCSURF_SURFACE_CONTROL); 542 542 + reg_state->dcsurf_surface_earliest_inuse = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE); 543 543 + reg_state->dcsurf_surface_earliest_inuse_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_C); 544 544 + reg_state->dcsurf_surface_earliest_inuse_high = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH); 545 545 + reg_state->dcsurf_surface_earliest_inuse_high_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C); 546 546 + reg_state->dcsurf_surface_flip_interrupt = REG_READ(DCSURF_SURFACE_FLIP_INTERRUPT); 547 547 + reg_state->dcsurf_surface_inuse = REG_READ(DCSURF_SURFACE_INUSE); 548 548 + reg_state->dcsurf_surface_inuse_c = REG_READ(DCSURF_SURFACE_INUSE_C); 549 549 + reg_state->dcsurf_surface_inuse_high = REG_READ(DCSURF_SURFACE_INUSE_HIGH); 550 550 + reg_state->dcsurf_surface_inuse_high_c = REG_READ(DCSURF_SURFACE_INUSE_HIGH_C); 551 551 + reg_state->dcsurf_surface_pitch = REG_READ(DCSURF_SURFACE_PITCH); 552 552 + reg_state->dcsurf_surface_pitch_c = REG_READ(DCSURF_SURFACE_PITCH_C); 553 553 + reg_state->dst_after_scaler = REG_READ(DST_AFTER_SCALER); 554 554 + reg_state->dst_dimensions = REG_READ(DST_DIMENSIONS); 555 555 + reg_state->dst_y_delta_drq_limit = REG_READ(DST_Y_DELTA_DRQ_LIMIT); 556 556 + reg_state->flip_parameters_0 = REG_READ(FLIP_PARAMETERS_0); 557 557 + reg_state->flip_parameters_1 = REG_READ(FLIP_PARAMETERS_1); 558 558 + reg_state->flip_parameters_2 = REG_READ(FLIP_PARAMETERS_2); 559 559 + reg_state->flip_parameters_3 = REG_READ(FLIP_PARAMETERS_3); 560 560 + reg_state->flip_parameters_4 = REG_READ(FLIP_PARAMETERS_4); 561 561 + reg_state->flip_parameters_5 = REG_READ(FLIP_PARAMETERS_5); 562 562 + reg_state->flip_parameters_6 = REG_READ(FLIP_PARAMETERS_6); 563 563 + reg_state->hubpreq_mem_pwr_ctrl = REG_READ(HUBPREQ_MEM_PWR_CTRL); 564 564 + reg_state->hubpreq_mem_pwr_status = REG_READ(HUBPREQ_MEM_PWR_STATUS); 565 565 + reg_state->nom_parameters_0 = REG_READ(NOM_PARAMETERS_0); 566 566 + reg_state->nom_parameters_1 = REG_READ(NOM_PARAMETERS_1); 567 567 + reg_state->nom_parameters_2 = REG_READ(NOM_PARAMETERS_2); 568 568 + reg_state->nom_parameters_3 = REG_READ(NOM_PARAMETERS_3); 569 569 + reg_state->nom_parameters_4 = REG_READ(NOM_PARAMETERS_4); 570 570 + reg_state->nom_parameters_5 = REG_READ(NOM_PARAMETERS_5); 571 571 + reg_state->nom_parameters_6 = REG_READ(NOM_PARAMETERS_6); 572 572 + reg_state->nom_parameters_7 = REG_READ(NOM_PARAMETERS_7); 573 573 + reg_state->per_line_delivery = REG_READ(PER_LINE_DELIVERY); 574 574 + reg_state->per_line_delivery_pre = REG_READ(PER_LINE_DELIVERY_PRE); 575 575 + reg_state->prefetch_settings = REG_READ(PREFETCH_SETTINGS); 576 576 + reg_state->prefetch_settings_c = REG_READ(PREFETCH_SETTINGS_C); 577 577 + reg_state->ref_freq_to_pix_freq = REG_READ(REF_FREQ_TO_PIX_FREQ); 578 578 + reg_state->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE); 579 579 + reg_state->vblank_parameters_0 = REG_READ(VBLANK_PARAMETERS_0); 580 580 + reg_state->vblank_parameters_1 = REG_READ(VBLANK_PARAMETERS_1); 581 581 + reg_state->vblank_parameters_2 = REG_READ(VBLANK_PARAMETERS_2); 582 582 + reg_state->vblank_parameters_3 = REG_READ(VBLANK_PARAMETERS_3); 583 583 + reg_state->vblank_parameters_4 = REG_READ(VBLANK_PARAMETERS_4); 584 584 + reg_state->vblank_parameters_5 = REG_READ(VBLANK_PARAMETERS_5); 585 585 + reg_state->vblank_parameters_6 = REG_READ(VBLANK_PARAMETERS_6); 586 586 + reg_state->vmid_settings_0 = REG_READ(VMID_SETTINGS_0); 587 587 + reg_state->hubpret_control = REG_READ(HUBPRET_CONTROL); 588 588 + reg_state->hubpret_interrupt = REG_READ(HUBPRET_INTERRUPT); 589 589 + reg_state->hubpret_mem_pwr_ctrl = REG_READ(HUBPRET_MEM_PWR_CTRL); 590 590 + reg_state->hubpret_mem_pwr_status = REG_READ(HUBPRET_MEM_PWR_STATUS); 591 591 + reg_state->hubpret_read_line_ctrl0 = REG_READ(HUBPRET_READ_LINE_CTRL0); 592 592 + reg_state->hubpret_read_line_ctrl1 = REG_READ(HUBPRET_READ_LINE_CTRL1); 593 593 + reg_state->hubpret_read_line_status = REG_READ(HUBPRET_READ_LINE_STATUS); 594 594 + reg_state->hubpret_read_line_value = REG_READ(HUBPRET_READ_LINE_VALUE); 595 595 + reg_state->hubpret_read_line0 = REG_READ(HUBPRET_READ_LINE0); 596 596 + reg_state->hubpret_read_line1 = REG_READ(HUBPRET_READ_LINE1); 597 597 + } 598 598 + 479 599 void hubp3_setup( 480 600 struct hubp *hubp, 481 601 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, ··· 623 503 REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0); 624 504 625 505 hubp_reset(hubp); 626 626 - } 627 627 - 628 628 - uint32_t hubp3_get_current_read_line(struct hubp *hubp) 629 629 - { 630 630 - uint32_t read_line = 0; 631 631 - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 632 632 - 633 633 - REG_GET(HUBPRET_READ_LINE_VALUE, 634 634 - PIPE_READ_LINE, 635 635 - &read_line); 636 636 - 637 637 - return read_line; 638 638 - } 639 639 - 640 640 - unsigned int hubp3_get_underflow_status(struct hubp *hubp) 641 641 - { 642 642 - uint32_t hubp_underflow = 0; 643 643 - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 644 644 - 645 645 - REG_GET(DCHUBP_CNTL, 646 646 - HUBP_UNDERFLOW_STATUS, 647 647 - &hubp_underflow); 648 648 - 649 649 - return hubp_underflow; 650 506 } 651 507 652 508 static struct hubp_funcs dcn30_hubp_funcs = { ··· 654 558 .hubp_soft_reset = hubp1_soft_reset, 655 559 .hubp_set_flip_int = hubp1_set_flip_int, 656 560 .hubp_clear_tiling = hubp3_clear_tiling, 657 657 - .hubp_get_underflow_status = hubp3_get_underflow_status, 658 658 - .hubp_get_current_read_line = hubp3_get_current_read_line, 561 561 + .hubp_read_reg_state = hubp3_read_reg_state 659 562 }; 660 563 661 564 bool hubp3_construct(

+2

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

reviewed

··· 296 296 297 297 void hubp3_read_state(struct hubp *hubp); 298 298 299 299 + void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state); 300 300 + 299 301 void hubp3_init(struct hubp *hubp); 300 302 301 303 void hubp3_clear_tiling(struct hubp *hubp);

+1 -3

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

reviewed

··· 110 110 .hubp_in_blank = hubp1_in_blank, 111 111 .program_extended_blank = hubp31_program_extended_blank, 112 112 .hubp_clear_tiling = hubp3_clear_tiling, 113 113 - .hubp_get_underflow_status = hubp3_get_underflow_status, 114 114 - .hubp_get_current_read_line = hubp3_get_current_read_line, 115 115 - .hubp_get_det_config_error = hubp31_get_det_config_error, 113 113 + .hubp_read_reg_state = hubp3_read_reg_state, 116 114 }; 117 115 118 116 bool hubp31_construct(

+1 -3

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

reviewed

··· 222 222 .hubp_update_mall_sel = hubp32_update_mall_sel, 223 223 .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, 224 224 .hubp_clear_tiling = hubp3_clear_tiling, 225 225 - .hubp_get_underflow_status = hubp3_get_underflow_status, 226 226 - .hubp_get_current_read_line = hubp3_get_current_read_line, 227 227 - .hubp_get_det_config_error = hubp31_get_det_config_error, 225 225 + .hubp_read_reg_state = hubp3_read_reg_state 228 226 }; 229 227 230 228 bool hubp32_construct(

+1 -3

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

reviewed

··· 209 209 .dmdata_load = hubp2_dmdata_load, 210 210 .dmdata_status_done = hubp2_dmdata_status_done, 211 211 .hubp_read_state = hubp3_read_state, 212 212 + .hubp_read_reg_state = hubp3_read_reg_state, 212 213 .hubp_clear_underflow = hubp2_clear_underflow, 213 214 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 214 215 .hubp_init = hubp35_init, ··· 219 218 .hubp_in_blank = hubp1_in_blank, 220 219 .program_extended_blank = hubp31_program_extended_blank_value, 221 220 .hubp_clear_tiling = hubp3_clear_tiling, 222 222 - .hubp_get_underflow_status = hubp3_get_underflow_status, 223 223 - .hubp_get_current_read_line = hubp3_get_current_read_line, 224 224 - .hubp_get_det_config_error = hubp31_get_det_config_error, 225 221 }; 226 222 227 223 bool hubp35_construct(

+14 -14

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

reviewed

··· 783 783 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 784 784 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 785 785 786 786 - REG_UPDATE(CURSOR_CONTROL, 787 787 - CURSOR_ENABLE, cur_en); 786 786 + if (!hubp->cursor_offload) 787 787 + REG_UPDATE(CURSOR_CONTROL, 788 788 + CURSOR_ENABLE, cur_en); 788 789 } 789 790 790 790 - REG_SET_2(CURSOR_POSITION, 0, 791 791 - CURSOR_X_POSITION, x_pos, 792 792 - CURSOR_Y_POSITION, y_pos); 791 791 + if (!hubp->cursor_offload) { 792 792 + REG_SET_2(CURSOR_POSITION, 0, 793 793 + CURSOR_X_POSITION, x_pos, 794 794 + CURSOR_Y_POSITION, y_pos); 793 795 794 794 - REG_SET_2(CURSOR_HOT_SPOT, 0, 795 795 - CURSOR_HOT_SPOT_X, pos->x_hotspot, 796 796 - CURSOR_HOT_SPOT_Y, pos->y_hotspot); 796 796 + REG_SET_2(CURSOR_HOT_SPOT, 0, 797 797 + CURSOR_HOT_SPOT_X, pos->x_hotspot, 798 798 + CURSOR_HOT_SPOT_Y, pos->y_hotspot); 797 799 798 798 - REG_SET(CURSOR_DST_OFFSET, 0, 799 799 - CURSOR_DST_X_OFFSET, dst_x_offset); 800 800 - 800 800 + REG_SET(CURSOR_DST_OFFSET, 0, 801 801 + CURSOR_DST_X_OFFSET, dst_x_offset); 802 802 + } 801 803 /* Cursor Position Register Config */ 802 804 hubp->pos.cur_ctl.bits.cur_enable = cur_en; 803 805 hubp->pos.position.bits.x_pos = pos->x; ··· 1073 1071 .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, 1074 1072 .hubp_clear_tiling = hubp401_clear_tiling, 1075 1073 .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, 1076 1076 - .hubp_get_underflow_status = hubp3_get_underflow_status, 1077 1077 - .hubp_get_current_read_line = hubp3_get_current_read_line, 1078 1078 - .hubp_get_det_config_error = hubp31_get_det_config_error, 1074 1074 + .hubp_read_reg_state = hubp3_read_reg_state 1079 1075 }; 1080 1076 1081 1077 bool hubp401_construct(

+1 -1

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

reviewed

··· 31 31 #include "dcn30/dcn30_hubp.h" 32 32 #include "dcn31/dcn31_hubp.h" 33 33 #include "dcn32/dcn32_hubp.h" 34 34 - #include "dml2/dml21/inc/dml_top_dchub_registers.h" 34 34 + #include "dml2_0/dml21/inc/dml_top_dchub_registers.h" 35 35 36 36 #define HUBP_3DLUT_FL_REG_LIST_DCN401(inst)\ 37 37 SRI_ARR_US(_3DLUT_FL_CONFIG, HUBP, inst),\

+73 -2

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

reviewed

··· 659 659 } 660 660 } 661 661 662 662 + static void 663 663 + dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) 664 664 + { 665 665 + struct dc_link *link = pipe_ctx->stream->link; 666 666 + struct dc_bios *bios = link->ctx->dc_bios; 667 667 + struct bp_encoder_control encoder_control = {0}; 668 668 + 669 669 + encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE; 670 670 + encoder_control.engine_id = link->link_enc->analog_engine; 671 671 + encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10; 672 672 + 673 673 + bios->funcs->encoder_control(bios, &encoder_control); 674 674 + } 675 675 + 662 676 void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 663 677 { 664 678 enum dc_lane_count lane_count = ··· 703 689 early_control = lane_count; 704 690 705 691 tg->funcs->set_early_control(tg, early_control); 692 692 + 693 693 + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) 694 694 + dce110_dac_encoder_control(pipe_ctx, true); 706 695 } 707 696 708 697 static enum bp_result link_transmitter_control( ··· 1193 1176 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 1194 1177 pipe_ctx->stream_res.stream_enc); 1195 1178 1196 1196 - dc->hwss.disable_audio_stream(pipe_ctx); 1179 1179 + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) 1180 1180 + dc->hwss.disable_audio_stream(pipe_ctx); 1197 1181 1198 1182 link_hwss->reset_stream_encoder(pipe_ctx); 1199 1183 ··· 1214 1196 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, 1215 1197 link_enc->transmitter - TRANSMITTER_UNIPHY_A); 1216 1198 } 1199 1199 + 1200 1200 + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) 1201 1201 + dce110_dac_encoder_control(pipe_ctx, false); 1217 1202 } 1218 1203 1219 1204 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, ··· 1602 1581 return DC_OK; 1603 1582 } 1604 1583 1584 1584 + static void 1585 1585 + dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) 1586 1586 + { 1587 1587 + struct dc_link *link = pipe_ctx->stream->link; 1588 1588 + struct dc_bios *bios = link->ctx->dc_bios; 1589 1589 + struct bp_crtc_source_select crtc_source_select = {0}; 1590 1590 + enum engine_id engine_id = link->link_enc->preferred_engine; 1591 1591 + uint8_t bit_depth; 1592 1592 + 1593 1593 + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) 1594 1594 + engine_id = link->link_enc->analog_engine; 1595 1595 + 1596 1596 + switch (pipe_ctx->stream->timing.display_color_depth) { 1597 1597 + case COLOR_DEPTH_UNDEFINED: 1598 1598 + bit_depth = 0; 1599 1599 + break; 1600 1600 + case COLOR_DEPTH_666: 1601 1601 + bit_depth = 6; 1602 1602 + break; 1603 1603 + default: 1604 1604 + case COLOR_DEPTH_888: 1605 1605 + bit_depth = 8; 1606 1606 + break; 1607 1607 + case COLOR_DEPTH_101010: 1608 1608 + bit_depth = 10; 1609 1609 + break; 1610 1610 + case COLOR_DEPTH_121212: 1611 1611 + bit_depth = 12; 1612 1612 + break; 1613 1613 + case COLOR_DEPTH_141414: 1614 1614 + bit_depth = 14; 1615 1615 + break; 1616 1616 + case COLOR_DEPTH_161616: 1617 1617 + bit_depth = 16; 1618 1618 + break; 1619 1619 + } 1620 1620 + 1621 1621 + crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; 1622 1622 + crtc_source_select.bit_depth = bit_depth; 1623 1623 + crtc_source_select.engine_id = engine_id; 1624 1624 + crtc_source_select.sink_signal = pipe_ctx->stream->signal; 1625 1625 + 1626 1626 + bios->funcs->select_crtc_source(bios, &crtc_source_select); 1627 1627 + } 1628 1628 + 1605 1629 enum dc_status dce110_apply_single_controller_ctx_to_hw( 1606 1630 struct pipe_ctx *pipe_ctx, 1607 1631 struct dc_state *context, ··· 1664 1598 1665 1599 if (hws->funcs.disable_stream_gating) { 1666 1600 hws->funcs.disable_stream_gating(dc, pipe_ctx); 1601 1601 + } 1602 1602 + 1603 1603 + if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) { 1604 1604 + dce110_select_crtc_source(pipe_ctx); 1667 1605 } 1668 1606 1669 1607 if (pipe_ctx->stream_res.audio != NULL) { ··· 1749 1679 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1750 1680 pipe_ctx->stream_res.tg, event_triggers, 2); 1751 1681 1752 1752 - if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1682 1682 + if (!dc_is_virtual_signal(pipe_ctx->stream->signal) && 1683 1683 + !dc_is_rgb_signal(pipe_ctx->stream->signal)) 1753 1684 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1754 1685 pipe_ctx->stream_res.stream_enc, 1755 1686 pipe_ctx->stream_res.tg->inst);

+36 -32

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

reviewed

··· 53 53 #include "link_service.h" 54 54 #include "dc_state_priv.h" 55 55 56 56 - 56 56 + #define TO_DCN_DCCG(dccg)\ 57 57 + container_of(dccg, struct dcn_dccg, base) 57 58 58 59 #define DC_LOGGER_INIT(logger) 59 60 ··· 1236 1235 { 1237 1236 struct hubbub *hubbub = dc->res_pool->hubbub; 1238 1237 1239 1239 - if (tg) { 1240 1240 - uint32_t v_blank_start = 0, v_blank_end = 0; 1241 1241 - 1242 1242 - out_data->otg_inst = tg->inst; 1243 1243 - 1244 1244 - tg->funcs->get_scanoutpos(tg, 1245 1245 - &v_blank_start, 1246 1246 - &v_blank_end, 1247 1247 - &out_data->h_position, 1248 1248 - &out_data->v_position); 1249 1249 - 1250 1250 - out_data->otg_frame_count = tg->funcs->get_frame_count(tg); 1251 1251 - 1252 1252 - out_data->otg_underflow = tg->funcs->is_optc_underflow_occurred(tg); 1238 1238 + if (hubbub) { 1239 1239 + if (hubbub->funcs->hubbub_read_reg_state) { 1240 1240 + hubbub->funcs->hubbub_read_reg_state(hubbub, out_data->hubbub_reg_state); 1241 1241 + } 1253 1242 } 1254 1243 1255 1244 for (int i = 0; i < MAX_PIPES; i++) { 1256 1245 struct hubp *hubp = dc->res_pool->hubps[i]; 1246 1246 + struct dpp *dpp = dc->res_pool->dpps[i]; 1247 1247 + struct output_pixel_processor *opp = dc->res_pool->opps[i]; 1248 1248 + struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1249 1249 + struct mpc *mpc = dc->res_pool->mpc; 1250 1250 + struct timing_generator *optc = dc->res_pool->timing_generators[i]; 1251 1251 + struct dccg *dccg = dc->res_pool->dccg; 1257 1252 1258 1258 - if (hubp) { 1259 1259 - if (hubp->funcs->hubp_get_underflow_status) 1260 1260 - out_data->hubps[i].hubp_underflow = hubp->funcs->hubp_get_underflow_status(hubp); 1253 1253 + if (hubp) 1254 1254 + if (hubp->funcs->hubp_read_reg_state) 1255 1255 + hubp->funcs->hubp_read_reg_state(hubp, out_data->hubp_reg_state[i]); 1261 1256 1262 1262 - if (hubp->funcs->hubp_in_blank) 1263 1263 - out_data->hubps[i].hubp_in_blank = hubp->funcs->hubp_in_blank(hubp); 1257 1257 + if (dpp) 1258 1258 + if (dpp->funcs->dpp_read_reg_state) 1259 1259 + dpp->funcs->dpp_read_reg_state(dpp, out_data->dpp_reg_state[i]); 1264 1260 1265 1265 - if (hubp->funcs->hubp_get_current_read_line) 1266 1266 - out_data->hubps[i].hubp_readline = hubp->funcs->hubp_get_current_read_line(hubp); 1261 1261 + if (opp) 1262 1262 + if (opp->funcs->opp_read_reg_state) 1263 1263 + opp->funcs->opp_read_reg_state(opp, out_data->opp_reg_state[i]); 1267 1264 1268 1268 - if (hubp->funcs->hubp_get_det_config_error) 1269 1269 - out_data->hubps[i].det_config_error = hubp->funcs->hubp_get_det_config_error(hubp); 1270 1270 - } 1265 1265 + if (dsc) 1266 1266 + if (dsc->funcs->dsc_read_reg_state) 1267 1267 + dsc->funcs->dsc_read_reg_state(dsc, out_data->dsc_reg_state[i]); 1268 1268 + 1269 1269 + if (mpc) 1270 1270 + if (mpc->funcs->mpc_read_reg_state) 1271 1271 + mpc->funcs->mpc_read_reg_state(mpc, i, out_data->mpc_reg_state[i]); 1272 1272 + 1273 1273 + if (optc) 1274 1274 + if (optc->funcs->optc_read_reg_state) 1275 1275 + optc->funcs->optc_read_reg_state(optc, out_data->optc_reg_state[i]); 1276 1276 + 1277 1277 + if (dccg) 1278 1278 + if (dccg->funcs->dccg_read_reg_state) 1279 1279 + dccg->funcs->dccg_read_reg_state(dccg, out_data->dccg_reg_state[i]); 1271 1280 } 1272 1272 - 1273 1273 - if (hubbub->funcs->get_det_sizes) 1274 1274 - hubbub->funcs->get_det_sizes(hubbub, out_data->curr_det_sizes, out_data->target_det_sizes); 1275 1275 - 1276 1276 - if (hubbub->funcs->compbuf_config_error) 1277 1277 - out_data->compbuf_config_error = hubbub->funcs->compbuf_config_error(hubbub); 1278 1278 - 1279 1281 }

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

reviewed

··· 1699 1699 p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode; 1700 1700 p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify; 1701 1701 p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch; 1702 1702 - p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->pos.cur_ctl.bits.line_per_chunk; 1702 1702 + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk; 1703 1703 1704 1704 p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; 1705 1705 p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode;

+2 -2

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

reviewed

··· 2978 2978 return; 2979 2979 2980 2980 stream_idx = top_pipe->pipe_idx; 2981 2981 - write_idx = cs->offload_streams[stream_idx].write_idx; 2981 2981 + write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */ 2982 2982 payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads); 2983 2983 2984 2984 p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn401; ··· 2996 2996 p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode; 2997 2997 p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify; 2998 2998 p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch; 2999 2999 - p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->pos.cur_ctl.bits.line_per_chunk; 2999 2999 + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk; 3000 3000 3001 3001 p->CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; 3002 3002 p->CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode;

+6 -6

drivers/gpu/drm/amd/display/dc/inc/core_types.h

reviewed

··· 58 58 #include "transform.h" 59 59 #include "dpp.h" 60 60 61 61 - #include "dml2/dml21/inc/dml_top_dchub_registers.h" 62 62 - #include "dml2/dml21/inc/dml_top_types.h" 61 61 + #include "dml2_0/dml21/inc/dml_top_dchub_registers.h" 62 62 + #include "dml2_0/dml21/inc/dml_top_types.h" 63 63 64 64 struct resource_pool; 65 65 struct dc_state; ··· 274 274 /* An array for accessing the link encoder objects that have been created. 275 275 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 276 276 */ 277 277 - struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 277 277 + struct link_encoder *link_encoders[MAX_LINK_ENCODERS]; 278 278 /* Number of DIG link encoder objects created - i.e. number of valid 279 279 * entries in link_encoders array. 280 280 */ ··· 514 514 struct link_enc_cfg_context { 515 515 enum link_enc_cfg_mode mode; 516 516 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 517 517 - enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 517 517 + enum engine_id link_enc_avail[MAX_LINK_ENCODERS]; 518 518 struct link_enc_assignment transient_assignments[MAX_PIPES]; 519 519 }; 520 520 ··· 526 526 uint8_t dp_clock_source_ref_count; 527 527 bool is_dsc_acquired[MAX_PIPES]; 528 528 struct link_enc_cfg_context link_enc_cfg_ctx; 529 529 - unsigned int dio_link_enc_to_link_idx[MAX_DIG_LINK_ENCODERS]; 530 530 - int dio_link_enc_ref_cnts[MAX_DIG_LINK_ENCODERS]; 529 529 + unsigned int dio_link_enc_to_link_idx[MAX_LINK_ENCODERS]; 530 530 + int dio_link_enc_ref_cnts[MAX_LINK_ENCODERS]; 531 531 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 532 532 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 533 533 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];

+120 -1

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

reviewed

··· 71 71 PIXEL_RATE_DIV_NA = 0xF 72 72 }; 73 73 74 74 + struct dcn_dccg_reg_state { 75 75 + uint32_t dc_mem_global_pwr_req_cntl; 76 76 + uint32_t dccg_audio_dtbclk_dto_modulo; 77 77 + uint32_t dccg_audio_dtbclk_dto_phase; 78 78 + uint32_t dccg_audio_dto_source; 79 79 + uint32_t dccg_audio_dto0_module; 80 80 + uint32_t dccg_audio_dto0_phase; 81 81 + uint32_t dccg_audio_dto1_module; 82 82 + uint32_t dccg_audio_dto1_phase; 83 83 + uint32_t dccg_cac_status; 84 84 + uint32_t dccg_cac_status2; 85 85 + uint32_t dccg_disp_cntl_reg; 86 86 + uint32_t dccg_ds_cntl; 87 87 + uint32_t dccg_ds_dto_incr; 88 88 + uint32_t dccg_ds_dto_modulo; 89 89 + uint32_t dccg_ds_hw_cal_interval; 90 90 + uint32_t dccg_gate_disable_cntl; 91 91 + uint32_t dccg_gate_disable_cntl2; 92 92 + uint32_t dccg_gate_disable_cntl3; 93 93 + uint32_t dccg_gate_disable_cntl4; 94 94 + uint32_t dccg_gate_disable_cntl5; 95 95 + uint32_t dccg_gate_disable_cntl6; 96 96 + uint32_t dccg_global_fgcg_rep_cntl; 97 97 + uint32_t dccg_gtc_cntl; 98 98 + uint32_t dccg_gtc_current; 99 99 + uint32_t dccg_gtc_dto_incr; 100 100 + uint32_t dccg_gtc_dto_modulo; 101 101 + uint32_t dccg_perfmon_cntl; 102 102 + uint32_t dccg_perfmon_cntl2; 103 103 + uint32_t dccg_soft_reset; 104 104 + uint32_t dccg_test_clk_sel; 105 105 + uint32_t dccg_vsync_cnt_ctrl; 106 106 + uint32_t dccg_vsync_cnt_int_ctrl; 107 107 + uint32_t dccg_vsync_otg0_latch_value; 108 108 + uint32_t dccg_vsync_otg1_latch_value; 109 109 + uint32_t dccg_vsync_otg2_latch_value; 110 110 + uint32_t dccg_vsync_otg3_latch_value; 111 111 + uint32_t dccg_vsync_otg4_latch_value; 112 112 + uint32_t dccg_vsync_otg5_latch_value; 113 113 + uint32_t dispclk_cgtt_blk_ctrl_reg; 114 114 + uint32_t dispclk_freq_change_cntl; 115 115 + uint32_t dp_dto_dbuf_en; 116 116 + uint32_t dp_dto0_modulo; 117 117 + uint32_t dp_dto0_phase; 118 118 + uint32_t dp_dto1_modulo; 119 119 + uint32_t dp_dto1_phase; 120 120 + uint32_t dp_dto2_modulo; 121 121 + uint32_t dp_dto2_phase; 122 122 + uint32_t dp_dto3_modulo; 123 123 + uint32_t dp_dto3_phase; 124 124 + uint32_t dpiaclk_540m_dto_modulo; 125 125 + uint32_t dpiaclk_540m_dto_phase; 126 126 + uint32_t dpiaclk_810m_dto_modulo; 127 127 + uint32_t dpiaclk_810m_dto_phase; 128 128 + uint32_t dpiaclk_dto_cntl; 129 129 + uint32_t dpiasymclk_cntl; 130 130 + uint32_t dppclk_cgtt_blk_ctrl_reg; 131 131 + uint32_t dppclk_ctrl; 132 132 + uint32_t dppclk_dto_ctrl; 133 133 + uint32_t dppclk0_dto_param; 134 134 + uint32_t dppclk1_dto_param; 135 135 + uint32_t dppclk2_dto_param; 136 136 + uint32_t dppclk3_dto_param; 137 137 + uint32_t dprefclk_cgtt_blk_ctrl_reg; 138 138 + uint32_t dprefclk_cntl; 139 139 + uint32_t dpstreamclk_cntl; 140 140 + uint32_t dscclk_dto_ctrl; 141 141 + uint32_t dscclk0_dto_param; 142 142 + uint32_t dscclk1_dto_param; 143 143 + uint32_t dscclk2_dto_param; 144 144 + uint32_t dscclk3_dto_param; 145 145 + uint32_t dtbclk_dto_dbuf_en; 146 146 + uint32_t dtbclk_dto0_modulo; 147 147 + uint32_t dtbclk_dto0_phase; 148 148 + uint32_t dtbclk_dto1_modulo; 149 149 + uint32_t dtbclk_dto1_phase; 150 150 + uint32_t dtbclk_dto2_modulo; 151 151 + uint32_t dtbclk_dto2_phase; 152 152 + uint32_t dtbclk_dto3_modulo; 153 153 + uint32_t dtbclk_dto3_phase; 154 154 + uint32_t dtbclk_p_cntl; 155 155 + uint32_t force_symclk_disable; 156 156 + uint32_t hdmicharclk0_clock_cntl; 157 157 + uint32_t hdmistreamclk_cntl; 158 158 + uint32_t hdmistreamclk0_dto_param; 159 159 + uint32_t microsecond_time_base_div; 160 160 + uint32_t millisecond_time_base_div; 161 161 + uint32_t otg_pixel_rate_div; 162 162 + uint32_t otg0_phypll_pixel_rate_cntl; 163 163 + uint32_t otg0_pixel_rate_cntl; 164 164 + uint32_t otg1_phypll_pixel_rate_cntl; 165 165 + uint32_t otg1_pixel_rate_cntl; 166 166 + uint32_t otg2_phypll_pixel_rate_cntl; 167 167 + uint32_t otg2_pixel_rate_cntl; 168 168 + uint32_t otg3_phypll_pixel_rate_cntl; 169 169 + uint32_t otg3_pixel_rate_cntl; 170 170 + uint32_t phyasymclk_clock_cntl; 171 171 + uint32_t phybsymclk_clock_cntl; 172 172 + uint32_t phycsymclk_clock_cntl; 173 173 + uint32_t phydsymclk_clock_cntl; 174 174 + uint32_t phyesymclk_clock_cntl; 175 175 + uint32_t phyplla_pixclk_resync_cntl; 176 176 + uint32_t phypllb_pixclk_resync_cntl; 177 177 + uint32_t phypllc_pixclk_resync_cntl; 178 178 + uint32_t phyplld_pixclk_resync_cntl; 179 179 + uint32_t phyplle_pixclk_resync_cntl; 180 180 + uint32_t refclk_cgtt_blk_ctrl_reg; 181 181 + uint32_t socclk_cgtt_blk_ctrl_reg; 182 182 + uint32_t symclk_cgtt_blk_ctrl_reg; 183 183 + uint32_t symclk_psp_cntl; 184 184 + uint32_t symclk32_le_cntl; 185 185 + uint32_t symclk32_se_cntl; 186 186 + uint32_t symclka_clock_enable; 187 187 + uint32_t symclkb_clock_enable; 188 188 + uint32_t symclkc_clock_enable; 189 189 + uint32_t symclkd_clock_enable; 190 190 + uint32_t symclke_clock_enable; 191 191 + }; 192 192 + 74 193 struct dccg { 75 194 struct dc_context *ctx; 76 195 const struct dccg_funcs *funcs; ··· 200 81 //int audio_dtbclk_khz;/* TODO needs to be removed */ 201 82 //int ref_dtbclk_khz;/* TODO needs to be removed */ 202 83 }; 203 203 - 204 84 struct dtbclk_dto_params { 205 85 const struct dc_crtc_timing *timing; 206 86 int otg_inst; ··· 332 214 void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h); 333 215 void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); 334 216 void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); 217 217 + void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); 335 218 }; 336 219 337 220 #endif //__DAL_DCCG_H__

+10 -2

drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h

reviewed

··· 137 137 uint32_t dram_state_cntl; 138 138 }; 139 139 140 140 + struct dcn_hubbub_reg_state { 141 141 + uint32_t det0_ctrl; 142 142 + uint32_t det1_ctrl; 143 143 + uint32_t det2_ctrl; 144 144 + uint32_t det3_ctrl; 145 145 + uint32_t compbuf_ctrl; 146 146 + }; 147 147 + 140 148 struct hubbub_system_latencies { 141 149 uint32_t max_latency_ns; 142 150 uint32_t avg_latency_ns; ··· 224 216 225 217 void (*init_watermarks)(struct hubbub *hubbub); 226 218 219 219 + void (*hubbub_read_reg_state)(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state); 220 220 + 227 221 /** 228 222 * @program_det_size: 229 223 * ··· 252 242 void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); 253 243 void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); 254 244 bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); 255 255 - void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes); 256 256 - uint32_t (*compbuf_config_error)(struct hubbub *hubbub); 257 245 struct hubbub_perfmon_funcs { 258 246 void (*reset)(struct hubbub *hubbub); 259 247 void (*start_measuring_max_memory_latency_ns)(

+15 -1

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

reviewed

··· 65 65 } bits; 66 66 uint32_t raw; 67 67 }; 68 68 - 69 68 struct dpp { 70 69 const struct dpp_funcs *funcs; 71 70 struct dc_context *ctx; ··· 202 203 uint32_t gamcor_mode; 203 204 }; 204 205 206 206 + struct dcn_dpp_reg_state { 207 207 + uint32_t recout_start; 208 208 + uint32_t recout_size; 209 209 + uint32_t scl_horz_filter_scale_ratio; 210 210 + uint32_t scl_vert_filter_scale_ratio; 211 211 + uint32_t scl_mode; 212 212 + uint32_t cm_control; 213 213 + uint32_t dpp_control; 214 214 + uint32_t dscl_control; 215 215 + uint32_t obuf_control; 216 216 + uint32_t mpc_size; 217 217 + }; 218 218 + 205 219 struct CM_bias_params { 206 220 uint32_t cm_bias_cr_r; 207 221 uint32_t cm_bias_y_g; ··· 237 225 struct CM_bias_params *bias_params); 238 226 239 227 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s); 228 228 + 229 229 + void (*dpp_read_reg_state)(struct dpp *dpp, struct dcn_dpp_reg_state *dpp_reg_state); 240 230 241 231 void (*dpp_reset)(struct dpp *dpp); 242 232

+3 -2

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

reviewed

··· 41 41 #include "mem_input.h" 42 42 #include "cursor_reg_cache.h" 43 43 44 44 - #include "dml2/dml21/inc/dml_top_dchub_registers.h" 45 45 - #include "dml2/dml21/inc/dml_top_types.h" 44 44 + #include "dml2_0/dml21/inc/dml_top_dchub_registers.h" 45 45 + #include "dml2_0/dml21/inc/dml_top_types.h" 46 46 47 47 #define OPP_ID_INVALID 0xf 48 48 #define MAX_TTU 0xffffff ··· 238 238 void (*hubp_clk_cntl)(struct hubp *hubp, bool enable); 239 239 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); 240 240 void (*hubp_read_state)(struct hubp *hubp); 241 241 + void (*hubp_read_reg_state)(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state); 241 242 void (*hubp_clear_underflow)(struct hubp *hubp); 242 243 void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp); 243 244 unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);

+24

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

reviewed

··· 51 51 52 52 #define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS) 53 53 54 54 + /** 55 55 + * define MAX_DIG_LINK_ENCODERS - maximum number of digital encoders 56 56 + * 57 57 + * Digital encoders are ENGINE_ID_DIGA...G, there are at most 7, 58 58 + * although not every GPU may have that many. 59 59 + */ 60 60 + #define MAX_DIG_LINK_ENCODERS 7 61 61 + 62 62 + /** 63 63 + * define MAX_DAC_LINK_ENCODERS - maximum number of analog link encoders 64 64 + * 65 65 + * Analog encoders are ENGINE_ID_DACA/B, there are at most 2, 66 66 + * although not every GPU may have that many. Modern GPUs typically 67 67 + * don't have analog encoders. 68 68 + */ 69 69 + #define MAX_DAC_LINK_ENCODERS 2 70 70 + 71 71 + /** 72 72 + * define MAX_LINK_ENCODERS - maximum number link encoders in total 73 73 + * 74 74 + * This includes both analog and digital encoders. 75 75 + */ 76 76 + #define MAX_LINK_ENCODERS (MAX_DIG_LINK_ENCODERS + MAX_DAC_LINK_ENCODERS) 77 77 + 54 78 #define MAX_DIG_LINK_ENCODERS 7 55 79 #define MAX_DWB_PIPES 1 56 80 #define MAX_HPO_DP2_ENCODERS 4

+2

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

reviewed

··· 47 47 enum hpd_source_id hpd_source; 48 48 /* TODO: in DAL2, here was pointer to EventManagerInterface */ 49 49 struct graphics_object_id encoder; 50 50 + enum engine_id analog_engine; 50 51 struct dc_context *ctx; 51 52 enum transmitter transmitter; 52 53 }; ··· 84 83 struct graphics_object_id connector; 85 84 uint32_t output_signals; 86 85 enum engine_id preferred_engine; 86 86 + enum engine_id analog_engine; 87 87 struct encoder_feature_support features; 88 88 enum transmitter transmitter; 89 89 enum hpd_source_id hpd_source;

+1 -1

drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h

reviewed

··· 29 29 #include "include/grph_object_id.h" 30 30 31 31 #include "dml/display_mode_structs.h" 32 32 - #include "dml2/dml21/inc/dml_top_dchub_registers.h" 32 32 + #include "dml2_0/dml21/inc/dml_top_dchub_registers.h" 33 33 34 34 struct dchub_init_data; 35 35 struct cstate_pstate_watermarks_st {

+27

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

reviewed

··· 350 350 struct mpc_rmcm_regs rmcm_regs; 351 351 }; 352 352 353 353 + struct dcn_mpc_reg_state { 354 354 + uint32_t mpcc_bot_sel; 355 355 + uint32_t mpcc_control; 356 356 + uint32_t mpcc_status; 357 357 + uint32_t mpcc_top_sel; 358 358 + uint32_t mpcc_opp_id; 359 359 + uint32_t mpcc_ogam_control; 360 360 + }; 361 361 + 353 362 /** 354 363 * struct mpc_funcs - funcs 355 364 */ ··· 382 373 struct mpc *mpc, 383 374 int mpcc_inst, 384 375 struct mpcc_state *s); 376 376 + /** 377 377 + * @mpc_read_reg_state: 378 378 + * 379 379 + * Read MPC register state for debugging underflow purposes. 380 380 + * 381 381 + * Parameters: 382 382 + * 383 383 + * - [in] mpc - MPC context 384 384 + * - [out] reg_state - MPC register state structure 385 385 + * 386 386 + * Return: 387 387 + * 388 388 + * void 389 389 + */ 390 390 + void (*mpc_read_reg_state)( 391 391 + struct mpc *mpc, 392 392 + int mpcc_inst, 393 393 + struct dcn_mpc_reg_state *mpc_reg_state); 385 394 386 395 /** 387 396 * @insert_plane:

+13

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

reviewed

··· 297 297 uint32_t num_segment_padded_pixels; 298 298 }; 299 299 300 300 + struct dcn_opp_reg_state { 301 301 + uint32_t dpg_control; 302 302 + uint32_t fmt_control; 303 303 + uint32_t oppbuf_control; 304 304 + uint32_t opp_pipe_control; 305 305 + uint32_t opp_pipe_crc_control; 306 306 + uint32_t opp_abm_control; 307 307 + uint32_t dscrm_dsc_forward_config; 308 308 + }; 309 309 + 300 310 struct opp_funcs { 301 311 302 312 ··· 378 368 struct output_pixel_processor *opp, 379 369 enum dc_pixel_encoding pixel_encoding, 380 370 bool is_primary); 371 371 + 372 372 + void (*opp_read_reg_state)( 373 373 + struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); 381 374 }; 382 375 383 376 #endif

+130

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

reviewed

··· 175 175 uint32_t otg_double_buffer_control; 176 176 }; 177 177 178 178 + struct dcn_optc_reg_state { 179 179 + uint32_t optc_bytes_per_pixel; 180 180 + uint32_t optc_data_format_control; 181 181 + uint32_t optc_data_source_select; 182 182 + uint32_t optc_input_clock_control; 183 183 + uint32_t optc_input_global_control; 184 184 + uint32_t optc_input_spare_register; 185 185 + uint32_t optc_memory_config; 186 186 + uint32_t optc_rsmu_underflow; 187 187 + uint32_t optc_underflow_threshold; 188 188 + uint32_t optc_width_control; 189 189 + 190 190 + uint32_t otg_3d_structure_control; 191 191 + uint32_t otg_clock_control; 192 192 + uint32_t otg_control; 193 193 + uint32_t otg_count_control; 194 194 + uint32_t otg_count_reset; 195 195 + uint32_t otg_crc_cntl; 196 196 + uint32_t otg_crc_sig_blue_control_mask; 197 197 + uint32_t otg_crc_sig_red_green_mask; 198 198 + uint32_t otg_crc0_data_b; 199 199 + uint32_t otg_crc0_data_rg; 200 200 + uint32_t otg_crc0_windowa_x_control; 201 201 + uint32_t otg_crc0_windowa_x_control_readback; 202 202 + uint32_t otg_crc0_windowa_y_control; 203 203 + uint32_t otg_crc0_windowa_y_control_readback; 204 204 + uint32_t otg_crc0_windowb_x_control; 205 205 + uint32_t otg_crc0_windowb_x_control_readback; 206 206 + uint32_t otg_crc0_windowb_y_control; 207 207 + uint32_t otg_crc0_windowb_y_control_readback; 208 208 + uint32_t otg_crc1_data_b; 209 209 + uint32_t otg_crc1_data_rg; 210 210 + uint32_t otg_crc1_windowa_x_control; 211 211 + uint32_t otg_crc1_windowa_x_control_readback; 212 212 + uint32_t otg_crc1_windowa_y_control; 213 213 + uint32_t otg_crc1_windowa_y_control_readback; 214 214 + uint32_t otg_crc1_windowb_x_control; 215 215 + uint32_t otg_crc1_windowb_x_control_readback; 216 216 + uint32_t otg_crc1_windowb_y_control; 217 217 + uint32_t otg_crc1_windowb_y_control_readback; 218 218 + uint32_t otg_crc2_data_b; 219 219 + uint32_t otg_crc2_data_rg; 220 220 + uint32_t otg_crc3_data_b; 221 221 + uint32_t otg_crc3_data_rg; 222 222 + uint32_t otg_dlpc_control; 223 223 + uint32_t otg_double_buffer_control; 224 224 + uint32_t otg_drr_control2; 225 225 + uint32_t otg_drr_control; 226 226 + uint32_t otg_drr_timing_int_status; 227 227 + uint32_t otg_drr_trigger_window; 228 228 + uint32_t otg_drr_v_total_change; 229 229 + uint32_t otg_drr_v_total_reach_range; 230 230 + uint32_t otg_dsc_start_position; 231 231 + uint32_t otg_force_count_now_cntl; 232 232 + uint32_t otg_global_control0; 233 233 + uint32_t otg_global_control1; 234 234 + uint32_t otg_global_control2; 235 235 + uint32_t otg_global_control3; 236 236 + uint32_t otg_global_control4; 237 237 + uint32_t otg_global_sync_status; 238 238 + uint32_t otg_gsl_control; 239 239 + uint32_t otg_gsl_vsync_gap; 240 240 + uint32_t otg_gsl_window_x; 241 241 + uint32_t otg_gsl_window_y; 242 242 + uint32_t otg_h_blank_start_end; 243 243 + uint32_t otg_h_sync_a; 244 244 + uint32_t otg_h_sync_a_cntl; 245 245 + uint32_t otg_h_timing_cntl; 246 246 + uint32_t otg_h_total; 247 247 + uint32_t otg_interlace_control; 248 248 + uint32_t otg_interlace_status; 249 249 + uint32_t otg_interrupt_control; 250 250 + uint32_t otg_long_vblank_status; 251 251 + uint32_t otg_m_const_dto0; 252 252 + uint32_t otg_m_const_dto1; 253 253 + uint32_t otg_manual_force_vsync_next_line; 254 254 + uint32_t otg_master_en; 255 255 + uint32_t otg_master_update_lock; 256 256 + uint32_t otg_master_update_mode; 257 257 + uint32_t otg_nom_vert_position; 258 258 + uint32_t otg_pipe_update_status; 259 259 + uint32_t otg_pixel_data_readback0; 260 260 + uint32_t otg_pixel_data_readback1; 261 261 + uint32_t otg_request_control; 262 262 + uint32_t otg_snapshot_control; 263 263 + uint32_t otg_snapshot_frame; 264 264 + uint32_t otg_snapshot_position; 265 265 + uint32_t otg_snapshot_status; 266 266 + uint32_t otg_spare_register; 267 267 + uint32_t otg_static_screen_control; 268 268 + uint32_t otg_status; 269 269 + uint32_t otg_status_frame_count; 270 270 + uint32_t otg_status_hv_count; 271 271 + uint32_t otg_status_position; 272 272 + uint32_t otg_status_vf_count; 273 273 + uint32_t otg_stereo_control; 274 274 + uint32_t otg_stereo_force_next_eye; 275 275 + uint32_t otg_stereo_status; 276 276 + uint32_t otg_trig_manual_control; 277 277 + uint32_t otg_triga_cntl; 278 278 + uint32_t otg_triga_manual_trig; 279 279 + uint32_t otg_trigb_cntl; 280 280 + uint32_t otg_trigb_manual_trig; 281 281 + uint32_t otg_update_lock; 282 282 + uint32_t otg_v_blank_start_end; 283 283 + uint32_t otg_v_count_stop_control; 284 284 + uint32_t otg_v_count_stop_control2; 285 285 + uint32_t otg_v_sync_a; 286 286 + uint32_t otg_v_sync_a_cntl; 287 287 + uint32_t otg_v_total; 288 288 + uint32_t otg_v_total_control; 289 289 + uint32_t otg_v_total_int_status; 290 290 + uint32_t otg_v_total_max; 291 291 + uint32_t otg_v_total_mid; 292 292 + uint32_t otg_v_total_min; 293 293 + uint32_t otg_vert_sync_control; 294 294 + uint32_t otg_vertical_interrupt0_control; 295 295 + uint32_t otg_vertical_interrupt0_position; 296 296 + uint32_t otg_vertical_interrupt1_control; 297 297 + uint32_t otg_vertical_interrupt1_position; 298 298 + uint32_t otg_vertical_interrupt2_control; 299 299 + uint32_t otg_vertical_interrupt2_position; 300 300 + uint32_t otg_vready_param; 301 301 + uint32_t otg_vstartup_param; 302 302 + uint32_t otg_vsync_nom_int_status; 303 303 + uint32_t otg_vupdate_keepout; 304 304 + uint32_t otg_vupdate_param; 305 305 + }; 306 306 + 178 307 /** 179 308 * struct timing_generator - Entry point to Output Timing Generator feature. 180 309 */ ··· 510 381 void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable); 511 382 bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked); 512 383 void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s); 384 384 + void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state); 513 385 }; 514 386 515 387 #endif

+1

drivers/gpu/drm/amd/display/dc/inc/resource.h

reviewed

··· 49 49 int num_video_plane; 50 50 int num_audio; 51 51 int num_stream_encoder; 52 52 + int num_analog_stream_encoder; 52 53 int num_pll; 53 54 int num_dwb; 54 55 int num_ddc;

+12 -7

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

reviewed

··· 58 58 return; 59 59 } 60 60 61 61 - link_enc->funcs->connect_dig_be_to_fe(link_enc, 62 62 - pipe_ctx->stream_res.stream_enc->id, true); 61 61 + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) 62 62 + link_enc->funcs->connect_dig_be_to_fe(link_enc, 63 63 + pipe_ctx->stream_res.stream_enc->id, true); 63 64 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 64 65 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link, 65 66 DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE); ··· 99 98 if (stream_enc->funcs->enable_stream) 100 99 stream_enc->funcs->enable_stream(stream_enc, 101 100 pipe_ctx->stream->signal, false); 102 102 - link_enc->funcs->connect_dig_be_to_fe( 103 103 - link_enc, 104 104 - pipe_ctx->stream_res.stream_enc->id, 105 105 - false); 101 101 + 102 102 + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) 103 103 + link_enc->funcs->connect_dig_be_to_fe( 104 104 + link_enc, 105 105 + pipe_ctx->stream_res.stream_enc->id, 106 106 + false); 107 107 + 106 108 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 107 109 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence( 108 110 pipe_ctx->stream->link, ··· 119 115 struct dc_stream_state *stream = pipe_ctx->stream; 120 116 struct dc_link *link = stream->link; 121 117 122 122 - if (!dc_is_virtual_signal(stream->signal)) 118 118 + if (!dc_is_virtual_signal(stream->signal) && 119 119 + !dc_is_rgb_signal(stream->signal)) 123 120 stream_encoder->funcs->setup_stereo_sync( 124 121 stream_encoder, 125 122 pipe_ctx->stream_res.tg->inst,

+146 -1

drivers/gpu/drm/amd/display/dc/link/link_detection.c

reviewed

··· 862 862 verify_link_capability_non_destructive(link); 863 863 } 864 864 865 865 + /** 866 866 + * link_detect_evaluate_edid_header() - Evaluate if an EDID header is acceptable. 867 867 + * 868 868 + * Evaluates an 8-byte EDID header to check if it's good enough 869 869 + * for the purpose of determining whether a display is connected 870 870 + * without reading the full EDID. 871 871 + */ 872 872 + static bool link_detect_evaluate_edid_header(uint8_t edid_header[8]) 873 873 + { 874 874 + int edid_header_score = 0; 875 875 + int i; 876 876 + 877 877 + for (i = 0; i < 8; ++i) 878 878 + edid_header_score += edid_header[i] == ((i == 0 || i == 7) ? 0x00 : 0xff); 879 879 + 880 880 + return edid_header_score >= 6; 881 881 + } 882 882 + 883 883 + /** 884 884 + * link_detect_ddc_probe() - Probe the DDC to see if a display is connected. 885 885 + * 886 886 + * Detect whether a display is connected to DDC without reading full EDID. 887 887 + * Reads only the EDID header (the first 8 bytes of EDID) from DDC and 888 888 + * evaluates whether that matches. 889 889 + */ 890 890 + static bool link_detect_ddc_probe(struct dc_link *link) 891 891 + { 892 892 + if (!link->ddc) 893 893 + return false; 894 894 + 895 895 + uint8_t edid_header[8] = {0}; 896 896 + bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header)); 897 897 + 898 898 + if (!ddc_probed) 899 899 + return false; 900 900 + 901 901 + if (!link_detect_evaluate_edid_header(edid_header)) 902 902 + return false; 903 903 + 904 904 + return true; 905 905 + } 906 906 + 907 907 + /** 908 908 + * link_detect_dac_load_detect() - Performs DAC load detection. 909 909 + * 910 910 + * Load detection can be used to detect the presence of an 911 911 + * analog display when we can't read DDC. This causes a visible 912 912 + * visual glitch so it should be used sparingly. 913 913 + */ 914 914 + static bool link_detect_dac_load_detect(struct dc_link *link) 915 915 + { 916 916 + struct dc_bios *bios = link->ctx->dc_bios; 917 917 + struct link_encoder *link_enc = link->link_enc; 918 918 + enum engine_id engine_id = link_enc->preferred_engine; 919 919 + enum dal_device_type device_type = DEVICE_TYPE_CRT; 920 920 + enum bp_result bp_result; 921 921 + uint32_t enum_id; 922 922 + 923 923 + switch (engine_id) { 924 924 + case ENGINE_ID_DACB: 925 925 + enum_id = 2; 926 926 + break; 927 927 + case ENGINE_ID_DACA: 928 928 + default: 929 929 + engine_id = ENGINE_ID_DACA; 930 930 + enum_id = 1; 931 931 + break; 932 932 + } 933 933 + 934 934 + bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id); 935 935 + return bp_result == BP_RESULT_OK; 936 936 + } 937 937 + 865 938 /* 866 939 * detect_link_and_local_sink() - Detect if a sink is attached to a given link 867 940 * ··· 1016 943 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1017 944 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1018 945 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 946 946 + break; 947 947 + } 948 948 + 949 949 + case SIGNAL_TYPE_RGB: { 950 950 + sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 951 951 + sink_caps.signal = SIGNAL_TYPE_RGB; 1019 952 break; 1020 953 } 1021 954 ··· 1149 1070 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n"); 1150 1071 break; 1151 1072 case EDID_NO_RESPONSE: 1073 1073 + /* Analog connectors without EDID: 1074 1074 + * - old monitor that actually doesn't have EDID 1075 1075 + * - cheap DVI-A cable or adapter that doesn't connect DDC 1076 1076 + */ 1077 1077 + if (dc_connector_supports_analog(link->link_id.id)) { 1078 1078 + /* If we didn't do DAC load detection yet, do it now 1079 1079 + * to verify there really is a display connected. 1080 1080 + */ 1081 1081 + if (link->type != dc_connection_dac_load && 1082 1082 + !link_detect_dac_load_detect(link)) { 1083 1083 + if (prev_sink) 1084 1084 + dc_sink_release(prev_sink); 1085 1085 + link_disconnect_sink(link); 1086 1086 + return false; 1087 1087 + } 1088 1088 + 1089 1089 + DC_LOG_INFO("%s detected analog display without EDID\n", __func__); 1090 1090 + link->type = dc_connection_dac_load; 1091 1091 + sink->edid_caps.analog = true; 1092 1092 + break; 1093 1093 + } 1094 1094 + 1152 1095 DC_LOG_ERROR("No EDID read.\n"); 1096 1096 + 1153 1097 /* 1154 1098 * Abort detection for non-DP connectors if we have 1155 1099 * no EDID ··· 1209 1107 break; 1210 1108 } 1211 1109 1110 1110 + sink->edid_caps.analog &= dc_connector_supports_analog(link->link_id.id); 1111 1111 + 1212 1112 // Check if edid is the same 1213 1113 if ((prev_sink) && 1214 1114 (edid_status == EDID_THE_SAME || edid_status == EDID_OK)) ··· 1241 1137 sink = prev_sink; 1242 1138 prev_sink = NULL; 1243 1139 } 1244 1244 - query_hdcp_capability(sink->sink_signal, link); 1140 1140 + 1141 1141 + if (!sink->edid_caps.analog) 1142 1142 + query_hdcp_capability(sink->sink_signal, link); 1245 1143 } 1144 1144 + 1145 1145 + /* DVI-I connector connected to analog display. */ 1146 1146 + if ((link->link_id.id == CONNECTOR_ID_DUAL_LINK_DVII || 1147 1147 + link->link_id.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 1148 1148 + sink->edid_caps.analog) 1149 1149 + sink->sink_signal = SIGNAL_TYPE_RGB; 1246 1150 1247 1151 /* HDMI-DVI Dongle */ 1248 1152 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && ··· 1348 1236 return true; 1349 1237 } 1350 1238 1239 1239 + /** 1240 1240 + * link_detect_analog() - Determines if an analog sink is connected. 1241 1241 + */ 1242 1242 + static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *type) 1243 1243 + { 1244 1244 + /* Don't care about connectors that don't support an analog signal. */ 1245 1245 + ASSERT(dc_connector_supports_analog(link->link_id.id)); 1246 1246 + 1247 1247 + if (link_detect_ddc_probe(link)) { 1248 1248 + *type = dc_connection_single; 1249 1249 + return true; 1250 1250 + } 1251 1251 + 1252 1252 + if (link_detect_dac_load_detect(link)) { 1253 1253 + *type = dc_connection_dac_load; 1254 1254 + return true; 1255 1255 + } 1256 1256 + 1257 1257 + *type = dc_connection_none; 1258 1258 + return true; 1259 1259 + } 1260 1260 + 1351 1261 /* 1352 1262 * link_detect_connection_type() - Determine if there is a sink connected 1353 1263 * ··· 1385 1251 *type = dc_connection_single; 1386 1252 return true; 1387 1253 } 1254 1254 + 1255 1255 + /* Ignore the HPD pin (if any) for analog connectors. 1256 1256 + * Instead rely on DDC and DAC. 1257 1257 + * 1258 1258 + * - VGA connectors don't have any HPD at all. 1259 1259 + * - Some DVI-A cables don't connect the HPD pin. 1260 1260 + * - Some DVI-A cables pull up the HPD pin. 1261 1261 + * (So it's high even when no display is connected.) 1262 1262 + */ 1263 1263 + if (dc_connector_supports_analog(link->link_id.id)) 1264 1264 + return link_detect_analog(link, type); 1388 1265 1389 1266 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1390 1267 /*in case it is not on*/

+7 -2

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

reviewed

··· 2258 2258 enable_link_lvds(pipe_ctx); 2259 2259 status = DC_OK; 2260 2260 break; 2261 2261 + case SIGNAL_TYPE_RGB: 2262 2262 + status = DC_OK; 2263 2263 + break; 2261 2264 case SIGNAL_TYPE_VIRTUAL: 2262 2265 status = enable_link_virtual(pipe_ctx); 2263 2266 break; ··· 2374 2371 set_avmute(pipe_ctx, true); 2375 2372 } 2376 2373 2377 2377 - dc->hwss.disable_audio_stream(pipe_ctx); 2374 2374 + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) 2375 2375 + dc->hwss.disable_audio_stream(pipe_ctx); 2378 2376 2379 2377 update_psp_stream_config(pipe_ctx, true); 2380 2378 dc->hwss.blank_stream(pipe_ctx); ··· 2660 2656 enable_stream_features(pipe_ctx); 2661 2657 update_psp_stream_config(pipe_ctx, false); 2662 2658 2663 2663 - dc->hwss.enable_audio_stream(pipe_ctx); 2659 2659 + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) 2660 2660 + dc->hwss.enable_audio_stream(pipe_ctx); 2664 2661 2665 2662 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2666 2663 set_avmute(pipe_ctx, false);

+56 -4

drivers/gpu/drm/amd/display/dc/link/link_factory.c

reviewed

··· 451 451 return channel; 452 452 } 453 453 454 454 + static enum engine_id find_analog_engine(struct dc_link *link) 455 455 + { 456 456 + struct dc_bios *bp = link->ctx->dc_bios; 457 457 + struct graphics_object_id encoder = {0}; 458 458 + enum bp_result bp_result = BP_RESULT_OK; 459 459 + int i; 460 460 + 461 461 + for (i = 0; i < 3; i++) { 462 462 + bp_result = bp->funcs->get_src_obj(bp, link->link_id, i, &encoder); 463 463 + 464 464 + if (bp_result != BP_RESULT_OK) 465 465 + return ENGINE_ID_UNKNOWN; 466 466 + 467 467 + switch (encoder.id) { 468 468 + case ENCODER_ID_INTERNAL_DAC1: 469 469 + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 470 470 + return ENGINE_ID_DACA; 471 471 + case ENCODER_ID_INTERNAL_DAC2: 472 472 + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 473 473 + return ENGINE_ID_DACB; 474 474 + } 475 475 + } 476 476 + 477 477 + return ENGINE_ID_UNKNOWN; 478 478 + } 479 479 + 480 480 + static bool transmitter_supported(const enum transmitter transmitter) 481 481 + { 482 482 + return transmitter != TRANSMITTER_UNKNOWN && 483 483 + transmitter != TRANSMITTER_NUTMEG_CRT && 484 484 + transmitter != TRANSMITTER_TRAVIS_CRT && 485 485 + transmitter != TRANSMITTER_TRAVIS_LCD; 486 486 + } 487 487 + 488 488 + static bool analog_engine_supported(const enum engine_id engine_id) 489 489 + { 490 490 + return engine_id == ENGINE_ID_DACA || 491 491 + engine_id == ENGINE_ID_DACB; 492 492 + } 493 493 + 454 494 static bool construct_phy(struct dc_link *link, 455 495 const struct link_init_data *init_params) 456 496 { ··· 521 481 522 482 link->link_id = 523 483 bios->funcs->get_connector_id(bios, init_params->connector_index); 484 484 + 485 485 + /* Determine early if the link has any supported encoders, 486 486 + * so that we avoid initializing DDC and HPD, etc. 487 487 + */ 488 488 + bp_funcs->get_src_obj(bios, link->link_id, 0, &enc_init_data.encoder); 489 489 + enc_init_data.transmitter = translate_encoder_to_transmitter(enc_init_data.encoder); 490 490 + enc_init_data.analog_engine = find_analog_engine(link); 491 491 + 492 492 + if (!transmitter_supported(enc_init_data.transmitter) && 493 493 + !analog_engine_supported(enc_init_data.analog_engine)) { 494 494 + DC_LOG_WARNING("link_id %d has unsupported encoder\n", link->link_id.id); 495 495 + return false; 496 496 + } 524 497 525 498 link->ep_type = DISPLAY_ENDPOINT_PHY; 526 499 ··· 582 529 case CONNECTOR_ID_DUAL_LINK_DVID: 583 530 case CONNECTOR_ID_DUAL_LINK_DVII: 584 531 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; 532 532 + break; 533 533 + case CONNECTOR_ID_VGA: 534 534 + link->connector_signal = SIGNAL_TYPE_RGB; 585 535 break; 586 536 case CONNECTOR_ID_DISPLAY_PORT: 587 537 case CONNECTOR_ID_MXM: ··· 667 611 dal_ddc_get_line(get_ddc_pin(link->ddc)); 668 612 669 613 enc_init_data.ctx = dc_ctx; 670 670 - bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, 671 671 - &enc_init_data.encoder); 672 614 enc_init_data.connector = link->link_id; 673 615 enc_init_data.channel = get_ddc_line(link); 674 616 enc_init_data.hpd_source = get_hpd_line(link); 675 617 676 618 link->hpd_src = enc_init_data.hpd_source; 677 619 678 678 - enc_init_data.transmitter = 679 679 - translate_encoder_to_transmitter(enc_init_data.encoder); 680 620 link->link_enc = 681 621 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); 682 622

+16

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

reviewed

··· 1514 1514 MPCC_OGAM_SELECT_CURRENT, &s->rgam_lut); 1515 1515 } 1516 1516 1517 1517 + void mpc3_read_reg_state( 1518 1518 + struct mpc *mpc, 1519 1519 + int mpcc_inst, struct dcn_mpc_reg_state *mpc_reg_state) 1520 1520 + { 1521 1521 + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1522 1522 + 1523 1523 + mpc_reg_state->mpcc_bot_sel = REG_READ(MPCC_BOT_SEL[mpcc_inst]); 1524 1524 + mpc_reg_state->mpcc_control = REG_READ(MPCC_CONTROL[mpcc_inst]); 1525 1525 + mpc_reg_state->mpcc_ogam_control = REG_READ(MPCC_OGAM_CONTROL[mpcc_inst]); 1526 1526 + mpc_reg_state->mpcc_opp_id = REG_READ(MPCC_OPP_ID[mpcc_inst]); 1527 1527 + mpc_reg_state->mpcc_status = REG_READ(MPCC_STATUS[mpcc_inst]); 1528 1528 + mpc_reg_state->mpcc_top_sel = REG_READ(MPCC_TOP_SEL[mpcc_inst]); 1529 1529 + 1530 1530 + } 1531 1531 + 1517 1532 static const struct mpc_funcs dcn30_mpc_funcs = { 1518 1533 .read_mpcc_state = mpc3_read_mpcc_state, 1519 1534 .insert_plane = mpc1_insert_plane, ··· 1559 1544 .release_rmu = mpcc3_release_rmu, 1560 1545 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, 1561 1546 .get_mpc_out_mux = mpc1_get_mpc_out_mux, 1547 1547 + .mpc_read_reg_state = mpc3_read_reg_state, 1562 1548 .set_bg_color = mpc1_set_bg_color, 1563 1549 .set_mpc_mem_lp_mode = mpc3_set_mpc_mem_lp_mode, 1564 1550 };

+5

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

reviewed

··· 1096 1096 struct mpc *mpc, int mpcc_id, 1097 1097 bool power_on); 1098 1098 1099 1099 + void mpc3_read_reg_state( 1100 1100 + struct mpc *mpc, 1101 1101 + int mpcc_inst, 1102 1102 + struct dcn_mpc_reg_state *mpc_reg_state); 1103 1103 + 1099 1104 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst); 1100 1105 1101 1106 enum dc_lut_mode mpc3_get_ogam_current(

+1

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

reviewed

··· 1020 1020 .release_rmu = NULL, 1021 1021 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, 1022 1022 .get_mpc_out_mux = mpc1_get_mpc_out_mux, 1023 1023 + .mpc_read_reg_state = mpc3_read_reg_state, 1023 1024 .set_bg_color = mpc1_set_bg_color, 1024 1025 }; 1025 1026

+1

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

reviewed

··· 598 598 .release_rmu = NULL, 599 599 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, 600 600 .get_mpc_out_mux = mpc1_get_mpc_out_mux, 601 601 + .mpc_read_reg_state = mpc3_read_reg_state, 601 602 .set_bg_color = mpc1_set_bg_color, 602 603 .set_movable_cm_location = mpc401_set_movable_cm_location, 603 604 .update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select,

+13 -1

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

reviewed

··· 372 372 REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval); 373 373 } 374 374 375 375 + 376 376 + void opp1_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state) 377 377 + { 378 378 + struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 379 379 + 380 380 + opp_reg_state->fmt_control = REG_READ(FMT_CONTROL); 381 381 + opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL); 382 382 + opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL); 383 383 + opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL); 384 384 + } 385 385 + 375 386 /*****************************************/ 376 387 /* Constructor, Destructor */ 377 388 /*****************************************/ ··· 403 392 .opp_program_dpg_dimensions = NULL, 404 393 .dpg_is_blanked = NULL, 405 394 .dpg_is_pending = NULL, 406 406 - .opp_destroy = opp1_destroy 395 395 + .opp_destroy = opp1_destroy, 396 396 + .opp_read_reg_state = opp1_read_reg_state 407 397 }; 408 398 409 399 void dcn10_opp_construct(struct dcn10_opp *oppn10,

+4 -2

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

reviewed

··· 63 63 uint32_t OPPBUF_CONTROL1; \ 64 64 uint32_t OPPBUF_3D_PARAMETERS_0; \ 65 65 uint32_t OPPBUF_3D_PARAMETERS_1; \ 66 66 - uint32_t OPP_PIPE_CONTROL 66 66 + uint32_t OPP_PIPE_CONTROL; \ 67 67 + uint32_t OPP_PIPE_CRC_CONTROL 67 68 68 69 #define OPP_MASK_SH_LIST_DCN(mask_sh) \ 69 70 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ ··· 154 153 const struct dcn10_opp_registers *regs; 155 154 const struct dcn10_opp_shift *opp_shift; 156 155 const struct dcn10_opp_mask *opp_mask; 157 157 - 158 156 bool is_write_to_ram_a_safe; 159 157 }; 160 158 ··· 187 187 void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable); 188 188 189 189 void opp1_destroy(struct output_pixel_processor **opp); 190 190 + 191 191 + void opp1_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); 190 192 191 193 #endif

+13

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

reviewed

··· 377 377 return 0; 378 378 } 379 379 380 380 + void opp2_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state) 381 381 + { 382 382 + struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); 383 383 + 384 384 + opp_reg_state->dpg_control = REG_READ(DPG_CONTROL); 385 385 + opp_reg_state->fmt_control = REG_READ(FMT_CONTROL); 386 386 + opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL); 387 387 + opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL); 388 388 + opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL); 389 389 + opp_reg_state->dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG); 390 390 + } 391 391 + 380 392 /*****************************************/ 381 393 /* Constructor, Destructor */ 382 394 /*****************************************/ ··· 407 395 .opp_destroy = opp1_destroy, 408 396 .opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel, 409 397 .opp_get_left_edge_extra_pixel_count = opp2_get_left_edge_extra_pixel_count, 398 398 + .opp_read_reg_state = opp2_read_reg_state 410 399 }; 411 400 412 401 void dcn20_opp_construct(struct dcn20_opp *oppn20,

+5 -1

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

reviewed

··· 59 59 uint32_t DPG_COLOUR_G_Y; \ 60 60 uint32_t DPG_COLOUR_R_CR; \ 61 61 uint32_t DPG_RAMP_CONTROL; \ 62 62 - uint32_t DPG_STATUS 62 62 + uint32_t DPG_STATUS; \ 63 63 + uint32_t DSCRM_DSC_FORWARD_CONFIG 63 64 64 65 #define OPP_DPG_MASK_SH_LIST(mask_sh) \ 65 66 OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \ ··· 172 171 173 172 uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp, 174 173 enum dc_pixel_encoding pixel_encoding, bool is_primary); 174 174 + 175 175 + void opp2_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); 176 176 + 175 177 #endif

+13

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

reviewed

··· 51 51 { 52 52 REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable); 53 53 } 54 54 + 55 55 + void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state) 56 56 + { 57 57 + struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); 58 58 + 59 59 + opp_reg_state->dpg_control = REG_READ(DPG_CONTROL); 60 60 + opp_reg_state->fmt_control = REG_READ(FMT_CONTROL); 61 61 + opp_reg_state->opp_abm_control = REG_READ(OPP_ABM_CONTROL); 62 62 + opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL); 63 63 + opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL); 64 64 + opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL); 65 65 + opp_reg_state->dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG); 66 66 + }

+3 -1

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h

reviewed

··· 31 31 32 32 #define OPP_REG_VARIABLE_LIST_DCN3_5 \ 33 33 OPP_REG_VARIABLE_LIST_DCN2_0; \ 34 34 - uint32_t OPP_TOP_CLK_CONTROL 34 34 + uint32_t OPP_TOP_CLK_CONTROL; \ 35 35 + uint32_t OPP_ABM_CONTROL 35 36 36 37 #define OPP_MASK_SH_LIST_DCN35(mask_sh) \ 37 38 OPP_MASK_SH_LIST_DCN20(mask_sh), \ ··· 65 64 66 65 void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable); 67 66 67 67 + void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); 68 68 #endif

+37 -1

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

reviewed

··· 209 209 uint32_t OPTC_WIDTH_CONTROL2; \ 210 210 uint32_t OTG_PSTATE_REGISTER; \ 211 211 uint32_t OTG_PIPE_UPDATE_STATUS; \ 212 212 - uint32_t INTERRUPT_DEST 212 212 + uint32_t INTERRUPT_DEST; \ 213 213 + uint32_t OPTC_INPUT_SPARE_REGISTER; \ 214 214 + uint32_t OPTC_RSMU_UNDERFLOW; \ 215 215 + uint32_t OPTC_UNDERFLOW_THRESHOLD; \ 216 216 + uint32_t OTG_COUNT_CONTROL; \ 217 217 + uint32_t OTG_COUNT_RESET; \ 218 218 + uint32_t OTG_CRC_SIG_BLUE_CONTROL_MASK; \ 219 219 + uint32_t OTG_CRC_SIG_RED_GREEN_MASK; \ 220 220 + uint32_t OTG_DLPC_CONTROL; \ 221 221 + uint32_t OTG_DRR_CONTROL2; \ 222 222 + uint32_t OTG_DRR_TIMING_INT_STATUS; \ 223 223 + uint32_t OTG_GLOBAL_CONTROL3; \ 224 224 + uint32_t OTG_GLOBAL_SYNC_STATUS; \ 225 225 + uint32_t OTG_GSL_VSYNC_GAP; \ 226 226 + uint32_t OTG_INTERLACE_STATUS; \ 227 227 + uint32_t OTG_INTERRUPT_CONTROL; \ 228 228 + uint32_t OTG_LONG_VBLANK_STATUS; \ 229 229 + uint32_t OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; \ 230 230 + uint32_t OTG_MASTER_EN; \ 231 231 + uint32_t OTG_PIXEL_DATA_READBACK0; \ 232 232 + uint32_t OTG_PIXEL_DATA_READBACK1; \ 233 233 + uint32_t OTG_REQUEST_CONTROL; \ 234 234 + uint32_t OTG_SNAPSHOT_CONTROL; \ 235 235 + uint32_t OTG_SNAPSHOT_FRAME; \ 236 236 + uint32_t OTG_SNAPSHOT_POSITION; \ 237 237 + uint32_t OTG_SNAPSHOT_STATUS; \ 238 238 + uint32_t OTG_SPARE_REGISTER; \ 239 239 + uint32_t OTG_STATUS_HV_COUNT; \ 240 240 + uint32_t OTG_STATUS_VF_COUNT; \ 241 241 + uint32_t OTG_STEREO_FORCE_NEXT_EYE; \ 242 242 + uint32_t OTG_TRIG_MANUAL_CONTROL; \ 243 243 + uint32_t OTG_TRIGB_CNTL; \ 244 244 + uint32_t OTG_TRIGB_MANUAL_TRIG; \ 245 245 + uint32_t OTG_UPDATE_LOCK; \ 246 246 + uint32_t OTG_V_TOTAL_INT_STATUS; \ 247 247 + uint32_t OTG_VSYNC_NOM_INT_STATUS 248 248 + 213 249 214 250 struct dcn_optc_registers { 215 251 OPTC_REG_VARIABLE_LIST_DCN;

+131

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

reviewed

··· 315 315 s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); 316 316 } 317 317 318 318 + void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state) 319 319 + { 320 320 + struct optc *optc1 = DCN10TG_FROM_TG(optc); 321 321 + 322 322 + optc_reg_state->optc_bytes_per_pixel = REG_READ(OPTC_BYTES_PER_PIXEL); 323 323 + optc_reg_state->optc_data_format_control = REG_READ(OPTC_DATA_FORMAT_CONTROL); 324 324 + optc_reg_state->optc_data_source_select = REG_READ(OPTC_DATA_SOURCE_SELECT); 325 325 + optc_reg_state->optc_input_clock_control = REG_READ(OPTC_INPUT_CLOCK_CONTROL); 326 326 + optc_reg_state->optc_input_global_control = REG_READ(OPTC_INPUT_GLOBAL_CONTROL); 327 327 + optc_reg_state->optc_input_spare_register = REG_READ(OPTC_INPUT_SPARE_REGISTER); 328 328 + optc_reg_state->optc_memory_config = REG_READ(OPTC_MEMORY_CONFIG); 329 329 + optc_reg_state->optc_rsmu_underflow = REG_READ(OPTC_RSMU_UNDERFLOW); 330 330 + optc_reg_state->optc_underflow_threshold = REG_READ(OPTC_UNDERFLOW_THRESHOLD); 331 331 + optc_reg_state->optc_width_control = REG_READ(OPTC_WIDTH_CONTROL); 332 332 + optc_reg_state->otg_3d_structure_control = REG_READ(OTG_3D_STRUCTURE_CONTROL); 333 333 + optc_reg_state->otg_clock_control = REG_READ(OTG_CLOCK_CONTROL); 334 334 + optc_reg_state->otg_control = REG_READ(OTG_CONTROL); 335 335 + optc_reg_state->otg_count_control = REG_READ(OTG_COUNT_CONTROL); 336 336 + optc_reg_state->otg_count_reset = REG_READ(OTG_COUNT_RESET); 337 337 + optc_reg_state->otg_crc_cntl = REG_READ(OTG_CRC_CNTL); 338 338 + optc_reg_state->otg_crc_sig_blue_control_mask = REG_READ(OTG_CRC_SIG_BLUE_CONTROL_MASK); 339 339 + optc_reg_state->otg_crc_sig_red_green_mask = REG_READ(OTG_CRC_SIG_RED_GREEN_MASK); 340 340 + optc_reg_state->otg_crc0_data_b = REG_READ(OTG_CRC0_DATA_B); 341 341 + optc_reg_state->otg_crc0_data_rg = REG_READ(OTG_CRC0_DATA_RG); 342 342 + optc_reg_state->otg_crc0_windowa_x_control = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL); 343 343 + optc_reg_state->otg_crc0_windowa_x_control_readback = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL_READBACK); 344 344 + optc_reg_state->otg_crc0_windowa_y_control = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL); 345 345 + optc_reg_state->otg_crc0_windowa_y_control_readback = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK); 346 346 + optc_reg_state->otg_crc0_windowb_x_control = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL); 347 347 + optc_reg_state->otg_crc0_windowb_x_control_readback = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL_READBACK); 348 348 + optc_reg_state->otg_crc0_windowb_y_control = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL); 349 349 + optc_reg_state->otg_crc0_windowb_y_control_readback = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK); 350 350 + optc_reg_state->otg_crc1_data_b = REG_READ(OTG_CRC1_DATA_B); 351 351 + optc_reg_state->otg_crc1_data_rg = REG_READ(OTG_CRC1_DATA_RG); 352 352 + optc_reg_state->otg_crc1_windowa_x_control = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL); 353 353 + optc_reg_state->otg_crc1_windowa_x_control_readback = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL_READBACK); 354 354 + optc_reg_state->otg_crc1_windowa_y_control = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL); 355 355 + optc_reg_state->otg_crc1_windowa_y_control_readback = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK); 356 356 + optc_reg_state->otg_crc1_windowb_x_control = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL); 357 357 + optc_reg_state->otg_crc1_windowb_x_control_readback = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL_READBACK); 358 358 + optc_reg_state->otg_crc1_windowb_y_control = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL); 359 359 + optc_reg_state->otg_crc1_windowb_y_control_readback = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK); 360 360 + optc_reg_state->otg_crc2_data_b = REG_READ(OTG_CRC2_DATA_B); 361 361 + optc_reg_state->otg_crc2_data_rg = REG_READ(OTG_CRC2_DATA_RG); 362 362 + optc_reg_state->otg_crc3_data_b = REG_READ(OTG_CRC3_DATA_B); 363 363 + optc_reg_state->otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG); 364 364 + optc_reg_state->otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL); 365 365 + optc_reg_state->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); 366 366 + optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2); 367 367 + optc_reg_state->otg_drr_control = REG_READ(OTG_DRR_CONTROL); 368 368 + optc_reg_state->otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS); 369 369 + optc_reg_state->otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW); 370 370 + optc_reg_state->otg_drr_v_total_change = REG_READ(OTG_DRR_V_TOTAL_CHANGE); 371 371 + optc_reg_state->otg_dsc_start_position = REG_READ(OTG_DSC_START_POSITION); 372 372 + optc_reg_state->otg_force_count_now_cntl = REG_READ(OTG_FORCE_COUNT_NOW_CNTL); 373 373 + optc_reg_state->otg_global_control0 = REG_READ(OTG_GLOBAL_CONTROL0); 374 374 + optc_reg_state->otg_global_control1 = REG_READ(OTG_GLOBAL_CONTROL1); 375 375 + optc_reg_state->otg_global_control2 = REG_READ(OTG_GLOBAL_CONTROL2); 376 376 + optc_reg_state->otg_global_control3 = REG_READ(OTG_GLOBAL_CONTROL3); 377 377 + optc_reg_state->otg_global_control4 = REG_READ(OTG_GLOBAL_CONTROL4); 378 378 + optc_reg_state->otg_global_sync_status = REG_READ(OTG_GLOBAL_SYNC_STATUS); 379 379 + optc_reg_state->otg_gsl_control = REG_READ(OTG_GSL_CONTROL); 380 380 + optc_reg_state->otg_gsl_vsync_gap = REG_READ(OTG_GSL_VSYNC_GAP); 381 381 + optc_reg_state->otg_gsl_window_x = REG_READ(OTG_GSL_WINDOW_X); 382 382 + optc_reg_state->otg_gsl_window_y = REG_READ(OTG_GSL_WINDOW_Y); 383 383 + optc_reg_state->otg_h_blank_start_end = REG_READ(OTG_H_BLANK_START_END); 384 384 + optc_reg_state->otg_h_sync_a = REG_READ(OTG_H_SYNC_A); 385 385 + optc_reg_state->otg_h_sync_a_cntl = REG_READ(OTG_H_SYNC_A_CNTL); 386 386 + optc_reg_state->otg_h_timing_cntl = REG_READ(OTG_H_TIMING_CNTL); 387 387 + optc_reg_state->otg_h_total = REG_READ(OTG_H_TOTAL); 388 388 + optc_reg_state->otg_interlace_control = REG_READ(OTG_INTERLACE_CONTROL); 389 389 + optc_reg_state->otg_interlace_status = REG_READ(OTG_INTERLACE_STATUS); 390 390 + optc_reg_state->otg_interrupt_control = REG_READ(OTG_INTERRUPT_CONTROL); 391 391 + optc_reg_state->otg_long_vblank_status = REG_READ(OTG_LONG_VBLANK_STATUS); 392 392 + optc_reg_state->otg_m_const_dto0 = REG_READ(OTG_M_CONST_DTO0); 393 393 + optc_reg_state->otg_m_const_dto1 = REG_READ(OTG_M_CONST_DTO1); 394 394 + optc_reg_state->otg_manual_force_vsync_next_line = REG_READ(OTG_MANUAL_FORCE_VSYNC_NEXT_LINE); 395 395 + optc_reg_state->otg_master_en = REG_READ(OTG_MASTER_EN); 396 396 + optc_reg_state->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK); 397 397 + optc_reg_state->otg_master_update_mode = REG_READ(OTG_MASTER_UPDATE_MODE); 398 398 + optc_reg_state->otg_nom_vert_position = REG_READ(OTG_NOM_VERT_POSITION); 399 399 + optc_reg_state->otg_pipe_update_status = REG_READ(OTG_PIPE_UPDATE_STATUS); 400 400 + optc_reg_state->otg_pixel_data_readback0 = REG_READ(OTG_PIXEL_DATA_READBACK0); 401 401 + optc_reg_state->otg_pixel_data_readback1 = REG_READ(OTG_PIXEL_DATA_READBACK1); 402 402 + optc_reg_state->otg_request_control = REG_READ(OTG_REQUEST_CONTROL); 403 403 + optc_reg_state->otg_snapshot_control = REG_READ(OTG_SNAPSHOT_CONTROL); 404 404 + optc_reg_state->otg_snapshot_frame = REG_READ(OTG_SNAPSHOT_FRAME); 405 405 + optc_reg_state->otg_snapshot_position = REG_READ(OTG_SNAPSHOT_POSITION); 406 406 + optc_reg_state->otg_snapshot_status = REG_READ(OTG_SNAPSHOT_STATUS); 407 407 + optc_reg_state->otg_spare_register = REG_READ(OTG_SPARE_REGISTER); 408 408 + optc_reg_state->otg_static_screen_control = REG_READ(OTG_STATIC_SCREEN_CONTROL); 409 409 + optc_reg_state->otg_status = REG_READ(OTG_STATUS); 410 410 + optc_reg_state->otg_status_frame_count = REG_READ(OTG_STATUS_FRAME_COUNT); 411 411 + optc_reg_state->otg_status_hv_count = REG_READ(OTG_STATUS_HV_COUNT); 412 412 + optc_reg_state->otg_status_position = REG_READ(OTG_STATUS_POSITION); 413 413 + optc_reg_state->otg_status_vf_count = REG_READ(OTG_STATUS_VF_COUNT); 414 414 + optc_reg_state->otg_stereo_control = REG_READ(OTG_STEREO_CONTROL); 415 415 + optc_reg_state->otg_stereo_force_next_eye = REG_READ(OTG_STEREO_FORCE_NEXT_EYE); 416 416 + optc_reg_state->otg_stereo_status = REG_READ(OTG_STEREO_STATUS); 417 417 + optc_reg_state->otg_trig_manual_control = REG_READ(OTG_TRIG_MANUAL_CONTROL); 418 418 + optc_reg_state->otg_triga_cntl = REG_READ(OTG_TRIGA_CNTL); 419 419 + optc_reg_state->otg_triga_manual_trig = REG_READ(OTG_TRIGA_MANUAL_TRIG); 420 420 + optc_reg_state->otg_trigb_cntl = REG_READ(OTG_TRIGB_CNTL); 421 421 + optc_reg_state->otg_trigb_manual_trig = REG_READ(OTG_TRIGB_MANUAL_TRIG); 422 422 + optc_reg_state->otg_update_lock = REG_READ(OTG_UPDATE_LOCK); 423 423 + optc_reg_state->otg_v_blank_start_end = REG_READ(OTG_V_BLANK_START_END); 424 424 + optc_reg_state->otg_v_count_stop_control = REG_READ(OTG_V_COUNT_STOP_CONTROL); 425 425 + optc_reg_state->otg_v_count_stop_control2 = REG_READ(OTG_V_COUNT_STOP_CONTROL2); 426 426 + optc_reg_state->otg_v_sync_a = REG_READ(OTG_V_SYNC_A); 427 427 + optc_reg_state->otg_v_sync_a_cntl = REG_READ(OTG_V_SYNC_A_CNTL); 428 428 + optc_reg_state->otg_v_total = REG_READ(OTG_V_TOTAL); 429 429 + optc_reg_state->otg_v_total_control = REG_READ(OTG_V_TOTAL_CONTROL); 430 430 + optc_reg_state->otg_v_total_int_status = REG_READ(OTG_V_TOTAL_INT_STATUS); 431 431 + optc_reg_state->otg_v_total_max = REG_READ(OTG_V_TOTAL_MAX); 432 432 + optc_reg_state->otg_v_total_mid = REG_READ(OTG_V_TOTAL_MID); 433 433 + optc_reg_state->otg_v_total_min = REG_READ(OTG_V_TOTAL_MIN); 434 434 + optc_reg_state->otg_vert_sync_control = REG_READ(OTG_VERT_SYNC_CONTROL); 435 435 + optc_reg_state->otg_vertical_interrupt0_control = REG_READ(OTG_VERTICAL_INTERRUPT0_CONTROL); 436 436 + optc_reg_state->otg_vertical_interrupt0_position = REG_READ(OTG_VERTICAL_INTERRUPT0_POSITION); 437 437 + optc_reg_state->otg_vertical_interrupt1_control = REG_READ(OTG_VERTICAL_INTERRUPT1_CONTROL); 438 438 + optc_reg_state->otg_vertical_interrupt1_position = REG_READ(OTG_VERTICAL_INTERRUPT1_POSITION); 439 439 + optc_reg_state->otg_vertical_interrupt2_control = REG_READ(OTG_VERTICAL_INTERRUPT2_CONTROL); 440 440 + optc_reg_state->otg_vertical_interrupt2_position = REG_READ(OTG_VERTICAL_INTERRUPT2_POSITION); 441 441 + optc_reg_state->otg_vready_param = REG_READ(OTG_VREADY_PARAM); 442 442 + optc_reg_state->otg_vstartup_param = REG_READ(OTG_VSTARTUP_PARAM); 443 443 + optc_reg_state->otg_vsync_nom_int_status = REG_READ(OTG_VSYNC_NOM_INT_STATUS); 444 444 + optc_reg_state->otg_vupdate_keepout = REG_READ(OTG_VUPDATE_KEEPOUT); 445 445 + optc_reg_state->otg_vupdate_param = REG_READ(OTG_VUPDATE_PARAM); 446 446 + } 447 447 + 318 448 static const struct timing_generator_funcs dcn31_tg_funcs = { 319 449 .validate_timing = optc1_validate_timing, 320 450 .program_timing = optc1_program_timing, ··· 507 377 .init_odm = optc3_init_odm, 508 378 .is_two_pixels_per_container = optc1_is_two_pixels_per_container, 509 379 .read_otg_state = optc31_read_otg_state, 380 380 + .optc_read_reg_state = optc31_read_reg_state, 510 381 }; 511 382 512 383 void dcn31_timing_generator_init(struct optc *optc1)

+2

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

reviewed

··· 274 274 void optc31_read_otg_state(struct timing_generator *optc, 275 275 struct dcn_otg_state *s); 276 276 277 277 + void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state); 278 278 + 277 279 #endif /* __DC_OPTC_DCN31_H__ */

+1

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

reviewed

··· 256 256 .set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode, 257 257 .is_two_pixels_per_container = optc1_is_two_pixels_per_container, 258 258 .read_otg_state = optc31_read_otg_state, 259 259 + .optc_read_reg_state = optc31_read_reg_state, 259 260 }; 260 261 261 262 void dcn314_timing_generator_init(struct optc *optc1)

+1

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

reviewed

··· 365 365 .get_otg_double_buffer_pending = optc3_get_otg_update_pending, 366 366 .get_pipe_update_pending = optc3_get_pipe_update_pending, 367 367 .read_otg_state = optc31_read_otg_state, 368 368 + .optc_read_reg_state = optc31_read_reg_state, 368 369 }; 369 370 370 371 void dcn32_timing_generator_init(struct optc *optc1)

+1

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

reviewed

··· 511 511 .set_long_vtotal = optc35_set_long_vtotal, 512 512 .is_two_pixels_per_container = optc1_is_two_pixels_per_container, 513 513 .read_otg_state = optc31_read_otg_state, 514 514 + .optc_read_reg_state = optc31_read_reg_state, 514 515 }; 515 516 516 517 void dcn35_timing_generator_init(struct optc *optc1)

+1

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

reviewed

··· 533 533 .set_vupdate_keepout = optc401_set_vupdate_keepout, 534 534 .wait_update_lock_status = optc401_wait_update_lock_status, 535 535 .read_otg_state = optc31_read_otg_state, 536 536 + .optc_read_reg_state = optc31_read_reg_state, 536 537 }; 537 538 538 539 void dcn401_timing_generator_init(struct optc *optc1)

+33 -5

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

reviewed

··· 78 78 #endif 79 79 80 80 #ifndef mmBIOS_SCRATCH_2 81 81 + #define mmBIOS_SCRATCH_0 0x05C9 81 82 #define mmBIOS_SCRATCH_2 0x05CB 82 83 #define mmBIOS_SCRATCH_3 0x05CC 83 84 #define mmBIOS_SCRATCH_6 0x05CF ··· 226 225 link_regs(4), 227 226 link_regs(5), 228 227 link_regs(6), 228 228 + { .DAC_ENABLE = mmDAC_ENABLE }, 229 229 }; 230 230 231 231 #define stream_enc_regs(id)\ ··· 370 368 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 371 369 372 370 static const struct bios_registers bios_regs = { 371 371 + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, 373 372 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 374 373 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 375 374 }; ··· 378 375 static const struct resource_caps res_cap = { 379 376 .num_timing_generator = 6, 380 377 .num_audio = 6, 378 378 + .num_analog_stream_encoder = 1, 381 379 .num_stream_encoder = 6, 382 380 .num_pll = 3, 383 381 .num_ddc = 6, ··· 406 402 } 407 403 }; 408 404 409 409 - static const struct dc_debug_options debug_defaults = { 410 410 - .enable_legacy_fast_update = true, 405 405 + static const struct dc_debug_options debug_defaults = { 0 }; 406 406 + 407 407 + static const struct dc_check_config config_defaults = { 408 408 + .enable_legacy_fast_update = true, 411 409 }; 412 410 413 411 #define CTX ctx ··· 489 483 490 484 if (!enc110) 491 485 return NULL; 486 486 + 487 487 + if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { 488 488 + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); 489 489 + return &enc110->base; 490 490 + } 492 491 493 492 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 494 493 &stream_enc_regs[eng_id], &se_shift, &se_mask); ··· 635 624 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 636 625 int link_regs_id; 637 626 638 638 - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 627 627 + if (!enc110) 628 628 + return NULL; 629 629 + 630 630 + if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { 631 631 + dce110_link_encoder_construct(enc110, 632 632 + enc_init_data, 633 633 + &link_enc_feature, 634 634 + &link_enc_regs[ENGINE_ID_DACA], 635 635 + NULL, 636 636 + NULL); 637 637 + return &enc110->base; 638 638 + } 639 639 + 640 640 + if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 639 641 return NULL; 640 642 641 643 link_regs_id = ··· 976 952 int i; 977 953 int j = -1; 978 954 struct dc_link *link = stream->link; 955 955 + enum engine_id preferred_engine = link->link_enc->preferred_engine; 956 956 + 957 957 + if (dc_is_rgb_signal(stream->signal)) 958 958 + preferred_engine = link->link_enc->analog_engine; 979 959 980 960 for (i = 0; i < pool->stream_enc_count; i++) { 981 961 if (!res_ctx->is_stream_enc_acquired[i] && ··· 988 960 * in daisy chain use case 989 961 */ 990 962 j = i; 991 991 - if (pool->stream_enc[i]->id == 992 992 - link->link_enc->preferred_engine) 963 963 + if (pool->stream_enc[i]->id == preferred_engine) 993 964 return pool->stream_enc[i]; 994 965 } 995 966 } ··· 1120 1093 dc->caps.disable_dp_clk_share = true; 1121 1094 dc->caps.extended_aux_timeout_support = false; 1122 1095 dc->debug = debug_defaults; 1096 1096 + dc->check_config = config_defaults; 1123 1097 1124 1098 for (i = 0; i < pool->base.pipe_count; i++) { 1125 1099 pool->base.timing_generators[i] =

+6 -1

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

reviewed

··· 82 82 #endif 83 83 84 84 #ifndef mmBIOS_SCRATCH_2 85 85 + #define mmBIOS_SCRATCH_0 0x05C9 85 86 #define mmBIOS_SCRATCH_2 0x05CB 86 87 #define mmBIOS_SCRATCH_3 0x05CC 87 88 #define mmBIOS_SCRATCH_6 0x05CF ··· 378 377 }; 379 378 380 379 static const struct bios_registers bios_regs = { 380 380 + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, 381 381 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 382 382 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 383 383 }; ··· 426 424 64 427 425 }; 428 426 429 429 - static const struct dc_debug_options debug_defaults = { 427 427 + static const struct dc_debug_options debug_defaults = { 0 }; 428 428 + 429 429 + static const struct dc_check_config config_defaults = { 430 430 .enable_legacy_fast_update = true, 431 431 }; 432 432 ··· 1380 1376 dc->caps.is_apu = true; 1381 1377 dc->caps.extended_aux_timeout_support = false; 1382 1378 dc->debug = debug_defaults; 1379 1379 + dc->check_config = config_defaults; 1383 1380 1384 1381 /************************************************* 1385 1382 * Create resources *

+7 -2

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

reviewed

··· 76 76 #endif 77 77 78 78 #ifndef mmBIOS_SCRATCH_2 79 79 + #define mmBIOS_SCRATCH_0 0x05C9 79 80 #define mmBIOS_SCRATCH_2 0x05CB 80 81 #define mmBIOS_SCRATCH_3 0x05CC 81 82 #define mmBIOS_SCRATCH_6 0x05CF ··· 386 385 }; 387 386 388 387 static const struct bios_registers bios_regs = { 388 388 + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, 389 389 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 390 390 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 391 391 }; ··· 431 429 64 432 430 }; 433 431 434 434 - static const struct dc_debug_options debug_defaults = { 435 435 - .enable_legacy_fast_update = true, 432 432 + static const struct dc_debug_options debug_defaults = { 0 }; 433 433 + 434 434 + static const struct dc_check_config config_defaults = { 435 435 + .enable_legacy_fast_update = true, 436 436 }; 437 437 438 438 #define CTX ctx ··· 1251 1247 dc->caps.dual_link_dvi = true; 1252 1248 dc->caps.extended_aux_timeout_support = false; 1253 1249 dc->debug = debug_defaults; 1250 1250 + dc->check_config = config_defaults; 1254 1251 1255 1252 /************************************************* 1256 1253 * Create resources *

+7 -2

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

reviewed

··· 491 491 return dce_i2c_hw; 492 492 } 493 493 static const struct bios_registers bios_regs = { 494 494 + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0 + NBIO_BASE(mmBIOS_SCRATCH_0_BASE_IDX), 494 495 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 495 496 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 496 497 }; ··· 527 526 }; 528 527 529 528 static const struct dc_debug_options debug_defaults = { 530 530 - .disable_clock_gate = true, 531 531 - .enable_legacy_fast_update = true, 529 529 + .disable_clock_gate = true, 530 530 + }; 531 531 + 532 532 + static const struct dc_check_config config_defaults = { 533 533 + .enable_legacy_fast_update = true, 532 534 }; 533 535 534 536 static struct clock_source *dce120_clock_source_create( ··· 1093 1089 dc->caps.psp_setup_panel_mode = true; 1094 1090 dc->caps.extended_aux_timeout_support = false; 1095 1091 dc->debug = debug_defaults; 1092 1092 + dc->check_config = config_defaults; 1096 1093 1097 1094 /************************************************* 1098 1095 * Create resources *

+27 -2

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

reviewed

··· 80 80 81 81 82 82 #ifndef mmBIOS_SCRATCH_2 83 83 + #define mmBIOS_SCRATCH_0 0x05C9 83 84 #define mmBIOS_SCRATCH_2 0x05CB 84 85 #define mmBIOS_SCRATCH_3 0x05CC 85 86 #define mmBIOS_SCRATCH_6 0x05CF ··· 241 240 link_regs(2), 242 241 link_regs(3), 243 242 link_regs(4), 244 244 - link_regs(5) 243 243 + link_regs(5), 244 244 + {0}, 245 245 + { .DAC_ENABLE = mmDAC_ENABLE }, 245 246 }; 246 247 247 248 #define stream_enc_regs(id)\ ··· 369 366 }; 370 367 371 368 static const struct bios_registers bios_regs = { 369 369 + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, 372 370 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 373 371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 374 372 }; ··· 377 373 static const struct resource_caps res_cap = { 378 374 .num_timing_generator = 6, 379 375 .num_audio = 6, 376 376 + .num_analog_stream_encoder = 1, 380 377 .num_stream_encoder = 6, 381 378 .num_pll = 3, 382 379 .num_ddc = 6, ··· 387 382 .num_timing_generator = 4, 388 383 .num_audio = 6, 389 384 .num_stream_encoder = 6, 385 385 + .num_analog_stream_encoder = 1, 390 386 .num_pll = 3, 391 387 .num_ddc = 6, 392 388 }; ··· 395 389 static const struct resource_caps res_cap_64 = { 396 390 .num_timing_generator = 2, 397 391 .num_audio = 2, 392 392 + .num_analog_stream_encoder = 1, 398 393 .num_stream_encoder = 2, 399 394 .num_pll = 3, 400 395 .num_ddc = 2, ··· 606 599 if (!enc110) 607 600 return NULL; 608 601 602 602 + if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { 603 603 + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); 604 604 + return &enc110->base; 605 605 + } 606 606 + 609 607 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 610 608 &stream_enc_regs[eng_id], 611 609 &se_shift, &se_mask); ··· 730 718 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 731 719 int link_regs_id; 732 720 733 733 - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 721 721 + if (!enc110) 722 722 + return NULL; 723 723 + 724 724 + if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { 725 725 + dce110_link_encoder_construct(enc110, 726 726 + enc_init_data, 727 727 + &link_enc_feature, 728 728 + &link_enc_regs[ENGINE_ID_DACA], 729 729 + NULL, 730 730 + NULL); 731 731 + return &enc110->base; 732 732 + } 733 733 + 734 734 + if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 734 735 return NULL; 735 736 736 737 link_regs_id =

+31 -3

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

reviewed

··· 78 78 79 79 80 80 #ifndef mmBIOS_SCRATCH_2 81 81 + #define mmBIOS_SCRATCH_0 0x05C9 81 82 #define mmBIOS_SCRATCH_2 0x05CB 82 83 #define mmBIOS_SCRATCH_3 0x05CC 83 84 #define mmBIOS_SCRATCH_6 0x05CF ··· 242 241 link_regs(4), 243 242 link_regs(5), 244 243 link_regs(6), 244 244 + { .DAC_ENABLE = mmDAC_ENABLE }, 245 245 }; 246 246 247 247 #define stream_enc_regs(id)\ ··· 370 368 }; 371 369 372 370 static const struct bios_registers bios_regs = { 371 371 + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, 373 372 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 374 373 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 375 374 }; ··· 378 375 static const struct resource_caps res_cap = { 379 376 .num_timing_generator = 6, 380 377 .num_audio = 6, 378 378 + .num_analog_stream_encoder = 1, 381 379 .num_stream_encoder = 6, 382 380 .num_pll = 3, 383 381 .num_ddc = 6, ··· 387 383 static const struct resource_caps res_cap_81 = { 388 384 .num_timing_generator = 4, 389 385 .num_audio = 7, 386 386 + .num_analog_stream_encoder = 1, 390 387 .num_stream_encoder = 7, 391 388 .num_pll = 3, 392 389 .num_ddc = 6, ··· 396 391 static const struct resource_caps res_cap_83 = { 397 392 .num_timing_generator = 2, 398 393 .num_audio = 6, 394 394 + .num_analog_stream_encoder = 1, 399 395 .num_stream_encoder = 6, 400 396 .num_pll = 2, 401 397 .num_ddc = 2, ··· 424 418 } 425 419 }; 426 420 427 427 - static const struct dc_debug_options debug_defaults = { 428 428 - .enable_legacy_fast_update = true, 421 421 + static const struct dc_debug_options debug_defaults = { 0 }; 422 422 + 423 423 + static const struct dc_check_config config_defaults = { 424 424 + .enable_legacy_fast_update = true, 429 425 }; 430 426 431 427 static const struct dce_dmcu_registers dmcu_regs = { ··· 613 605 if (!enc110) 614 606 return NULL; 615 607 608 608 + if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { 609 609 + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); 610 610 + return &enc110->base; 611 611 + } 612 612 + 616 613 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 617 614 &stream_enc_regs[eng_id], 618 615 &se_shift, &se_mask); ··· 737 724 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 738 725 int link_regs_id; 739 726 740 740 - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 727 727 + if (!enc110) 728 728 + return NULL; 729 729 + 730 730 + if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { 731 731 + dce110_link_encoder_construct(enc110, 732 732 + enc_init_data, 733 733 + &link_enc_feature, 734 734 + &link_enc_regs[ENGINE_ID_DACA], 735 735 + NULL, 736 736 + NULL); 737 737 + return &enc110->base; 738 738 + } 739 739 + 740 740 + if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 741 741 return NULL; 742 742 743 743 link_regs_id = ··· 945 919 dc->caps.dual_link_dvi = true; 946 920 dc->caps.extended_aux_timeout_support = false; 947 921 dc->debug = debug_defaults; 922 922 + dc->check_config = config_defaults; 948 923 949 924 /************************************************* 950 925 * Create resources * ··· 1347 1320 dc->caps.min_horizontal_blanking_period = 80; 1348 1321 dc->caps.is_apu = true; 1349 1322 dc->debug = debug_defaults; 1323 1323 + dc->check_config = config_defaults; 1350 1324 1351 1325 /************************************************* 1352 1326 * Create resources *

+6 -1

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

reviewed

··· 556 556 .recovery_enabled = false, /*enable this by default after testing.*/ 557 557 .max_downscale_src_width = 3840, 558 558 .underflow_assert_delay_us = 0xFFFFFFFF, 559 559 - .enable_legacy_fast_update = true, 560 559 .using_dml2 = false, 560 560 + }; 561 561 + 562 562 + static const struct dc_check_config config_defaults = { 563 563 + .enable_legacy_fast_update = true, 561 564 }; 562 565 563 566 static void dcn10_dpp_destroy(struct dpp **dpp) ··· 1398 1395 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1399 1396 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1400 1397 dc->caps.color.mpc.ocsc = 0; 1398 1398 + dc->debug = debug_defaults_drv; 1399 1399 + dc->check_config = config_defaults; 1401 1400 1402 1401 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1403 1402 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

reviewed

··· 718 718 .scl_reset_length10 = true, 719 719 .sanity_checks = false, 720 720 .underflow_assert_delay_us = 0xFFFFFFFF, 721 721 - .enable_legacy_fast_update = true, 722 721 .using_dml2 = false, 722 722 + }; 723 723 + 724 724 + static const struct dc_check_config config_defaults = { 725 725 + .enable_legacy_fast_update = true, 723 726 }; 724 727 725 728 void dcn20_dpp_destroy(struct dpp **dpp) ··· 2474 2471 dc->caps.color.mpc.ocsc = 1; 2475 2472 2476 2473 dc->caps.dp_hdmi21_pcon_support = true; 2474 2474 + dc->check_config = config_defaults; 2477 2475 2478 2476 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2479 2477 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

reviewed

··· 614 614 .sanity_checks = false, 615 615 .underflow_assert_delay_us = 0xFFFFFFFF, 616 616 .enable_tri_buf = true, 617 617 - .enable_legacy_fast_update = true, 618 617 .using_dml2 = false, 618 618 + }; 619 619 + 620 620 + static const struct dc_check_config config_defaults = { 621 621 + .enable_legacy_fast_update = true, 619 622 }; 620 623 621 624 static void dcn201_dpp_destroy(struct dpp **dpp) ··· 1154 1151 dc->caps.color.mpc.ocsc = 1; 1155 1152 1156 1153 dc->debug = debug_defaults_drv; 1154 1154 + dc->check_config = config_defaults; 1157 1155 1158 1156 /*a0 only, remove later*/ 1159 1157 dc->work_arounds.no_connect_phy_config = true;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

reviewed

··· 626 626 .usbc_combo_phy_reset_wa = true, 627 627 .dmub_command_table = true, 628 628 .use_max_lb = true, 629 629 - .enable_legacy_fast_update = true, 630 629 .using_dml2 = false, 630 630 + }; 631 631 + 632 632 + static const struct dc_check_config config_defaults = { 633 633 + .enable_legacy_fast_update = true, 631 634 }; 632 635 633 636 static const struct dc_panel_config panel_config_defaults = { ··· 1461 1458 dc->caps.color.mpc.ocsc = 1; 1462 1459 1463 1460 dc->caps.dp_hdmi21_pcon_support = true; 1461 1461 + dc->check_config = config_defaults; 1464 1462 1465 1463 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1466 1464 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

reviewed

··· 727 727 .dmub_command_table = true, 728 728 .use_max_lb = true, 729 729 .exit_idle_opt_for_cursor_updates = true, 730 730 - .enable_legacy_fast_update = false, 731 730 .using_dml2 = false, 731 731 + }; 732 732 + 733 733 + static const struct dc_check_config config_defaults = { 734 734 + .enable_legacy_fast_update = false, 732 735 }; 733 736 734 737 static const struct dc_panel_config panel_config_defaults = { ··· 2377 2374 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 2378 2375 } 2379 2376 } 2377 2377 + dc->check_config = config_defaults; 2380 2378 2381 2379 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2382 2380 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

reviewed

··· 701 701 .dmub_command_table = true, 702 702 .use_max_lb = false, 703 703 .exit_idle_opt_for_cursor_updates = true, 704 704 - .enable_legacy_fast_update = true, 705 704 .using_dml2 = false, 705 705 + }; 706 706 + 707 707 + static const struct dc_check_config config_defaults = { 708 708 + .enable_legacy_fast_update = true, 706 709 }; 707 710 708 711 static void dcn301_dpp_destroy(struct dpp **dpp) ··· 1501 1498 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1502 1499 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1503 1500 } 1501 1501 + dc->check_config = config_defaults; 1504 1502 1505 1503 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1506 1504 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

reviewed

··· 98 98 .dmub_command_table = true, 99 99 .use_max_lb = true, 100 100 .exit_idle_opt_for_cursor_updates = true, 101 101 - .enable_legacy_fast_update = false, 102 101 .using_dml2 = false, 102 102 + }; 103 103 + 104 104 + static const struct dc_check_config config_defaults = { 105 105 + .enable_legacy_fast_update = false, 103 106 }; 104 107 105 108 static const struct dc_panel_config panel_config_defaults = { ··· 1293 1290 &is_vbios_interop_enabled); 1294 1291 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1295 1292 } 1293 1293 + dc->check_config = config_defaults; 1296 1294 1297 1295 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1298 1296 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

reviewed

··· 98 98 .dmub_command_table = true, 99 99 .use_max_lb = true, 100 100 .exit_idle_opt_for_cursor_updates = true, 101 101 - .enable_legacy_fast_update = false, 102 101 .using_dml2 = false, 102 102 + }; 103 103 + 104 104 + static const struct dc_check_config config_defaults = { 105 105 + .enable_legacy_fast_update = false, 103 106 }; 104 107 105 108 static const struct dc_panel_config panel_config_defaults = { ··· 1237 1234 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1238 1235 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1239 1236 } 1237 1237 + dc->check_config = config_defaults; 1240 1238 1241 1239 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1242 1240 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

reviewed

··· 888 888 } 889 889 }, 890 890 .disable_z10 = true, 891 891 - .enable_legacy_fast_update = true, 892 891 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 893 892 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE, 894 893 .using_dml2 = false, 894 894 + }; 895 895 + 896 896 + static const struct dc_check_config config_defaults = { 897 897 + .enable_legacy_fast_update = true, 895 898 }; 896 899 897 900 static const struct dc_panel_config panel_config_defaults = { ··· 1981 1978 dc->caps.vbios_lttpr_aware = true; 1982 1979 } 1983 1980 } 1981 1981 + dc->check_config = config_defaults; 1984 1982 1985 1983 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1986 1984 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

reviewed

··· 924 924 }, 925 925 926 926 .seamless_boot_odm_combine = true, 927 927 - .enable_legacy_fast_update = true, 928 927 .using_dml2 = false, 929 928 .disable_dsc_power_gate = true, 930 929 .min_disp_clk_khz = 100000, 930 930 + }; 931 931 + 932 932 + static const struct dc_check_config config_defaults = { 933 933 + .enable_legacy_fast_update = true, 931 934 }; 932 935 933 936 static const struct dc_panel_config panel_config_defaults = { ··· 1913 1910 dc->caps.vbios_lttpr_aware = true; 1914 1911 } 1915 1912 } 1913 1913 + dc->check_config = config_defaults; 1916 1914 1917 1915 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1918 1916 dc->debug = debug_defaults_drv;

+6 -1

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

reviewed

··· 887 887 .afmt = true, 888 888 } 889 889 }, 890 890 - .enable_legacy_fast_update = true, 891 890 .psr_power_use_phy_fsm = 0, 892 891 .using_dml2 = false, 892 892 + .min_disp_clk_khz = 100000, 893 893 + }; 894 894 + 895 895 + static const struct dc_check_config config_defaults = { 896 896 + .enable_legacy_fast_update = true, 893 897 }; 894 898 895 899 static const struct dc_panel_config panel_config_defaults = { ··· 1943 1939 dc->caps.vbios_lttpr_aware = true; 1944 1940 } 1945 1941 } 1942 1942 + dc->check_config = config_defaults; 1946 1943 1947 1944 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1948 1945 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

reviewed

··· 882 882 .afmt = true, 883 883 } 884 884 }, 885 885 - .enable_legacy_fast_update = true, 886 885 .using_dml2 = false, 886 886 + }; 887 887 + 888 888 + static const struct dc_check_config config_defaults = { 889 889 + .enable_legacy_fast_update = true, 887 890 }; 888 891 889 892 static const struct dc_panel_config panel_config_defaults = { ··· 1818 1815 dc->caps.vbios_lttpr_aware = true; 1819 1816 } 1820 1817 } 1818 1818 + dc->check_config = config_defaults; 1821 1819 1822 1820 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1823 1821 dc->debug = debug_defaults_drv;

+6 -2

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

reviewed

··· 92 92 93 93 #include "dc_state_priv.h" 94 94 95 95 - #include "dml2/dml2_wrapper.h" 95 95 + #include "dml2_0/dml2_wrapper.h" 96 96 97 97 #define DC_LOGGER_INIT(logger) 98 98 ··· 738 738 .disable_dp_plus_plus_wa = true, 739 739 .fpo_vactive_min_active_margin_us = 200, 740 740 .fpo_vactive_max_blank_us = 1000, 741 741 - .enable_legacy_fast_update = false, 742 741 .disable_stutter_for_wm_program = true 742 742 + }; 743 743 + 744 744 + static const struct dc_check_config config_defaults = { 745 745 + .enable_legacy_fast_update = false, 743 746 }; 744 747 745 748 static struct dce_aux *dcn32_aux_engine_create( ··· 2297 2294 dc->caps.vbios_lttpr_aware = true; 2298 2295 } 2299 2296 } 2297 2297 + dc->check_config = config_defaults; 2300 2298 2301 2299 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2302 2300 dc->debug = debug_defaults_drv;

+5 -1

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

reviewed

··· 731 731 .disable_subvp_high_refresh = false, 732 732 .fpo_vactive_min_active_margin_us = 200, 733 733 .fpo_vactive_max_blank_us = 1000, 734 734 - .enable_legacy_fast_update = false, 735 734 .disable_dc_mode_overwrite = true, 736 735 .using_dml2 = false, 736 736 + }; 737 737 + 738 738 + static const struct dc_check_config config_defaults = { 739 739 + .enable_legacy_fast_update = false, 737 740 }; 738 741 739 742 static struct dce_aux *dcn321_aux_engine_create( ··· 1800 1797 dc->caps.vbios_lttpr_aware = true; 1801 1798 } 1802 1799 } 1800 1800 + dc->check_config = config_defaults; 1803 1801 1804 1802 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1805 1803 dc->debug = debug_defaults_drv;

+6 -2

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

reviewed

··· 33 33 #include "resource.h" 34 34 #include "include/irq_service_interface.h" 35 35 #include "dcn35_resource.h" 36 36 - #include "dml2/dml2_wrapper.h" 36 36 + #include "dml2_0/dml2_wrapper.h" 37 37 38 38 #include "dcn20/dcn20_resource.h" 39 39 #include "dcn30/dcn30_resource.h" ··· 767 767 .using_dml2 = true, 768 768 .support_eDP1_5 = true, 769 769 .enable_hpo_pg_support = false, 770 770 - .enable_legacy_fast_update = true, 771 770 .enable_single_display_2to1_odm_policy = true, 772 771 .disable_idle_power_optimizations = false, 773 772 .dmcub_emulation = false, ··· 785 786 .static_screen_wait_frames = 2, 786 787 .disable_timeout = true, 787 788 .min_disp_clk_khz = 50000, 789 789 + }; 790 790 + 791 791 + static const struct dc_check_config config_defaults = { 792 792 + .enable_legacy_fast_update = true, 788 793 }; 789 794 790 795 static const struct dc_panel_config panel_config_defaults = { ··· 1949 1946 dc->caps.vbios_lttpr_aware = true; 1950 1947 } 1951 1948 } 1949 1949 + dc->check_config = config_defaults; 1952 1950 1953 1951 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1954 1952 dc->debug = debug_defaults_drv;

+6 -2

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

reviewed

··· 83 83 #include "vm_helper.h" 84 84 #include "dcn20/dcn20_vmid.h" 85 85 86 86 - #include "dml2/dml2_wrapper.h" 86 86 + #include "dml2_0/dml2_wrapper.h" 87 87 88 88 #include "link_enc_cfg.h" 89 89 #define DC_LOGGER_INIT(logger) ··· 747 747 .using_dml2 = true, 748 748 .support_eDP1_5 = true, 749 749 .enable_hpo_pg_support = false, 750 750 - .enable_legacy_fast_update = true, 751 750 .enable_single_display_2to1_odm_policy = true, 752 751 .disable_idle_power_optimizations = false, 753 752 .dmcub_emulation = false, ··· 765 766 .static_screen_wait_frames = 2, 766 767 .notify_dpia_hr_bw = true, 767 768 .min_disp_clk_khz = 50000, 769 769 + }; 770 770 + 771 771 + static const struct dc_check_config config_defaults = { 772 772 + .enable_legacy_fast_update = true, 768 773 }; 769 774 770 775 static const struct dc_panel_config panel_config_defaults = { ··· 1920 1917 dc->caps.vbios_lttpr_aware = true; 1921 1918 } 1922 1919 } 1920 1920 + dc->check_config = config_defaults; 1923 1921 1924 1922 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1925 1923 dc->debug = debug_defaults_drv;

+6 -2

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

reviewed

··· 11 11 #include "resource.h" 12 12 #include "include/irq_service_interface.h" 13 13 #include "dcn36_resource.h" 14 14 - #include "dml2/dml2_wrapper.h" 14 14 + #include "dml2_0/dml2_wrapper.h" 15 15 16 16 #include "dcn20/dcn20_resource.h" 17 17 #include "dcn30/dcn30_resource.h" ··· 748 748 .using_dml2 = true, 749 749 .support_eDP1_5 = true, 750 750 .enable_hpo_pg_support = false, 751 751 - .enable_legacy_fast_update = true, 752 751 .enable_single_display_2to1_odm_policy = true, 753 752 .disable_idle_power_optimizations = false, 754 753 .dmcub_emulation = false, ··· 766 767 .static_screen_wait_frames = 2, 767 768 .disable_timeout = true, 768 769 .min_disp_clk_khz = 50000, 770 770 + }; 771 771 + 772 772 + static const struct dc_check_config config_defaults = { 773 773 + .enable_legacy_fast_update = true, 769 774 }; 770 775 771 776 static const struct dc_panel_config panel_config_defaults = { ··· 1921 1918 dc->caps.vbios_lttpr_aware = true; 1922 1919 } 1923 1920 } 1921 1921 + dc->check_config = config_defaults; 1924 1922 1925 1923 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1926 1924 dc->debug = debug_defaults_drv;

+6 -2

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

reviewed

··· 73 73 74 74 #include "dc_state_priv.h" 75 75 76 76 - #include "dml2/dml2_wrapper.h" 76 76 + #include "dml2_0/dml2_wrapper.h" 77 77 78 78 #define DC_LOGGER_INIT(logger) 79 79 ··· 721 721 .alloc_extra_way_for_cursor = true, 722 722 .min_prefetch_in_strobe_ns = 60000, // 60us 723 723 .disable_unbounded_requesting = false, 724 724 - .enable_legacy_fast_update = false, 725 724 .dcc_meta_propagation_delay_us = 10, 726 725 .fams_version = { 727 726 .minor = 1, ··· 734 735 } 735 736 }, 736 737 .force_cositing = CHROMA_COSITING_NONE + 1, 738 738 + }; 739 739 + 740 740 + static const struct dc_check_config config_defaults = { 741 741 + .enable_legacy_fast_update = false, 737 742 }; 738 743 739 744 static struct dce_aux *dcn401_aux_engine_create( ··· 1998 1995 dc->caps.vbios_lttpr_aware = true; 1999 1996 } 2000 1997 } 1998 1998 + dc->check_config = config_defaults; 2001 1999 2002 2000 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2003 2001 dc->debug = debug_defaults_drv;

+1 -1

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

reviewed

··· 9 9 #include "dc.h" 10 10 #include "clk_mgr.h" 11 11 #include "soc_and_ip_translator.h" 12 12 - #include "dml2/dml21/inc/dml_top_soc_parameter_types.h" 12 12 + #include "dml2_0/dml21/inc/dml_top_soc_parameter_types.h" 13 13 14 14 void dcn401_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator); 15 15

+25

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

reviewed

··· 363 363 uint8_t is_pwait : 1; 364 364 }; 365 365 366 366 + /** 367 367 + * struct dmub_preos_info - preos fw info before loading post os fw. 368 368 + */ 369 369 + struct dmub_preos_info { 370 370 + uint64_t fb_base; 371 371 + uint64_t fb_offset; 372 372 + uint64_t trace_buffer_phy_addr; 373 373 + uint32_t trace_buffer_size; 374 374 + uint32_t fw_version; 375 375 + uint32_t boot_status; 376 376 + uint32_t boot_options; 377 377 + }; 378 378 + 366 379 struct dmub_srv_inbox { 367 380 /* generic status */ 368 381 uint64_t num_submitted; ··· 501 488 uint32_t (*get_current_time)(struct dmub_srv *dmub); 502 489 503 490 void (*get_diagnostic_data)(struct dmub_srv *dmub); 491 491 + bool (*get_preos_fw_info)(struct dmub_srv *dmub); 504 492 505 493 bool (*should_detect)(struct dmub_srv *dmub); 506 494 void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx); ··· 602 588 enum dmub_srv_power_state_type power_state; 603 589 struct dmub_diagnostic_data debug; 604 590 struct dmub_fb lsdma_rb_fb; 591 591 + struct dmub_preos_info preos_info; 605 592 }; 606 593 607 594 /** ··· 1087 1072 * DMUB_STATUS_INVALID - unspecified error 1088 1073 */ 1089 1074 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub); 1075 1075 + 1076 1076 + /** 1077 1077 + * dmub_srv_get_preos_info() - retrieves preos fw info 1078 1078 + * @dmub: the dmub service 1079 1079 + * 1080 1080 + * Return: 1081 1081 + * true - preos fw info retrieved successfully 1082 1082 + * false - preos fw info not retrieved successfully 1083 1083 + */ 1084 1084 + bool dmub_srv_get_preos_info(struct dmub_srv *dmub); 1090 1085 1091 1086 #endif /* _DMUB_SRV_H_ */

+9 -3

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

reviewed

··· 485 485 */ 486 486 uint32_t enable_visual_confirm_debug : 1; 487 487 488 488 - uint32_t reserved : 18; 488 488 + /** 489 489 + * 0x4000 (bit 14) 490 490 + * @debug_log_enabled: Debug Log Enabled 491 491 + */ 492 492 + uint32_t debug_log_enabled : 1; 493 493 + 494 494 + uint32_t reserved : 17; 489 495 } bitfields; 490 496 491 497 uint32_t u32All; ··· 4614 4608 */ 4615 4609 uint16_t coasting_vtotal_high; 4616 4610 /** 4617 4617 - * Explicit padding to 4 byte boundary. 4611 4611 + * frame skip number. 4618 4612 */ 4619 4619 - uint8_t pad[2]; 4613 4613 + uint16_t frame_skip_number; 4620 4614 }; 4621 4615 4622 4616 /**

+31 -19

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

reviewed

··· 89 89 void dmub_dcn32_reset(struct dmub_srv *dmub) 90 90 { 91 91 union dmub_gpint_data_register cmd; 92 92 - const uint32_t timeout = 100000; 93 93 - uint32_t in_reset, is_enabled, scratch, i, pwait_mode; 92 92 + const uint32_t timeout_us = 1 * 1000 * 1000; //1s 93 93 + const uint32_t poll_delay_us = 1; //1us 94 94 + uint32_t i = 0; 95 95 + uint32_t enabled, in_reset, scratch, pwait_mode; 94 96 95 95 - REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); 96 96 - REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); 97 97 + REG_GET(DMCUB_CNTL, 98 98 + DMCUB_ENABLE, &enabled); 99 99 + REG_GET(DMCUB_CNTL2, 100 100 + DMCUB_SOFT_RESET, &in_reset); 97 101 98 98 - if (in_reset == 0 && is_enabled != 0) { 102 102 + if (enabled && in_reset == 0) { 99 103 cmd.bits.status = 1; 100 104 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 101 105 cmd.bits.param = 0; 102 106 103 107 dmub->hw_funcs.set_gpint(dmub, cmd); 104 108 105 105 - for (i = 0; i < timeout; ++i) { 106 106 - if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) 107 107 - break; 108 108 - 109 109 - udelay(1); 110 110 - } 111 111 - 112 112 - for (i = 0; i < timeout; ++i) { 109 109 + for (; i < timeout_us; i++) { 113 110 scratch = REG_READ(DMCUB_SCRATCH7); 114 111 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 115 112 break; 116 113 117 117 - udelay(1); 114 114 + udelay(poll_delay_us); 118 115 } 119 116 120 120 - for (i = 0; i < timeout; ++i) { 117 117 + for (; i < timeout_us; i++) { 121 118 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); 122 119 if (pwait_mode & (1 << 0)) 123 120 break; 124 121 125 125 - udelay(1); 122 122 + udelay(poll_delay_us); 126 123 } 127 127 - /* Force reset in case we timed out, DMCUB is likely hung. */ 128 124 } 129 125 130 130 - if (is_enabled) { 126 126 + if (enabled) { 131 127 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 132 128 udelay(1); 133 129 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 134 130 } 131 131 + 132 132 + if (i >= timeout_us) { 133 133 + /* timeout should never occur */ 134 134 + BREAK_TO_DEBUGGER(); 135 135 + } 136 136 + 137 137 + REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0); 138 138 + REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0); 139 139 + REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0); 140 140 + REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0); 141 141 + REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0); 142 142 + REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0); 135 143 136 144 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 137 145 REG_WRITE(DMCUB_INBOX1_WPTR, 0); ··· 149 141 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 150 142 REG_WRITE(DMCUB_SCRATCH0, 0); 151 143 152 152 - /* Clear the GPINT command manually so we don't send anything during boot. */ 144 144 + /* Clear the GPINT command manually so we don't reset again. */ 153 145 cmd.all = 0; 154 146 dmub->hw_funcs.set_gpint(dmub, cmd); 155 147 } ··· 171 163 172 164 dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset); 173 165 166 166 + /* reset and disable DMCUB and MMHUBBUB DMUIF */ 174 167 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 168 168 + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 175 169 176 170 dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 177 171 ··· 203 193 { 204 194 union dmub_addr offset; 205 195 196 196 + /* reset and disable DMCUB and MMHUBBUB DMUIF */ 206 197 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 198 198 + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 207 199 208 200 offset = cw0->offset; 209 201

+39

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

reviewed

··· 521 521 522 522 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 523 523 } 524 524 + 525 525 + bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub) 526 526 + { 527 527 + uint64_t region3_cw5_offset; 528 528 + uint32_t top_addr, top_addr_enable, offset_low; 529 529 + uint32_t offset_high, base_addr, fw_version; 530 530 + bool is_vbios_fw = false; 531 531 + 532 532 + memset(&dmub->preos_info, 0, sizeof(dmub->preos_info)); 533 533 + 534 534 + fw_version = REG_READ(DMCUB_SCRATCH1); 535 535 + is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false; 536 536 + if (!is_vbios_fw) 537 537 + return false; 538 538 + 539 539 + dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0); 540 540 + dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1); 541 541 + dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14); 542 542 + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, 543 543 + DMCUB_REGION3_CW5_ENABLE, &top_addr_enable); 544 544 + if (top_addr_enable) { 545 545 + dmub_dcn35_get_fb_base_offset(dmub, 546 546 + &dmub->preos_info.fb_base, &dmub->preos_info.fb_offset); 547 547 + offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET); 548 548 + offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH); 549 549 + region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low; 550 550 + dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset 551 551 + - dmub->preos_info.fb_base + dmub->preos_info.fb_offset; 552 552 + 553 553 + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, 554 554 + DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr); 555 555 + base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF; 556 556 + dmub->preos_info.trace_buffer_size = 557 557 + (top_addr > base_addr) ? (top_addr - base_addr + 1) : 0; 558 558 + } 559 559 + 560 560 + return true; 561 561 + } 562 562 + 524 563 void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub) 525 564 { 526 565 /* DMCUB_REGION3_TMR_AXI_SPACE values:

+2

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

reviewed

··· 285 285 286 286 void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); 287 287 288 288 + bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub); 289 289 + 288 290 #endif /* _DMUB_DCN35_H_ */

+14 -3

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

reviewed

··· 81 81 dmub->hw_funcs.set_gpint(dmub, cmd); 82 82 83 83 for (; i < timeout_us; i++) { 84 84 - scratch = dmub->hw_funcs.get_gpint_response(dmub); 84 84 + scratch = REG_READ(DMCUB_SCRATCH7); 85 85 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 86 86 break; 87 87 ··· 97 97 } 98 98 } 99 99 100 100 + if (enabled) { 101 101 + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 102 102 + udelay(1); 103 103 + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 104 104 + } 105 105 + 100 106 if (i >= timeout_us) { 101 107 /* timeout should never occur */ 102 108 BREAK_TO_DEBUGGER(); 103 109 } 110 110 + 111 111 + REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0); 112 112 + REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0); 113 113 + REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0); 114 114 + REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0); 115 115 + REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0); 116 116 + REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0); 104 117 105 118 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 106 119 REG_WRITE(DMCUB_INBOX1_WPTR, 0); ··· 147 134 148 135 /* reset and disable DMCUB and MMHUBBUB DMUIF */ 149 136 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 150 150 - REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 151 137 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 152 138 153 139 dmub_dcn401_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); ··· 180 168 181 169 /* reset and disable DMCUB and MMHUBBUB DMUIF */ 182 170 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 183 183 - REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 184 171 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 185 172 186 173 offset = cw0->offset;

+9

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

reviewed

··· 359 359 360 360 funcs->get_current_time = dmub_dcn35_get_current_time; 361 361 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 362 362 + funcs->get_preos_fw_info = dmub_dcn35_get_preos_fw_info; 362 363 363 364 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 364 365 if (asic == DMUB_ASIC_DCN351) ··· 1372 1371 dmub_srv_update_reg_inbox0_status(dmub); 1373 1372 1374 1373 return DMUB_STATUS_OK; 1374 1374 + } 1375 1375 + 1376 1376 + bool dmub_srv_get_preos_info(struct dmub_srv *dmub) 1377 1377 + { 1378 1378 + if (!dmub || !dmub->hw_funcs.get_preos_fw_info) 1379 1379 + return false; 1380 1380 + 1381 1381 + return dmub->hw_funcs.get_preos_fw_info(dmub); 1375 1382 }

+6 -5

drivers/gpu/drm/amd/display/include/bios_parser_types.h

reviewed

··· 135 135 struct bp_crtc_source_select { 136 136 enum engine_id engine_id; 137 137 enum controller_id controller_id; 138 138 - /* from GPU Tx aka asic_signal */ 139 139 - enum signal_type signal; 140 140 - /* sink_signal may differ from asicSignal if Translator encoder */ 141 138 enum signal_type sink_signal; 142 142 - enum display_output_bit_depth display_output_bit_depth; 143 143 - bool enable_dp_audio; 139 139 + uint8_t bit_depth; 144 140 }; 145 141 146 142 struct bp_transmitter_control { ··· 160 164 bool coherent; 161 165 bool multi_path; 162 166 bool single_pll_mode; 167 167 + }; 168 168 + 169 169 + struct bp_load_detection_parameters { 170 170 + enum engine_id engine_id; 171 171 + uint16_t device_id; 163 172 }; 164 173 165 174 struct bp_hw_crtc_timing_parameters {

+1

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

reviewed

··· 169 169 uint32_t engine_clk_ss_percentage; 170 170 } feature; 171 171 172 172 + uint32_t max_pixel_clock; /* in KHz */ 172 173 uint32_t default_display_engine_pll_frequency; /* in KHz */ 173 174 uint32_t external_clock_source_frequency_for_dp; /* in KHz */ 174 175 uint32_t smu_gpu_pll_output_freq; /* in KHz */

+7

drivers/gpu/drm/amd/display/include/grph_object_id.h

reviewed

··· 310 310 } 311 311 return false; 312 312 } 313 313 + 314 314 + static inline bool dc_connector_supports_analog(const enum connector_id conn) 315 315 + { 316 316 + return conn == CONNECTOR_ID_VGA || 317 317 + conn == CONNECTOR_ID_SINGLE_LINK_DVII || 318 318 + conn == CONNECTOR_ID_DUAL_LINK_DVII; 319 319 + } 313 320 #endif

+12

drivers/gpu/drm/amd/display/include/signal_types.h

reviewed

··· 118 118 } 119 119 } 120 120 121 121 + /** 122 122 + * dc_is_rgb_signal() - Whether the signal is analog RGB. 123 123 + * 124 124 + * Returns whether the given signal type is an analog RGB signal 125 125 + * that is used with a DAC on VGA or DVI-I connectors. 126 126 + * Not to be confused with other uses of "RGB", such as RGB color space. 127 127 + */ 128 128 + static inline bool dc_is_rgb_signal(enum signal_type signal) 129 129 + { 130 130 + return (signal == SIGNAL_TYPE_RGB); 131 131 + } 132 132 + 121 133 static inline bool dc_is_tmds_signal(enum signal_type signal) 122 134 { 123 135 switch (signal) {

+1 -1

drivers/gpu/drm/amd/include/amd_cper.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 */ 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 /* 3 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 4 *

+1 -1

drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 */ 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 3 3 /* 4 4 * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved.

+117

drivers/gpu/drm/amd/include/kgd_pp_interface.h

reviewed

··· 532 532 uint8_t content_revision; 533 533 }; 534 534 535 535 + enum amdgpu_metrics_attr_id { 536 536 + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT, 537 537 + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM, 538 538 + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC, 539 539 + AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER, 540 540 + AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY, 541 541 + AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY, 542 542 + AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH, 543 543 + AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR, 544 544 + AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER, 545 545 + AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER, 546 546 + AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC, 547 547 + AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC, 548 548 + AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC, 549 549 + AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC, 550 550 + AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC, 551 551 + AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS, 552 552 + AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH, 553 553 + AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED, 554 554 + AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH, 555 555 + AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED, 556 556 + AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC, 557 557 + AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC, 558 558 + AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC, 559 559 + AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST, 560 560 + AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC, 561 561 + AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC, 562 562 + AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC, 563 563 + AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC, 564 564 + AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC, 565 565 + AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC, 566 566 + AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC, 567 567 + AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS, 568 568 + AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP, 569 569 + AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK, 570 570 + AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK, 571 571 + AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0, 572 572 + AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0, 573 573 + AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK, 574 574 + AMDGPU_METRICS_ATTR_ID_NUM_PARTITION, 575 575 + AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY, 576 576 + AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST, 577 577 + AMDGPU_METRICS_ATTR_ID_JPEG_BUSY, 578 578 + AMDGPU_METRICS_ATTR_ID_VCN_BUSY, 579 579 + AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC, 580 580 + AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC, 581 581 + AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, 582 582 + AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, 583 583 + AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, 584 584 + AMDGPU_METRICS_ATTR_ID_MAX, 585 585 + }; 586 586 + 587 587 + enum amdgpu_metrics_attr_type { 588 588 + AMDGPU_METRICS_TYPE_U8, 589 589 + AMDGPU_METRICS_TYPE_S8, 590 590 + AMDGPU_METRICS_TYPE_U16, 591 591 + AMDGPU_METRICS_TYPE_S16, 592 592 + AMDGPU_METRICS_TYPE_U32, 593 593 + AMDGPU_METRICS_TYPE_S32, 594 594 + AMDGPU_METRICS_TYPE_U64, 595 595 + AMDGPU_METRICS_TYPE_S64, 596 596 + AMDGPU_METRICS_TYPE_MAX, 597 597 + }; 598 598 + 599 599 + enum amdgpu_metrics_attr_unit { 600 600 + /* None */ 601 601 + AMDGPU_METRICS_UNIT_NONE, 602 602 + /* MHz*/ 603 603 + AMDGPU_METRICS_UNIT_CLOCK_1, 604 604 + /* Degree Celsius*/ 605 605 + AMDGPU_METRICS_UNIT_TEMP_1, 606 606 + /* Watts*/ 607 607 + AMDGPU_METRICS_UNIT_POWER_1, 608 608 + /* In nanoseconds*/ 609 609 + AMDGPU_METRICS_UNIT_TIME_1, 610 610 + /* In 10 nanoseconds*/ 611 611 + AMDGPU_METRICS_UNIT_TIME_2, 612 612 + /* Speed in GT/s */ 613 613 + AMDGPU_METRICS_UNIT_SPEED_1, 614 614 + /* Speed in 0.1 GT/s */ 615 615 + AMDGPU_METRICS_UNIT_SPEED_2, 616 616 + /* Bandwidth GB/s */ 617 617 + AMDGPU_METRICS_UNIT_BW_1, 618 618 + /* Data in KB */ 619 619 + AMDGPU_METRICS_UNIT_DATA_1, 620 620 + /* Percentage */ 621 621 + AMDGPU_METRICS_UNIT_PERCENT, 622 622 + AMDGPU_METRICS_UNIT_MAX, 623 623 + }; 624 624 + 625 625 + #define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000 626 626 + #define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24 627 627 + #define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000 628 628 + #define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20 629 629 + #define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00 630 630 + #define AMDGPU_METRICS_ATTR_ID_SHIFT 10 631 631 + #define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF 632 632 + #define AMDGPU_METRICS_ATTR_INST_SHIFT 0 633 633 + 634 634 + #define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \ 635 635 + (((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \ 636 636 + ((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \ 637 637 + ((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst)) 638 638 + 535 639 /* 536 640 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 537 641 * Use gpu_metrics_v1_1 or later instead. ··· 1323 1219 1324 1220 /* PCIE other end recovery counter */ 1325 1221 uint32_t pcie_lc_perf_other_end_recovery; 1222 1222 + }; 1223 1223 + 1224 1224 + struct gpu_metrics_attr { 1225 1225 + /* Field type encoded with AMDGPU_METRICS_ENC_ATTR */ 1226 1226 + uint64_t attr_encoding; 1227 1227 + /* Attribute value, depends on attr_encoding */ 1228 1228 + void *attr_value; 1229 1229 + }; 1230 1230 + 1231 1231 + struct gpu_metrics_v1_9 { 1232 1232 + struct metrics_table_header common_header; 1233 1233 + int attr_count; 1234 1234 + struct gpu_metrics_attr metrics_attrs[]; 1326 1235 }; 1327 1236 1328 1237 /*

-1

drivers/gpu/drm/amd/pm/amdgpu_pm.c

reviewed

··· 174 174 */ 175 175 static inline void amdgpu_pm_put_access(struct amdgpu_device *adev) 176 176 { 177 177 - pm_runtime_mark_last_busy(adev->dev); 178 177 pm_runtime_put_autosuspend(adev->dev); 179 178 } 180 179

+1 -1

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

reviewed

··· 2024 2024 table->VoltageResponseTime = 0; 2025 2025 table->PhaseResponseTime = 0; 2026 2026 table->MemoryThermThrottleEnable = 1; 2027 2027 - table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ 2027 2027 + table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); 2028 2028 table->PCIeGenInterval = 1; 2029 2029 table->VRConfig = 0; 2030 2030

+1 -1

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

reviewed

··· 2028 2028 table->VoltageResponseTime = 0; 2029 2029 table->PhaseResponseTime = 0; 2030 2030 table->MemoryThermThrottleEnable = 1; 2031 2031 - table->PCIeBootLinkLevel = 0; 2031 2031 + table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); 2032 2032 table->PCIeGenInterval = 1; 2033 2033 2034 2034 result = iceland_populate_smc_svi2_config(hwmgr, table);

+2 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

reviewed

··· 450 450 ((pgm == 4) && (fw_ver >= 0x4557000))) 451 451 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); 452 452 453 453 - if ((pgm == 0) && (fw_ver >= 0x00558200)) 453 453 + if ((pgm == 0 && fw_ver >= 0x00558200) || 454 454 + (pgm == 7 && fw_ver >= 0x07551400)) 454 455 smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); 455 456 } 456 457

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

reviewed

··· 969 969 table_index); 970 970 uint32_t table_size; 971 971 int ret = 0; 972 972 - if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0) 972 972 + if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) 973 973 return -EINVAL; 974 974 975 975 table_size = smu_table->tables[table_index].size;

-1

drivers/gpu/drm/radeon/radeon_acpi.c

reviewed

··· 408 408 pm_runtime_get_sync(rdev_to_drm(rdev)->dev); 409 409 /* Just fire off a uevent and let userspace tell us what to do */ 410 410 drm_helper_hpd_irq_event(rdev_to_drm(rdev)); 411 411 - pm_runtime_mark_last_busy(rdev_to_drm(rdev)->dev); 412 411 pm_runtime_put_autosuspend(rdev_to_drm(rdev)->dev); 413 412 } 414 413 }

+5 -15

drivers/gpu/drm/radeon/radeon_connectors.c

reviewed

··· 875 875 876 876 radeon_connector_update_scratch_regs(connector, ret); 877 877 878 878 - if (!drm_kms_helper_is_poll_worker()) { 879 879 - pm_runtime_mark_last_busy(connector->dev->dev); 878 878 + if (!drm_kms_helper_is_poll_worker()) 880 879 pm_runtime_put_autosuspend(connector->dev->dev); 881 881 - } 882 880 883 881 return ret; 884 882 } ··· 1064 1066 radeon_connector_update_scratch_regs(connector, ret); 1065 1067 1066 1068 out: 1067 1067 - if (!drm_kms_helper_is_poll_worker()) { 1068 1068 - pm_runtime_mark_last_busy(connector->dev->dev); 1069 1069 + if (!drm_kms_helper_is_poll_worker()) 1069 1070 pm_runtime_put_autosuspend(connector->dev->dev); 1070 1070 - } 1071 1071 1072 1072 return ret; 1073 1073 } ··· 1150 1154 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false); 1151 1155 radeon_connector_update_scratch_regs(connector, ret); 1152 1156 1153 1153 - if (!drm_kms_helper_is_poll_worker()) { 1154 1154 - pm_runtime_mark_last_busy(connector->dev->dev); 1157 1157 + if (!drm_kms_helper_is_poll_worker()) 1155 1158 pm_runtime_put_autosuspend(connector->dev->dev); 1156 1156 - } 1157 1159 1158 1160 return ret; 1159 1161 } ··· 1396 1402 } 1397 1403 1398 1404 exit: 1399 1399 - if (!drm_kms_helper_is_poll_worker()) { 1400 1400 - pm_runtime_mark_last_busy(connector->dev->dev); 1405 1405 + if (!drm_kms_helper_is_poll_worker()) 1401 1406 pm_runtime_put_autosuspend(connector->dev->dev); 1402 1402 - } 1403 1407 1404 1408 return ret; 1405 1409 } ··· 1706 1714 } 1707 1715 1708 1716 out: 1709 1709 - if (!drm_kms_helper_is_poll_worker()) { 1710 1710 - pm_runtime_mark_last_busy(connector->dev->dev); 1717 1717 + if (!drm_kms_helper_is_poll_worker()) 1711 1718 pm_runtime_put_autosuspend(connector->dev->dev); 1712 1712 - } 1713 1719 1714 1720 return ret; 1715 1721 }

-2

drivers/gpu/drm/radeon/radeon_display.c

reviewed

··· 644 644 if (crtc->enabled) 645 645 active = true; 646 646 647 647 - pm_runtime_mark_last_busy(dev->dev); 648 648 - 649 647 rdev = dev->dev_private; 650 648 /* if we have active crtcs and we don't have a power ref, 651 649 take the current one */

+9 -27

drivers/gpu/drm/radeon/radeon_drv.c

reviewed

··· 262 262 unsigned long flags = 0; 263 263 struct drm_device *ddev; 264 264 struct radeon_device *rdev; 265 265 + struct device *dev = &pdev->dev; 265 266 const struct drm_format_info *format; 266 267 int ret; 267 268 ··· 278 277 case CHIP_VERDE: 279 278 case CHIP_OLAND: 280 279 case CHIP_HAINAN: 281 281 - dev_info(&pdev->dev, 280 280 + dev_info(dev, 282 281 "SI support disabled by module param\n"); 283 282 return -ENODEV; 284 283 } ··· 290 289 case CHIP_HAWAII: 291 290 case CHIP_KABINI: 292 291 case CHIP_MULLINS: 293 293 - dev_info(&pdev->dev, 292 292 + dev_info(dev, 294 293 "CIK support disabled by module param\n"); 295 294 return -ENODEV; 296 295 } ··· 304 303 if (ret) 305 304 return ret; 306 305 307 307 - rdev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*rdev), ddev); 306 306 + rdev = devm_drm_dev_alloc(dev, &kms_driver, typeof(*rdev), ddev); 308 307 if (IS_ERR(rdev)) 309 308 return PTR_ERR(rdev); 310 309 311 311 - rdev->dev = &pdev->dev; 310 310 + rdev->dev = dev; 312 311 rdev->pdev = pdev; 313 312 ddev = rdev_to_drm(rdev); 314 313 ddev->dev_private = rdev; 315 314 316 315 ret = pci_enable_device(pdev); 317 316 if (ret) 318 318 - goto err_free; 317 317 + return ret; 319 318 320 319 pci_set_drvdata(pdev, ddev); 321 320 322 321 ret = radeon_driver_load_kms(ddev, flags); 323 322 if (ret) 324 324 - goto err_agp; 323 323 + goto err; 325 324 326 325 ret = drm_dev_register(ddev, flags); 327 326 if (ret) 328 328 - goto err_agp; 327 327 + goto err; 329 328 330 329 if (rdev->mc.real_vram_size <= (8 * 1024 * 1024)) 331 330 format = drm_format_info(DRM_FORMAT_C8); ··· 338 337 339 338 return 0; 340 339 341 341 - err_agp: 340 340 + err: 342 341 pci_disable_device(pdev); 343 343 - err_free: 344 344 - drm_dev_put(ddev); 345 342 return ret; 346 346 - } 347 347 - 348 348 - static void 349 349 - radeon_pci_remove(struct pci_dev *pdev) 350 350 - { 351 351 - struct drm_device *dev = pci_get_drvdata(pdev); 352 352 - 353 353 - drm_put_dev(dev); 354 343 } 355 344 356 345 static void 357 346 radeon_pci_shutdown(struct pci_dev *pdev) 358 347 { 359 359 - /* if we are running in a VM, make sure the device 360 360 - * torn down properly on reboot/shutdown 361 361 - */ 362 362 - if (radeon_device_is_virtual()) 363 363 - radeon_pci_remove(pdev); 364 364 - 365 348 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) 366 349 /* 367 350 * Some adapters need to be suspended before a ··· 462 477 } 463 478 } 464 479 465 465 - pm_runtime_mark_last_busy(dev); 466 480 pm_runtime_autosuspend(dev); 467 481 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 468 482 return 1; ··· 483 499 484 500 ret = drm_ioctl(filp, cmd, arg); 485 501 486 486 - pm_runtime_mark_last_busy(dev->dev); 487 502 pm_runtime_put_autosuspend(dev->dev); 488 503 return ret; 489 504 } ··· 596 613 .name = DRIVER_NAME, 597 614 .id_table = pciidlist, 598 615 .probe = radeon_pci_probe, 599 599 - .remove = radeon_pci_remove, 600 616 .shutdown = radeon_pci_shutdown, 601 617 .driver.pm = &radeon_pm_ops, 602 618 };

-2

drivers/gpu/drm/radeon/radeon_fbdev.c

reviewed

··· 154 154 return 0; 155 155 156 156 err_pm_runtime_mark_last_busy: 157 157 - pm_runtime_mark_last_busy(rdev_to_drm(rdev)->dev); 158 157 pm_runtime_put_autosuspend(rdev_to_drm(rdev)->dev); 159 158 return ret; 160 159 } ··· 163 164 struct drm_fb_helper *fb_helper = info->par; 164 165 struct radeon_device *rdev = fb_helper->dev->dev_private; 165 166 166 166 - pm_runtime_mark_last_busy(rdev_to_drm(rdev)->dev); 167 167 pm_runtime_put_autosuspend(rdev_to_drm(rdev)->dev); 168 168 169 169 return 0;

-5

drivers/gpu/drm/radeon/radeon_kms.c

reviewed

··· 84 84 rdev->agp = NULL; 85 85 86 86 done_free: 87 87 - kfree(rdev); 88 87 dev->dev_private = NULL; 89 88 } 90 89 ··· 169 170 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 170 171 pm_runtime_set_active(dev->dev); 171 172 pm_runtime_allow(dev->dev); 172 172 - pm_runtime_mark_last_busy(dev->dev); 173 173 pm_runtime_put_autosuspend(dev->dev); 174 174 } 175 175 ··· 675 677 file_priv->driver_priv = fpriv; 676 678 } 677 679 678 678 - pm_runtime_mark_last_busy(dev->dev); 679 680 pm_runtime_put_autosuspend(dev->dev); 680 681 return 0; 681 682 ··· 684 687 kfree(fpriv); 685 688 686 689 err_suspend: 687 687 - pm_runtime_mark_last_busy(dev->dev); 688 690 pm_runtime_put_autosuspend(dev->dev); 689 691 return r; 690 692 } ··· 733 737 kfree(fpriv); 734 738 file_priv->driver_priv = NULL; 735 739 } 736 736 - pm_runtime_mark_last_busy(dev->dev); 737 740 pm_runtime_put_autosuspend(dev->dev); 738 741 } 739 742