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drm/amdgpu/pm: Fix the param type of set_power_profile_mode

Function .set_power_profile_mode need an array as input
parameter. So define variable workload as an array to fix
the below coverity warning.

"Passing &workload to function hwmgr->hwmgr_func->set_power_profile_mode
which uses it as an array. This might corrupt or misinterpret adjacent
memory locations"

Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Ma Jun and committed by
Alex Deucher
f683f240 0991e49d

+16 -16
+4 -4
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
··· 929 929 enum PP_SMC_POWER_PROFILE type, bool en) 930 930 { 931 931 struct pp_hwmgr *hwmgr = handle; 932 - long workload; 932 + long workload[1]; 933 933 uint32_t index; 934 934 935 935 if (!hwmgr || !hwmgr->pm_en) ··· 947 947 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); 948 948 index = fls(hwmgr->workload_mask); 949 949 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0; 950 - workload = hwmgr->workload_setting[index]; 950 + workload[0] = hwmgr->workload_setting[index]; 951 951 } else { 952 952 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); 953 953 index = fls(hwmgr->workload_mask); 954 954 index = index <= Workload_Policy_Max ? index - 1 : 0; 955 - workload = hwmgr->workload_setting[index]; 955 + workload[0] = hwmgr->workload_setting[index]; 956 956 } 957 957 958 958 if (type == PP_SMC_POWER_PROFILE_COMPUTE && ··· 962 962 } 963 963 964 964 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 965 - hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0); 965 + hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0); 966 966 967 967 return 0; 968 968 }
+4 -4
drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
··· 269 269 struct pp_power_state *new_ps) 270 270 { 271 271 uint32_t index; 272 - long workload; 272 + long workload[1]; 273 273 274 274 if (hwmgr->not_vf) { 275 275 if (!skip_display_settings) ··· 294 294 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 295 295 index = fls(hwmgr->workload_mask); 296 296 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0; 297 - workload = hwmgr->workload_setting[index]; 297 + workload[0] = hwmgr->workload_setting[index]; 298 298 299 - if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode) 300 - hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0); 299 + if (hwmgr->power_profile_mode != workload[0] && hwmgr->hwmgr_func->set_power_profile_mode) 300 + hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0); 301 301 } 302 302 303 303 return 0;
+8 -8
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 2210 2210 { 2211 2211 int ret = 0; 2212 2212 int index = 0; 2213 - long workload; 2213 + long workload[1]; 2214 2214 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2215 2215 2216 2216 if (!skip_display_settings) { ··· 2250 2250 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2251 2251 index = fls(smu->workload_mask); 2252 2252 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2253 - workload = smu->workload_setting[index]; 2253 + workload[0] = smu->workload_setting[index]; 2254 2254 2255 - if (smu->power_profile_mode != workload) 2256 - smu_bump_power_profile_mode(smu, &workload, 0); 2255 + if (smu->power_profile_mode != workload[0]) 2256 + smu_bump_power_profile_mode(smu, workload, 0); 2257 2257 } 2258 2258 2259 2259 return ret; ··· 2303 2303 { 2304 2304 struct smu_context *smu = handle; 2305 2305 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2306 - long workload; 2306 + long workload[1]; 2307 2307 uint32_t index; 2308 2308 2309 2309 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) ··· 2316 2316 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2317 2317 index = fls(smu->workload_mask); 2318 2318 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2319 - workload = smu->workload_setting[index]; 2319 + workload[0] = smu->workload_setting[index]; 2320 2320 } else { 2321 2321 smu->workload_mask |= (1 << smu->workload_prority[type]); 2322 2322 index = fls(smu->workload_mask); 2323 2323 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2324 - workload = smu->workload_setting[index]; 2324 + workload[0] = smu->workload_setting[index]; 2325 2325 } 2326 2326 2327 2327 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2328 2328 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2329 - smu_bump_power_profile_mode(smu, &workload, 0); 2329 + smu_bump_power_profile_mode(smu, workload, 0); 2330 2330 2331 2331 return 0; 2332 2332 }