Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-4.9-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
"Fixes marked for stable:
- fix system reset interrupt winkle wakeups
- fix setting of AIL in hypervisor mode
Fixes for code merged this cycle:
- fix exception vector build with 2.23 era binutils
- fix missing update of HID register on secondary CPUs
Other:
- fix missing pr_cont()s
- invalidate ERAT on tlbiel for POWER9 DD1"
* tag 'powerpc-4.9-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/mm: Fix missing update of HID register on secondary CPUs
powerpc/mm/radix: Invalidate ERAT on tlbiel for POWER9 DD1
powerpc/64: Fix setting of AIL in hypervisor mode
powerpc/oops: Fix missing pr_cont()s in instruction dump
powerpc/oops: Fix missing pr_cont()s in show_regs()
powerpc/oops: Fix missing pr_cont()s in print_msr_bits() et. al.
powerpc/oops: Fix missing pr_cont()s in show_stack()
powerpc: Fix exception vector build with 2.23 era binutils
powerpc/64s: Fix system reset interrupt winkle wakeups
+68
-33
+12
-3
arch/powerpc/include/asm/exception-64s.h
+12
-3
arch/powerpc/include/asm/exception-64s.h
···
91
91
*/
92
92
#define LOAD_HANDLER(reg, label) \
93
93
ld reg,PACAKBASE(r13); /* get high part of &label */ \
94
-
ori reg,reg,(FIXED_SYMBOL_ABS_ADDR(label))@l;
94
+
ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label);
95
95
96
96
#define __LOAD_HANDLER(reg, label) \
97
97
ld reg,PACAKBASE(r13); \
···
158
158
std ra,offset(r13); \
159
159
END_FTR_SECTION_NESTED(ftr,ftr,943)
160
160
161
-
#define EXCEPTION_PROLOG_0(area) \
162
-
GET_PACA(r13); \
161
+
#define EXCEPTION_PROLOG_0_PACA(area) \
163
162
std r9,area+EX_R9(r13); /* save r9 */ \
164
163
OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
165
164
HMT_MEDIUM; \
166
165
std r10,area+EX_R10(r13); /* save r10 - r12 */ \
167
166
OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
167
+
168
+
#define EXCEPTION_PROLOG_0(area) \
169
+
GET_PACA(r13); \
170
+
EXCEPTION_PROLOG_0_PACA(area)
168
171
169
172
#define __EXCEPTION_PROLOG_1(area, extra, vec) \
170
173
OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
···
196
193
197
194
#define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \
198
195
EXCEPTION_PROLOG_0(area); \
196
+
EXCEPTION_PROLOG_1(area, extra, vec); \
197
+
EXCEPTION_PROLOG_PSERIES_1(label, h);
198
+
199
+
/* Have the PACA in r13 already */
200
+
#define EXCEPTION_PROLOG_PSERIES_PACA(area, label, h, extra, vec) \
201
+
EXCEPTION_PROLOG_0_PACA(area); \
199
202
EXCEPTION_PROLOG_1(area, extra, vec); \
200
203
EXCEPTION_PROLOG_PSERIES_1(label, h);
201
204
+1
arch/powerpc/include/asm/ppc-opcode.h
+1
arch/powerpc/include/asm/ppc-opcode.h
+8
-3
arch/powerpc/kernel/exceptions-64s.S
+8
-3
arch/powerpc/kernel/exceptions-64s.S
···
116
116
117
117
EXC_REAL_BEGIN(system_reset, 0x100, 0x200)
118
118
SET_SCRATCH0(r13)
119
-
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
119
+
GET_PACA(r13)
120
+
clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */
121
+
EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD,
120
122
IDLETEST, 0x100)
121
123
122
124
EXC_REAL_END(system_reset, 0x100, 0x200)
···
126
124
127
125
#ifdef CONFIG_PPC_P7_NAP
128
126
EXC_COMMON_BEGIN(system_reset_idle_common)
127
+
BEGIN_FTR_SECTION
128
+
GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */
129
+
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
129
130
bl pnv_restore_hyp_resource
130
131
131
132
li r0,PNV_THREAD_RUNNING
···
174
169
SET_SCRATCH0(r13) /* save r13 */
175
170
/*
176
171
* Running native on arch 2.06 or later, we may wakeup from winkle
177
-
* inside machine check. If yes, then last bit of HSPGR0 would be set
172
+
* inside machine check. If yes, then last bit of HSPRG0 would be set
178
173
* to 1. Hence clear it unconditionally.
179
174
*/
180
175
GET_PACA(r13)
···
393
388
/*
394
389
* Go back to winkle. Please note that this thread was woken up in
395
390
* machine check from winkle and have not restored the per-subcore
396
-
* state. Hence before going back to winkle, set last bit of HSPGR0
391
+
* state. Hence before going back to winkle, set last bit of HSPRG0
397
392
* to 1. This will make sure that if this thread gets woken up
398
393
* again at reset vector 0x100 then it will get chance to restore
399
394
* the subcore state.
+21
-21
arch/powerpc/kernel/process.c
+21
-21
arch/powerpc/kernel/process.c
···
1215
1215
int instr;
1216
1216
1217
1217
if (!(i % 8))
1218
-
printk("\n");
1218
+
pr_cont("\n");
1219
1219
1220
1220
#if !defined(CONFIG_BOOKE)
1221
1221
/* If executing with the IMMU off, adjust pc rather
···
1227
1227
1228
1228
if (!__kernel_text_address(pc) ||
1229
1229
probe_kernel_address((unsigned int __user *)pc, instr)) {
1230
-
printk(KERN_CONT "XXXXXXXX ");
1230
+
pr_cont("XXXXXXXX ");
1231
1231
} else {
1232
1232
if (regs->nip == pc)
1233
-
printk(KERN_CONT "<%08x> ", instr);
1233
+
pr_cont("<%08x> ", instr);
1234
1234
else
1235
-
printk(KERN_CONT "%08x ", instr);
1235
+
pr_cont("%08x ", instr);
1236
1236
}
1237
1237
1238
1238
pc += sizeof(int);
1239
1239
}
1240
1240
1241
-
printk("\n");
1241
+
pr_cont("\n");
1242
1242
}
1243
1243
1244
1244
struct regbit {
···
1282
1282
1283
1283
for (; bits->bit; ++bits)
1284
1284
if (val & bits->bit) {
1285
-
printk("%s%s", s, bits->name);
1285
+
pr_cont("%s%s", s, bits->name);
1286
1286
s = sep;
1287
1287
}
1288
1288
}
···
1305
1305
* T: Transactional (bit 34)
1306
1306
*/
1307
1307
if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1308
-
printk(",TM[");
1308
+
pr_cont(",TM[");
1309
1309
print_bits(val, msr_tm_bits, "");
1310
-
printk("]");
1310
+
pr_cont("]");
1311
1311
}
1312
1312
}
1313
1313
#else
···
1316
1316
1317
1317
static void print_msr_bits(unsigned long val)
1318
1318
{
1319
-
printk("<");
1319
+
pr_cont("<");
1320
1320
print_bits(val, msr_bits, ",");
1321
1321
print_tm_bits(val);
1322
-
printk(">");
1322
+
pr_cont(">");
1323
1323
}
1324
1324
1325
1325
#ifdef CONFIG_PPC64
···
1347
1347
printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1348
1348
trap = TRAP(regs);
1349
1349
if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1350
-
printk("CFAR: "REG" ", regs->orig_gpr3);
1350
+
pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1351
1351
if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1352
1352
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1353
-
printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1353
+
pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1354
1354
#else
1355
-
printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1355
+
pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1356
1356
#endif
1357
1357
#ifdef CONFIG_PPC64
1358
-
printk("SOFTE: %ld ", regs->softe);
1358
+
pr_cont("SOFTE: %ld ", regs->softe);
1359
1359
#endif
1360
1360
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1361
1361
if (MSR_TM_ACTIVE(regs->msr))
1362
-
printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1362
+
pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1363
1363
#endif
1364
1364
1365
1365
for (i = 0; i < 32; i++) {
1366
1366
if ((i % REGS_PER_LINE) == 0)
1367
-
printk("\nGPR%02d: ", i);
1368
-
printk(REG " ", regs->gpr[i]);
1367
+
pr_cont("\nGPR%02d: ", i);
1368
+
pr_cont(REG " ", regs->gpr[i]);
1369
1369
if (i == LAST_VOLATILE && !FULL_REGS(regs))
1370
1370
break;
1371
1371
}
1372
-
printk("\n");
1372
+
pr_cont("\n");
1373
1373
#ifdef CONFIG_KALLSYMS
1374
1374
/*
1375
1375
* Lookup NIP late so we have the best change of getting the
···
1900
1900
printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1901
1901
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1902
1902
if ((ip == rth) && curr_frame >= 0) {
1903
-
printk(" (%pS)",
1903
+
pr_cont(" (%pS)",
1904
1904
(void *)current->ret_stack[curr_frame].ret);
1905
1905
curr_frame--;
1906
1906
}
1907
1907
#endif
1908
1908
if (firstframe)
1909
-
printk(" (unreliable)");
1910
-
printk("\n");
1909
+
pr_cont(" (unreliable)");
1910
+
pr_cont("\n");
1911
1911
}
1912
1912
firstframe = 0;
1913
1913
+14
-6
arch/powerpc/kernel/setup_64.c
+14
-6
arch/powerpc/kernel/setup_64.c
···
226
226
if (firmware_has_feature(FW_FEATURE_OPAL))
227
227
opal_configure_cores();
228
228
229
-
/* Enable AIL if supported, and we are in hypervisor mode */
230
-
if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
231
-
early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
232
-
unsigned long lpcr = mfspr(SPRN_LPCR);
233
-
mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
234
-
}
229
+
/* AIL on native is done in cpu_ready_for_interrupts() */
235
230
}
236
231
}
237
232
238
233
static void cpu_ready_for_interrupts(void)
239
234
{
235
+
/*
236
+
* Enable AIL if supported, and we are in hypervisor mode. This
237
+
* is called once for every processor.
238
+
*
239
+
* If we are not in hypervisor mode the job is done once for
240
+
* the whole partition in configure_exceptions().
241
+
*/
242
+
if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
243
+
early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
244
+
unsigned long lpcr = mfspr(SPRN_LPCR);
245
+
mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
246
+
}
247
+
240
248
/* Set IR and DR in PACA MSR */
241
249
get_paca()->kernel_msr = MSR_KERNEL;
242
250
}
+4
arch/powerpc/mm/hash_utils_64.c
+4
arch/powerpc/mm/hash_utils_64.c
···
1029
1029
{
1030
1030
/* Initialize hash table for that CPU */
1031
1031
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1032
+
1033
+
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
1034
+
update_hid_for_hash();
1035
+
1032
1036
if (!cpu_has_feature(CPU_FTR_ARCH_300))
1033
1037
mtspr(SPRN_SDR1, _SDR1);
1034
1038
else
+4
arch/powerpc/mm/pgtable-radix.c
+4
arch/powerpc/mm/pgtable-radix.c
···
388
388
* update partition table control register and UPRT
389
389
*/
390
390
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
391
+
392
+
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
393
+
update_hid_for_radix();
394
+
391
395
lpcr = mfspr(SPRN_LPCR);
392
396
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
393
397
+4
arch/powerpc/mm/tlb-radix.c
+4
arch/powerpc/mm/tlb-radix.c
···
50
50
for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
51
51
__tlbiel_pid(pid, set, ric);
52
52
}
53
+
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
54
+
asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
53
55
return;
54
56
}
55
57
···
85
83
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
86
84
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
87
85
asm volatile("ptesync": : :"memory");
86
+
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
87
+
asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
88
88
}
89
89
90
90
static inline void _tlbie_va(unsigned long va, unsigned long pid,