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ARM: dts: r9a06g032: Fill the UART DMA properties

UART 0 to 2 do not have DMA support, while UART 3 to 7 do.

Fill the "dmas" and "dma-names" properties for each of these nodes.

Please mind that these nodes go through the dmamux node which will
redirect the requests to the right DMA controller. The first 4 cells of
the "dmas" properties will be transferred as-is to the DMA
controllers. The last 2 cells are consumed by the dmamux. Which means
cell 0 and 4 are almost redundant, one giving the controller request ID
and the other the dmamux channel which is a 1:1 translation of the
request IDs, shifted by 16 when pointing to the second DMA controller.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20220421095323.101811-11-miquel.raynal@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Miquel Raynal and committed by
Geert Uytterhoeven f691d4b6 6002e2f1

+10
+10
arch/arm/boot/dts/r9a06g032.dtsi
··· 145 145 reg-io-width = <4>; 146 146 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; 147 147 clock-names = "baudclk", "apb_pclk"; 148 + dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; 149 + dma-names = "rx", "tx"; 148 150 status = "disabled"; 149 151 }; 150 152 ··· 158 156 reg-io-width = <4>; 159 157 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; 160 158 clock-names = "baudclk", "apb_pclk"; 159 + dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; 160 + dma-names = "rx", "tx"; 161 161 status = "disabled"; 162 162 }; 163 163 ··· 171 167 reg-io-width = <4>; 172 168 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; 173 169 clock-names = "baudclk", "apb_pclk"; 170 + dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; 171 + dma-names = "rx", "tx"; 174 172 status = "disabled"; 175 173 }; 176 174 ··· 184 178 reg-io-width = <4>; 185 179 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; 186 180 clock-names = "baudclk", "apb_pclk"; 181 + dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; 182 + dma-names = "rx", "tx"; 187 183 status = "disabled"; 188 184 }; 189 185 ··· 197 189 reg-io-width = <4>; 198 190 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; 199 191 clock-names = "baudclk", "apb_pclk"; 192 + dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; 193 + dma-names = "rx", "tx"; 200 194 status = "disabled"; 201 195 }; 202 196