tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2019-08-30' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Nothing too crazy, there's probably more patches than I'd like at this
stage, but they are all pretty self contained:

amdgpu:
- Fix GFXOFF regression for PCO and RV2
- Fix missing fence reference
- Fix VG20 power readings on certain SMU firmware versions
- Fix dpm level setup for VG20
- Add an ATPX laptop quirk

i915:
- Fix DP MST max BPC property creation after DRM register
- Fix unused ggtt deballooning and NULL dereference in guest
- Fix DSC eDP transcoder identification
- Fix WARN from DMA API debug by setting DMA max segment size

qxl:
- Make qxl reservel the vga ports using vgaargb to prevent switching to vga compatibility mode.

omap:
- Fix omap port lookup for SDI output

virtio:
- Use virtio_max_dma_size to fix an issue with swiotlb.

komeda:
- Compiler fixes to komeda.
- Add missing of_node_get() call in komeda.
- Reorder the komeda de-init functions"

* tag 'drm-fixes-2019-08-30' of git://anongit.freedesktop.org/drm/drm:
drm/komeda: Reordered the komeda's de-init functions
drm/amdgpu: fix GFXOFF on Picasso and Raven2
drm/amdgpu: Add APTX quirk for Dell Latitude 5495
drm/amd/powerplay: correct Vega20 dpm level related settings
drm/i915: Call dma_set_max_seg_size() in i915_driver_hw_probe()
drm/i915/dp: Fix DSC enable code to use cpu_transcoder instead of encoder->type
drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest
drm/i915: Do not create a new max_bpc prop for MST connectors
drm/powerplay: Fix Vega20 power reading again
drm/powerplay: Fix Vega20 Average Power value v4
drm/amdgpu: fix dma_fence_wait without reference
drm/komeda: Add missing of_node_get() call
drm/komeda: Clean warning 'komeda_component_add' might be a candidate for 'gnu_printf'
drm/komeda: Fix warning -Wunused-but-set-variable
drm/komeda: Fix error: not allocating enough data 1592 vs 1584
drm/virtio: use virtio_max_dma_size
drm/omap: Fix port lookup for SDI output
drm/qxl: get vga ioports

Linus Torvalds f69f1992 26538100

+161 -47
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
··· 574 574 { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX }, 575 575 { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX }, 576 576 { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX }, 577 + { 0x1002, 0x699f, 0x1028, 0x0814, AMDGPU_PX_QUIRK_FORCE_ATPX }, 577 578 { 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX }, 578 579 { 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX }, 579 580 { 0, 0, 0, 0, 0 },
+15 -12
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
··· 534 534 struct drm_sched_entity *entity) 535 535 { 536 536 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 537 - unsigned idx = centity->sequence & (amdgpu_sched_jobs - 1); 538 - struct dma_fence *other = centity->fences[idx]; 537 + struct dma_fence *other; 538 + unsigned idx; 539 + long r; 539 540 540 - if (other) { 541 - signed long r; 542 - r = dma_fence_wait(other, true); 543 - if (r < 0) { 544 - if (r != -ERESTARTSYS) 545 - DRM_ERROR("Error (%ld) waiting for fence!\n", r); 541 + spin_lock(&ctx->ring_lock); 542 + idx = centity->sequence & (amdgpu_sched_jobs - 1); 543 + other = dma_fence_get(centity->fences[idx]); 544 + spin_unlock(&ctx->ring_lock); 546 545 547 - return r; 548 - } 549 - } 546 + if (!other) 547 + return 0; 550 548 551 - return 0; 549 + r = dma_fence_wait(other, true); 550 + if (r < 0 && r != -ERESTARTSYS) 551 + DRM_ERROR("Error (%ld) waiting for fence!\n", r); 552 + 553 + dma_fence_put(other); 554 + return r; 552 555 } 553 556 554 557 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
+7 -7
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 596 596 case CHIP_VEGA20: 597 597 break; 598 598 case CHIP_RAVEN: 599 - if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) 600 - break; 601 - if ((adev->gfx.rlc_fw_version != 106 && 602 - adev->gfx.rlc_fw_version < 531) || 603 - (adev->gfx.rlc_fw_version == 53815) || 604 - (adev->gfx.rlc_feature_version < 1) || 605 - !adev->gfx.rlc.is_rlc_v2_1) 599 + if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) 600 + &&((adev->gfx.rlc_fw_version != 106 && 601 + adev->gfx.rlc_fw_version < 531) || 602 + (adev->gfx.rlc_fw_version == 53815) || 603 + (adev->gfx.rlc_feature_version < 1) || 604 + !adev->gfx.rlc.is_rlc_v2_1)) 606 605 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 606 + 607 607 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 608 608 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 609 609 AMD_PG_SUPPORT_CP |
+59 -7
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
··· 2101 2101 if (ret) 2102 2102 return ret; 2103 2103 2104 - *query = metrics_table.CurrSocketPower << 8; 2104 + /* For the 40.46 release, they changed the value name */ 2105 + if (hwmgr->smu_version == 0x282e00) 2106 + *query = metrics_table.AverageSocketPower << 8; 2107 + else 2108 + *query = metrics_table.CurrSocketPower << 8; 2105 2109 2106 2110 return ret; 2107 2111 } ··· 2353 2349 data->dpm_table.soc_table.dpm_state.soft_max_level = 2354 2350 data->dpm_table.soc_table.dpm_levels[soft_level].value; 2355 2351 2356 - ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); 2352 + ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2353 + FEATURE_DPM_UCLK_MASK | 2354 + FEATURE_DPM_SOCCLK_MASK); 2357 2355 PP_ASSERT_WITH_CODE(!ret, 2358 2356 "Failed to upload boot level to highest!", 2359 2357 return ret); 2360 2358 2361 - ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF); 2359 + ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2360 + FEATURE_DPM_UCLK_MASK | 2361 + FEATURE_DPM_SOCCLK_MASK); 2362 2362 PP_ASSERT_WITH_CODE(!ret, 2363 2363 "Failed to upload dpm max level to highest!", 2364 2364 return ret); ··· 2395 2387 data->dpm_table.soc_table.dpm_state.soft_max_level = 2396 2388 data->dpm_table.soc_table.dpm_levels[soft_level].value; 2397 2389 2398 - ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); 2390 + ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2391 + FEATURE_DPM_UCLK_MASK | 2392 + FEATURE_DPM_SOCCLK_MASK); 2399 2393 PP_ASSERT_WITH_CODE(!ret, 2400 2394 "Failed to upload boot level to highest!", 2401 2395 return ret); 2402 2396 2403 - ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF); 2397 + ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2398 + FEATURE_DPM_UCLK_MASK | 2399 + FEATURE_DPM_SOCCLK_MASK); 2404 2400 PP_ASSERT_WITH_CODE(!ret, 2405 2401 "Failed to upload dpm max level to highest!", 2406 2402 return ret); ··· 2415 2403 2416 2404 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 2417 2405 { 2406 + struct vega20_hwmgr *data = 2407 + (struct vega20_hwmgr *)(hwmgr->backend); 2408 + uint32_t soft_min_level, soft_max_level; 2418 2409 int ret = 0; 2419 2410 2420 - ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); 2411 + /* gfxclk soft min/max settings */ 2412 + soft_min_level = 2413 + vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 2414 + soft_max_level = 2415 + vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 2416 + 2417 + data->dpm_table.gfx_table.dpm_state.soft_min_level = 2418 + data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 2419 + data->dpm_table.gfx_table.dpm_state.soft_max_level = 2420 + data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2421 + 2422 + /* uclk soft min/max settings */ 2423 + soft_min_level = 2424 + vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 2425 + soft_max_level = 2426 + vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); 2427 + 2428 + data->dpm_table.mem_table.dpm_state.soft_min_level = 2429 + data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2430 + data->dpm_table.mem_table.dpm_state.soft_max_level = 2431 + data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2432 + 2433 + /* socclk soft min/max settings */ 2434 + soft_min_level = 2435 + vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 2436 + soft_max_level = 2437 + vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); 2438 + 2439 + data->dpm_table.soc_table.dpm_state.soft_min_level = 2440 + data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2441 + data->dpm_table.soc_table.dpm_state.soft_max_level = 2442 + data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2443 + 2444 + ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2445 + FEATURE_DPM_UCLK_MASK | 2446 + FEATURE_DPM_SOCCLK_MASK); 2421 2447 PP_ASSERT_WITH_CODE(!ret, 2422 2448 "Failed to upload DPM Bootup Levels!", 2423 2449 return ret); 2424 2450 2425 - ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF); 2451 + ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2452 + FEATURE_DPM_UCLK_MASK | 2453 + FEATURE_DPM_SOCCLK_MASK); 2426 2454 PP_ASSERT_WITH_CODE(!ret, 2427 2455 "Failed to upload DPM Max Levels!", 2428 2456 return ret);
+10 -1
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
··· 3050 3050 3051 3051 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value) 3052 3052 { 3053 + uint32_t smu_version; 3053 3054 int ret = 0; 3054 3055 SmuMetrics_t metrics; 3055 3056 ··· 3061 3060 if (ret) 3062 3061 return ret; 3063 3062 3064 - *value = metrics.CurrSocketPower << 8; 3063 + ret = smu_get_smc_version(smu, NULL, &smu_version); 3064 + if (ret) 3065 + return ret; 3066 + 3067 + /* For the 40.46 release, they changed the value name */ 3068 + if (smu_version == 0x282e00) 3069 + *value = metrics.AverageSocketPower << 8; 3070 + else 3071 + *value = metrics.CurrSocketPower << 8; 3065 3072 3066 3073 return 0; 3067 3074 }
+1 -1
drivers/gpu/drm/arm/display/komeda/komeda_dev.c
··· 127 127 pipe->of_output_port = 128 128 of_graph_get_port_by_id(np, KOMEDA_OF_PORT_OUTPUT); 129 129 130 - pipe->of_node = np; 130 + pipe->of_node = of_node_get(np); 131 131 132 132 return 0; 133 133 }
+17 -12
drivers/gpu/drm/arm/display/komeda/komeda_kms.c
··· 14 14 #include <drm/drm_gem_cma_helper.h> 15 15 #include <drm/drm_gem_framebuffer_helper.h> 16 16 #include <drm/drm_irq.h> 17 - #include <drm/drm_vblank.h> 18 17 #include <drm/drm_probe_helper.h> 18 + #include <drm/drm_vblank.h> 19 19 20 20 #include "komeda_dev.h" 21 21 #include "komeda_framebuffer.h" ··· 147 147 struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_st); 148 148 struct komeda_plane_state *kplane_st; 149 149 struct drm_plane_state *plane_st; 150 - struct drm_framebuffer *fb; 151 150 struct drm_plane *plane; 152 151 struct list_head zorder_list; 153 152 int order = 0, err; ··· 172 173 173 174 list_for_each_entry(kplane_st, &zorder_list, zlist_node) { 174 175 plane_st = &kplane_st->base; 175 - fb = plane_st->fb; 176 176 plane = plane_st->plane; 177 177 178 178 plane_st->normalized_zpos = order++; ··· 204 206 struct drm_atomic_state *state) 205 207 { 206 208 struct drm_crtc *crtc; 207 - struct drm_crtc_state *old_crtc_st, *new_crtc_st; 209 + struct drm_crtc_state *new_crtc_st; 208 210 int i, err; 209 211 210 212 err = drm_atomic_helper_check_modeset(dev, state); ··· 215 217 * so need to add all affected_planes (even unchanged) to 216 218 * drm_atomic_state. 217 219 */ 218 - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_st, new_crtc_st, i) { 220 + for_each_new_crtc_in_state(state, crtc, new_crtc_st, i) { 219 221 err = drm_atomic_add_affected_planes(state, crtc); 220 222 if (err) 221 223 return err; ··· 306 308 komeda_kms_irq_handler, IRQF_SHARED, 307 309 drm->driver->name, drm); 308 310 if (err) 309 - goto cleanup_mode_config; 311 + goto free_component_binding; 310 312 311 313 err = mdev->funcs->enable_irq(mdev); 312 314 if (err) 313 - goto cleanup_mode_config; 315 + goto free_component_binding; 314 316 315 317 drm->irq_enabled = true; 316 318 ··· 318 320 319 321 err = drm_dev_register(drm, 0); 320 322 if (err) 321 - goto cleanup_mode_config; 323 + goto free_interrupts; 322 324 323 325 return kms; 324 326 325 - cleanup_mode_config: 327 + free_interrupts: 326 328 drm_kms_helper_poll_fini(drm); 327 329 drm->irq_enabled = false; 330 + mdev->funcs->disable_irq(mdev); 331 + free_component_binding: 332 + component_unbind_all(mdev->dev, drm); 333 + cleanup_mode_config: 328 334 drm_mode_config_cleanup(drm); 329 335 komeda_kms_cleanup_private_objs(kms); 336 + drm->dev_private = NULL; 337 + drm_dev_put(drm); 330 338 free_kms: 331 339 kfree(kms); 332 340 return ERR_PTR(err); ··· 343 339 struct drm_device *drm = &kms->base; 344 340 struct komeda_dev *mdev = drm->dev_private; 345 341 346 - drm->irq_enabled = false; 347 - mdev->funcs->disable_irq(mdev); 348 342 drm_dev_unregister(drm); 349 343 drm_kms_helper_poll_fini(drm); 344 + drm_atomic_helper_shutdown(drm); 345 + drm->irq_enabled = false; 346 + mdev->funcs->disable_irq(mdev); 350 347 component_unbind_all(mdev->dev, drm); 351 - komeda_kms_cleanup_private_objs(kms); 352 348 drm_mode_config_cleanup(drm); 349 + komeda_kms_cleanup_private_objs(kms); 353 350 drm->dev_private = NULL; 354 351 drm_dev_put(drm); 355 352 }
+1
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
··· 480 480 struct seq_file *sf); 481 481 482 482 /* component APIs */ 483 + extern __printf(10, 11) 483 484 struct komeda_component * 484 485 komeda_component_add(struct komeda_pipeline *pipe, 485 486 size_t comp_sz, u32 id, u32 hw_id,
+1 -1
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
··· 148 148 if (!kcrtc->master->wb_layer) 149 149 return 0; 150 150 151 - kwb_conn = kzalloc(sizeof(*wb_conn), GFP_KERNEL); 151 + kwb_conn = kzalloc(sizeof(*kwb_conn), GFP_KERNEL); 152 152 if (!kwb_conn) 153 153 return -ENOMEM; 154 154
+9 -1
drivers/gpu/drm/i915/display/intel_dp_mst.c
··· 539 539 540 540 intel_attach_force_audio_property(connector); 541 541 intel_attach_broadcast_rgb_property(connector); 542 - drm_connector_attach_max_bpc_property(connector, 6, 12); 542 + 543 + /* 544 + * Reuse the prop from the SST connector because we're 545 + * not allowed to create new props after device registration. 546 + */ 547 + connector->max_bpc_property = 548 + intel_dp->attached_connector->base.max_bpc_property; 549 + if (connector->max_bpc_property) 550 + drm_connector_attach_max_bpc_property(connector, 6, 12); 543 551 544 552 return connector; 545 553
+1 -1
drivers/gpu/drm/i915/display/intel_vdsc.c
··· 541 541 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 542 542 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 543 543 DRM_INFO("PPS2 = 0x%08x\n", pps_val); 544 - if (encoder->type == INTEL_OUTPUT_EDP) { 544 + if (cpu_transcoder == TRANSCODER_EDP) { 545 545 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); 546 546 /* 547 547 * If 2 VDSC instances are needed, configure PPS for second
+6
drivers/gpu/drm/i915/i915_drv.c
··· 1598 1598 1599 1599 pci_set_master(pdev); 1600 1600 1601 + /* 1602 + * We don't have a max segment size, so set it to the max so sg's 1603 + * debugging layer doesn't complain 1604 + */ 1605 + dma_set_max_seg_size(&pdev->dev, UINT_MAX); 1606 + 1601 1607 /* overlay on gen2 is broken and can't address above 1G */ 1602 1608 if (IS_GEN(dev_priv, 2)) { 1603 1609 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
+3
drivers/gpu/drm/i915/i915_vgpu.c
··· 101 101 static void vgt_deballoon_space(struct i915_ggtt *ggtt, 102 102 struct drm_mm_node *node) 103 103 { 104 + if (!drm_mm_node_allocated(node)) 105 + return; 106 + 104 107 DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n", 105 108 node->start, 106 109 node->start + node->size,
+3 -1
drivers/gpu/drm/omapdrm/dss/output.c
··· 4 4 * Author: Archit Taneja <archit@ti.com> 5 5 */ 6 6 7 + #include <linux/bitops.h> 7 8 #include <linux/kernel.h> 8 9 #include <linux/module.h> 9 10 #include <linux/platform_device.h> ··· 21 20 { 22 21 struct device_node *remote_node; 23 22 24 - remote_node = of_graph_get_remote_node(out->dev->of_node, 0, 0); 23 + remote_node = of_graph_get_remote_node(out->dev->of_node, 24 + ffs(out->of_ports) - 1, 0); 25 25 if (!remote_node) { 26 26 dev_dbg(out->dev, "failed to find video sink\n"); 27 27 return 0;
+19 -1
drivers/gpu/drm/qxl/qxl_drv.c
··· 59 59 static struct drm_driver qxl_driver; 60 60 static struct pci_driver qxl_pci_driver; 61 61 62 + static bool is_vga(struct pci_dev *pdev) 63 + { 64 + return pdev->class == PCI_CLASS_DISPLAY_VGA << 8; 65 + } 66 + 62 67 static int 63 68 qxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 64 69 { ··· 88 83 if (ret) 89 84 goto disable_pci; 90 85 86 + if (is_vga(pdev)) { 87 + ret = vga_get_interruptible(pdev, VGA_RSRC_LEGACY_IO); 88 + if (ret) { 89 + DRM_ERROR("can't get legacy vga ioports\n"); 90 + goto disable_pci; 91 + } 92 + } 93 + 91 94 ret = qxl_device_init(qdev, &qxl_driver, pdev); 92 95 if (ret) 93 - goto disable_pci; 96 + goto put_vga; 94 97 95 98 ret = qxl_modeset_init(qdev); 96 99 if (ret) ··· 118 105 qxl_modeset_fini(qdev); 119 106 unload: 120 107 qxl_device_fini(qdev); 108 + put_vga: 109 + if (is_vga(pdev)) 110 + vga_put(pdev, VGA_RSRC_LEGACY_IO); 121 111 disable_pci: 122 112 pci_disable_device(pdev); 123 113 free_dev: ··· 138 122 139 123 qxl_modeset_fini(qdev); 140 124 qxl_device_fini(qdev); 125 + if (is_vga(pdev)) 126 + vga_put(pdev, VGA_RSRC_LEGACY_IO); 141 127 142 128 dev->dev_private = NULL; 143 129 kfree(qdev);
+8 -2
drivers/gpu/drm/virtio/virtgpu_object.c
··· 204 204 .interruptible = false, 205 205 .no_wait_gpu = false 206 206 }; 207 + size_t max_segment; 207 208 208 209 /* wtf swapping */ 209 210 if (bo->pages) ··· 216 215 if (!bo->pages) 217 216 goto out; 218 217 219 - ret = sg_alloc_table_from_pages(bo->pages, pages, nr_pages, 0, 220 - nr_pages << PAGE_SHIFT, GFP_KERNEL); 218 + max_segment = virtio_max_dma_size(qdev->vdev); 219 + max_segment &= PAGE_MASK; 220 + if (max_segment > SCATTERLIST_MAX_SEGMENT) 221 + max_segment = SCATTERLIST_MAX_SEGMENT; 222 + ret = __sg_alloc_table_from_pages(bo->pages, pages, nr_pages, 0, 223 + nr_pages << PAGE_SHIFT, 224 + max_segment, GFP_KERNEL); 221 225 if (ret) 222 226 goto out; 223 227 return 0;