tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: GPU vm support 5-level page table

If GPU supports 5-level page table, but CPU disable 5-level page table
by using boot option no5lvl or CPU feature not available, the virtual
address will be 48bit, not needed to enable 5-level page table on GPU
vm.

If adev->vm_manager.num_level, number of pde levels, set to 4, then
gfxhub and mmhub register VM_CONTEXTx_CNTL/PAGE_TABLE_DEPTH will set
to 4 to enable 5-level page table in page table walker.

Set vm_manager.root_level to AMDGPU_VM_PDE3, then update GPU mapping
will allocate and update PDE3/PDE2/PDE1/PDE0/PTB 5-level page tables.

If max_level is not 4, no change for the logic to support features
needed by old ASICs.

v2: squash in CONFIG fix

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Acked-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Philip Yang and committed by
Alex Deucher f6b1c1f5 bc5094e2

+23 -1
+20
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 2360 2360 unsigned max_bits) 2361 2361 { 2362 2362 unsigned int max_size = 1 << (max_bits - 30); 2363 + bool sys_5level_pgtable = false; 2363 2364 unsigned int vm_size; 2364 2365 uint64_t tmp; 2366 + 2367 + #ifdef CONFIG_X86_64 2368 + /* 2369 + * Refer to function configure_5level_paging() for details. 2370 + */ 2371 + sys_5level_pgtable = (native_read_cr4() & X86_CR4_LA57); 2372 + #endif 2373 + 2374 + /* 2375 + * If GPU supports 5-level page table, but system uses 4-level page table, 2376 + * then use 4-level page table on GPU 2377 + */ 2378 + if (max_level == 4 && !sys_5level_pgtable) { 2379 + min_vm_size = 256 * 1024; 2380 + max_level = 3; 2381 + } 2365 2382 2366 2383 /* adjust vm size first */ 2367 2384 if (amdgpu_vm_size != -1) { ··· 2422 2405 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; 2423 2406 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp); 2424 2407 switch (adev->vm_manager.num_level) { 2408 + case 4: 2409 + adev->vm_manager.root_level = AMDGPU_VM_PDB3; 2410 + break; 2425 2411 case 3: 2426 2412 adev->vm_manager.root_level = AMDGPU_VM_PDB2; 2427 2413 break;
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
··· 186 186 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 187 187 188 188 /* VMPT level enumerate, and the hiberachy is: 189 - * PDB2->PDB1->PDB0->PTB 189 + * PDB3->PDB2->PDB1->PDB0->PTB 190 190 */ 191 191 enum amdgpu_vm_level { 192 + AMDGPU_VM_PDB3, 192 193 AMDGPU_VM_PDB2, 193 194 AMDGPU_VM_PDB1, 194 195 AMDGPU_VM_PDB0,
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
··· 51 51 unsigned int level) 52 52 { 53 53 switch (level) { 54 + case AMDGPU_VM_PDB3: 54 55 case AMDGPU_VM_PDB2: 55 56 case AMDGPU_VM_PDB1: 56 57 case AMDGPU_VM_PDB0: