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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
watchdog: Add Watchdog Timer driver for RZ/V2H(P)
Add Watchdog Timer driver for RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20240829193831.80768-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
authored by
Lad Prabhakar
and committed by
Wim Van Sebroeck
f6febd0a
892067cd
+282
+9
drivers/watchdog/Kconfig
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drivers/watchdog/Kconfig
···
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This driver adds watchdog support for the integrated watchdogs in the
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Renesas RZ/G2L SoCs. These watchdogs can be used to reset a system.
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config RENESAS_RZV2HWDT
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tristate "Renesas RZ/V2H(P) WDT Watchdog"
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depends on ARCH_R9A09G057 || COMPILE_TEST
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depends on PM || COMPILE_TEST
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select WATCHDOG_CORE
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help
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This driver adds watchdog support for the integrated watchdogs in the
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Renesas RZ/V2H(P) SoCs. These watchdogs can be used to reset a system.
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config ASPEED_WATCHDOG
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tristate "Aspeed BMC watchdog support"
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depends on ARCH_ASPEED || COMPILE_TEST
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drivers/watchdog/Makefile
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drivers/watchdog/Makefile
···
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obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o
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obj-$(CONFIG_RENESAS_RZN1WDT) += rzn1_wdt.o
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obj-$(CONFIG_RENESAS_RZG2LWDT) += rzg2l_wdt.o
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obj-$(CONFIG_RENESAS_RZV2HWDT) += rzv2h_wdt.o
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obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
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obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
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obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o
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drivers/watchdog/rzv2h_wdt.c
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drivers/watchdog/rzv2h_wdt.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/V2H(P) WDT Watchdog Driver
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*
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* Copyright (C) 2024 Renesas Electronics Corporation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/units.h>
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#include <linux/watchdog.h>
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#define WDTRR 0x00 /* WDT Refresh Register RW, 8 */
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#define WDTCR 0x02 /* WDT Control Register RW, 16 */
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#define WDTSR 0x04 /* WDT Status Register RW, 16 */
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#define WDTRCR 0x06 /* WDT Reset Control Register RW, 8 */
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#define WDTCR_TOPS_1024 0x00
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#define WDTCR_TOPS_16384 0x03
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#define WDTCR_CKS_CLK_1 0x00
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#define WDTCR_CKS_CLK_256 0x50
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#define WDTCR_RPES_0 0x300
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#define WDTCR_RPES_75 0x000
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#define WDTCR_RPSS_25 0x00
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#define WDTCR_RPSS_100 0x3000
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#define WDTRCR_RSTIRQS BIT(7)
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#define MAX_TIMEOUT_CYCLES 16384
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#define CLOCK_DIV_BY_256 256
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#define WDT_DEFAULT_TIMEOUT 60U
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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struct rzv2h_wdt_priv {
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void __iomem *base;
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struct clk *pclk;
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struct clk *oscclk;
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struct reset_control *rstc;
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struct watchdog_device wdev;
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};
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static int rzv2h_wdt_ping(struct watchdog_device *wdev)
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{
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struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
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/*
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* The down-counter is refreshed and starts counting operation on
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* a write of the values 00h and FFh to the WDTRR register.
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*/
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writeb(0x0, priv->base + WDTRR);
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writeb(0xFF, priv->base + WDTRR);
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return 0;
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}
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static void rzv2h_wdt_setup(struct watchdog_device *wdev, u16 wdtcr)
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{
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struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
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/* Configure the timeout, clock division ratio, and window start and end positions. */
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writew(wdtcr, priv->base + WDTCR);
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/* Enable interrupt output to the ICU. */
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writeb(0, priv->base + WDTRCR);
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/* Clear underflow flag and refresh error flag. */
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writew(0, priv->base + WDTSR);
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}
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static int rzv2h_wdt_start(struct watchdog_device *wdev)
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{
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struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
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int ret;
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ret = pm_runtime_resume_and_get(wdev->parent);
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if (ret)
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return ret;
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ret = reset_control_deassert(priv->rstc);
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if (ret) {
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pm_runtime_put(wdev->parent);
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return ret;
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}
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/* delay to handle clock halt after de-assert operation */
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udelay(3);
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/*
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* WDTCR
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* - CKS[7:4] - Clock Division Ratio Select - 0101b: oscclk/256
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* - RPSS[13:12] - Window Start Position Select - 11b: 100%
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* - RPES[9:8] - Window End Position Select - 11b: 0%
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* - TOPS[1:0] - Timeout Period Select - 11b: 16384 cycles (3FFFh)
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*/
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rzv2h_wdt_setup(wdev, WDTCR_CKS_CLK_256 | WDTCR_RPSS_100 |
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WDTCR_RPES_0 | WDTCR_TOPS_16384);
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/*
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* Down counting starts after writing the sequence 00h -> FFh to the
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* WDTRR register. Hence, call the ping operation after loading the counter.
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*/
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rzv2h_wdt_ping(wdev);
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return 0;
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}
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static int rzv2h_wdt_stop(struct watchdog_device *wdev)
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{
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struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
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int ret;
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ret = reset_control_assert(priv->rstc);
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if (ret)
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return ret;
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ret = pm_runtime_put(wdev->parent);
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if (ret < 0)
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return ret;
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return 0;
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}
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static const struct watchdog_info rzv2h_wdt_ident = {
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.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
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.identity = "Renesas RZ/V2H WDT Watchdog",
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};
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static int rzv2h_wdt_restart(struct watchdog_device *wdev,
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unsigned long action, void *data)
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{
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struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
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int ret;
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if (!watchdog_active(wdev)) {
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ret = clk_enable(priv->pclk);
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if (ret)
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return ret;
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ret = clk_enable(priv->oscclk);
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if (ret) {
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clk_disable(priv->pclk);
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return ret;
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}
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ret = reset_control_deassert(priv->rstc);
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if (ret) {
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clk_disable(priv->oscclk);
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clk_disable(priv->pclk);
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return ret;
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}
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} else {
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/*
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* Writing to the WDT Control Register (WDTCR) or WDT Reset
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* Control Register (WDTRCR) is possible once between the
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* release from the reset state and the first refresh operation.
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* Therefore, issue a reset if the watchdog is active.
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*/
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ret = reset_control_reset(priv->rstc);
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if (ret)
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return ret;
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}
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/* delay to handle clock halt after de-assert operation */
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udelay(3);
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/*
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* WDTCR
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* - CKS[7:4] - Clock Division Ratio Select - 0000b: oscclk/1
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* - RPSS[13:12] - Window Start Position Select - 00b: 25%
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* - RPES[9:8] - Window End Position Select - 00b: 75%
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* - TOPS[1:0] - Timeout Period Select - 00b: 1024 cycles (03FFh)
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*/
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rzv2h_wdt_setup(wdev, WDTCR_CKS_CLK_1 | WDTCR_RPSS_25 |
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WDTCR_RPES_75 | WDTCR_TOPS_1024);
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rzv2h_wdt_ping(wdev);
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/* wait for underflow to trigger... */
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udelay(5);
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return 0;
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}
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static const struct watchdog_ops rzv2h_wdt_ops = {
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.owner = THIS_MODULE,
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.start = rzv2h_wdt_start,
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.stop = rzv2h_wdt_stop,
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.ping = rzv2h_wdt_ping,
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.restart = rzv2h_wdt_restart,
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};
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static int rzv2h_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rzv2h_wdt_priv *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->pclk = devm_clk_get_prepared(&pdev->dev, "pclk");
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if (IS_ERR(priv->pclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
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priv->oscclk = devm_clk_get_prepared(&pdev->dev, "oscclk");
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if (IS_ERR(priv->oscclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->oscclk), "no oscclk");
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priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(priv->rstc))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
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"failed to get cpg reset");
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priv->wdev.max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * CLOCK_DIV_BY_256) /
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clk_get_rate(priv->oscclk);
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dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);
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ret = devm_pm_runtime_enable(&pdev->dev);
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if (ret)
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return ret;
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priv->wdev.min_timeout = 1;
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priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
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priv->wdev.info = &rzv2h_wdt_ident;
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priv->wdev.ops = &rzv2h_wdt_ops;
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priv->wdev.parent = dev;
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watchdog_set_drvdata(&priv->wdev, priv);
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watchdog_set_nowayout(&priv->wdev, nowayout);
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watchdog_stop_on_unregister(&priv->wdev);
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ret = watchdog_init_timeout(&priv->wdev, 0, dev);
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if (ret)
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dev_warn(dev, "Specified timeout invalid, using default");
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return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
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}
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static const struct of_device_id rzv2h_wdt_ids[] = {
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{ .compatible = "renesas,r9a09g057-wdt", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rzv2h_wdt_ids);
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static struct platform_driver rzv2h_wdt_driver = {
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.driver = {
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.name = "rzv2h_wdt",
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.of_match_table = rzv2h_wdt_ids,
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},
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.probe = rzv2h_wdt_probe,
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};
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module_platform_driver(rzv2h_wdt_driver);
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MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
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MODULE_DESCRIPTION("Renesas RZ/V2H(P) WDT Watchdog Driver");