Merge tag 'amd-drm-next-6.15-2025-03-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

··· 189 189 .set_address_watch = kgd_gfx_aldebaran_set_address_watch, 190 190 .clear_address_watch = kgd_gfx_v9_clear_address_watch, 191 191 .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times, 192 - .build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info, 192 + .build_dequeue_wait_counts_packet_info = kgd_gfx_v9_build_dequeue_wait_counts_packet_info, 193 193 .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, 194 194 .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, 195 195 .hqd_reset = kgd_gfx_v9_hqd_reset,

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

··· 415 415 .set_address_watch = kgd_gfx_v9_set_address_watch, 416 416 .clear_address_watch = kgd_gfx_v9_clear_address_watch, 417 417 .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times, 418 - .build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info, 418 + .build_dequeue_wait_counts_packet_info = kgd_gfx_v9_build_dequeue_wait_counts_packet_info, 419 419 .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy, 420 420 .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, 421 421 .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

··· 541 541 .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy, 542 542 .program_trap_handler_settings = 543 543 kgd_gfx_v9_program_trap_handler_settings, 544 - .build_grace_period_packet_info = 545 - kgd_gfx_v9_build_grace_period_packet_info, 544 + .build_dequeue_wait_counts_packet_info = 545 + kgd_gfx_v9_build_dequeue_wait_counts_packet_info, 546 546 .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times, 547 547 .enable_debug_trap = kgd_aldebaran_enable_debug_trap, 548 548 .disable_debug_trap = kgd_gfx_v9_4_3_disable_debug_trap,

+14 -14

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

··· 1021 1021 *wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2)); 1022 1022 } 1023 1023 1024 - void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, 1024 + void kgd_gfx_v10_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev, 1025 1025 uint32_t wait_times, 1026 - uint32_t grace_period, 1026 + uint32_t sch_wave, 1027 + uint32_t que_sleep, 1027 1028 uint32_t *reg_offset, 1028 1029 uint32_t *reg_data) 1029 1030 { 1030 1031 *reg_data = wait_times; 1031 1032 1032 - /* 1033 - * The CP cannont handle a 0 grace period input and will result in 1034 - * an infinite grace period being set so set to 1 to prevent this. 1035 - */ 1036 - if (grace_period == 0) 1037 - grace_period = 1; 1038 - 1039 - *reg_data = REG_SET_FIELD(*reg_data, 1040 - CP_IQ_WAIT_TIME2, 1041 - SCH_WAVE, 1042 - grace_period); 1033 + if (sch_wave) 1034 + *reg_data = REG_SET_FIELD(*reg_data, 1035 + CP_IQ_WAIT_TIME2, 1036 + SCH_WAVE, 1037 + sch_wave); 1038 + if (que_sleep) 1039 + *reg_data = REG_SET_FIELD(*reg_data, 1040 + CP_IQ_WAIT_TIME2, 1041 + QUE_SLEEP, 1042 + que_sleep); 1043 1043 1044 1044 *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2); 1045 1045 } ··· 1115 1115 .set_address_watch = kgd_gfx_v10_set_address_watch, 1116 1116 .clear_address_watch = kgd_gfx_v10_clear_address_watch, 1117 1117 .get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times, 1118 - .build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info, 1118 + .build_dequeue_wait_counts_packet_info = kgd_gfx_v10_build_dequeue_wait_counts_packet_info, 1119 1119 .program_trap_handler_settings = program_trap_handler_settings, 1120 1120 .hqd_get_pq_addr = kgd_gfx_v10_hqd_get_pq_addr, 1121 1121 .hqd_reset = kgd_gfx_v10_hqd_reset,

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

··· 51 51 void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev, 52 52 uint32_t *wait_times, 53 53 uint32_t inst); 54 - void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, 54 + void kgd_gfx_v10_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev, 55 55 uint32_t wait_times, 56 - uint32_t grace_period, 56 + uint32_t sch_wave, 57 + uint32_t que_sleep, 57 58 uint32_t *reg_offset, 58 59 uint32_t *reg_data); 59 60 uint64_t kgd_gfx_v10_hqd_get_pq_addr(struct amdgpu_device *adev,

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

··· 673 673 .set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3, 674 674 .program_trap_handler_settings = program_trap_handler_settings_v10_3, 675 675 .get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times, 676 - .build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info, 676 + .build_dequeue_wait_counts_packet_info = kgd_gfx_v10_build_dequeue_wait_counts_packet_info, 677 677 .enable_debug_trap = kgd_gfx_v10_enable_debug_trap, 678 678 .disable_debug_trap = kgd_gfx_v10_disable_debug_trap, 679 679 .validate_trap_override_request = kgd_gfx_v10_validate_trap_override_request,

+14 -14

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

··· 1077 1077 adev->gfx.cu_info.max_waves_per_simd; 1078 1078 } 1079 1079 1080 - void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, 1080 + void kgd_gfx_v9_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev, 1081 1081 uint32_t wait_times, 1082 - uint32_t grace_period, 1082 + uint32_t sch_wave, 1083 + uint32_t que_sleep, 1083 1084 uint32_t *reg_offset, 1084 1085 uint32_t *reg_data) 1085 1086 { 1086 1087 *reg_data = wait_times; 1087 1088 1088 - /* 1089 - * The CP cannot handle a 0 grace period input and will result in 1090 - * an infinite grace period being set so set to 1 to prevent this. 1091 - */ 1092 - if (grace_period == 0) 1093 - grace_period = 1; 1094 - 1095 - *reg_data = REG_SET_FIELD(*reg_data, 1096 - CP_IQ_WAIT_TIME2, 1097 - SCH_WAVE, 1098 - grace_period); 1089 + if (sch_wave) 1090 + *reg_data = REG_SET_FIELD(*reg_data, 1091 + CP_IQ_WAIT_TIME2, 1092 + SCH_WAVE, 1093 + sch_wave); 1094 + if (que_sleep) 1095 + *reg_data = REG_SET_FIELD(*reg_data, 1096 + CP_IQ_WAIT_TIME2, 1097 + QUE_SLEEP, 1098 + que_sleep); 1099 1099 1100 1100 *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2); 1101 1101 } ··· 1255 1255 .set_address_watch = kgd_gfx_v9_set_address_watch, 1256 1256 .clear_address_watch = kgd_gfx_v9_clear_address_watch, 1257 1257 .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times, 1258 - .build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info, 1258 + .build_dequeue_wait_counts_packet_info = kgd_gfx_v9_build_dequeue_wait_counts_packet_info, 1259 1259 .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy, 1260 1260 .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, 1261 1261 .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

··· 97 97 void kgd_gfx_v9_get_iq_wait_times(struct amdgpu_device *adev, 98 98 uint32_t *wait_times, 99 99 uint32_t inst); 100 - void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, 100 + void kgd_gfx_v9_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev, 101 101 uint32_t wait_times, 102 - uint32_t grace_period, 102 + uint32_t sch_wave, 103 + uint32_t que_sleep, 103 104 uint32_t *reg_offset, 104 105 uint32_t *reg_data); 105 106 uint64_t kgd_gfx_v9_hqd_get_pq_addr(struct amdgpu_device *adev,

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

··· 1990 1990 uint32_t max_freq, min_freq; 1991 1991 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1992 1992 1993 - if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1993 + if (amdgpu_sriov_multi_vf_mode(adev)) 1994 1994 return -EINVAL; 1995 1995 1996 1996 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 2757 2757 if (!total) 2758 2758 return -ENODEV; 2759 2759 2760 + if (adev->gmc.xgmi.supported) 2761 + amdgpu_xgmi_early_init(adev); 2762 + 2760 2763 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); 2761 2764 if (ip_block->status.valid != false) 2762 2765 amdgpu_amdkfd_device_probe(adev);

-3

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

··· 2772 2772 break; 2773 2773 } 2774 2774 2775 - if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0)) 2776 - adev->gmc.xgmi.supported = true; 2777 - 2778 2775 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2779 2776 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2780 2777 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0);

+2 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 122 122 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 123 123 * - 3.61.0 - Contains fix for RV/PCO compute queues 124 124 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 125 + * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 125 126 */ 126 127 #define KMS_DRIVER_MAJOR 3 127 - #define KMS_DRIVER_MINOR 62 128 + #define KMS_DRIVER_MINOR 63 128 129 #define KMS_DRIVER_PATCHLEVEL 0 129 130 130 131 /*

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

··· 2002 2002 if (adev->kfd.init_complete) { 2003 2003 WARN_ON_ONCE(!adev->gfx.kfd_sch_inactive[idx]); 2004 2004 WARN_ON_ONCE(adev->gfx.kfd_sch_req_count[idx]); 2005 - amdgpu_amdkfd_start_sched(adev, idx); 2006 - adev->gfx.kfd_sch_inactive[idx] = false; 2005 + amdgpu_amdkfd_start_sched(adev, idx); 2006 + adev->gfx.kfd_sch_inactive[idx] = false; 2007 2007 } 2008 2008 } 2009 2009 mutex_unlock(&adev->enforce_isolation_mutex);

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

··· 166 166 if (amdgpu_ring_sched_ready(ring)) 167 167 drm_sched_start(&ring->sched, 0); 168 168 dev_err(adev->dev, "Ring %s reset succeeded\n", ring->sched.name); 169 + drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE); 169 170 goto exit; 170 171 } 171 172 dev_err(adev->dev, "Ring %s reset failure\n", ring->sched.name);

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

··· 143 143 const struct amdgpu_mes_funcs *funcs; 144 144 145 145 /* mes resource_1 bo*/ 146 - struct amdgpu_bo *resource_1; 147 - uint64_t resource_1_gpu_addr; 148 - void *resource_1_addr; 146 + struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 147 + uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 148 + void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 149 149 150 150 }; 151 151

+25 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

··· 2836 2836 2837 2837 save_nps = (bps[0].retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; 2838 2838 2839 + /*old asics just have pa in eeprom*/ 2840 + if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { 2841 + memcpy(err_data->err_addr, bps, 2842 + sizeof(struct eeprom_table_record) * adev->umc.retire_unit); 2843 + goto out; 2844 + } 2845 + 2839 2846 for (i = 0; i < adev->umc.retire_unit; i++) 2840 2847 bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); 2841 2848 ··· 2865 2858 } 2866 2859 } 2867 2860 2861 + out: 2868 2862 return __amdgpu_ras_restore_bad_pages(adev, err_data->err_addr, adev->umc.retire_unit); 2869 2863 } 2870 2864 ··· 2989 2981 2990 2982 /* only new entries are saved */ 2991 2983 if (save_count > 0) { 2992 - for (i = 0; i < unit_num; i++) { 2984 + /*old asics only save pa to eeprom like before*/ 2985 + if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { 2993 2986 if (amdgpu_ras_eeprom_append(control, 2994 - &data->bps[bad_page_num + i * adev->umc.retire_unit], 2995 - 1)) { 2987 + &data->bps[bad_page_num], save_count)) { 2996 2988 dev_err(adev->dev, "Failed to save EEPROM table data!"); 2997 2989 return -EIO; 2998 2990 } 2991 + } else { 2992 + for (i = 0; i < unit_num; i++) { 2993 + if (amdgpu_ras_eeprom_append(control, 2994 + &data->bps[bad_page_num + 2995 + i * adev->umc.retire_unit], 1)) { 2996 + dev_err(adev->dev, "Failed to save EEPROM table data!"); 2997 + return -EIO; 2998 + } 2999 + } 2999 3000 } 3001 + 3000 3002 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); 3001 3003 } 3002 3004 ··· 3785 3767 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : 3786 3768 adev->ras_hw_enabled & amdgpu_ras_mask; 3787 3769 3788 - /* aca is disabled by default except for psp v13_0_12 */ 3770 + /* aca is disabled by default except for psp v13_0_6/v13_0_12/v13_0_14 */ 3789 3771 adev->aca.is_enabled = 3790 - (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12)); 3772 + (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3773 + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 3774 + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)); 3791 3775 3792 3776 /* bad page feature is not applicable to specific app platform */ 3793 3777 if (adev->gmc.is_app_apu &&

+7 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

··· 727 727 - control->ras_fri) 728 728 % control->ras_max_record_count; 729 729 730 - control->ras_num_mca_recs += num; 731 - control->ras_num_bad_pages += num * adev->umc.retire_unit; 730 + /*old asics only save pa to eeprom like before*/ 731 + if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) 732 + control->ras_num_pa_recs += num; 733 + else 734 + control->ras_num_mca_recs += num; 732 735 736 + control->ras_num_bad_pages = control->ras_num_pa_recs + 737 + control->ras_num_mca_recs * adev->umc.retire_unit; 733 738 Out: 734 739 kfree(buf); 735 740 return res;

+5 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

··· 614 614 vf2pf_info->decode_usage = 0; 615 615 616 616 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 617 - vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr; 618 - 619 - if (adev->mes.resource_1) { 620 - vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size; 617 + if (amdgpu_sriov_is_mes_info_enable(adev)) { 618 + vf2pf_info->mes_info_addr = 619 + (uint64_t)(adev->mes.resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE); 620 + vf2pf_info->mes_info_size = 621 + adev->mes.resource_1[0]->tbo.base.size - AMDGPU_GPU_PAGE_SIZE; 621 622 } 622 623 vf2pf_info->checksum = 623 624 amd_sriov_msg_checksum(

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

··· 364 364 365 365 #define amdgpu_sriov_is_pp_one_vf(adev) \ 366 366 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 367 + #define amdgpu_sriov_multi_vf_mode(adev) \ 368 + (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 367 369 #define amdgpu_sriov_is_debug(adev) \ 368 370 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 369 371 #define amdgpu_sriov_is_normal(adev) \

+3 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

··· 844 844 { 845 845 bool peer_mode = bw_mode == AMDGPU_XGMI_BW_MODE_PER_PEER; 846 846 int unit_scale = bw_unit == AMDGPU_XGMI_BW_UNIT_MBYTES ? 1000 : 1; 847 - int speed = 25, num_lanes = 16, num_links = !peer_mode ? 1 : -1; 847 + int num_lanes = adev->gmc.xgmi.max_width; 848 + int speed = adev->gmc.xgmi.max_speed; 849 + int num_links = !peer_mode ? 1 : -1; 848 850 849 851 if (!(min_bw && max_bw)) 850 852 return -EINVAL;

+40 -33

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

··· 40 40 #include "amdgpu_connectors.h" 41 41 #include "amdgpu_display.h" 42 42 43 + #include "dce_v6_0.h" 44 + #include "sid.h" 45 + 43 46 #include "bif/bif_3_0_d.h" 44 47 #include "bif/bif_3_0_sh_mask.h" 48 + 45 49 #include "oss/oss_1_0_d.h" 46 50 #include "oss/oss_1_0_sh_mask.h" 51 + 47 52 #include "gca/gfx_6_0_d.h" 48 53 #include "gca/gfx_6_0_sh_mask.h" 54 + #include "gca/gfx_7_2_enum.h" 55 + 49 56 #include "gmc/gmc_6_0_d.h" 50 57 #include "gmc/gmc_6_0_sh_mask.h" 58 + 51 59 #include "dce/dce_6_0_d.h" 52 60 #include "dce/dce_6_0_sh_mask.h" 53 - #include "gca/gfx_7_2_enum.h" 54 - #include "dce_v6_0.h" 61 + 55 62 #include "si_enums.h" 56 63 57 64 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); ··· 66 59 67 60 static const u32 crtc_offsets[6] = 68 61 { 69 - SI_CRTC0_REGISTER_OFFSET, 70 - SI_CRTC1_REGISTER_OFFSET, 71 - SI_CRTC2_REGISTER_OFFSET, 72 - SI_CRTC3_REGISTER_OFFSET, 73 - SI_CRTC4_REGISTER_OFFSET, 74 - SI_CRTC5_REGISTER_OFFSET 62 + CRTC0_REGISTER_OFFSET, 63 + CRTC1_REGISTER_OFFSET, 64 + CRTC2_REGISTER_OFFSET, 65 + CRTC3_REGISTER_OFFSET, 66 + CRTC4_REGISTER_OFFSET, 67 + CRTC5_REGISTER_OFFSET 75 68 }; 76 69 77 70 static const u32 hpd_offsets[] = 78 71 { 79 - mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 80 - mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 81 - mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 82 - mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 83 - mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 84 - mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 72 + HPD0_REGISTER_OFFSET, 73 + HPD1_REGISTER_OFFSET, 74 + HPD2_REGISTER_OFFSET, 75 + HPD3_REGISTER_OFFSET, 76 + HPD4_REGISTER_OFFSET, 77 + HPD5_REGISTER_OFFSET 85 78 }; 86 79 87 80 static const uint32_t dig_offsets[] = { 88 - SI_CRTC0_REGISTER_OFFSET, 89 - SI_CRTC1_REGISTER_OFFSET, 90 - SI_CRTC2_REGISTER_OFFSET, 91 - SI_CRTC3_REGISTER_OFFSET, 92 - SI_CRTC4_REGISTER_OFFSET, 93 - SI_CRTC5_REGISTER_OFFSET, 81 + CRTC0_REGISTER_OFFSET, 82 + CRTC1_REGISTER_OFFSET, 83 + CRTC2_REGISTER_OFFSET, 84 + CRTC3_REGISTER_OFFSET, 85 + CRTC4_REGISTER_OFFSET, 86 + CRTC5_REGISTER_OFFSET, 94 87 (0x13830 - 0x7030) >> 2, 95 88 }; 96 89 ··· 1396 1389 1397 1390 static const u32 pin_offsets[7] = 1398 1391 { 1399 - (0x1780 - 0x1780), 1400 - (0x1786 - 0x1780), 1401 - (0x178c - 0x1780), 1402 - (0x1792 - 0x1780), 1403 - (0x1798 - 0x1780), 1404 - (0x179d - 0x1780), 1405 - (0x17a4 - 0x1780), 1392 + AUD0_REGISTER_OFFSET, 1393 + AUD1_REGISTER_OFFSET, 1394 + AUD2_REGISTER_OFFSET, 1395 + AUD3_REGISTER_OFFSET, 1396 + AUD4_REGISTER_OFFSET, 1397 + AUD5_REGISTER_OFFSET, 1398 + AUD6_REGISTER_OFFSET, 1406 1399 }; 1407 1400 1408 1401 static int dce_v6_0_audio_init(struct amdgpu_device *adev) ··· 2961 2954 2962 2955 switch (crtc) { 2963 2956 case 0: 2964 - reg_block = SI_CRTC0_REGISTER_OFFSET; 2957 + reg_block = CRTC0_REGISTER_OFFSET; 2965 2958 break; 2966 2959 case 1: 2967 - reg_block = SI_CRTC1_REGISTER_OFFSET; 2960 + reg_block = CRTC1_REGISTER_OFFSET; 2968 2961 break; 2969 2962 case 2: 2970 - reg_block = SI_CRTC2_REGISTER_OFFSET; 2963 + reg_block = CRTC2_REGISTER_OFFSET; 2971 2964 break; 2972 2965 case 3: 2973 - reg_block = SI_CRTC3_REGISTER_OFFSET; 2966 + reg_block = CRTC3_REGISTER_OFFSET; 2974 2967 break; 2975 2968 case 4: 2976 - reg_block = SI_CRTC4_REGISTER_OFFSET; 2969 + reg_block = CRTC4_REGISTER_OFFSET; 2977 2970 break; 2978 2971 case 5: 2979 - reg_block = SI_CRTC5_REGISTER_OFFSET; 2972 + reg_block = CRTC5_REGISTER_OFFSET; 2980 2973 break; 2981 2974 default: 2982 2975 DRM_DEBUG("invalid crtc %d\n", crtc);

+32 -15

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 62 62 #define regPC_CONFIG_CNTL_1 0x194d 63 63 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 64 64 65 + #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 66 + #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 67 + #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 68 + #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 69 + #define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000 70 + #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 71 + #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 72 + 73 + #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 74 + #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 75 + #define regCP_MQD_CONTROL_DEFAULT 0x00000100 76 + #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 77 + #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 78 + #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 79 + #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 80 + #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 81 + 65 82 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 66 83 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 67 84 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); ··· 3982 3965 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 3983 3966 priority = 1; 3984 3967 3985 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3968 + tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 3986 3969 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 3987 3970 mqd->cp_gfx_hqd_queue_priority = tmp; 3988 3971 } ··· 4004 3987 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4005 3988 4006 3989 /* set up mqd control */ 4007 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3990 + tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 4008 3991 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 4009 3992 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 4010 3993 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 4011 3994 mqd->cp_gfx_mqd_control = tmp; 4012 3995 4013 3996 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 4014 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3997 + tmp = regCP_GFX_HQD_VMID_DEFAULT; 4015 3998 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 4016 3999 mqd->cp_gfx_hqd_vmid = 0; 4017 4000 ··· 4019 4002 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 4020 4003 4021 4004 /* set up time quantum */ 4022 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 4005 + tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 4023 4006 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 4024 4007 mqd->cp_gfx_hqd_quantum = tmp; 4025 4008 ··· 4041 4024 4042 4025 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 4043 4026 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 4044 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 4027 + tmp = regCP_GFX_HQD_CNTL_DEFAULT; 4045 4028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 4046 4029 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 4047 4030 #ifdef __BIG_ENDIAN ··· 4050 4033 mqd->cp_gfx_hqd_cntl = tmp; 4051 4034 4052 4035 /* set up cp_doorbell_control */ 4053 - tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 4036 + tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 4054 4037 if (prop->use_doorbell) { 4055 4038 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4056 4039 DOORBELL_OFFSET, prop->doorbell_index); ··· 4062 4045 mqd->cp_rb_doorbell_control = tmp; 4063 4046 4064 4047 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4065 - mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 4048 + mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 4066 4049 4067 4050 /* active the queue */ 4068 4051 mqd->cp_gfx_hqd_active = 1; ··· 4148 4131 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4149 4132 4150 4133 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4151 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4134 + tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 4152 4135 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4153 4136 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4154 4137 4155 4138 mqd->cp_hqd_eop_control = tmp; 4156 4139 4157 4140 /* enable doorbell? */ 4158 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4141 + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4159 4142 4160 4143 if (prop->use_doorbell) { 4161 4144 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, ··· 4184 4167 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4185 4168 4186 4169 /* set MQD vmid to 0 */ 4187 - tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4170 + tmp = regCP_MQD_CONTROL_DEFAULT; 4188 4171 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4189 4172 mqd->cp_mqd_control = tmp; 4190 4173 ··· 4194 4177 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4195 4178 4196 4179 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4197 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4180 + tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 4198 4181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4199 4182 (order_base_2(prop->queue_size / 4) - 1)); 4200 4183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, ··· 4220 4203 tmp = 0; 4221 4204 /* enable the doorbell if requested */ 4222 4205 if (prop->use_doorbell) { 4223 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4206 + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4224 4207 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4225 4208 DOORBELL_OFFSET, prop->doorbell_index); 4226 4209 ··· 4235 4218 mqd->cp_hqd_pq_doorbell_control = tmp; 4236 4219 4237 4220 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4238 - mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4221 + mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 4239 4222 4240 4223 /* set the vmid for the queue */ 4241 4224 mqd->cp_hqd_vmid = 0; 4242 4225 4243 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4226 + tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 4244 4227 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4245 4228 mqd->cp_hqd_persistent_state = tmp; 4246 4229 4247 4230 /* set MIN_IB_AVAIL_SIZE */ 4248 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4231 + tmp = regCP_HQD_IB_CONTROL_DEFAULT; 4249 4232 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4250 4233 mqd->cp_hqd_ib_control = tmp; 4251 4234

+34 -16

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

··· 50 50 51 51 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 52 52 53 + #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 54 + #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 55 + #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 56 + #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 57 + #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 58 + #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 59 + #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 60 + 61 + #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 62 + #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 63 + #define regCP_MQD_CONTROL_DEFAULT 0x00000100 64 + #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 65 + #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 66 + #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 67 + #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 68 + #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 69 + 70 + 53 71 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 54 72 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 55 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); ··· 2455 2437 (void **)&adev->gfx.me.me_fw_data_ptr); 2456 2438 if (r) { 2457 2439 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2458 - gfx_v12_0_pfp_fini(adev); 2440 + gfx_v12_0_me_fini(adev); 2459 2441 return r; 2460 2442 } 2461 2443 ··· 2909 2891 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2910 2892 2911 2893 /* set up mqd control */ 2912 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2894 + tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2913 2895 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2914 2896 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2915 2897 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2916 2898 mqd->cp_gfx_mqd_control = tmp; 2917 2899 2918 2900 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2919 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2901 + tmp = regCP_GFX_HQD_VMID_DEFAULT; 2920 2902 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2921 2903 mqd->cp_gfx_hqd_vmid = 0; 2922 2904 2923 2905 /* set up default queue priority level 2924 2906 * 0x0 = low priority, 0x1 = high priority */ 2925 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2907 + tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2926 2908 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2927 2909 mqd->cp_gfx_hqd_queue_priority = tmp; 2928 2910 2929 2911 /* set up time quantum */ 2930 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2912 + tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2931 2913 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2932 2914 mqd->cp_gfx_hqd_quantum = tmp; 2933 2915 ··· 2949 2931 2950 2932 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2951 2933 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2952 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2934 + tmp = regCP_GFX_HQD_CNTL_DEFAULT; 2953 2935 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2954 2936 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2955 2937 #ifdef __BIG_ENDIAN ··· 2958 2940 mqd->cp_gfx_hqd_cntl = tmp; 2959 2941 2960 2942 /* set up cp_doorbell_control */ 2961 - tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2943 + tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 2962 2944 if (prop->use_doorbell) { 2963 2945 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2964 2946 DOORBELL_OFFSET, prop->doorbell_index); ··· 2970 2952 mqd->cp_rb_doorbell_control = tmp; 2971 2953 2972 2954 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2973 - mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2955 + mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 2974 2956 2975 2957 /* active the queue */ 2976 2958 mqd->cp_gfx_hqd_active = 1; ··· 3065 3047 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3066 3048 3067 3049 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3068 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3050 + tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3069 3051 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3070 3052 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3071 3053 3072 3054 mqd->cp_hqd_eop_control = tmp; 3073 3055 3074 3056 /* enable doorbell? */ 3075 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3057 + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3076 3058 3077 3059 if (prop->use_doorbell) { 3078 3060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, ··· 3101 3083 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3102 3084 3103 3085 /* set MQD vmid to 0 */ 3104 - tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3086 + tmp = regCP_MQD_CONTROL_DEFAULT; 3105 3087 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3106 3088 mqd->cp_mqd_control = tmp; 3107 3089 ··· 3111 3093 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3112 3094 3113 3095 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3114 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3096 + tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3115 3097 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3116 3098 (order_base_2(prop->queue_size / 4) - 1)); 3117 3099 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, ··· 3136 3118 tmp = 0; 3137 3119 /* enable the doorbell if requested */ 3138 3120 if (prop->use_doorbell) { 3139 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3121 + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3140 3122 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3141 3123 DOORBELL_OFFSET, prop->doorbell_index); 3142 3124 ··· 3151 3133 mqd->cp_hqd_pq_doorbell_control = tmp; 3152 3134 3153 3135 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3154 - mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3136 + mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3155 3137 3156 3138 /* set the vmid for the queue */ 3157 3139 mqd->cp_hqd_vmid = 0; 3158 3140 3159 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3141 + tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3160 3142 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3161 3143 mqd->cp_hqd_persistent_state = tmp; 3162 3144 3163 3145 /* set MIN_IB_AVAIL_SIZE */ 3164 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3146 + tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3165 3147 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3166 3148 mqd->cp_hqd_ib_control = tmp; 3167 3149

+13 -2

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

··· 28 28 #include "amdgpu_gfx.h" 29 29 #include "amdgpu_ucode.h" 30 30 #include "clearstate_si.h" 31 + #include "si.h" 32 + #include "sid.h" 33 + 31 34 #include "bif/bif_3_0_d.h" 32 35 #include "bif/bif_3_0_sh_mask.h" 36 + 33 37 #include "oss/oss_1_0_d.h" 34 38 #include "oss/oss_1_0_sh_mask.h" 39 + 35 40 #include "gca/gfx_6_0_d.h" 36 41 #include "gca/gfx_6_0_sh_mask.h" 42 + #include "gca/gfx_7_2_enum.h" 43 + 37 44 #include "gmc/gmc_6_0_d.h" 38 45 #include "gmc/gmc_6_0_sh_mask.h" 46 + 39 47 #include "dce/dce_6_0_d.h" 40 48 #include "dce/dce_6_0_sh_mask.h" 41 - #include "gca/gfx_7_2_enum.h" 49 + 42 50 #include "si_enums.h" 43 - #include "si.h" 51 + 52 + #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 53 + #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 54 + #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 44 55 45 56 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 46 57 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

··· 1821 1821 DOORBELL_SOURCE, 0); 1822 1822 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1823 1823 DOORBELL_HIT, 0); 1824 - if (amdgpu_sriov_vf(adev)) 1824 + if (amdgpu_sriov_multi_vf_mode(adev)) 1825 1825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1826 1826 DOORBELL_MODE, 1); 1827 1827 } else {

-37

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

··· 505 505 hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs; 506 506 } 507 507 508 - static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) 509 - { 510 - u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); 511 - u32 max_region = 512 - REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 513 - u32 max_num_physical_nodes = 0; 514 - u32 max_physical_node_id = 0; 515 - 516 - switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 517 - case IP_VERSION(4, 8, 0): 518 - max_num_physical_nodes = 4; 519 - max_physical_node_id = 3; 520 - break; 521 - default: 522 - return -EINVAL; 523 - } 524 - 525 - /* PF_MAX_REGION=0 means xgmi is disabled */ 526 - if (max_region) { 527 - adev->gmc.xgmi.num_physical_nodes = max_region + 1; 528 - if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 529 - return -EINVAL; 530 - 531 - adev->gmc.xgmi.physical_node_id = 532 - REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 533 - if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 534 - return -EINVAL; 535 - 536 - adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( 537 - RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), 538 - GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 539 - } 540 - 541 - return 0; 542 - } 543 - 544 508 static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) 545 509 { 546 510 int i; ··· 660 696 .gart_disable = gfxhub_v2_1_gart_disable, 661 697 .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default, 662 698 .init = gfxhub_v2_1_init, 663 - .get_xgmi_info = gfxhub_v2_1_get_xgmi_info, 664 699 .utcl2_harvest = gfxhub_v2_1_utcl2_harvest, 665 700 .mode2_save_regs = gfxhub_v2_1_save_regs, 666 701 .mode2_restore_regs = gfxhub_v2_1_restore_regs,

+2 -19

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

··· 501 501 uint64_t *flags) 502 502 { 503 503 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 504 - struct amdgpu_device *bo_adev; 505 - bool coherent, is_system; 506 - 507 504 508 505 *flags &= ~AMDGPU_PTE_EXECUTABLE; 509 506 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; ··· 516 519 *flags &= ~AMDGPU_PTE_VALID; 517 520 } 518 521 519 - if (!bo) 520 - return; 521 - 522 - if (bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 523 - AMDGPU_GEM_CREATE_UNCACHED)) 524 - *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 525 - 526 - bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 527 - coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 528 - is_system = (bo->tbo.resource->mem_type == TTM_PL_TT) || 529 - (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT); 530 - 531 522 if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) 532 523 *flags |= AMDGPU_PTE_DCC; 533 524 534 - /* WA for HW bug */ 535 - if (is_system || ((bo_adev != adev) && coherent)) 536 - *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 537 - 525 + if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) 526 + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 538 527 } 539 528 540 529 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev)

+29 -30

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

··· 740 740 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 741 741 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 742 742 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 743 - mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 744 - mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 745 - mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = 746 - mes->resource_1_gpu_addr + MES11_HW_RESOURCE_1_SIZE; 743 + 744 + mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 745 + if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 746 + mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 747 + mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 748 + mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 749 + } 747 750 748 751 return mes_v11_0_submit_pkt_and_poll_completion(mes, 749 752 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), ··· 1384 1381 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1385 1382 { 1386 1383 struct amdgpu_device *adev = ip_block->adev; 1387 - int pipe, r; 1384 + int pipe, r, bo_size; 1388 1385 1389 1386 adev->mes.funcs = &mes_v11_0_funcs; 1390 1387 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; ··· 1419 1416 if (r) 1420 1417 return r; 1421 1418 1422 - if (amdgpu_sriov_is_mes_info_enable(adev) || 1423 - adev->gfx.enable_cleaner_shader) { 1424 - r = amdgpu_bo_create_kernel(adev, 1425 - MES11_HW_RESOURCE_1_SIZE + AMDGPU_GPU_PAGE_SIZE, 1426 - PAGE_SIZE, 1427 - AMDGPU_GEM_DOMAIN_VRAM, 1428 - &adev->mes.resource_1, 1429 - &adev->mes.resource_1_gpu_addr, 1430 - &adev->mes.resource_1_addr); 1431 - if (r) { 1432 - dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1433 - return r; 1434 - } 1419 + bo_size = AMDGPU_GPU_PAGE_SIZE; 1420 + if (amdgpu_sriov_is_mes_info_enable(adev)) 1421 + bo_size += MES11_HW_RESOURCE_1_SIZE; 1422 + 1423 + /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1424 + r = amdgpu_bo_create_kernel(adev, 1425 + bo_size, 1426 + PAGE_SIZE, 1427 + AMDGPU_GEM_DOMAIN_VRAM, 1428 + &adev->mes.resource_1[0], 1429 + &adev->mes.resource_1_gpu_addr[0], 1430 + &adev->mes.resource_1_addr[0]); 1431 + if (r) { 1432 + dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1433 + return r; 1435 1434 } 1436 1435 1437 1436 return 0; ··· 1444 1439 struct amdgpu_device *adev = ip_block->adev; 1445 1440 int pipe; 1446 1441 1447 - if (amdgpu_sriov_is_mes_info_enable(adev) || 1448 - adev->gfx.enable_cleaner_shader) { 1449 - amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1450 - &adev->mes.resource_1_addr); 1451 - } 1442 + amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1443 + &adev->mes.resource_1_addr[0]); 1452 1444 1453 1445 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1454 1446 kfree(adev->mes.mqd_backup[pipe]); ··· 1634 1632 if (r) 1635 1633 goto failure; 1636 1634 1637 - if (amdgpu_sriov_is_mes_info_enable(adev) || 1638 - adev->gfx.enable_cleaner_shader) { 1639 - r = mes_v11_0_set_hw_resources_1(&adev->mes); 1640 - if (r) { 1641 - DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1642 - goto failure; 1643 - } 1635 + r = mes_v11_0_set_hw_resources_1(&adev->mes); 1636 + if (r) { 1637 + DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1638 + goto failure; 1644 1639 } 1645 1640 1646 1641 r = mes_v11_0_query_sched_status(&adev->mes);

+20 -23

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

··· 687 687 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 688 688 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa; 689 689 mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr = 690 - mes->resource_1_gpu_addr; 690 + mes->resource_1_gpu_addr[pipe]; 691 691 692 692 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 693 693 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), ··· 1519 1519 if (r) 1520 1520 return r; 1521 1521 1522 - if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1522 + if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) { 1523 1523 r = mes_v12_0_kiq_ring_init(adev); 1524 - else 1524 + } 1525 + else { 1525 1526 r = mes_v12_0_ring_init(adev, pipe); 1526 - if (r) 1527 - return r; 1528 - } 1529 - 1530 - if (adev->enable_uni_mes) { 1531 - r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, 1532 - AMDGPU_GEM_DOMAIN_VRAM, 1533 - &adev->mes.resource_1, 1534 - &adev->mes.resource_1_gpu_addr, 1535 - &adev->mes.resource_1_addr); 1536 - if (r) { 1537 - dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1538 - return r; 1527 + if (r) 1528 + return r; 1529 + r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, 1530 + AMDGPU_GEM_DOMAIN_VRAM, 1531 + &adev->mes.resource_1[pipe], 1532 + &adev->mes.resource_1_gpu_addr[pipe], 1533 + &adev->mes.resource_1_addr[pipe]); 1534 + if (r) { 1535 + dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe); 1536 + return r; 1537 + } 1539 1538 } 1540 1539 } 1541 1540 ··· 1546 1547 struct amdgpu_device *adev = ip_block->adev; 1547 1548 int pipe; 1548 1549 1549 - if (adev->enable_uni_mes) 1550 - amdgpu_bo_free_kernel(&adev->mes.resource_1, 1551 - &adev->mes.resource_1_gpu_addr, 1552 - &adev->mes.resource_1_addr); 1553 - 1554 1550 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1551 + amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe], 1552 + &adev->mes.resource_1_gpu_addr[pipe], 1553 + &adev->mes.resource_1_addr[pipe]); 1554 + 1555 1555 kfree(adev->mes.mqd_backup[pipe]); 1556 1556 1557 1557 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], ··· 1749 1751 if (r) 1750 1752 goto failure; 1751 1753 1752 - if (adev->enable_uni_mes) 1753 - mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1754 + mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1754 1755 1755 1756 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1756 1757

+18 -18

drivers/gpu/drm/amd/amdgpu/nv.c

··· 78 78 79 79 /* Navi1x */ 80 80 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = { 81 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 82 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 81 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 82 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 83 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 84 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 84 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 85 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 86 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 86 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)}, 87 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 88 88 }; 89 89 ··· 104 104 }; 105 105 106 106 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = { 107 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 108 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 107 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 108 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 109 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 110 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 110 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 111 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 112 112 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 113 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, ··· 115 115 }; 116 116 117 117 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = { 118 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 119 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 118 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 119 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 120 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 121 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 121 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 122 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 123 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 124 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, ··· 141 141 }; 142 142 143 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = { 144 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 145 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 144 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 145 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 146 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 147 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 147 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 148 148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 149 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 149 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 150 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 151 151 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 152 152 }; 153 153 154 154 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = { 155 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 156 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 155 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 156 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 157 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 158 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 158 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 159 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 160 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 160 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 161 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 162 162 }; 163 163

+34 -34

drivers/gpu/drm/amd/amdgpu/si.c

··· 1124 1124 {mmCP_STALLED_STAT3}, 1125 1125 {GB_ADDR_CONFIG}, 1126 1126 {MC_ARB_RAMCFG}, 1127 - {GB_TILE_MODE0}, 1128 - {GB_TILE_MODE1}, 1129 - {GB_TILE_MODE2}, 1130 - {GB_TILE_MODE3}, 1131 - {GB_TILE_MODE4}, 1132 - {GB_TILE_MODE5}, 1133 - {GB_TILE_MODE6}, 1134 - {GB_TILE_MODE7}, 1135 - {GB_TILE_MODE8}, 1136 - {GB_TILE_MODE9}, 1137 - {GB_TILE_MODE10}, 1138 - {GB_TILE_MODE11}, 1139 - {GB_TILE_MODE12}, 1140 - {GB_TILE_MODE13}, 1141 - {GB_TILE_MODE14}, 1142 - {GB_TILE_MODE15}, 1143 - {GB_TILE_MODE16}, 1144 - {GB_TILE_MODE17}, 1145 - {GB_TILE_MODE18}, 1146 - {GB_TILE_MODE19}, 1147 - {GB_TILE_MODE20}, 1148 - {GB_TILE_MODE21}, 1149 - {GB_TILE_MODE22}, 1150 - {GB_TILE_MODE23}, 1151 - {GB_TILE_MODE24}, 1152 - {GB_TILE_MODE25}, 1153 - {GB_TILE_MODE26}, 1154 - {GB_TILE_MODE27}, 1155 - {GB_TILE_MODE28}, 1156 - {GB_TILE_MODE29}, 1157 - {GB_TILE_MODE30}, 1158 - {GB_TILE_MODE31}, 1127 + {mmGB_TILE_MODE0}, 1128 + {mmGB_TILE_MODE1}, 1129 + {mmGB_TILE_MODE2}, 1130 + {mmGB_TILE_MODE3}, 1131 + {mmGB_TILE_MODE4}, 1132 + {mmGB_TILE_MODE5}, 1133 + {mmGB_TILE_MODE6}, 1134 + {mmGB_TILE_MODE7}, 1135 + {mmGB_TILE_MODE8}, 1136 + {mmGB_TILE_MODE9}, 1137 + {mmGB_TILE_MODE10}, 1138 + {mmGB_TILE_MODE11}, 1139 + {mmGB_TILE_MODE12}, 1140 + {mmGB_TILE_MODE13}, 1141 + {mmGB_TILE_MODE14}, 1142 + {mmGB_TILE_MODE15}, 1143 + {mmGB_TILE_MODE16}, 1144 + {mmGB_TILE_MODE17}, 1145 + {mmGB_TILE_MODE18}, 1146 + {mmGB_TILE_MODE19}, 1147 + {mmGB_TILE_MODE20}, 1148 + {mmGB_TILE_MODE21}, 1149 + {mmGB_TILE_MODE22}, 1150 + {mmGB_TILE_MODE23}, 1151 + {mmGB_TILE_MODE24}, 1152 + {mmGB_TILE_MODE25}, 1153 + {mmGB_TILE_MODE26}, 1154 + {mmGB_TILE_MODE27}, 1155 + {mmGB_TILE_MODE28}, 1156 + {mmGB_TILE_MODE29}, 1157 + {mmGB_TILE_MODE30}, 1158 + {mmGB_TILE_MODE31}, 1159 1159 {CC_RB_BACKEND_DISABLE, true}, 1160 - {GC_USER_RB_BACKEND_DISABLE, true}, 1161 - {PA_SC_RASTER_CONFIG, true}, 1160 + {mmGC_USER_RB_BACKEND_DISABLE, true}, 1161 + {mmPA_SC_RASTER_CONFIG, true}, 1162 1162 }; 1163 1163 1164 1164 static uint32_t si_get_register_value(struct amdgpu_device *adev,

-12

drivers/gpu/drm/amd/amdgpu/si_enums.h

··· 121 121 #define CURSOR_UPDATE_LOCK (1 << 16) 122 122 #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 123 123 124 - #define SI_CRTC0_REGISTER_OFFSET 0 125 - #define SI_CRTC1_REGISTER_OFFSET 0x300 126 - #define SI_CRTC2_REGISTER_OFFSET 0x2600 127 - #define SI_CRTC3_REGISTER_OFFSET 0x2900 128 - #define SI_CRTC4_REGISTER_OFFSET 0x2c00 129 - #define SI_CRTC5_REGISTER_OFFSET 0x2f00 130 124 131 - #define DMA0_REGISTER_OFFSET 0x000 132 - #define DMA1_REGISTER_OFFSET 0x200 133 125 #define ES_AND_GS_AUTO 3 134 126 #define RADEON_PACKET_TYPE3 3 135 127 #define CE_PARTITION_BASE 3 ··· 152 160 #define GFX6_NUM_COMPUTE_RINGS 2 153 161 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 154 162 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 155 - 156 - #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 157 - #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002 158 - #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 159 163 160 164 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 161 165 (((op) & 0xFF) << 8) | \

+24 -345

drivers/gpu/drm/amd/amdgpu/sid.h

··· 26 26 27 27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 28 28 29 - #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 30 - #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 31 - #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 32 - 33 29 #define SI_MAX_SH_GPRS 256 34 30 #define SI_MAX_TEMP_GPRS 16 35 31 #define SI_MAX_SH_THREADS 256 ··· 692 696 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528 693 697 694 698 /* DCE6 ELD audio interface */ 695 - #define AZ_F0_CODEC_ENDPOINT_INDEX 0x1780 696 - # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0) 697 - # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8) 698 - #define AZ_F0_CODEC_ENDPOINT_DATA 0x1781 699 - 700 - #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 701 - #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 702 - #define SPEAKER_ALLOCATION_MASK (0x7f << 0) 703 - #define SPEAKER_ALLOCATION_SHIFT 0 704 - #define HDMI_CONNECTION (1 << 16) 705 - #define DP_CONNECTION (1 << 17) 706 - 707 699 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */ 708 700 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */ 709 701 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */ ··· 893 909 #define CRTC_STATUS_FRAME_COUNT 0x1BA6 894 910 895 911 /* Audio clocks */ 896 - #define DCCG_AUDIO_DTO_SOURCE 0x05ac 897 - # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 898 - # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 899 - 900 912 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 901 913 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 902 914 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 903 915 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 904 - 905 - #define AFMT_AUDIO_SRC_CONTROL 0x1c4f 906 - #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) 907 - /* AFMT_AUDIO_SRC_SELECT 908 - * 0 = stream0 909 - * 1 = stream1 910 - * 2 = stream2 911 - * 3 = stream3 912 - * 4 = stream4 913 - * 5 = stream5 914 - */ 915 916 916 917 #define GRBM_CNTL 0x2000 917 918 #define GRBM_READ_TIMEOUT(x) ((x) << 0) ··· 946 977 #define SE_DB_BUSY (1 << 30) 947 978 #define SE_CB_BUSY (1 << 31) 948 979 949 - #define GRBM_SOFT_RESET 0x2008 950 - #define SOFT_RESET_CP (1 << 0) 951 - #define SOFT_RESET_CB (1 << 1) 952 - #define SOFT_RESET_RLC (1 << 2) 953 - #define SOFT_RESET_DB (1 << 3) 954 - #define SOFT_RESET_GDS (1 << 4) 955 - #define SOFT_RESET_PA (1 << 5) 956 - #define SOFT_RESET_SC (1 << 6) 957 - #define SOFT_RESET_BCI (1 << 7) 958 - #define SOFT_RESET_SPI (1 << 8) 959 - #define SOFT_RESET_SX (1 << 10) 960 - #define SOFT_RESET_TC (1 << 11) 961 - #define SOFT_RESET_TA (1 << 12) 962 - #define SOFT_RESET_VGT (1 << 14) 963 - #define SOFT_RESET_IA (1 << 15) 964 - 965 - #define GRBM_GFX_INDEX 0x200B 966 - #define INSTANCE_INDEX(x) ((x) << 0) 967 - #define SH_INDEX(x) ((x) << 8) 968 - #define SE_INDEX(x) ((x) << 16) 969 - #define SH_BROADCAST_WRITES (1 << 29) 970 - #define INSTANCE_BROADCAST_WRITES (1 << 30) 971 - #define SE_BROADCAST_WRITES (1 << 31) 972 - 973 980 #define GRBM_INT_CNTL 0x2018 974 981 # define RDERR_INT_ENABLE (1 << 0) 975 982 # define GUI_IDLE_INT_ENABLE (1 << 19) ··· 990 1045 991 1046 #define VGT_VTX_VECT_EJECT_REG 0x222C 992 1047 993 - #define VGT_CACHE_INVALIDATION 0x2231 994 - #define CACHE_INVALIDATION(x) ((x) << 0) 995 - #define VC_ONLY 0 996 - #define TC_ONLY 1 997 - #define VC_AND_TC 2 998 - #define AUTO_INVLD_EN(x) ((x) << 6) 999 - #define NO_AUTO 0 1000 - #define ES_AUTO 1 1001 - #define GS_AUTO 2 1002 - #define ES_AND_GS_AUTO 3 1003 1048 #define VGT_ESGS_RING_SIZE 0x2232 1004 1049 #define VGT_GSVS_RING_SIZE 0x2233 1005 1050 ··· 1006 1071 #define VGT_HS_OFFCHIP_PARAM 0x226C 1007 1072 1008 1073 #define VGT_TF_MEMORY_BASE 0x226E 1009 - 1010 - #define CC_GC_SHADER_ARRAY_CONFIG 0x226F 1011 - #define INACTIVE_CUS_MASK 0xFFFF0000 1012 - #define INACTIVE_CUS_SHIFT 16 1013 - #define GC_USER_SHADER_ARRAY_CONFIG 0x2270 1014 1074 1015 1075 #define PA_CL_ENHANCE 0x2285 1016 1076 #define CLIP_VTX_REORDER_ENA (1 << 0) ··· 1099 1169 #define ROW_SIZE_MASK 0x30000000 1100 1170 #define ROW_SIZE_SHIFT 28 1101 1171 1102 - #define GB_TILE_MODE0 0x2644 1103 - # define MICRO_TILE_MODE(x) ((x) << 0) 1104 - # define ADDR_SURF_DISPLAY_MICRO_TILING 0 1105 - # define ADDR_SURF_THIN_MICRO_TILING 1 1106 - # define ADDR_SURF_DEPTH_MICRO_TILING 2 1107 - # define ARRAY_MODE(x) ((x) << 2) 1108 - # define ARRAY_LINEAR_GENERAL 0 1109 - # define ARRAY_LINEAR_ALIGNED 1 1110 - # define ARRAY_1D_TILED_THIN1 2 1111 - # define ARRAY_2D_TILED_THIN1 4 1112 - # define PIPE_CONFIG(x) ((x) << 6) 1113 - # define ADDR_SURF_P2 0 1114 - # define ADDR_SURF_P4_8x16 4 1115 - # define ADDR_SURF_P4_16x16 5 1116 - # define ADDR_SURF_P4_16x32 6 1117 - # define ADDR_SURF_P4_32x32 7 1118 - # define ADDR_SURF_P8_16x16_8x16 8 1119 - # define ADDR_SURF_P8_16x32_8x16 9 1120 - # define ADDR_SURF_P8_32x32_8x16 10 1121 - # define ADDR_SURF_P8_16x32_16x16 11 1122 - # define ADDR_SURF_P8_32x32_16x16 12 1123 - # define ADDR_SURF_P8_32x32_16x32 13 1124 - # define ADDR_SURF_P8_32x64_32x32 14 1125 - # define TILE_SPLIT(x) ((x) << 11) 1126 - # define ADDR_SURF_TILE_SPLIT_64B 0 1127 - # define ADDR_SURF_TILE_SPLIT_128B 1 1128 - # define ADDR_SURF_TILE_SPLIT_256B 2 1129 - # define ADDR_SURF_TILE_SPLIT_512B 3 1130 - # define ADDR_SURF_TILE_SPLIT_1KB 4 1131 - # define ADDR_SURF_TILE_SPLIT_2KB 5 1132 - # define ADDR_SURF_TILE_SPLIT_4KB 6 1133 - # define BANK_WIDTH(x) ((x) << 14) 1134 - # define ADDR_SURF_BANK_WIDTH_1 0 1135 - # define ADDR_SURF_BANK_WIDTH_2 1 1136 - # define ADDR_SURF_BANK_WIDTH_4 2 1137 - # define ADDR_SURF_BANK_WIDTH_8 3 1138 - # define BANK_HEIGHT(x) ((x) << 16) 1139 - # define ADDR_SURF_BANK_HEIGHT_1 0 1140 - # define ADDR_SURF_BANK_HEIGHT_2 1 1141 - # define ADDR_SURF_BANK_HEIGHT_4 2 1142 - # define ADDR_SURF_BANK_HEIGHT_8 3 1143 - # define MACRO_TILE_ASPECT(x) ((x) << 18) 1144 - # define ADDR_SURF_MACRO_ASPECT_1 0 1145 - # define ADDR_SURF_MACRO_ASPECT_2 1 1146 - # define ADDR_SURF_MACRO_ASPECT_4 2 1147 - # define ADDR_SURF_MACRO_ASPECT_8 3 1148 - # define NUM_BANKS(x) ((x) << 20) 1149 - # define ADDR_SURF_2_BANK 0 1150 - # define ADDR_SURF_4_BANK 1 1151 - # define ADDR_SURF_8_BANK 2 1152 - # define ADDR_SURF_16_BANK 3 1153 - #define GB_TILE_MODE1 0x2645 1154 - #define GB_TILE_MODE2 0x2646 1155 - #define GB_TILE_MODE3 0x2647 1156 - #define GB_TILE_MODE4 0x2648 1157 - #define GB_TILE_MODE5 0x2649 1158 - #define GB_TILE_MODE6 0x264a 1159 - #define GB_TILE_MODE7 0x264b 1160 - #define GB_TILE_MODE8 0x264c 1161 - #define GB_TILE_MODE9 0x264d 1162 - #define GB_TILE_MODE10 0x264e 1163 - #define GB_TILE_MODE11 0x264f 1164 - #define GB_TILE_MODE12 0x2650 1165 - #define GB_TILE_MODE13 0x2651 1166 - #define GB_TILE_MODE14 0x2652 1167 - #define GB_TILE_MODE15 0x2653 1168 - #define GB_TILE_MODE16 0x2654 1169 - #define GB_TILE_MODE17 0x2655 1170 - #define GB_TILE_MODE18 0x2656 1171 - #define GB_TILE_MODE19 0x2657 1172 - #define GB_TILE_MODE20 0x2658 1173 - #define GB_TILE_MODE21 0x2659 1174 - #define GB_TILE_MODE22 0x265a 1175 - #define GB_TILE_MODE23 0x265b 1176 - #define GB_TILE_MODE24 0x265c 1177 - #define GB_TILE_MODE25 0x265d 1178 - #define GB_TILE_MODE26 0x265e 1179 - #define GB_TILE_MODE27 0x265f 1180 - #define GB_TILE_MODE28 0x2660 1181 - #define GB_TILE_MODE29 0x2661 1182 - #define GB_TILE_MODE30 0x2662 1183 - #define GB_TILE_MODE31 0x2663 1184 - 1185 1172 #define CB_PERFCOUNTER0_SELECT0 0x2688 1186 1173 #define CB_PERFCOUNTER0_SELECT1 0x2689 1187 1174 #define CB_PERFCOUNTER1_SELECT0 0x268A ··· 1109 1262 #define CB_PERFCOUNTER3_SELECT1 0x268F 1110 1263 1111 1264 #define CB_CGTT_SCLK_CTRL 0x2698 1112 - 1113 - #define GC_USER_RB_BACKEND_DISABLE 0x26DF 1114 - #define BACKEND_DISABLE_MASK 0x00FF0000 1115 - #define BACKEND_DISABLE_SHIFT 16 1116 1265 1117 1266 #define TCP_CHAN_STEER_LO 0x2B03 1118 1267 #define TCP_CHAN_STEER_HI 0x2B94 ··· 1163 1320 # define CP_RINGID1_INT_STAT (1 << 30) 1164 1321 # define CP_RINGID0_INT_STAT (1 << 31) 1165 1322 1166 - #define CP_MEM_SLP_CNTL 0x3079 1167 - # define CP_MEM_LS_EN (1 << 0) 1168 - 1169 - #define CP_DEBUG 0x307F 1170 - 1171 - #define RLC_CNTL 0x30C0 1172 - # define RLC_ENABLE (1 << 0) 1173 - #define RLC_RL_BASE 0x30C1 1174 - #define RLC_RL_SIZE 0x30C2 1175 - #define RLC_LB_CNTL 0x30C3 1176 - # define LOAD_BALANCE_ENABLE (1 << 0) 1177 - #define RLC_SAVE_AND_RESTORE_BASE 0x30C4 1178 - #define RLC_LB_CNTR_MAX 0x30C5 1179 - #define RLC_LB_CNTR_INIT 0x30C6 1180 - 1181 - #define RLC_CLEAR_STATE_RESTORE_BASE 0x30C8 1182 - 1183 - #define RLC_UCODE_ADDR 0x30CB 1184 - #define RLC_UCODE_DATA 0x30CC 1185 - 1186 - #define RLC_GPU_CLOCK_COUNT_LSB 0x30CE 1187 - #define RLC_GPU_CLOCK_COUNT_MSB 0x30CF 1188 - #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0 1189 - #define RLC_MC_CNTL 0x30D1 1190 - #define RLC_UCODE_CNTL 0x30D2 1191 - #define RLC_STAT 0x30D3 1192 - # define RLC_BUSY_STATUS (1 << 0) 1193 - # define GFX_POWER_STATUS (1 << 1) 1194 - # define GFX_CLOCK_STATUS (1 << 2) 1195 - # define GFX_LS_STATUS (1 << 3) 1196 - 1197 - #define RLC_PG_CNTL 0x30D7 1198 - # define GFX_PG_ENABLE (1 << 0) 1199 - # define GFX_PG_SRC (1 << 1) 1200 - 1201 - #define RLC_CGTT_MGCG_OVERRIDE 0x3100 1202 - #define RLC_CGCG_CGLS_CTRL 0x3101 1203 - # define CGCG_EN (1 << 0) 1204 - # define CGLS_EN (1 << 1) 1205 - 1206 - #define RLC_TTOP_D 0x3105 1207 - # define RLC_PUD(x) ((x) << 0) 1208 - # define RLC_PUD_MASK (0xff << 0) 1209 - # define RLC_PDD(x) ((x) << 8) 1210 - # define RLC_PDD_MASK (0xff << 8) 1211 - # define RLC_TTPD(x) ((x) << 16) 1212 - # define RLC_TTPD_MASK (0xff << 16) 1213 - # define RLC_MSD(x) ((x) << 24) 1214 - # define RLC_MSD_MASK (0xff << 24) 1215 - 1216 - #define RLC_LB_INIT_CU_MASK 0x3107 1217 - 1218 - #define RLC_PG_AO_CU_MASK 0x310B 1219 - #define RLC_MAX_PG_CU 0x310C 1220 - # define MAX_PU_CU(x) ((x) << 0) 1221 - # define MAX_PU_CU_MASK (0xff << 0) 1222 - #define RLC_AUTO_PG_CTRL 0x310C 1223 - # define AUTO_PG_EN (1 << 0) 1224 - # define GRBM_REG_SGIT(x) ((x) << 3) 1225 - # define GRBM_REG_SGIT_MASK (0xffff << 3) 1226 - # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19) 1227 - # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19) 1228 - 1229 - #define RLC_SERDES_WR_MASTER_MASK_0 0x3115 1230 - #define RLC_SERDES_WR_MASTER_MASK_1 0x3116 1231 - #define RLC_SERDES_WR_CTRL 0x3117 1232 - 1233 - #define RLC_SERDES_MASTER_BUSY_0 0x3119 1234 - #define RLC_SERDES_MASTER_BUSY_1 0x311A 1235 - 1236 - #define RLC_GCPM_GENERAL_3 0x311E 1237 - 1238 - #define DB_RENDER_CONTROL 0xA000 1239 - 1240 - #define DB_DEPTH_INFO 0xA00F 1241 - 1242 - #define PA_SC_RASTER_CONFIG 0xA0D4 1243 - # define RB_MAP_PKR0(x) ((x) << 0) 1244 - # define RB_MAP_PKR0_MASK (0x3 << 0) 1245 - # define RB_MAP_PKR1(x) ((x) << 2) 1246 - # define RB_MAP_PKR1_MASK (0x3 << 2) 1247 - # define RASTER_CONFIG_RB_MAP_0 0 1248 - # define RASTER_CONFIG_RB_MAP_1 1 1249 - # define RASTER_CONFIG_RB_MAP_2 2 1250 - # define RASTER_CONFIG_RB_MAP_3 3 1323 + // #define PA_SC_RASTER_CONFIG 0xA0D4 1251 1324 # define RB_XSEL2(x) ((x) << 4) 1252 1325 # define RB_XSEL2_MASK (0x3 << 4) 1253 1326 # define RB_XSEL (1 << 6) 1254 1327 # define RB_YSEL (1 << 7) 1255 1328 # define PKR_MAP(x) ((x) << 8) 1256 - # define PKR_MAP_MASK (0x3 << 8) 1257 - # define RASTER_CONFIG_PKR_MAP_0 0 1258 - # define RASTER_CONFIG_PKR_MAP_1 1 1259 - # define RASTER_CONFIG_PKR_MAP_2 2 1260 - # define RASTER_CONFIG_PKR_MAP_3 3 1261 1329 # define PKR_XSEL(x) ((x) << 10) 1262 1330 # define PKR_XSEL_MASK (0x3 << 10) 1263 1331 # define PKR_YSEL(x) ((x) << 12) ··· 1180 1426 # define SC_YSEL(x) ((x) << 20) 1181 1427 # define SC_YSEL_MASK (0x3 << 20) 1182 1428 # define SE_MAP(x) ((x) << 24) 1183 - # define SE_MAP_MASK (0x3 << 24) 1184 - # define RASTER_CONFIG_SE_MAP_0 0 1185 - # define RASTER_CONFIG_SE_MAP_1 1 1186 - # define RASTER_CONFIG_SE_MAP_2 2 1187 - # define RASTER_CONFIG_SE_MAP_3 3 1188 1429 # define SE_XSEL(x) ((x) << 26) 1189 1430 # define SE_XSEL_MASK (0x3 << 26) 1190 1431 # define SE_YSEL(x) ((x) << 28) 1191 1432 # define SE_YSEL_MASK (0x3 << 28) 1192 - 1193 - 1194 - #define VGT_EVENT_INITIATOR 0xA2A4 1195 - # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1196 - # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 1197 - # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 1198 - # define CACHE_FLUSH_TS (4 << 0) 1199 - # define CACHE_FLUSH (6 << 0) 1200 - # define CS_PARTIAL_FLUSH (7 << 0) 1201 - # define VGT_STREAMOUT_RESET (10 << 0) 1202 - # define END_OF_PIPE_INCR_DE (11 << 0) 1203 - # define END_OF_PIPE_IB_END (12 << 0) 1204 - # define RST_PIX_CNT (13 << 0) 1205 - # define VS_PARTIAL_FLUSH (15 << 0) 1206 - # define PS_PARTIAL_FLUSH (16 << 0) 1207 - # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 1208 - # define ZPASS_DONE (21 << 0) 1209 - # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 1210 - # define PERFCOUNTER_START (23 << 0) 1211 - # define PERFCOUNTER_STOP (24 << 0) 1212 - # define PIPELINESTAT_START (25 << 0) 1213 - # define PIPELINESTAT_STOP (26 << 0) 1214 - # define PERFCOUNTER_SAMPLE (27 << 0) 1215 - # define SAMPLE_PIPELINESTAT (30 << 0) 1216 - # define SAMPLE_STREAMOUTSTATS (32 << 0) 1217 - # define RESET_VTX_CNT (33 << 0) 1218 - # define VGT_FLUSH (36 << 0) 1219 - # define BOTTOM_OF_PIPE_TS (40 << 0) 1220 - # define DB_CACHE_FLUSH_AND_INV (42 << 0) 1221 - # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 1222 - # define FLUSH_AND_INV_DB_META (44 << 0) 1223 - # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 1224 - # define FLUSH_AND_INV_CB_META (46 << 0) 1225 - # define CS_DONE (47 << 0) 1226 - # define PS_DONE (48 << 0) 1227 - # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 1228 - # define THREAD_TRACE_START (51 << 0) 1229 - # define THREAD_TRACE_STOP (52 << 0) 1230 - # define THREAD_TRACE_FLUSH (54 << 0) 1231 - # define THREAD_TRACE_FINISH (55 << 0) 1232 1433 1233 1434 /* PIF PHY0 registers idx/data 0x8/0xc */ 1234 1435 #define PB0_PIF_CNTL 0x10 ··· 1700 1991 1701 1992 //#dce stupp 1702 1993 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 1703 - #define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/4 1704 - #define SI_CRTC1_REGISTER_OFFSET 0x300 //(0x79f0 - 0x6df0)/4 1705 - #define SI_CRTC2_REGISTER_OFFSET 0x2600 //(0x105f0 - 0x6df0)/4 1706 - #define SI_CRTC3_REGISTER_OFFSET 0x2900 //(0x111f0 - 0x6df0)/4 1707 - #define SI_CRTC4_REGISTER_OFFSET 0x2c00 //(0x11df0 - 0x6df0)/4 1708 - #define SI_CRTC5_REGISTER_OFFSET 0x2f00 //(0x129f0 - 0x6df0)/4 1994 + #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4 1995 + #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4 1996 + #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4 1997 + #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4 1998 + #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4 1999 + #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4 2000 + 2001 + /* hpd instance offsets */ 2002 + #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 2003 + #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 2004 + #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 2005 + #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 2006 + #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 2007 + #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 2008 + 2009 + /* audio endpt instance offsets */ 2010 + #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780) 2011 + #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780) 2012 + #define AUD2_REGISTER_OFFSET (0x178c - 0x1780) 2013 + #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780) 2014 + #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780) 2015 + #define AUD5_REGISTER_OFFSET (0x179d - 0x1780) 2016 + #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780) 1709 2017 1710 2018 #define CURSOR_WIDTH 64 1711 2019 #define CURSOR_HEIGHT 64 ··· 1762 2036 #define EVERGREEN_DATA_FORMAT 0x1ac0 1763 2037 # define EVERGREEN_INTERLEAVE_EN (1 << 0) 1764 2038 1765 - #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 1766 - #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc 1767 - 1768 2039 #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) 1769 2040 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) 1770 2041 #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) ··· 1772 2049 1773 2050 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1847 1774 2051 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a47 1775 - 1776 - #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 1777 - #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 1778 - #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 1779 - #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 1780 - #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 1781 - #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 1782 - 1783 - #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 1784 - #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 1785 - #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 1786 - #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 1787 - #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 1788 - #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 1789 - 1790 - #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 1791 - #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 1792 - #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 1793 - #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 1794 - #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 1795 - #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 1796 - 1797 - #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 1798 - #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 1799 - 1800 - #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1 1801 2052 1802 2053 #define R600_D1GRPH_SWAP_CONTROL 0x1843 1803 2054 #define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) ··· 1795 2098 # define R600_SCK_OVERWRITE (1 << 1) 1796 2099 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 1797 2100 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 1798 - 1799 - #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 1800 2101 1801 2102 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 1802 2103 #define FMT_TRUNCATE_EN (1 << 0) ··· 2099 2404 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800 2100 2405 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb 2101 2406 2102 - #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 2103 - #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 2104 - #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 2105 - #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 2106 - #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 2107 - #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 2108 - #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 2109 - #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 2110 - #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 2111 - #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 2112 - #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 2113 - #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 2114 - 2115 2407 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 2116 2408 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 2117 2409 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 ··· 2108 2426 #define MC_SEQ_MISC0__MT__HBM 0x60000000 2109 2427 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 2110 2428 2111 - #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 2112 2429 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2113 - #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 2114 - #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 2115 2430 #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 2116 2431 #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 2117 2432 #define PACKET3_SEM_SEL_WAIT (0x7 << 29)

+10 -11

drivers/gpu/drm/amd/amdgpu/soc15.c

··· 102 102 /* Vega */ 103 103 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 104 104 { 105 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 106 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 105 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 106 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 107 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 108 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 108 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 109 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 110 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 111 110 }; 112 111 113 112 static const struct amdgpu_video_codecs vega_video_codecs_decode = ··· 118 119 /* Raven */ 119 120 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 120 121 { 121 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 122 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 122 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 123 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 123 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 124 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 125 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 125 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 126 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 127 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)}, 127 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 128 129 }; 129 130 ··· 136 137 /* Renoir, Arcturus */ 137 138 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 138 139 { 139 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 140 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 140 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 141 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 141 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 142 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 143 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 143 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 144 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 145 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},

+2 -8

drivers/gpu/drm/amd/amdgpu/soc21.c

··· 117 117 }; 118 118 119 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 121 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 122 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 123 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 124 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 125 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 122 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 126 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 127 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 128 125 }; 129 126 130 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 131 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 132 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 133 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 134 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 135 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 136 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 130 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 137 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 138 132 }; 139 133

+1 -1

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

··· 284 284 return 0; 285 285 } 286 286 287 - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCN); 287 + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE); 288 288 if (!ip_block) 289 289 return -EINVAL; 290 290

+116 -4

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

··· 107 107 SOC15_IH_CLIENTID_VCN1 108 108 }; 109 109 110 + static void vcn_v2_5_idle_work_handler(struct work_struct *work) 111 + { 112 + struct amdgpu_vcn_inst *vcn_inst = 113 + container_of(work, struct amdgpu_vcn_inst, idle_work.work); 114 + struct amdgpu_device *adev = vcn_inst->adev; 115 + unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 116 + unsigned int i, j; 117 + int r = 0; 118 + 119 + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 120 + struct amdgpu_vcn_inst *v = &adev->vcn.inst[i]; 121 + 122 + if (adev->vcn.harvest_config & (1 << i)) 123 + continue; 124 + 125 + for (j = 0; j < v->num_enc_rings; ++j) 126 + fence[i] += amdgpu_fence_count_emitted(&v->ring_enc[j]); 127 + 128 + /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 129 + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 130 + !v->using_unified_queue) { 131 + struct dpg_pause_state new_state; 132 + 133 + if (fence[i] || 134 + unlikely(atomic_read(&v->dpg_enc_submission_cnt))) 135 + new_state.fw_based = VCN_DPG_STATE__PAUSE; 136 + else 137 + new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 138 + 139 + v->pause_dpg_mode(v, &new_state); 140 + } 141 + 142 + fence[i] += amdgpu_fence_count_emitted(&v->ring_dec); 143 + fences += fence[i]; 144 + 145 + } 146 + 147 + if (!fences && !atomic_read(&adev->vcn.inst[0].total_submission_cnt)) { 148 + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 149 + AMD_PG_STATE_GATE); 150 + r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 151 + false); 152 + if (r) 153 + dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 154 + } else { 155 + schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT); 156 + } 157 + } 158 + 159 + static void vcn_v2_5_ring_begin_use(struct amdgpu_ring *ring) 160 + { 161 + struct amdgpu_device *adev = ring->adev; 162 + struct amdgpu_vcn_inst *v = &adev->vcn.inst[ring->me]; 163 + int r = 0; 164 + 165 + atomic_inc(&adev->vcn.inst[0].total_submission_cnt); 166 + 167 + if (!cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work)) { 168 + r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 169 + true); 170 + if (r) 171 + dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 172 + } 173 + 174 + mutex_lock(&adev->vcn.inst[0].vcn_pg_lock); 175 + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 176 + AMD_PG_STATE_UNGATE); 177 + 178 + /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 179 + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 180 + !v->using_unified_queue) { 181 + struct dpg_pause_state new_state; 182 + 183 + if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 184 + atomic_inc(&v->dpg_enc_submission_cnt); 185 + new_state.fw_based = VCN_DPG_STATE__PAUSE; 186 + } else { 187 + unsigned int fences = 0; 188 + unsigned int i; 189 + 190 + for (i = 0; i < v->num_enc_rings; ++i) 191 + fences += amdgpu_fence_count_emitted(&v->ring_enc[i]); 192 + 193 + if (fences || atomic_read(&v->dpg_enc_submission_cnt)) 194 + new_state.fw_based = VCN_DPG_STATE__PAUSE; 195 + else 196 + new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 197 + } 198 + v->pause_dpg_mode(v, &new_state); 199 + } 200 + mutex_unlock(&adev->vcn.inst[0].vcn_pg_lock); 201 + } 202 + 203 + static void vcn_v2_5_ring_end_use(struct amdgpu_ring *ring) 204 + { 205 + struct amdgpu_device *adev = ring->adev; 206 + 207 + /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 208 + if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 209 + ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC && 210 + !adev->vcn.inst[ring->me].using_unified_queue) 211 + atomic_dec(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 212 + 213 + atomic_dec(&adev->vcn.inst[0].total_submission_cnt); 214 + 215 + schedule_delayed_work(&adev->vcn.inst[0].idle_work, 216 + VCN_IDLE_TIMEOUT); 217 + } 218 + 110 219 /** 111 220 * vcn_v2_5_early_init - set function pointers and load microcode 112 221 * ··· 309 200 r = amdgpu_vcn_sw_init(adev, j); 310 201 if (r) 311 202 return r; 203 + 204 + /* Override the work func */ 205 + adev->vcn.inst[j].idle_work.work.func = vcn_v2_5_idle_work_handler; 312 206 313 207 amdgpu_vcn_setup_ucode(adev, j); 314 208 ··· 1773 1661 .insert_start = vcn_v2_0_dec_ring_insert_start, 1774 1662 .insert_end = vcn_v2_0_dec_ring_insert_end, 1775 1663 .pad_ib = amdgpu_ring_generic_pad_ib, 1776 - .begin_use = amdgpu_vcn_ring_begin_use, 1777 - .end_use = amdgpu_vcn_ring_end_use, 1664 + .begin_use = vcn_v2_5_ring_begin_use, 1665 + .end_use = vcn_v2_5_ring_end_use, 1778 1666 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1779 1667 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1780 1668 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, ··· 1871 1759 .insert_nop = amdgpu_ring_insert_nop, 1872 1760 .insert_end = vcn_v2_0_enc_ring_insert_end, 1873 1761 .pad_ib = amdgpu_ring_generic_pad_ib, 1874 - .begin_use = amdgpu_vcn_ring_begin_use, 1875 - .end_use = amdgpu_vcn_ring_end_use, 1762 + .begin_use = vcn_v2_5_ring_begin_use, 1763 + .end_use = vcn_v2_5_ring_end_use, 1876 1764 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1877 1765 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1878 1766 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

+18 -25

drivers/gpu/drm/amd/amdgpu/vi.c

··· 167 167 { 168 168 { 169 169 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 170 - .max_width = 4096, 171 - .max_height = 4096, 172 - .max_pixels_per_frame = 4096 * 4096, 170 + .max_width = 1920, 171 + .max_height = 1088, 172 + .max_pixels_per_frame = 1920 * 1088, 173 173 .max_level = 3, 174 174 }, 175 175 { 176 176 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 177 - .max_width = 4096, 178 - .max_height = 4096, 179 - .max_pixels_per_frame = 4096 * 4096, 177 + .max_width = 1920, 178 + .max_height = 1088, 179 + .max_pixels_per_frame = 1920 * 1088, 180 180 .max_level = 5, 181 181 }, 182 182 { ··· 188 188 }, 189 189 { 190 190 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 191 - .max_width = 4096, 192 - .max_height = 4096, 193 - .max_pixels_per_frame = 4096 * 4096, 191 + .max_width = 1920, 192 + .max_height = 1088, 193 + .max_pixels_per_frame = 1920 * 1088, 194 194 .max_level = 4, 195 195 }, 196 196 }; ··· 206 206 { 207 207 { 208 208 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 209 - .max_width = 4096, 210 - .max_height = 4096, 211 - .max_pixels_per_frame = 4096 * 4096, 209 + .max_width = 1920, 210 + .max_height = 1088, 211 + .max_pixels_per_frame = 1920 * 1088, 212 212 .max_level = 3, 213 213 }, 214 214 { 215 215 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 216 - .max_width = 4096, 217 - .max_height = 4096, 218 - .max_pixels_per_frame = 4096 * 4096, 216 + .max_width = 1920, 217 + .max_height = 1088, 218 + .max_pixels_per_frame = 1920 * 1088, 219 219 .max_level = 5, 220 220 }, 221 221 { ··· 227 227 }, 228 228 { 229 229 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 230 - .max_width = 4096, 231 - .max_height = 4096, 232 - .max_pixels_per_frame = 4096 * 4096, 230 + .max_width = 1920, 231 + .max_height = 1088, 232 + .max_pixels_per_frame = 1920 * 1088, 233 233 .max_level = 4, 234 234 }, 235 235 { ··· 238 238 .max_height = 4096, 239 239 .max_pixels_per_frame = 4096 * 4096, 240 240 .max_level = 186, 241 - }, 242 - { 243 - .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 244 - .max_width = 4096, 245 - .max_height = 4096, 246 - .max_pixels_per_frame = 4096 * 4096, 247 - .max_level = 0, 248 241 }, 249 242 }; 250 243

+373 -330

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h

··· 3644 3644 }; 3645 3645 3646 3646 static const uint32_t cwsr_trap_gfx12_hex[] = { 3647 - 0xbfa00001, 0xbfa0024b, 3647 + 0xbfa00001, 0xbfa002a2, 3648 3648 0xb0804009, 0xb8f8f804, 3649 3649 0x9178ff78, 0x00008c00, 3650 3650 0xb8fbf811, 0x8b6eff78, ··· 3718 3718 0x00011677, 0xd7610000, 3719 3719 0x00011a79, 0xd7610000, 3720 3720 0x00011c7e, 0xd7610000, 3721 - 0x00011e7f, 0xbefe00ff, 3721 + 0x00011e7f, 0xd8500000, 3722 + 0x00000000, 0xd8500000, 3723 + 0x00000000, 0xd8500000, 3724 + 0x00000000, 0xd8500000, 3725 + 0x00000000, 0xd8500000, 3726 + 0x00000000, 0xd8500000, 3727 + 0x00000000, 0xd8500000, 3728 + 0x00000000, 0xd8500000, 3729 + 0x00000000, 0xbefe00ff, 3722 3730 0x00003fff, 0xbeff0080, 3723 3731 0xee0a407a, 0x000c0000, 3724 3732 0x00004000, 0xd760007a, ··· 3763 3755 0x00000200, 0xbef600ff, 3764 3756 0x01000000, 0x7e000280, 3765 3757 0x7e020280, 0x7e040280, 3766 - 0xbefd0080, 0xbe804ec2, 3767 - 0xbf94fffe, 0xb8faf804, 3768 - 0x8b7a847a, 0x91788478, 3769 - 0x8c787a78, 0xd7610002, 3770 - 0x0000fa71, 0x807d817d, 3771 - 0xd7610002, 0x0000fa6c, 3772 - 0x807d817d, 0x917aff6d, 3773 - 0x80000000, 0xd7610002, 3774 - 0x0000fa7a, 0x807d817d, 3775 - 0xd7610002, 0x0000fa6e, 3776 - 0x807d817d, 0xd7610002, 3777 - 0x0000fa6f, 0x807d817d, 3778 - 0xd7610002, 0x0000fa78, 3779 - 0x807d817d, 0xb8faf811, 3780 - 0xd7610002, 0x0000fa7a, 3781 - 0x807d817d, 0xd7610002, 3782 - 0x0000fa7b, 0x807d817d, 3783 - 0xb8f1f801, 0xd7610002, 3784 - 0x0000fa71, 0x807d817d, 3785 - 0xb8f1f814, 0xd7610002, 3786 - 0x0000fa71, 0x807d817d, 3787 - 0xb8f1f815, 0xd7610002, 3788 - 0x0000fa71, 0x807d817d, 3789 - 0xb8f1f812, 0xd7610002, 3790 - 0x0000fa71, 0x807d817d, 3791 - 0xb8f1f813, 0xd7610002, 3792 - 0x0000fa71, 0x807d817d, 3758 + 0xbe804ec2, 0xbf94fffe, 3759 + 0xb8faf804, 0x8b7a847a, 3760 + 0x91788478, 0x8c787a78, 3761 + 0x917aff6d, 0x80000000, 3762 + 0xd7610002, 0x00010071, 3763 + 0xd7610002, 0x0001026c, 3764 + 0xd7610002, 0x0001047a, 3765 + 0xd7610002, 0x0001066e, 3766 + 0xd7610002, 0x0001086f, 3767 + 0xd7610002, 0x00010a78, 3768 + 0xd7610002, 0x00010e7b, 3769 + 0xd8500000, 0x00000000, 3770 + 0xd8500000, 0x00000000, 3771 + 0xd8500000, 0x00000000, 3772 + 0xd8500000, 0x00000000, 3773 + 0xd8500000, 0x00000000, 3774 + 0xd8500000, 0x00000000, 3775 + 0xd8500000, 0x00000000, 3776 + 0xd8500000, 0x00000000, 3777 + 0xb8faf811, 0xd7610002, 3778 + 0x00010c7a, 0xb8faf801, 3779 + 0xd7610002, 0x0001107a, 3780 + 0xb8faf814, 0xd7610002, 3781 + 0x0001127a, 0xb8faf815, 3782 + 0xd7610002, 0x0001147a, 3783 + 0xb8faf812, 0xd7610002, 3784 + 0x0001167a, 0xb8faf813, 3785 + 0xd7610002, 0x0001187a, 3793 3786 0xb8faf802, 0xd7610002, 3794 - 0x0000fa7a, 0x807d817d, 3795 - 0xbefa50c1, 0xbfc70000, 3796 - 0xd7610002, 0x0000fa7a, 3797 - 0x807d817d, 0xbefe00ff, 3787 + 0x00011a7a, 0xbefa50c1, 3788 + 0xbfc70000, 0xd7610002, 3789 + 0x00011c7a, 0xd8500000, 3790 + 0x00000000, 0xd8500000, 3791 + 0x00000000, 0xd8500000, 3792 + 0x00000000, 0xd8500000, 3793 + 0x00000000, 0xd8500000, 3794 + 0x00000000, 0xd8500000, 3795 + 0x00000000, 0xd8500000, 3796 + 0x00000000, 0xd8500000, 3797 + 0x00000000, 0xbefe00ff, 3798 3798 0x0000ffff, 0xbeff0080, 3799 3799 0xc4068070, 0x008ce802, 3800 3800 0x00000000, 0xbefe00c1, ··· 3817 3801 0xbe824102, 0xbe844104, 3818 3802 0xbe864106, 0xbe884108, 3819 3803 0xbe8a410a, 0xbe8c410c, 3820 - 0xbe8e410e, 0xd7610002, 3821 - 0x0000f200, 0x80798179, 3822 - 0xd7610002, 0x0000f201, 3823 - 0x80798179, 0xd7610002, 3824 - 0x0000f202, 0x80798179, 3825 - 0xd7610002, 0x0000f203, 3826 - 0x80798179, 0xd7610002, 3827 - 0x0000f204, 0x80798179, 3828 - 0xd7610002, 0x0000f205, 3829 - 0x80798179, 0xd7610002, 3830 - 0x0000f206, 0x80798179, 3831 - 0xd7610002, 0x0000f207, 3832 - 0x80798179, 0xd7610002, 3833 - 0x0000f208, 0x80798179, 3834 - 0xd7610002, 0x0000f209, 3835 - 0x80798179, 0xd7610002, 3836 - 0x0000f20a, 0x80798179, 3837 - 0xd7610002, 0x0000f20b, 3838 - 0x80798179, 0xd7610002, 3839 - 0x0000f20c, 0x80798179, 3840 - 0xd7610002, 0x0000f20d, 3841 - 0x80798179, 0xd7610002, 3842 - 0x0000f20e, 0x80798179, 3843 - 0xd7610002, 0x0000f20f, 3844 - 0x80798179, 0xbf06a079, 3845 - 0xbfa10007, 0xc4068070, 3846 - 0x008ce802, 0x00000000, 3847 - 0x8070ff70, 0x00000080, 3848 - 0xbef90080, 0x7e040280, 3849 - 0x807d907d, 0xbf0aff7d, 3850 - 0x00000060, 0xbfa2ffbb, 3851 - 0xbe804100, 0xbe824102, 3852 - 0xbe844104, 0xbe864106, 3853 - 0xbe884108, 0xbe8a410a, 3854 - 0xd7610002, 0x0000f200, 3855 - 0x80798179, 0xd7610002, 3856 - 0x0000f201, 0x80798179, 3857 - 0xd7610002, 0x0000f202, 3858 - 0x80798179, 0xd7610002, 3859 - 0x0000f203, 0x80798179, 3860 - 0xd7610002, 0x0000f204, 3861 - 0x80798179, 0xd7610002, 3862 - 0x0000f205, 0x80798179, 3863 - 0xd7610002, 0x0000f206, 3864 - 0x80798179, 0xd7610002, 3865 - 0x0000f207, 0x80798179, 3866 - 0xd7610002, 0x0000f208, 3867 - 0x80798179, 0xd7610002, 3868 - 0x0000f209, 0x80798179, 3869 - 0xd7610002, 0x0000f20a, 3870 - 0x80798179, 0xd7610002, 3871 - 0x0000f20b, 0x80798179, 3804 + 0xbe8e410e, 0xbf068079, 3805 + 0xbfa10032, 0xd7610002, 3806 + 0x00010000, 0xd7610002, 3807 + 0x00010201, 0xd7610002, 3808 + 0x00010402, 0xd7610002, 3809 + 0x00010603, 0xd7610002, 3810 + 0x00010804, 0xd7610002, 3811 + 0x00010a05, 0xd7610002, 3812 + 0x00010c06, 0xd7610002, 3813 + 0x00010e07, 0xd7610002, 3814 + 0x00011008, 0xd7610002, 3815 + 0x00011209, 0xd7610002, 3816 + 0x0001140a, 0xd7610002, 3817 + 0x0001160b, 0xd7610002, 3818 + 0x0001180c, 0xd7610002, 3819 + 0x00011a0d, 0xd7610002, 3820 + 0x00011c0e, 0xd7610002, 3821 + 0x00011e0f, 0xd8500000, 3822 + 0x00000000, 0xd8500000, 3823 + 0x00000000, 0xd8500000, 3824 + 0x00000000, 0xd8500000, 3825 + 0x00000000, 0xd8500000, 3826 + 0x00000000, 0xd8500000, 3827 + 0x00000000, 0xd8500000, 3828 + 0x00000000, 0xd8500000, 3829 + 0x00000000, 0x80799079, 3830 + 0xbfa00038, 0xd7610002, 3831 + 0x00012000, 0xd7610002, 3832 + 0x00012201, 0xd7610002, 3833 + 0x00012402, 0xd7610002, 3834 + 0x00012603, 0xd7610002, 3835 + 0x00012804, 0xd7610002, 3836 + 0x00012a05, 0xd7610002, 3837 + 0x00012c06, 0xd7610002, 3838 + 0x00012e07, 0xd7610002, 3839 + 0x00013008, 0xd7610002, 3840 + 0x00013209, 0xd7610002, 3841 + 0x0001340a, 0xd7610002, 3842 + 0x0001360b, 0xd7610002, 3843 + 0x0001380c, 0xd7610002, 3844 + 0x00013a0d, 0xd7610002, 3845 + 0x00013c0e, 0xd7610002, 3846 + 0x00013e0f, 0xd8500000, 3847 + 0x00000000, 0xd8500000, 3848 + 0x00000000, 0xd8500000, 3849 + 0x00000000, 0xd8500000, 3850 + 0x00000000, 0xd8500000, 3851 + 0x00000000, 0xd8500000, 3852 + 0x00000000, 0xd8500000, 3853 + 0x00000000, 0xd8500000, 3854 + 0x00000000, 0x80799079, 3872 3855 0xc4068070, 0x008ce802, 3873 - 0x00000000, 0xbefe00c1, 3874 - 0x857d9973, 0x8b7d817d, 3875 - 0xbf06817d, 0xbfa20002, 3876 - 0xbeff0080, 0xbfa00001, 3877 - 0xbeff00c1, 0xb8fb4306, 3878 - 0x8b7bc17b, 0xbfa10044, 3879 - 0x8b7aff6d, 0x80000000, 3880 - 0xbfa10041, 0x847b897b, 3881 - 0xbef6007b, 0xb8f03b05, 3882 - 0x80708170, 0xbf0d9973, 3883 - 0xbfa20002, 0x84708970, 3884 - 0xbfa00001, 0x84708a70, 3885 - 0xb8fa1e06, 0x847a8a7a, 3886 - 0x80707a70, 0x8070ff70, 3887 - 0x00000200, 0x8070ff70, 3888 - 0x00000080, 0xbef600ff, 3889 - 0x01000000, 0xd71f0000, 3890 - 0x000100c1, 0xd7200000, 3891 - 0x000200c1, 0x16000084, 3892 - 0x857d9973, 0x8b7d817d, 3893 - 0xbf06817d, 0xbefd0080, 3894 - 0xbfa20013, 0xbe8300ff, 3895 - 0x00000080, 0xbf800000, 3896 - 0xbf800000, 0xbf800000, 3897 - 0xd8d80000, 0x01000000, 3898 - 0xbf8a0000, 0xc4068070, 3899 - 0x008ce801, 0x00000000, 3900 - 0x807d037d, 0x80700370, 3901 - 0xd5250000, 0x0001ff00, 3902 - 0x00000080, 0xbf0a7b7d, 3903 - 0xbfa2fff3, 0xbfa00012, 3904 - 0xbe8300ff, 0x00000100, 3856 + 0x00000000, 0x8070ff70, 3857 + 0x00000080, 0xbef90080, 3858 + 0x7e040280, 0x807d907d, 3859 + 0xbf0aff7d, 0x00000060, 3860 + 0xbfa2ff88, 0xbe804100, 3861 + 0xbe824102, 0xbe844104, 3862 + 0xbe864106, 0xbe884108, 3863 + 0xbe8a410a, 0xd7610002, 3864 + 0x00010000, 0xd7610002, 3865 + 0x00010201, 0xd7610002, 3866 + 0x00010402, 0xd7610002, 3867 + 0x00010603, 0xd7610002, 3868 + 0x00010804, 0xd7610002, 3869 + 0x00010a05, 0xd7610002, 3870 + 0x00010c06, 0xd7610002, 3871 + 0x00010e07, 0xd7610002, 3872 + 0x00011008, 0xd7610002, 3873 + 0x00011209, 0xd7610002, 3874 + 0x0001140a, 0xd7610002, 3875 + 0x0001160b, 0xd8500000, 3876 + 0x00000000, 0xd8500000, 3877 + 0x00000000, 0xd8500000, 3878 + 0x00000000, 0xd8500000, 3879 + 0x00000000, 0xd8500000, 3880 + 0x00000000, 0xd8500000, 3881 + 0x00000000, 0xd8500000, 3882 + 0x00000000, 0xd8500000, 3883 + 0x00000000, 0xc4068070, 3884 + 0x008ce802, 0x00000000, 3885 + 0xbefe00c1, 0x857d9973, 3886 + 0x8b7d817d, 0xbf06817d, 3887 + 0xbfa20002, 0xbeff0080, 3888 + 0xbfa00001, 0xbeff00c1, 3889 + 0xb8fb4306, 0x8b7bc17b, 3890 + 0xbfa10044, 0x8b7aff6d, 3891 + 0x80000000, 0xbfa10041, 3892 + 0x847b897b, 0xbef6007b, 3893 + 0xb8f03b05, 0x80708170, 3894 + 0xbf0d9973, 0xbfa20002, 3895 + 0x84708970, 0xbfa00001, 3896 + 0x84708a70, 0xb8fa1e06, 3897 + 0x847a8a7a, 0x80707a70, 3898 + 0x8070ff70, 0x00000200, 3899 + 0x8070ff70, 0x00000080, 3900 + 0xbef600ff, 0x01000000, 3901 + 0xd71f0000, 0x000100c1, 3902 + 0xd7200000, 0x000200c1, 3903 + 0x16000084, 0x857d9973, 3904 + 0x8b7d817d, 0xbf06817d, 3905 + 0xbefd0080, 0xbfa20013, 3906 + 0xbe8300ff, 0x00000080, 3905 3907 0xbf800000, 0xbf800000, 3906 3908 0xbf800000, 0xd8d80000, 3907 3909 0x01000000, 0xbf8a0000, 3908 3910 0xc4068070, 0x008ce801, 3909 3911 0x00000000, 0x807d037d, 3910 3912 0x80700370, 0xd5250000, 3911 - 0x0001ff00, 0x00000100, 3913 + 0x0001ff00, 0x00000080, 3912 3914 0xbf0a7b7d, 0xbfa2fff3, 3913 - 0xbefe00c1, 0x857d9973, 3914 - 0x8b7d817d, 0xbf06817d, 3915 - 0xbfa20004, 0xbef000ff, 3916 - 0x00000200, 0xbeff0080, 3917 - 0xbfa00003, 0xbef000ff, 3918 - 0x00000400, 0xbeff00c1, 3919 - 0xb8fb3b05, 0x807b817b, 3920 - 0x847b827b, 0x857d9973, 3921 - 0x8b7d817d, 0xbf06817d, 3922 - 0xbfa2001b, 0xbef600ff, 3923 - 0x01000000, 0xbefd0084, 3924 - 0xbf0a7b7d, 0xbfa10040, 3925 - 0x7e008700, 0x7e028701, 3926 - 0x7e048702, 0x7e068703, 3927 - 0xc4068070, 0x008ce800, 3928 - 0x00000000, 0xc4068070, 3929 - 0x008ce801, 0x00008000, 3930 - 0xc4068070, 0x008ce802, 3931 - 0x00010000, 0xc4068070, 3932 - 0x008ce803, 0x00018000, 3933 - 0x807d847d, 0x8070ff70, 3934 - 0x00000200, 0xbf0a7b7d, 3935 - 0xbfa2ffeb, 0xbfa0002a, 3915 + 0xbfa00012, 0xbe8300ff, 3916 + 0x00000100, 0xbf800000, 3917 + 0xbf800000, 0xbf800000, 3918 + 0xd8d80000, 0x01000000, 3919 + 0xbf8a0000, 0xc4068070, 3920 + 0x008ce801, 0x00000000, 3921 + 0x807d037d, 0x80700370, 3922 + 0xd5250000, 0x0001ff00, 3923 + 0x00000100, 0xbf0a7b7d, 3924 + 0xbfa2fff3, 0xbefe00c1, 3925 + 0x857d9973, 0x8b7d817d, 3926 + 0xbf06817d, 0xbfa20004, 3927 + 0xbef000ff, 0x00000200, 3928 + 0xbeff0080, 0xbfa00003, 3929 + 0xbef000ff, 0x00000400, 3930 + 0xbeff00c1, 0xb8fb3b05, 3931 + 0x807b817b, 0x847b827b, 3932 + 0x857d9973, 0x8b7d817d, 3933 + 0xbf06817d, 0xbfa2001b, 3936 3934 0xbef600ff, 0x01000000, 3937 3935 0xbefd0084, 0xbf0a7b7d, 3938 - 0xbfa10015, 0x7e008700, 3936 + 0xbfa10040, 0x7e008700, 3939 3937 0x7e028701, 0x7e048702, 3940 3938 0x7e068703, 0xc4068070, 3941 3939 0x008ce800, 0x00000000, 3942 3940 0xc4068070, 0x008ce801, 3943 - 0x00010000, 0xc4068070, 3944 - 0x008ce802, 0x00020000, 3941 + 0x00008000, 0xc4068070, 3942 + 0x008ce802, 0x00010000, 3945 3943 0xc4068070, 0x008ce803, 3946 - 0x00030000, 0x807d847d, 3947 - 0x8070ff70, 0x00000400, 3944 + 0x00018000, 0x807d847d, 3945 + 0x8070ff70, 0x00000200, 3948 3946 0xbf0a7b7d, 0xbfa2ffeb, 3949 - 0xb8fb1e06, 0x8b7bc17b, 3950 - 0xbfa1000d, 0x847b837b, 3951 - 0x807b7d7b, 0xbefe00c1, 3952 - 0xbeff0080, 0x7e008700, 3947 + 0xbfa0002a, 0xbef600ff, 3948 + 0x01000000, 0xbefd0084, 3949 + 0xbf0a7b7d, 0xbfa10015, 3950 + 0x7e008700, 0x7e028701, 3951 + 0x7e048702, 0x7e068703, 3953 3952 0xc4068070, 0x008ce800, 3954 - 0x00000000, 0x807d817d, 3955 - 0x8070ff70, 0x00000080, 3956 - 0xbf0a7b7d, 0xbfa2fff7, 3957 - 0xbfa0016e, 0xbef4007e, 3958 - 0x8b75ff7f, 0x0000ffff, 3959 - 0x8c75ff75, 0x00040000, 3960 - 0xbef60080, 0xbef700ff, 3961 - 0x10807fac, 0xbef1007f, 3962 - 0xb8f20742, 0x84729972, 3963 - 0x8b6eff7f, 0x04000000, 3964 - 0xbfa1003b, 0xbefe00c1, 3965 - 0x857d9972, 0x8b7d817d, 3966 - 0xbf06817d, 0xbfa20002, 3967 - 0xbeff0080, 0xbfa00001, 3968 - 0xbeff00c1, 0xb8ef4306, 3969 - 0x8b6fc16f, 0xbfa10030, 3970 - 0x846f896f, 0xbef6006f, 3953 + 0x00000000, 0xc4068070, 3954 + 0x008ce801, 0x00010000, 3955 + 0xc4068070, 0x008ce802, 3956 + 0x00020000, 0xc4068070, 3957 + 0x008ce803, 0x00030000, 3958 + 0x807d847d, 0x8070ff70, 3959 + 0x00000400, 0xbf0a7b7d, 3960 + 0xbfa2ffeb, 0xb8fb1e06, 3961 + 0x8b7bc17b, 0xbfa1000d, 3962 + 0x847b837b, 0x807b7d7b, 3963 + 0xbefe00c1, 0xbeff0080, 3964 + 0x7e008700, 0xc4068070, 3965 + 0x008ce800, 0x00000000, 3966 + 0x807d817d, 0x8070ff70, 3967 + 0x00000080, 0xbf0a7b7d, 3968 + 0xbfa2fff7, 0xbfa0016e, 3969 + 0xbef4007e, 0x8b75ff7f, 3970 + 0x0000ffff, 0x8c75ff75, 3971 + 0x00040000, 0xbef60080, 3972 + 0xbef700ff, 0x10807fac, 3973 + 0xbef1007f, 0xb8f20742, 3974 + 0x84729972, 0x8b6eff7f, 3975 + 0x04000000, 0xbfa1003b, 3976 + 0xbefe00c1, 0x857d9972, 3977 + 0x8b7d817d, 0xbf06817d, 3978 + 0xbfa20002, 0xbeff0080, 3979 + 0xbfa00001, 0xbeff00c1, 3980 + 0xb8ef4306, 0x8b6fc16f, 3981 + 0xbfa10030, 0x846f896f, 3982 + 0xbef6006f, 0xb8f83b05, 3983 + 0x80788178, 0xbf0d9972, 3984 + 0xbfa20002, 0x84788978, 3985 + 0xbfa00001, 0x84788a78, 3986 + 0xb8ee1e06, 0x846e8a6e, 3987 + 0x80786e78, 0x8078ff78, 3988 + 0x00000200, 0x8078ff78, 3989 + 0x00000080, 0xbef600ff, 3990 + 0x01000000, 0x857d9972, 3991 + 0x8b7d817d, 0xbf06817d, 3992 + 0xbefd0080, 0xbfa2000d, 3993 + 0xc4050078, 0x0080e800, 3994 + 0x00000000, 0xbf8a0000, 3995 + 0xdac00000, 0x00000000, 3996 + 0x807dff7d, 0x00000080, 3997 + 0x8078ff78, 0x00000080, 3998 + 0xbf0a6f7d, 0xbfa2fff4, 3999 + 0xbfa0000c, 0xc4050078, 4000 + 0x0080e800, 0x00000000, 4001 + 0xbf8a0000, 0xdac00000, 4002 + 0x00000000, 0x807dff7d, 4003 + 0x00000100, 0x8078ff78, 4004 + 0x00000100, 0xbf0a6f7d, 4005 + 0xbfa2fff4, 0xbef80080, 4006 + 0xbefe00c1, 0x857d9972, 4007 + 0x8b7d817d, 0xbf06817d, 4008 + 0xbfa20002, 0xbeff0080, 4009 + 0xbfa00001, 0xbeff00c1, 4010 + 0xb8ef3b05, 0x806f816f, 4011 + 0x846f826f, 0x857d9972, 4012 + 0x8b7d817d, 0xbf06817d, 4013 + 0xbfa2002c, 0xbef600ff, 4014 + 0x01000000, 0xbeee0078, 4015 + 0x8078ff78, 0x00000200, 4016 + 0xbefd0084, 0xbf0a6f7d, 4017 + 0xbfa10061, 0xc4050078, 4018 + 0x008ce800, 0x00000000, 4019 + 0xc4050078, 0x008ce801, 4020 + 0x00008000, 0xc4050078, 4021 + 0x008ce802, 0x00010000, 4022 + 0xc4050078, 0x008ce803, 4023 + 0x00018000, 0xbf8a0000, 4024 + 0x7e008500, 0x7e028501, 4025 + 0x7e048502, 0x7e068503, 4026 + 0x807d847d, 0x8078ff78, 4027 + 0x00000200, 0xbf0a6f7d, 4028 + 0xbfa2ffea, 0xc405006e, 4029 + 0x008ce800, 0x00000000, 4030 + 0xc405006e, 0x008ce801, 4031 + 0x00008000, 0xc405006e, 4032 + 0x008ce802, 0x00010000, 4033 + 0xc405006e, 0x008ce803, 4034 + 0x00018000, 0xbf8a0000, 4035 + 0xbfa0003d, 0xbef600ff, 4036 + 0x01000000, 0xbeee0078, 4037 + 0x8078ff78, 0x00000400, 4038 + 0xbefd0084, 0xbf0a6f7d, 4039 + 0xbfa10016, 0xc4050078, 4040 + 0x008ce800, 0x00000000, 4041 + 0xc4050078, 0x008ce801, 4042 + 0x00010000, 0xc4050078, 4043 + 0x008ce802, 0x00020000, 4044 + 0xc4050078, 0x008ce803, 4045 + 0x00030000, 0xbf8a0000, 4046 + 0x7e008500, 0x7e028501, 4047 + 0x7e048502, 0x7e068503, 4048 + 0x807d847d, 0x8078ff78, 4049 + 0x00000400, 0xbf0a6f7d, 4050 + 0xbfa2ffea, 0xb8ef1e06, 4051 + 0x8b6fc16f, 0xbfa1000f, 4052 + 0x846f836f, 0x806f7d6f, 4053 + 0xbefe00c1, 0xbeff0080, 4054 + 0xc4050078, 0x008ce800, 4055 + 0x00000000, 0xbf8a0000, 4056 + 0x7e008500, 0x807d817d, 4057 + 0x8078ff78, 0x00000080, 4058 + 0xbf0a6f7d, 0xbfa2fff6, 4059 + 0xbeff00c1, 0xc405006e, 4060 + 0x008ce800, 0x00000000, 4061 + 0xc405006e, 0x008ce801, 4062 + 0x00010000, 0xc405006e, 4063 + 0x008ce802, 0x00020000, 4064 + 0xc405006e, 0x008ce803, 4065 + 0x00030000, 0xbf8a0000, 3971 4066 0xb8f83b05, 0x80788178, 3972 4067 0xbf0d9972, 0xbfa20002, 3973 4068 0x84788978, 0xbfa00001, 3974 4069 0x84788a78, 0xb8ee1e06, 3975 4070 0x846e8a6e, 0x80786e78, 3976 4071 0x8078ff78, 0x00000200, 3977 - 0x8078ff78, 0x00000080, 4072 + 0x80f8ff78, 0x00000050, 3978 4073 0xbef600ff, 0x01000000, 3979 - 0x857d9972, 0x8b7d817d, 3980 - 0xbf06817d, 0xbefd0080, 3981 - 0xbfa2000d, 0xc4050078, 3982 - 0x0080e800, 0x00000000, 3983 - 0xbf8a0000, 0xdac00000, 3984 - 0x00000000, 0x807dff7d, 3985 - 0x00000080, 0x8078ff78, 3986 - 0x00000080, 0xbf0a6f7d, 3987 - 0xbfa2fff4, 0xbfa0000c, 3988 - 0xc4050078, 0x0080e800, 3989 - 0x00000000, 0xbf8a0000, 3990 - 0xdac00000, 0x00000000, 3991 - 0x807dff7d, 0x00000100, 3992 - 0x8078ff78, 0x00000100, 3993 - 0xbf0a6f7d, 0xbfa2fff4, 3994 - 0xbef80080, 0xbefe00c1, 3995 - 0x857d9972, 0x8b7d817d, 3996 - 0xbf06817d, 0xbfa20002, 3997 - 0xbeff0080, 0xbfa00001, 3998 - 0xbeff00c1, 0xb8ef3b05, 3999 - 0x806f816f, 0x846f826f, 4000 - 0x857d9972, 0x8b7d817d, 4001 - 0xbf06817d, 0xbfa2002c, 4002 - 0xbef600ff, 0x01000000, 4003 - 0xbeee0078, 0x8078ff78, 4004 - 0x00000200, 0xbefd0084, 4005 - 0xbf0a6f7d, 0xbfa10061, 4006 - 0xc4050078, 0x008ce800, 4007 - 0x00000000, 0xc4050078, 4008 - 0x008ce801, 0x00008000, 4009 - 0xc4050078, 0x008ce802, 4010 - 0x00010000, 0xc4050078, 4011 - 0x008ce803, 0x00018000, 4012 - 0xbf8a0000, 0x7e008500, 4013 - 0x7e028501, 0x7e048502, 4014 - 0x7e068503, 0x807d847d, 4015 - 0x8078ff78, 0x00000200, 4016 - 0xbf0a6f7d, 0xbfa2ffea, 4017 - 0xc405006e, 0x008ce800, 4018 - 0x00000000, 0xc405006e, 4019 - 0x008ce801, 0x00008000, 4020 - 0xc405006e, 0x008ce802, 4021 - 0x00010000, 0xc405006e, 4022 - 0x008ce803, 0x00018000, 4023 - 0xbf8a0000, 0xbfa0003d, 4024 - 0xbef600ff, 0x01000000, 4025 - 0xbeee0078, 0x8078ff78, 4026 - 0x00000400, 0xbefd0084, 4027 - 0xbf0a6f7d, 0xbfa10016, 4028 - 0xc4050078, 0x008ce800, 4029 - 0x00000000, 0xc4050078, 4030 - 0x008ce801, 0x00010000, 4031 - 0xc4050078, 0x008ce802, 4032 - 0x00020000, 0xc4050078, 4033 - 0x008ce803, 0x00030000, 4034 - 0xbf8a0000, 0x7e008500, 4035 - 0x7e028501, 0x7e048502, 4036 - 0x7e068503, 0x807d847d, 4037 - 0x8078ff78, 0x00000400, 4038 - 0xbf0a6f7d, 0xbfa2ffea, 4039 - 0xb8ef1e06, 0x8b6fc16f, 4040 - 0xbfa1000f, 0x846f836f, 4041 - 0x806f7d6f, 0xbefe00c1, 4042 - 0xbeff0080, 0xc4050078, 4043 - 0x008ce800, 0x00000000, 4044 - 0xbf8a0000, 0x7e008500, 4045 - 0x807d817d, 0x8078ff78, 4046 - 0x00000080, 0xbf0a6f7d, 4047 - 0xbfa2fff6, 0xbeff00c1, 4048 - 0xc405006e, 0x008ce800, 4049 - 0x00000000, 0xc405006e, 4050 - 0x008ce801, 0x00010000, 4051 - 0xc405006e, 0x008ce802, 4052 - 0x00020000, 0xc405006e, 4053 - 0x008ce803, 0x00030000, 4054 - 0xbf8a0000, 0xb8f83b05, 4055 - 0x80788178, 0xbf0d9972, 4056 - 0xbfa20002, 0x84788978, 4057 - 0xbfa00001, 0x84788a78, 4058 - 0xb8ee1e06, 0x846e8a6e, 4059 - 0x80786e78, 0x8078ff78, 4060 - 0x00000200, 0x80f8ff78, 4061 - 0x00000050, 0xbef600ff, 4062 - 0x01000000, 0xbefd00ff, 4063 - 0x0000006c, 0x80f89078, 4064 - 0xf462403a, 0xf0000000, 4065 - 0xbf8a0000, 0x80fd847d, 4066 - 0xbf800000, 0xbe804300, 4067 - 0xbe824302, 0x80f8a078, 4068 - 0xf462603a, 0xf0000000, 4069 - 0xbf8a0000, 0x80fd887d, 4070 - 0xbf800000, 0xbe804300, 4071 - 0xbe824302, 0xbe844304, 4072 - 0xbe864306, 0x80f8c078, 4073 - 0xf462803a, 0xf0000000, 4074 - 0xbf8a0000, 0x80fd907d, 4075 - 0xbf800000, 0xbe804300, 4076 - 0xbe824302, 0xbe844304, 4077 - 0xbe864306, 0xbe884308, 4078 - 0xbe8a430a, 0xbe8c430c, 4079 - 0xbe8e430e, 0xbf06807d, 4080 - 0xbfa1fff0, 0xb980f801, 4081 - 0x00000000, 0xb8f83b05, 4082 - 0x80788178, 0xbf0d9972, 4083 - 0xbfa20002, 0x84788978, 4084 - 0xbfa00001, 0x84788a78, 4085 - 0xb8ee1e06, 0x846e8a6e, 4086 - 0x80786e78, 0x8078ff78, 4087 - 0x00000200, 0xbef600ff, 4088 - 0x01000000, 0xbeff0071, 4089 - 0xf4621bfa, 0xf0000000, 4090 - 0x80788478, 0xf4621b3a, 4091 - 0xf0000000, 0x80788478, 4092 - 0xf4621b7a, 0xf0000000, 4093 - 0x80788478, 0xf4621c3a, 4094 - 0xf0000000, 0x80788478, 4095 - 0xf4621c7a, 0xf0000000, 4096 - 0x80788478, 0xf4621eba, 4097 - 0xf0000000, 0x80788478, 4098 - 0xf4621efa, 0xf0000000, 4099 - 0x80788478, 0xf4621e7a, 4100 - 0xf0000000, 0x80788478, 4101 - 0xf4621cfa, 0xf0000000, 4102 - 0x80788478, 0xf4621bba, 4103 - 0xf0000000, 0x80788478, 4104 - 0xbf8a0000, 0xb96ef814, 4105 - 0xf4621bba, 0xf0000000, 4106 - 0x80788478, 0xbf8a0000, 4107 - 0xb96ef815, 0xf4621bba, 4108 - 0xf0000000, 0x80788478, 4109 - 0xbf8a0000, 0xb96ef812, 4110 - 0xf4621bba, 0xf0000000, 4111 - 0x80788478, 0xbf8a0000, 4112 - 0xb96ef813, 0x8b6eff7f, 4113 - 0x04000000, 0xbfa1000d, 4114 - 0x80788478, 0xf4621bba, 4115 - 0xf0000000, 0x80788478, 4116 - 0xbf8a0000, 0xbf0d806e, 4117 - 0xbfa10006, 0x856e906e, 4118 - 0x8b6e6e6e, 0xbfa10003, 4119 - 0xbe804ec1, 0x816ec16e, 4120 - 0xbfa0fffb, 0xbefd006f, 4121 - 0xbefe0070, 0xbeff0071, 4122 - 0xb97b2011, 0x857b867b, 4123 - 0xb97b0191, 0x857b827b, 4124 - 0xb97bba11, 0xb973f801, 4125 - 0xb8ee3b05, 0x806e816e, 4074 + 0xbefd00ff, 0x0000006c, 4075 + 0x80f89078, 0xf462403a, 4076 + 0xf0000000, 0xbf8a0000, 4077 + 0x80fd847d, 0xbf800000, 4078 + 0xbe804300, 0xbe824302, 4079 + 0x80f8a078, 0xf462603a, 4080 + 0xf0000000, 0xbf8a0000, 4081 + 0x80fd887d, 0xbf800000, 4082 + 0xbe804300, 0xbe824302, 4083 + 0xbe844304, 0xbe864306, 4084 + 0x80f8c078, 0xf462803a, 4085 + 0xf0000000, 0xbf8a0000, 4086 + 0x80fd907d, 0xbf800000, 4087 + 0xbe804300, 0xbe824302, 4088 + 0xbe844304, 0xbe864306, 4089 + 0xbe884308, 0xbe8a430a, 4090 + 0xbe8c430c, 0xbe8e430e, 4091 + 0xbf06807d, 0xbfa1fff0, 4092 + 0xb980f801, 0x00000000, 4093 + 0xb8f83b05, 0x80788178, 4126 4094 0xbf0d9972, 0xbfa20002, 4127 - 0x846e896e, 0xbfa00001, 4128 - 0x846e8a6e, 0xb8ef1e06, 4129 - 0x846f8a6f, 0x806e6f6e, 4130 - 0x806eff6e, 0x00000200, 4131 - 0x806e746e, 0x826f8075, 4132 - 0x8b6fff6f, 0x0000ffff, 4133 - 0xf4605c37, 0xf8000050, 4134 - 0xf4605d37, 0xf8000060, 4135 - 0xf4601e77, 0xf8000074, 4136 - 0xbf8a0000, 0x8b6dff6d, 4137 - 0x0000ffff, 0x8bfe7e7e, 4138 - 0x8bea6a6a, 0xb97af804, 4095 + 0x84788978, 0xbfa00001, 4096 + 0x84788a78, 0xb8ee1e06, 4097 + 0x846e8a6e, 0x80786e78, 4098 + 0x8078ff78, 0x00000200, 4099 + 0xbef600ff, 0x01000000, 4100 + 0xbeff0071, 0xf4621bfa, 4101 + 0xf0000000, 0x80788478, 4102 + 0xf4621b3a, 0xf0000000, 4103 + 0x80788478, 0xf4621b7a, 4104 + 0xf0000000, 0x80788478, 4105 + 0xf4621c3a, 0xf0000000, 4106 + 0x80788478, 0xf4621c7a, 4107 + 0xf0000000, 0x80788478, 4108 + 0xf4621eba, 0xf0000000, 4109 + 0x80788478, 0xf4621efa, 4110 + 0xf0000000, 0x80788478, 4111 + 0xf4621e7a, 0xf0000000, 4112 + 0x80788478, 0xf4621cfa, 4113 + 0xf0000000, 0x80788478, 4114 + 0xf4621bba, 0xf0000000, 4115 + 0x80788478, 0xbf8a0000, 4116 + 0xb96ef814, 0xf4621bba, 4117 + 0xf0000000, 0x80788478, 4118 + 0xbf8a0000, 0xb96ef815, 4119 + 0xf4621bba, 0xf0000000, 4120 + 0x80788478, 0xbf8a0000, 4121 + 0xb96ef812, 0xf4621bba, 4122 + 0xf0000000, 0x80788478, 4123 + 0xbf8a0000, 0xb96ef813, 4124 + 0x8b6eff7f, 0x04000000, 4125 + 0xbfa1000d, 0x80788478, 4126 + 0xf4621bba, 0xf0000000, 4127 + 0x80788478, 0xbf8a0000, 4128 + 0xbf0d806e, 0xbfa10006, 4129 + 0x856e906e, 0x8b6e6e6e, 4130 + 0xbfa10003, 0xbe804ec1, 4131 + 0x816ec16e, 0xbfa0fffb, 4132 + 0xbefd006f, 0xbefe0070, 4133 + 0xbeff0071, 0xb97b2011, 4134 + 0x857b867b, 0xb97b0191, 4135 + 0x857b827b, 0xb97bba11, 4136 + 0xb973f801, 0xb8ee3b05, 4137 + 0x806e816e, 0xbf0d9972, 4138 + 0xbfa20002, 0x846e896e, 4139 + 0xbfa00001, 0x846e8a6e, 4140 + 0xb8ef1e06, 0x846f8a6f, 4141 + 0x806e6f6e, 0x806eff6e, 4142 + 0x00000200, 0x806e746e, 4143 + 0x826f8075, 0x8b6fff6f, 4144 + 0x0000ffff, 0xf4605c37, 4145 + 0xf8000050, 0xf4605d37, 4146 + 0xf8000060, 0xf4601e77, 4147 + 0xf8000074, 0xbf8a0000, 4148 + 0x8b6dff6d, 0x0000ffff, 4149 + 0x8bfe7e7e, 0x8bea6a6a, 4150 + 0xb97af804, 0xbe804ec2, 4151 + 0xbf94fffe, 0xbe804a6c, 4139 4152 0xbe804ec2, 0xbf94fffe, 4140 - 0xbe804a6c, 0xbe804ec2, 4141 - 0xbf94fffe, 0xbfb10000, 4153 + 0xbfb10000, 0xbf9f0000, 4142 4154 0xbf9f0000, 0xbf9f0000, 4143 4155 0xbf9f0000, 0xbf9f0000, 4144 - 0xbf9f0000, 0x00000000, 4145 4156 }; 4146 4157 4147 4158 static const uint32_t cwsr_trap_gfx9_5_0_hex[] = {

+44 -38

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm

··· 30 30 #define CHIP_GFX12 37 31 31 32 32 #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised 33 + #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) 33 34 34 35 var SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK = 0x4 35 36 var SQ_WAVE_STATE_PRIV_SCC_SHIFT = 9 ··· 352 351 v_writelane_b32 v0, ttmp13, 0xD 353 352 v_writelane_b32 v0, exec_lo, 0xE 354 353 v_writelane_b32 v0, exec_hi, 0xF 354 + valu_sgpr_hazard() 355 355 356 356 s_mov_b32 exec_lo, 0x3FFF 357 357 s_mov_b32 exec_hi, 0x0 ··· 419 417 v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource 420 418 v_mov_b32 v1, 0x0 //Offset[63:32] from buffer resource 421 419 v_mov_b32 v2, 0x0 //Set of SGPRs for TCP store 422 - s_mov_b32 m0, 0x0 //Next lane of v2 to write to 423 420 424 421 // Ensure no further changes to barrier or LDS state. 425 422 // STATE_PRIV.BARRIER_COMPLETE may change up to this point. ··· 431 430 s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK 432 431 s_or_b32 s_save_state_priv, s_save_state_priv, s_save_tmp 433 432 434 - write_hwreg_to_v2(s_save_m0) 435 - write_hwreg_to_v2(s_save_pc_lo) 436 433 s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 437 - write_hwreg_to_v2(s_save_tmp) 438 - write_hwreg_to_v2(s_save_exec_lo) 439 - write_hwreg_to_v2(s_save_exec_hi) 440 - write_hwreg_to_v2(s_save_state_priv) 434 + v_writelane_b32 v2, s_save_m0, 0x0 435 + v_writelane_b32 v2, s_save_pc_lo, 0x1 436 + v_writelane_b32 v2, s_save_tmp, 0x2 437 + v_writelane_b32 v2, s_save_exec_lo, 0x3 438 + v_writelane_b32 v2, s_save_exec_hi, 0x4 439 + v_writelane_b32 v2, s_save_state_priv, 0x5 440 + v_writelane_b32 v2, s_save_xnack_mask, 0x7 441 + valu_sgpr_hazard() 441 442 442 443 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 443 - write_hwreg_to_v2(s_save_tmp) 444 + v_writelane_b32 v2, s_save_tmp, 0x6 444 445 445 - write_hwreg_to_v2(s_save_xnack_mask) 446 + s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_MODE) 447 + v_writelane_b32 v2, s_save_tmp, 0x8 446 448 447 - s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_MODE) 448 - write_hwreg_to_v2(s_save_m0) 449 + s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) 450 + v_writelane_b32 v2, s_save_tmp, 0x9 449 451 450 - s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) 451 - write_hwreg_to_v2(s_save_m0) 452 + s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) 453 + v_writelane_b32 v2, s_save_tmp, 0xA 452 454 453 - s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) 454 - write_hwreg_to_v2(s_save_m0) 455 + s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) 456 + v_writelane_b32 v2, s_save_tmp, 0xB 455 457 456 - s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) 457 - write_hwreg_to_v2(s_save_m0) 458 - 459 - s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_TRAP_CTRL) 460 - write_hwreg_to_v2(s_save_m0) 458 + s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_TRAP_CTRL) 459 + v_writelane_b32 v2, s_save_tmp, 0xC 461 460 462 461 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATUS) 463 - write_hwreg_to_v2(s_save_tmp) 462 + v_writelane_b32 v2, s_save_tmp, 0xD 464 463 465 464 s_get_barrier_state s_save_tmp, -1 466 465 s_wait_kmcnt (0) 467 - write_hwreg_to_v2(s_save_tmp) 466 + v_writelane_b32 v2, s_save_tmp, 0xE 467 + valu_sgpr_hazard() 468 468 469 469 // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. 470 470 s_mov_b32 exec_lo, 0xFFFF ··· 499 497 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 500 498 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 501 499 502 - write_16sgpr_to_v2(s0) 503 - 504 - s_cmp_eq_u32 ttmp13, 0x20 //have 32 VGPR lanes filled? 505 - s_cbranch_scc0 L_SAVE_SGPR_SKIP_TCP_STORE 500 + s_cmp_eq_u32 ttmp13, 0x0 501 + s_cbranch_scc0 L_WRITE_V2_SECOND_HALF 502 + write_16sgpr_to_v2(s0, 0x0) 503 + s_branch L_SAVE_SGPR_SKIP_TCP_STORE 504 + L_WRITE_V2_SECOND_HALF: 505 + write_16sgpr_to_v2(s0, 0x10) 506 506 507 507 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 508 508 s_add_u32 s_save_mem_offset, s_save_mem_offset, 0x80 ··· 1060 1056 s_endpgm_saved 1061 1057 end 1062 1058 1063 - function write_hwreg_to_v2(s) 1064 - // Copy into VGPR for later TCP store. 1065 - v_writelane_b32 v2, s, m0 1066 - s_add_u32 m0, m0, 0x1 1067 - end 1068 - 1069 - 1070 - function write_16sgpr_to_v2(s) 1059 + function write_16sgpr_to_v2(s, lane_offset) 1071 1060 // Copy into VGPR for later TCP store. 1072 1061 for var sgpr_idx = 0; sgpr_idx < 16; sgpr_idx ++ 1073 - v_writelane_b32 v2, s[sgpr_idx], ttmp13 1074 - s_add_u32 ttmp13, ttmp13, 0x1 1062 + v_writelane_b32 v2, s[sgpr_idx], sgpr_idx + lane_offset 1075 1063 end 1064 + valu_sgpr_hazard() 1065 + s_add_u32 ttmp13, ttmp13, 0x10 1076 1066 end 1077 1067 1078 1068 function write_12sgpr_to_v2(s) 1079 1069 // Copy into VGPR for later TCP store. 1080 1070 for var sgpr_idx = 0; sgpr_idx < 12; sgpr_idx ++ 1081 - v_writelane_b32 v2, s[sgpr_idx], ttmp13 1082 - s_add_u32 ttmp13, ttmp13, 0x1 1071 + v_writelane_b32 v2, s[sgpr_idx], sgpr_idx 1083 1072 end 1073 + valu_sgpr_hazard() 1084 1074 end 1085 1075 1086 1076 function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) ··· 1125 1127 function get_wave_size2(s_reg) 1126 1128 s_getreg_b32 s_reg, hwreg(HW_REG_WAVE_STATUS,SQ_WAVE_STATUS_WAVE64_SHIFT,SQ_WAVE_STATUS_WAVE64_SIZE) 1127 1129 s_lshl_b32 s_reg, s_reg, S_WAVE_SIZE 1130 + end 1131 + 1132 + function valu_sgpr_hazard 1133 + #if HAVE_VALU_SGPR_HAZARD 1134 + for var rep = 0; rep < 8; rep ++ 1135 + ds_nop 1136 + end 1137 + #endif 1128 1138 end

+6 -6

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

··· 357 357 return 0; 358 358 359 359 if (!pdd->proc_ctx_cpu_ptr) { 360 - r = amdgpu_amdkfd_alloc_gtt_mem(adev, 361 - AMDGPU_MES_PROC_CTX_SIZE, 362 - &pdd->proc_ctx_bo, 363 - &pdd->proc_ctx_gpu_addr, 364 - &pdd->proc_ctx_cpu_ptr, 365 - false); 360 + r = amdgpu_amdkfd_alloc_gtt_mem(adev, 361 + AMDGPU_MES_PROC_CTX_SIZE, 362 + &pdd->proc_ctx_bo, 363 + &pdd->proc_ctx_gpu_addr, 364 + &pdd->proc_ctx_cpu_ptr, 365 + false); 366 366 if (r) { 367 367 dev_err(adev->dev, 368 368 "failed to allocate process context bo\n");

+24 -29

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

··· 43 43 /* Size of the per-pipe EOP queue */ 44 44 #define CIK_HPD_EOP_BYTES_LOG2 11 45 45 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 46 + /* See unmap_queues_cpsch() */ 47 + #define USE_DEFAULT_GRACE_PERIOD 0xffffffff 46 48 47 49 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 48 50 u32 pasid, unsigned int vmid); ··· 1221 1219 decrement_queue_count(dqm, qpd, q); 1222 1220 1223 1221 if (dqm->dev->kfd->shared_resources.enable_mes) { 1224 - retval = remove_queue_mes(dqm, q, qpd); 1225 - if (retval) { 1222 + int err; 1223 + 1224 + err = remove_queue_mes(dqm, q, qpd); 1225 + if (err) { 1226 1226 dev_err(dev, "Failed to evict queue %d\n", 1227 1227 q->properties.queue_id); 1228 - goto out; 1228 + retval = err; 1229 1229 } 1230 1230 } 1231 1231 } ··· 1750 1746 1751 1747 init_sdma_bitmaps(dqm); 1752 1748 1753 - if (dqm->dev->kfd2kgd->get_iq_wait_times) 1754 - dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev, 1755 - &dqm->wait_times, 1756 - ffs(dqm->dev->xcc_mask) - 1); 1749 + update_dqm_wait_times(dqm); 1757 1750 return 0; 1758 1751 } 1759 1752 ··· 1846 1845 /* clear hang status when driver try to start the hw scheduler */ 1847 1846 dqm->sched_running = true; 1848 1847 1849 - if (!dqm->dev->kfd->shared_resources.enable_mes) 1848 + if (!dqm->dev->kfd->shared_resources.enable_mes) { 1849 + if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 1850 + KFD_DEQUEUE_WAIT_INIT, 0 /* unused */)) 1851 + dev_err(dev, "Setting optimized dequeue wait failed. Using default values\n"); 1850 1852 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1851 - 1852 - /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */ 1853 - if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu && 1854 - (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) { 1855 - uint32_t reg_offset = 0; 1856 - uint32_t grace_period = 1; 1857 - 1858 - retval = pm_update_grace_period(&dqm->packet_mgr, 1859 - grace_period); 1860 - if (retval) 1861 - dev_err(dev, "Setting grace timeout failed\n"); 1862 - else if (dqm->dev->kfd2kgd->build_grace_period_packet_info) 1863 - /* Update dqm->wait_times maintained in software */ 1864 - dqm->dev->kfd2kgd->build_grace_period_packet_info( 1865 - dqm->dev->adev, dqm->wait_times, 1866 - grace_period, &reg_offset, 1867 - &dqm->wait_times); 1868 1853 } 1869 1854 1870 1855 /* setup per-queue reset detection buffer */ ··· 2346 2359 return is_sdma ? reset_hung_queues_sdma(dqm) : reset_hung_queues(dqm); 2347 2360 } 2348 2361 2349 - /* dqm->lock mutex has to be locked before calling this function */ 2362 + /* dqm->lock mutex has to be locked before calling this function 2363 + * 2364 + * @grace_period: If USE_DEFAULT_GRACE_PERIOD then default wait time 2365 + * for context switch latency. Lower values are used by debugger 2366 + * since context switching are triggered at high frequency. 2367 + * This is configured by setting CP_IQ_WAIT_TIME2.SCH_WAVE 2368 + * 2369 + */ 2350 2370 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 2351 2371 enum kfd_unmap_queues_filter filter, 2352 2372 uint32_t filter_param, ··· 2372 2378 return -EIO; 2373 2379 2374 2380 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2375 - retval = pm_update_grace_period(&dqm->packet_mgr, grace_period); 2381 + retval = pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2382 + KFD_DEQUEUE_WAIT_SET_SCH_WAVE, grace_period); 2376 2383 if (retval) 2377 2384 goto out; 2378 2385 } ··· 2414 2419 2415 2420 /* We need to reset the grace period value for this device */ 2416 2421 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2417 - if (pm_update_grace_period(&dqm->packet_mgr, 2418 - USE_DEFAULT_GRACE_PERIOD)) 2422 + if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2423 + KFD_DEQUEUE_WAIT_RESET, 0 /* unused */)) 2419 2424 dev_err(dev, "Failed to reset grace period\n"); 2420 2425 } 2421 2426

+10 -1

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h

··· 37 37 38 38 #define KFD_MES_PROCESS_QUANTUM 100000 39 39 #define KFD_MES_GANG_QUANTUM 10000 40 - #define USE_DEFAULT_GRACE_PERIOD 0xffffffff 41 40 42 41 struct device_process_node { 43 42 struct qcm_process_device *qpd; ··· 359 360 /* SDMA activity counter is stored at queue's RPTR + 0x8 location. */ 360 361 return get_user(*val, q_rptr + 1); 361 362 } 363 + 364 + static inline void update_dqm_wait_times(struct device_queue_manager *dqm) 365 + { 366 + if (dqm->dev->kfd2kgd->get_iq_wait_times) 367 + dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev, 368 + &dqm->wait_times, 369 + ffs(dqm->dev->xcc_mask) - 1); 370 + } 371 + 372 + 362 373 #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */

+1 -2

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c

··· 71 71 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; 72 72 73 73 if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 3) || 74 - KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 4) || 75 - KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 5, 0)) 74 + KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 4)) 76 75 qpd->sh_mem_config |= (1 << SH_MEM_CONFIG__F8_MODE__SHIFT); 77 76 78 77 if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 5, 0)) {

+24 -3

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

··· 554 554 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 555 555 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 556 556 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 557 - if (amdgpu_sriov_vf(mm->dev->adev)) 557 + if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 558 558 m->cp_hqd_pq_doorbell_control |= 1 << 559 559 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 560 560 m->cp_mqd_stride_size = kfd_hiq_mqd_stride(mm->dev); ··· 667 667 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); 668 668 669 669 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 670 - 670 + if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 671 + m->cp_hqd_pq_doorbell_control |= 1 << 672 + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 671 673 m->cp_mqd_stride_size = offset; 672 674 673 675 /* ··· 729 727 m = get_mqd(mqd + size * xcc); 730 728 update_mqd(mm, m, q, minfo); 731 729 730 + if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 731 + m->cp_hqd_pq_doorbell_control |= 1 << 732 + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 732 733 update_cu_mask(mm, m, minfo, xcc); 733 734 734 735 if (q->format == KFD_QUEUE_FORMAT_AQL) { ··· 754 749 } 755 750 } 756 751 752 + static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 753 + struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 754 + struct queue_properties *qp, 755 + const void *mqd_src, 756 + const void *ctl_stack_src, u32 ctl_stack_size) 757 + { 758 + restore_mqd(mm, mqd, mqd_mem_obj, gart_addr, qp, mqd_src, ctl_stack_src, ctl_stack_size); 759 + if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) { 760 + struct v9_mqd *m; 761 + 762 + m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 763 + m->cp_hqd_pq_doorbell_control |= 1 << 764 + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 765 + } 766 + } 757 767 static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 758 768 enum kfd_preempt_type type, unsigned int timeout, 759 769 uint32_t pipe_id, uint32_t queue_id) ··· 903 883 mqd->is_occupied = kfd_is_occupied_cp; 904 884 mqd->get_checkpoint_info = get_checkpoint_info; 905 885 mqd->checkpoint_mqd = checkpoint_mqd; 906 - mqd->restore_mqd = restore_mqd; 907 886 mqd->mqd_size = sizeof(struct v9_mqd); 908 887 mqd->mqd_stride = mqd_stride_v9; 909 888 #if defined(CONFIG_DEBUG_FS) ··· 914 895 mqd->init_mqd = init_mqd_v9_4_3; 915 896 mqd->load_mqd = load_mqd_v9_4_3; 916 897 mqd->update_mqd = update_mqd_v9_4_3; 898 + mqd->restore_mqd = restore_mqd_v9_4_3; 917 899 mqd->destroy_mqd = destroy_mqd_v9_4_3; 918 900 mqd->get_wave_state = get_wave_state_v9_4_3; 919 901 } else { 920 902 mqd->init_mqd = init_mqd; 921 903 mqd->load_mqd = load_mqd; 922 904 mqd->update_mqd = update_mqd; 905 + mqd->restore_mqd = restore_mqd; 923 906 mqd->destroy_mqd = kfd_destroy_mqd_cp; 924 907 mqd->get_wave_state = get_wave_state; 925 908 }

+23 -3

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c

··· 396 396 return retval; 397 397 } 398 398 399 - int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period) 399 + /* pm_config_dequeue_wait_counts: Configure dequeue timer Wait Counts 400 + * by writing to CP_IQ_WAIT_TIME2 registers. 401 + * 402 + * @cmd: See emum kfd_config_dequeue_wait_counts_cmd definition 403 + * @value: Depends on the cmd. This parameter is unused for 404 + * KFD_DEQUEUE_WAIT_INIT and KFD_DEQUEUE_WAIT_RESET. For 405 + * KFD_DEQUEUE_WAIT_SET_SCH_WAVE it holds value to be set 406 + * 407 + */ 408 + int pm_config_dequeue_wait_counts(struct packet_manager *pm, 409 + enum kfd_config_dequeue_wait_counts_cmd cmd, 410 + uint32_t value) 400 411 { 401 412 struct kfd_node *node = pm->dqm->dev; 402 413 struct device *dev = node->adev->dev; 403 414 int retval = 0; 404 415 uint32_t *buffer, size; 405 416 406 - size = pm->pmf->set_grace_period_size; 417 + if (!pm->pmf->config_dequeue_wait_counts || 418 + !pm->pmf->config_dequeue_wait_counts_size) 419 + return 0; 420 + 421 + size = pm->pmf->config_dequeue_wait_counts_size; 407 422 408 423 mutex_lock(&pm->lock); 409 424 ··· 434 419 goto out; 435 420 } 436 421 437 - retval = pm->pmf->set_grace_period(pm, buffer, grace_period); 422 + retval = pm->pmf->config_dequeue_wait_counts(pm, buffer, 423 + cmd, value); 438 424 if (!retval) 439 425 retval = kq_submit_packet(pm->priv_queue); 440 426 else 441 427 kq_rollback_packet(pm->priv_queue); 442 428 } 429 + 430 + /* If default value is modified, cache that value in dqm->wait_times */ 431 + if (!retval && cmd == KFD_DEQUEUE_WAIT_INIT) 432 + update_dqm_wait_times(pm->dqm); 443 433 444 434 out: 445 435 mutex_unlock(&pm->lock);

+62 -14

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

··· 297 297 return 0; 298 298 } 299 299 300 - static int pm_set_grace_period_v9(struct packet_manager *pm, 300 + static inline void pm_build_dequeue_wait_counts_packet_info(struct packet_manager *pm, 301 + uint32_t sch_value, uint32_t que_sleep, uint32_t *reg_offset, 302 + uint32_t *reg_data) 303 + { 304 + pm->dqm->dev->kfd2kgd->build_dequeue_wait_counts_packet_info( 305 + pm->dqm->dev->adev, 306 + pm->dqm->wait_times, 307 + sch_value, 308 + que_sleep, 309 + reg_offset, 310 + reg_data); 311 + } 312 + 313 + static int pm_config_dequeue_wait_counts_v9(struct packet_manager *pm, 301 314 uint32_t *buffer, 302 - uint32_t grace_period) 315 + enum kfd_config_dequeue_wait_counts_cmd cmd, 316 + uint32_t value) 303 317 { 304 318 struct pm4_mec_write_data_mmio *packet; 305 319 uint32_t reg_offset = 0; 306 320 uint32_t reg_data = 0; 307 321 308 - pm->dqm->dev->kfd2kgd->build_grace_period_packet_info( 309 - pm->dqm->dev->adev, 310 - pm->dqm->wait_times, 311 - grace_period, 312 - &reg_offset, 313 - &reg_data); 322 + switch (cmd) { 323 + case KFD_DEQUEUE_WAIT_INIT: { 324 + uint32_t sch_wave = 0, que_sleep = 0; 325 + /* Reduce CP_IQ_WAIT_TIME2.QUE_SLEEP to 0x1 from default 0x40. 326 + * On a 1GHz machine this is roughly 1 microsecond, which is 327 + * about how long it takes to load data out of memory during 328 + * queue connect 329 + * QUE_SLEEP: Wait Count for Dequeue Retry. 330 + */ 331 + if (KFD_GC_VERSION(pm->dqm->dev) >= IP_VERSION(9, 4, 1) && 332 + KFD_GC_VERSION(pm->dqm->dev) < IP_VERSION(10, 0, 0)) { 333 + que_sleep = 1; 314 334 315 - if (grace_period == USE_DEFAULT_GRACE_PERIOD) 316 - reg_data = pm->dqm->wait_times; 335 + /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */ 336 + if (amdgpu_emu_mode == 0 && pm->dqm->dev->adev->gmc.is_app_apu && 337 + (KFD_GC_VERSION(pm->dqm->dev) == IP_VERSION(9, 4, 3))) 338 + sch_wave = 1; 339 + } else { 340 + return 0; 341 + } 342 + pm_build_dequeue_wait_counts_packet_info(pm, sch_wave, que_sleep, 343 + &reg_offset, &reg_data); 344 + 345 + break; 346 + } 347 + case KFD_DEQUEUE_WAIT_RESET: 348 + /* reg_data would be set to dqm->wait_times */ 349 + pm_build_dequeue_wait_counts_packet_info(pm, 0, 0, &reg_offset, &reg_data); 350 + break; 351 + 352 + case KFD_DEQUEUE_WAIT_SET_SCH_WAVE: 353 + /* The CP cannot handle value 0 and it will result in 354 + * an infinite grace period being set so set to 1 to prevent this. Also 355 + * avoid debugger API breakage as it sets 0 and expects a low value. 356 + */ 357 + if (!value) 358 + value = 1; 359 + pm_build_dequeue_wait_counts_packet_info(pm, value, 0, &reg_offset, &reg_data); 360 + break; 361 + default: 362 + pr_err("Invalid dequeue wait cmd\n"); 363 + return -EINVAL; 364 + } 317 365 318 366 packet = (struct pm4_mec_write_data_mmio *)buffer; 319 367 memset(buffer, 0, sizeof(struct pm4_mec_write_data_mmio)); ··· 463 415 .set_resources = pm_set_resources_v9, 464 416 .map_queues = pm_map_queues_v9, 465 417 .unmap_queues = pm_unmap_queues_v9, 466 - .set_grace_period = pm_set_grace_period_v9, 418 + .config_dequeue_wait_counts = pm_config_dequeue_wait_counts_v9, 467 419 .query_status = pm_query_status_v9, 468 420 .release_mem = NULL, 469 421 .map_process_size = sizeof(struct pm4_mes_map_process), ··· 471 423 .set_resources_size = sizeof(struct pm4_mes_set_resources), 472 424 .map_queues_size = sizeof(struct pm4_mes_map_queues), 473 425 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues), 474 - .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio), 426 + .config_dequeue_wait_counts_size = sizeof(struct pm4_mec_write_data_mmio), 475 427 .query_status_size = sizeof(struct pm4_mes_query_status), 476 428 .release_mem_size = 0, 477 429 }; ··· 482 434 .set_resources = pm_set_resources_v9, 483 435 .map_queues = pm_map_queues_v9, 484 436 .unmap_queues = pm_unmap_queues_v9, 485 - .set_grace_period = pm_set_grace_period_v9, 437 + .config_dequeue_wait_counts = pm_config_dequeue_wait_counts_v9, 486 438 .query_status = pm_query_status_v9, 487 439 .release_mem = NULL, 488 440 .map_process_size = sizeof(struct pm4_mes_map_process_aldebaran), ··· 490 442 .set_resources_size = sizeof(struct pm4_mes_set_resources), 491 443 .map_queues_size = sizeof(struct pm4_mes_map_queues), 492 444 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues), 493 - .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio), 445 + .config_dequeue_wait_counts_size = sizeof(struct pm4_mec_write_data_mmio), 494 446 .query_status_size = sizeof(struct pm4_mes_query_status), 495 447 .release_mem_size = 0, 496 448 };

+2 -2

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c

··· 304 304 .set_resources = pm_set_resources_vi, 305 305 .map_queues = pm_map_queues_vi, 306 306 .unmap_queues = pm_unmap_queues_vi, 307 - .set_grace_period = NULL, 307 + .config_dequeue_wait_counts = NULL, 308 308 .query_status = pm_query_status_vi, 309 309 .release_mem = pm_release_mem_vi, 310 310 .map_process_size = sizeof(struct pm4_mes_map_process), ··· 312 312 .set_resources_size = sizeof(struct pm4_mes_set_resources), 313 313 .map_queues_size = sizeof(struct pm4_mes_map_queues), 314 314 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues), 315 - .set_grace_period_size = 0, 315 + .config_dequeue_wait_counts_size = 0, 316 316 .query_status_size = sizeof(struct pm4_mes_query_status), 317 317 .release_mem_size = sizeof(struct pm4_mec_release_mem) 318 318 };

+24 -4

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

··· 1389 1389 #define KFD_FENCE_COMPLETED (100) 1390 1390 #define KFD_FENCE_INIT (10) 1391 1391 1392 + /** 1393 + * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring 1394 + * dequeue wait counts. 1395 + * 1396 + * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a 1397 + * certain ASICs. For these ASICs, this is default value used by RESET 1398 + * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value 1399 + * for certain ASICs. For others set it to default hardware reset value 1400 + * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait 1401 + * 1402 + */ 1403 + enum kfd_config_dequeue_wait_counts_cmd { 1404 + KFD_DEQUEUE_WAIT_INIT = 1, 1405 + KFD_DEQUEUE_WAIT_RESET = 2, 1406 + KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3 1407 + }; 1408 + 1409 + 1392 1410 struct packet_manager { 1393 1411 struct device_queue_manager *dqm; 1394 1412 struct kernel_queue *priv_queue; ··· 1432 1414 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1433 1415 enum kfd_unmap_queues_filter mode, 1434 1416 uint32_t filter_param, bool reset); 1435 - int (*set_grace_period)(struct packet_manager *pm, uint32_t *buffer, 1436 - uint32_t grace_period); 1417 + int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer, 1418 + enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value); 1437 1419 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1438 1420 uint64_t fence_address, uint64_t fence_value); 1439 1421 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); ··· 1444 1426 int set_resources_size; 1445 1427 int map_queues_size; 1446 1428 int unmap_queues_size; 1447 - int set_grace_period_size; 1429 + int config_dequeue_wait_counts_size; 1448 1430 int query_status_size; 1449 1431 int release_mem_size; 1450 1432 }; ··· 1467 1449 1468 1450 void pm_release_ib(struct packet_manager *pm); 1469 1451 1470 - int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period); 1452 + int pm_config_dequeue_wait_counts(struct packet_manager *pm, 1453 + enum kfd_config_dequeue_wait_counts_cmd cmd, 1454 + uint32_t wait_counts_config); 1471 1455 1472 1456 /* Following PM funcs can be shared among VI and AI */ 1473 1457 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);

+18 -21

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

··· 1287 1287 break; 1288 1288 case IP_VERSION(12, 0, 0): 1289 1289 case IP_VERSION(12, 0, 1): 1290 - if (domain == SVM_RANGE_VRAM_DOMAIN) { 1291 - if (bo_node != node) 1292 - mapping_flags |= AMDGPU_VM_MTYPE_NC; 1293 - } else { 1294 - mapping_flags |= coherent ? 1295 - AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; 1296 - } 1290 + mapping_flags |= AMDGPU_VM_MTYPE_NC; 1297 1291 break; 1298 1292 default: 1299 1293 mapping_flags |= coherent ? ··· 3003 3009 goto out; 3004 3010 } 3005 3011 3006 - /* check if this page fault time stamp is before svms->checkpoint_ts */ 3007 - if (svms->checkpoint_ts[gpuidx] != 0) { 3008 - if (amdgpu_ih_ts_after_or_equal(ts, svms->checkpoint_ts[gpuidx])) { 3009 - pr_debug("draining retry fault, drop fault 0x%llx\n", addr); 3010 - r = 0; 3011 - goto out; 3012 - } else 3013 - /* ts is after svms->checkpoint_ts now, reset svms->checkpoint_ts 3014 - * to zero to avoid following ts wrap around give wrong comparing 3015 - */ 3016 - svms->checkpoint_ts[gpuidx] = 0; 3017 - } 3018 - 3019 3012 if (!p->xnack_enabled) { 3020 3013 pr_debug("XNACK not enabled for pasid 0x%x\n", pasid); 3021 3014 r = -EFAULT; ··· 3022 3041 mmap_read_lock(mm); 3023 3042 retry_write_locked: 3024 3043 mutex_lock(&svms->lock); 3044 + 3045 + /* check if this page fault time stamp is before svms->checkpoint_ts */ 3046 + if (svms->checkpoint_ts[gpuidx] != 0) { 3047 + if (amdgpu_ih_ts_after_or_equal(ts, svms->checkpoint_ts[gpuidx])) { 3048 + pr_debug("draining retry fault, drop fault 0x%llx\n", addr); 3049 + r = -EAGAIN; 3050 + goto out_unlock_svms; 3051 + } else { 3052 + /* ts is after svms->checkpoint_ts now, reset svms->checkpoint_ts 3053 + * to zero to avoid following ts wrap around give wrong comparing 3054 + */ 3055 + svms->checkpoint_ts[gpuidx] = 0; 3056 + } 3057 + } 3058 + 3025 3059 prange = svm_range_from_addr(svms, addr, NULL); 3026 3060 if (!prange) { 3027 3061 pr_debug("failed to find prange svms 0x%p address [0x%llx]\n", ··· 3162 3166 mutex_unlock(&svms->lock); 3163 3167 mmap_read_unlock(mm); 3164 3168 3165 - svm_range_count_fault(node, p, gpuidx); 3169 + if (r != -EAGAIN) 3170 + svm_range_count_fault(node, p, gpuidx); 3166 3171 3167 3172 mmput(mm); 3168 3173 out:

+32 -5

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 250 250 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 251 251 static void handle_hpd_rx_irq(void *param); 252 252 253 + static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 254 + int bl_idx, 255 + u32 user_brightness); 256 + 253 257 static bool 254 258 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 255 259 struct drm_crtc_state *new_crtc_state); ··· 3141 3137 } 3142 3138 } 3143 3139 3140 + static int dm_prepare_suspend(struct amdgpu_ip_block *ip_block) 3141 + { 3142 + struct amdgpu_device *adev = ip_block->adev; 3143 + 3144 + if (amdgpu_in_reset(adev)) 3145 + return 0; 3146 + 3147 + WARN_ON(adev->dm.cached_state); 3148 + adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 3149 + if (IS_ERR(adev->dm.cached_state)) 3150 + return PTR_ERR(adev->dm.cached_state); 3151 + 3152 + return 0; 3153 + } 3154 + 3144 3155 static int dm_suspend(struct amdgpu_ip_block *ip_block) 3145 3156 { 3146 3157 struct amdgpu_device *adev = ip_block->adev; ··· 3186 3167 return 0; 3187 3168 } 3188 3169 3189 - WARN_ON(adev->dm.cached_state); 3190 - adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 3191 - if (IS_ERR(adev->dm.cached_state)) 3192 - return PTR_ERR(adev->dm.cached_state); 3170 + if (!adev->dm.cached_state) { 3171 + adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 3172 + if (IS_ERR(adev->dm.cached_state)) 3173 + return PTR_ERR(adev->dm.cached_state); 3174 + } 3193 3175 3194 3176 s3_handle_hdmi_cec(adev_to_drm(adev), true); 3195 3177 ··· 3452 3432 3453 3433 mutex_unlock(&dm->dc_lock); 3454 3434 3435 + /* set the backlight after a reset */ 3436 + for (i = 0; i < dm->num_of_edps; i++) { 3437 + if (dm->backlight_dev[i]) 3438 + amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 3439 + } 3440 + 3455 3441 return 0; 3456 3442 } 3457 3443 ··· 3622 3596 .early_fini = amdgpu_dm_early_fini, 3623 3597 .hw_init = dm_hw_init, 3624 3598 .hw_fini = dm_hw_fini, 3599 + .prepare_suspend = dm_prepare_suspend, 3625 3600 .suspend = dm_suspend, 3626 3601 .resume = dm_resume, 3627 3602 .is_idle = dm_is_idle, ··· 5013 4986 dm->backlight_dev[aconnector->bl_idx] = 5014 4987 backlight_device_register(bl_name, aconnector->base.kdev, dm, 5015 4988 &amdgpu_dm_backlight_ops, &props); 4989 + dm->brightness[aconnector->bl_idx] = props.brightness; 5016 4990 5017 4991 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 5018 4992 DRM_ERROR("DM: Backlight registration failed!\n"); ··· 5081 5053 aconnector->bl_idx = bl_idx; 5082 5054 5083 5055 amdgpu_dm_update_backlight_caps(dm, bl_idx); 5084 - dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 5085 5056 dm->backlight_link[bl_idx] = link; 5086 5057 dm->num_of_edps++; 5087 5058

+13 -30

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

··· 172 172 struct mod_hdcp_display_adjustment display_adjust; 173 173 unsigned int conn_index = aconnector->base.index; 174 174 175 - mutex_lock(&hdcp_w->mutex); 175 + guard(mutex)(&hdcp_w->mutex); 176 176 hdcp_w->aconnector[conn_index] = aconnector; 177 177 178 178 memset(&link_adjust, 0, sizeof(link_adjust)); ··· 209 209 mod_hdcp_update_display(&hdcp_w->hdcp, conn_index, &link_adjust, &display_adjust, &hdcp_w->output); 210 210 211 211 process_output(hdcp_w); 212 - mutex_unlock(&hdcp_w->mutex); 213 212 } 214 213 215 214 static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, ··· 219 220 struct drm_connector_state *conn_state = aconnector->base.state; 220 221 unsigned int conn_index = aconnector->base.index; 221 222 222 - mutex_lock(&hdcp_w->mutex); 223 + guard(mutex)(&hdcp_w->mutex); 223 224 hdcp_w->aconnector[conn_index] = aconnector; 224 225 225 226 /* the removal of display will invoke auth reset -> hdcp destroy and ··· 238 239 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); 239 240 240 241 process_output(hdcp_w); 241 - mutex_unlock(&hdcp_w->mutex); 242 242 } 243 243 244 244 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index) ··· 245 247 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 246 248 unsigned int conn_index; 247 249 248 - mutex_lock(&hdcp_w->mutex); 250 + guard(mutex)(&hdcp_w->mutex); 249 251 250 252 mod_hdcp_reset_connection(&hdcp_w->hdcp, &hdcp_w->output); 251 253 ··· 257 259 } 258 260 259 261 process_output(hdcp_w); 260 - 261 - mutex_unlock(&hdcp_w->mutex); 262 262 } 263 263 264 264 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index) ··· 273 277 hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue, 274 278 callback_dwork); 275 279 276 - mutex_lock(&hdcp_work->mutex); 280 + guard(mutex)(&hdcp_work->mutex); 277 281 278 282 cancel_delayed_work(&hdcp_work->callback_dwork); 279 283 ··· 281 285 &hdcp_work->output); 282 286 283 287 process_output(hdcp_work); 284 - 285 - mutex_unlock(&hdcp_work->mutex); 286 288 } 287 289 288 290 static void event_property_update(struct work_struct *work) ··· 317 323 continue; 318 324 319 325 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 320 - mutex_lock(&hdcp_work->mutex); 326 + guard(mutex)(&hdcp_work->mutex); 321 327 322 328 if (conn_state->commit) { 323 329 ret = wait_for_completion_interruptible_timeout(&conn_state->commit->hw_done, ··· 349 355 drm_hdcp_update_content_protection(connector, 350 356 DRM_MODE_CONTENT_PROTECTION_DESIRED); 351 357 } 352 - mutex_unlock(&hdcp_work->mutex); 353 358 drm_modeset_unlock(&dev->mode_config.connection_mutex); 354 359 } 355 360 } ··· 361 368 struct amdgpu_dm_connector *aconnector; 362 369 unsigned int conn_index; 363 370 364 - mutex_lock(&hdcp_work->mutex); 371 + guard(mutex)(&hdcp_work->mutex); 365 372 366 373 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; 367 374 conn_index++) { ··· 401 408 schedule_work(&hdcp_work->property_update_work); 402 409 } 403 410 } 404 - 405 - mutex_unlock(&hdcp_work->mutex); 406 411 } 407 412 408 413 static void event_watchdog_timer(struct work_struct *work) ··· 411 420 struct hdcp_workqueue, 412 421 watchdog_timer_dwork); 413 422 414 - mutex_lock(&hdcp_work->mutex); 423 + guard(mutex)(&hdcp_work->mutex); 415 424 416 425 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); 417 426 ··· 420 429 &hdcp_work->output); 421 430 422 431 process_output(hdcp_work); 423 - 424 - mutex_unlock(&hdcp_work->mutex); 425 432 } 426 433 427 434 static void event_cpirq(struct work_struct *work) ··· 428 439 429 440 hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work); 430 441 431 - mutex_lock(&hdcp_work->mutex); 442 + guard(mutex)(&hdcp_work->mutex); 432 443 433 444 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output); 434 445 435 446 process_output(hdcp_work); 436 - 437 - mutex_unlock(&hdcp_work->mutex); 438 447 } 439 448 440 449 void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work) ··· 442 455 for (i = 0; i < hdcp_work->max_link; i++) { 443 456 cancel_delayed_work_sync(&hdcp_work[i].callback_dwork); 444 457 cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork); 458 + cancel_delayed_work_sync(&hdcp_work[i].property_validate_dwork); 445 459 } 446 460 447 461 sysfs_remove_bin_file(kobj, &hdcp_work[0].attr); ··· 457 469 struct mod_hdcp hdcp = hdcp_work->hdcp; 458 470 struct psp_context *psp = hdcp.config.psp.handle; 459 471 struct ta_dtm_shared_memory *dtm_cmd; 460 - bool res = true; 461 472 462 473 if (!psp->dtm_context.context.initialized) { 463 474 DRM_INFO("Failed to enable ASSR, DTM TA is not initialized."); ··· 465 478 466 479 dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf; 467 480 468 - mutex_lock(&psp->dtm_context.mutex); 481 + guard(mutex)(&psp->dtm_context.mutex); 469 482 memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory)); 470 483 471 484 dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE; ··· 477 490 478 491 if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { 479 492 DRM_INFO("Failed to enable ASSR"); 480 - res = false; 493 + return false; 481 494 } 482 495 483 - mutex_unlock(&psp->dtm_context.mutex); 484 - 485 - return res; 496 + return true; 486 497 } 487 498 488 499 static void update_config(void *handle, struct cp_psp_stream_config *config) ··· 541 556 (!!aconnector->base.state) ? 542 557 aconnector->base.state->hdcp_content_type : -1); 543 558 544 - mutex_lock(&hdcp_w->mutex); 559 + guard(mutex)(&hdcp_w->mutex); 545 560 546 561 mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output); 547 562 548 563 process_output(hdcp_w); 549 - mutex_unlock(&hdcp_w->mutex); 550 - 551 564 } 552 565 553 566 /**

+45 -19

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

··· 890 890 struct drm_device *dev = adev_to_drm(adev); 891 891 struct drm_connector *connector; 892 892 struct drm_connector_list_iter iter; 893 + int irq_type; 893 894 int i; 895 + 896 + /* First, clear all hpd and hpdrx interrupts */ 897 + for (i = DC_IRQ_SOURCE_HPD1; i <= DC_IRQ_SOURCE_HPD6RX; i++) { 898 + if (!dc_interrupt_set(adev->dm.dc, i, false)) 899 + drm_err(dev, "Failed to clear hpd(rx) source=%d on init\n", 900 + i); 901 + } 894 902 895 903 drm_connector_list_iter_begin(dev, &iter); 896 904 drm_for_each_connector_iter(connector, &iter) { ··· 912 904 913 905 dc_link = amdgpu_dm_connector->dc_link; 914 906 907 + /* 908 + * Get a base driver irq reference for hpd ints for the lifetime 909 + * of dm. Note that only hpd interrupt types are registered with 910 + * base driver; hpd_rx types aren't. IOW, amdgpu_irq_get/put on 911 + * hpd_rx isn't available. DM currently controls hpd_rx 912 + * explicitly with dc_interrupt_set() 913 + */ 915 914 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 916 - dc_interrupt_set(adev->dm.dc, 917 - dc_link->irq_source_hpd, 918 - true); 915 + irq_type = dc_link->irq_source_hpd - DC_IRQ_SOURCE_HPD1; 916 + /* 917 + * TODO: There's a mismatch between mode_info.num_hpd 918 + * and what bios reports as the # of connectors with hpd 919 + * sources. Since the # of hpd source types registered 920 + * with base driver == mode_info.num_hpd, we have to 921 + * fallback to dc_interrupt_set for the remaining types. 922 + */ 923 + if (irq_type < adev->mode_info.num_hpd) { 924 + if (amdgpu_irq_get(adev, &adev->hpd_irq, irq_type)) 925 + drm_err(dev, "DM_IRQ: Failed get HPD for source=%d)!\n", 926 + dc_link->irq_source_hpd); 927 + } else { 928 + dc_interrupt_set(adev->dm.dc, 929 + dc_link->irq_source_hpd, 930 + true); 931 + } 919 932 } 920 933 921 934 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { ··· 946 917 } 947 918 } 948 919 drm_connector_list_iter_end(&iter); 949 - 950 - /* Update reference counts for HPDs */ 951 - for (i = DC_IRQ_SOURCE_HPD1; i <= adev->mode_info.num_hpd; i++) { 952 - if (amdgpu_irq_get(adev, &adev->hpd_irq, i - DC_IRQ_SOURCE_HPD1)) 953 - drm_err(dev, "DM_IRQ: Failed get HPD for source=%d)!\n", i); 954 - } 955 920 } 956 921 957 922 /** ··· 961 938 struct drm_device *dev = adev_to_drm(adev); 962 939 struct drm_connector *connector; 963 940 struct drm_connector_list_iter iter; 964 - int i; 941 + int irq_type; 965 942 966 943 drm_connector_list_iter_begin(dev, &iter); 967 944 drm_for_each_connector_iter(connector, &iter) { ··· 975 952 dc_link = amdgpu_dm_connector->dc_link; 976 953 977 954 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 978 - dc_interrupt_set(adev->dm.dc, 979 - dc_link->irq_source_hpd, 980 - false); 955 + irq_type = dc_link->irq_source_hpd - DC_IRQ_SOURCE_HPD1; 956 + 957 + /* TODO: See same TODO in amdgpu_dm_hpd_init() */ 958 + if (irq_type < adev->mode_info.num_hpd) { 959 + if (amdgpu_irq_put(adev, &adev->hpd_irq, irq_type)) 960 + drm_err(dev, "DM_IRQ: Failed put HPD for source=%d!\n", 961 + dc_link->irq_source_hpd); 962 + } else { 963 + dc_interrupt_set(adev->dm.dc, 964 + dc_link->irq_source_hpd, 965 + false); 966 + } 981 967 } 982 968 983 969 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { ··· 996 964 } 997 965 } 998 966 drm_connector_list_iter_end(&iter); 999 - 1000 - /* Update reference counts for HPDs */ 1001 - for (i = DC_IRQ_SOURCE_HPD1; i <= adev->mode_info.num_hpd; i++) { 1002 - if (amdgpu_irq_put(adev, &adev->hpd_irq, i - DC_IRQ_SOURCE_HPD1)) 1003 - drm_err(dev, "DM_IRQ: Failed put HPD for source=%d!\n", i); 1004 - } 1005 967 }

+1 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

··· 700 700 uint64_t mod_4k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_4K_2D); 701 701 uint64_t mod_256b = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256B_2D); 702 702 uint64_t dcc = ver | AMD_FMT_MOD_SET(DCC, 1); 703 - uint8_t max_comp_block[] = {1, 0}; 703 + uint8_t max_comp_block[] = {2, 1, 0}; 704 704 uint64_t max_comp_block_mod[ARRAY_SIZE(max_comp_block)] = {0}; 705 705 uint8_t i = 0, j = 0; 706 706 uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b, DRM_FORMAT_MOD_LINEAR};

-2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

··· 194 194 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 195 195 if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK) 196 196 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK; 197 - if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK) 198 - new_clocks->dispclk_khz = MIN_DPP_DISP_CLK; 199 197 200 198 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 201 199 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

-2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

··· 201 201 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 202 202 if (new_clocks->dppclk_khz < 100000) 203 203 new_clocks->dppclk_khz = 100000; 204 - if (new_clocks->dispclk_khz < 100000) 205 - new_clocks->dispclk_khz = 100000; 206 204 207 205 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 208 206 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

+8 -2

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 453 453 454 454 if (dc->caps.max_v_total != 0 && 455 455 (adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) { 456 + stream->adjust.timing_adjust_pending = false; 456 457 if (adjust->allow_otg_v_count_halt) 457 458 return set_long_vtotal(dc, stream, adjust); 458 459 else ··· 467 466 dc->hwss.set_drr(&pipe, 468 467 1, 469 468 *adjust); 470 - 469 + stream->adjust.timing_adjust_pending = false; 471 470 return true; 472 471 } 473 472 } ··· 3166 3165 if (update->vrr_active_fixed) 3167 3166 stream->vrr_active_fixed = *update->vrr_active_fixed; 3168 3167 3169 - if (update->crtc_timing_adjust) 3168 + if (update->crtc_timing_adjust) { 3169 + if (stream->adjust.v_total_min != update->crtc_timing_adjust->v_total_min || 3170 + stream->adjust.v_total_max != update->crtc_timing_adjust->v_total_max) 3171 + update->crtc_timing_adjust->timing_adjust_pending = true; 3170 3172 stream->adjust = *update->crtc_timing_adjust; 3173 + update->crtc_timing_adjust->timing_adjust_pending = false; 3174 + } 3171 3175 3172 3176 if (update->dpms_off) 3173 3177 stream->dpms_off = *update->dpms_off;

+23 -1

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

··· 659 659 } 660 660 } 661 661 662 + void set_drr_and_clear_adjust_pending( 663 + struct pipe_ctx *pipe_ctx, 664 + struct dc_stream_state *stream, 665 + struct drr_params *params) 666 + { 667 + /* params can be null.*/ 668 + if (pipe_ctx && pipe_ctx->stream_res.tg && 669 + pipe_ctx->stream_res.tg->funcs->set_drr) 670 + pipe_ctx->stream_res.tg->funcs->set_drr( 671 + pipe_ctx->stream_res.tg, params); 672 + 673 + if (stream) 674 + stream->adjust.timing_adjust_pending = false; 675 + } 676 + 662 677 void get_fams2_visual_confirm_color( 663 678 struct dc *dc, 664 679 struct dc_state *context, ··· 817 802 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC; 818 803 (*num_steps)++; 819 804 } 820 - 805 + if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && 806 + dc->hwss.update_visual_confirm_color) { 807 + block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc; 808 + block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe; 809 + block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; 810 + block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM; 811 + (*num_steps)++; 812 + } 821 813 if (current_mpc_pipe->stream->update_flags.bits.out_csc) { 822 814 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc; 823 815 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

+5 -2

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

··· 3623 3623 break; 3624 3624 case COLOR_DEPTH_121212: 3625 3625 normalized_pix_clk = (pix_clk * 36) / 24; 3626 - break; 3626 + break; 3627 + case COLOR_DEPTH_141414: 3628 + normalized_pix_clk = (pix_clk * 42) / 24; 3629 + break; 3627 3630 case COLOR_DEPTH_161616: 3628 3631 normalized_pix_clk = (pix_clk * 48) / 24; 3629 - break; 3632 + break; 3630 3633 default: 3631 3634 ASSERT(0); 3632 3635 break;

+1 -1

drivers/gpu/drm/amd/display/dc/dc.h

··· 53 53 struct set_config_cmd_payload; 54 54 struct dmub_notification; 55 55 56 - #define DC_VER "3.2.323" 56 + #define DC_VER "3.2.324" 57 57 58 58 /** 59 59 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC

+143 -129

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

··· 70 70 } 71 71 } 72 72 73 - void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 73 + bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv) 74 74 { 75 - struct dmub_srv *dmub = dc_dmub_srv->dmub; 76 - struct dc_context *dc_ctx = dc_dmub_srv->ctx; 75 + struct dmub_srv *dmub; 76 + struct dc_context *dc_ctx; 77 77 enum dmub_status status; 78 78 79 + if (!dc_dmub_srv || !dc_dmub_srv->dmub) 80 + return false; 81 + 82 + dc_ctx = dc_dmub_srv->ctx; 83 + dmub = dc_dmub_srv->dmub; 84 + 79 85 do { 80 - status = dmub_srv_wait_for_idle(dmub, 100000); 86 + status = dmub_srv_wait_for_pending(dmub, 100000); 81 87 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 82 88 83 89 if (status != DMUB_STATUS_OK) { 84 90 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 85 91 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 86 92 } 93 + 94 + return status == DMUB_STATUS_OK; 87 95 } 88 96 89 97 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv) ··· 134 126 } 135 127 } 136 128 137 - bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 129 + static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 130 + unsigned int count, 131 + union dmub_rb_cmd *cmd_list) 132 + { 133 + struct dc_context *dc_ctx; 134 + struct dmub_srv *dmub; 135 + enum dmub_status status = DMUB_STATUS_OK; 136 + int i; 137 + 138 + if (!dc_dmub_srv || !dc_dmub_srv->dmub) 139 + return false; 140 + 141 + dc_ctx = dc_dmub_srv->ctx; 142 + dmub = dc_dmub_srv->dmub; 143 + 144 + for (i = 0 ; i < count; i++) { 145 + /* confirm no messages pending */ 146 + do { 147 + status = dmub_srv_wait_for_idle(dmub, 100000); 148 + } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 149 + 150 + /* queue command */ 151 + if (status == DMUB_STATUS_OK) 152 + status = dmub_srv_reg_cmd_execute(dmub, &cmd_list[i]); 153 + 154 + /* check for errors */ 155 + if (status != DMUB_STATUS_OK) { 156 + break; 157 + } 158 + } 159 + 160 + if (status != DMUB_STATUS_OK) { 161 + if (status != DMUB_STATUS_POWER_STATE_D3) { 162 + DC_ERROR("Error starting DMUB execution: status=%d\n", status); 163 + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 164 + } 165 + return false; 166 + } 167 + 168 + return true; 169 + } 170 + 171 + static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 138 172 unsigned int count, 139 173 union dmub_rb_cmd *cmd_list) 140 174 { ··· 193 143 194 144 for (i = 0 ; i < count; i++) { 195 145 // Queue command 196 - status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 146 + if (!cmd_list[i].cmd_common.header.multi_cmd_pending || 147 + dmub_rb_num_free(&dmub->inbox1.rb) >= count - i) { 148 + status = dmub_srv_fb_cmd_queue(dmub, &cmd_list[i]); 149 + } else { 150 + status = DMUB_STATUS_QUEUE_FULL; 151 + } 197 152 198 153 if (status == DMUB_STATUS_QUEUE_FULL) { 199 154 /* Execute and wait for queue to become empty again. */ 200 - status = dmub_srv_cmd_execute(dmub); 155 + status = dmub_srv_fb_cmd_execute(dmub); 201 156 if (status == DMUB_STATUS_POWER_STATE_D3) 202 157 return false; 203 158 ··· 211 156 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 212 157 213 158 /* Requeue the command. */ 214 - status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 159 + status = dmub_srv_fb_cmd_queue(dmub, &cmd_list[i]); 215 160 } 216 161 217 162 if (status != DMUB_STATUS_OK) { ··· 223 168 } 224 169 } 225 170 226 - status = dmub_srv_cmd_execute(dmub); 171 + status = dmub_srv_fb_cmd_execute(dmub); 227 172 if (status != DMUB_STATUS_OK) { 228 173 if (status != DMUB_STATUS_POWER_STATE_D3) { 229 174 DC_ERROR("Error starting DMUB execution: status=%d\n", status); ··· 233 178 } 234 179 235 180 return true; 181 + } 182 + 183 + bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 184 + unsigned int count, 185 + union dmub_rb_cmd *cmd_list) 186 + { 187 + bool res = false; 188 + 189 + if (dc_dmub_srv && dc_dmub_srv->dmub) { 190 + if (dc_dmub_srv->dmub->inbox_type == DMUB_CMD_INTERFACE_REG) { 191 + res = dc_dmub_srv_reg_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list); 192 + } else { 193 + res = dc_dmub_srv_fb_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list); 194 + } 195 + } 196 + 197 + return res; 236 198 } 237 199 238 200 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, ··· 272 200 273 201 if (status != DMUB_STATUS_OK) { 274 202 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 275 - if (!dmub->debug.timeout_occured) { 276 - dmub->debug.timeout_occured = true; 277 - dmub->debug.timeout_cmd = *cmd_list; 278 - dmub->debug.timestamp = dm_get_timestamp(dc_dmub_srv->ctx); 203 + if (!dmub->debug.timeout_info.timeout_occured) { 204 + dmub->debug.timeout_info.timeout_occured = true; 205 + if (cmd_list) 206 + dmub->debug.timeout_info.timeout_cmd = *cmd_list; 207 + dmub->debug.timeout_info.timestamp = dm_get_timestamp(dc_dmub_srv->ctx); 279 208 } 280 209 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 281 210 return false; 282 211 } 283 212 284 213 // Copy data back from ring buffer into command 285 - if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 286 - dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list); 214 + if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY && cmd_list) { 215 + dmub_srv_cmd_get_response(dc_dmub_srv->dmub, cmd_list); 216 + } 287 217 } 288 218 289 219 return true; ··· 298 224 299 225 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type) 300 226 { 301 - struct dc_context *dc_ctx; 302 - struct dmub_srv *dmub; 303 - enum dmub_status status; 304 - int i; 305 - 306 - if (!dc_dmub_srv || !dc_dmub_srv->dmub) 227 + if (!dc_dmub_srv_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list)) 307 228 return false; 308 229 309 - dc_ctx = dc_dmub_srv->ctx; 310 - dmub = dc_dmub_srv->dmub; 311 - 312 - for (i = 0 ; i < count; i++) { 313 - // Queue command 314 - status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 315 - 316 - if (status == DMUB_STATUS_QUEUE_FULL) { 317 - /* Execute and wait for queue to become empty again. */ 318 - status = dmub_srv_cmd_execute(dmub); 319 - if (status == DMUB_STATUS_POWER_STATE_D3) 320 - return false; 321 - 322 - status = dmub_srv_wait_for_idle(dmub, 100000); 323 - if (status != DMUB_STATUS_OK) 324 - return false; 325 - 326 - /* Requeue the command. */ 327 - status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 328 - } 329 - 330 - if (status != DMUB_STATUS_OK) { 331 - if (status != DMUB_STATUS_POWER_STATE_D3) { 332 - DC_ERROR("Error queueing DMUB command: status=%d\n", status); 333 - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 334 - } 335 - return false; 336 - } 337 - } 338 - 339 - status = dmub_srv_cmd_execute(dmub); 340 - if (status != DMUB_STATUS_OK) { 341 - if (status != DMUB_STATUS_POWER_STATE_D3) { 342 - DC_ERROR("Error starting DMUB execution: status=%d\n", status); 343 - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 344 - } 345 - return false; 346 - } 347 - 348 - // Wait for DMUB to process command 349 - if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { 350 - if (dc_dmub_srv->ctx->dc->debug.disable_timeout) { 351 - do { 352 - status = dmub_srv_wait_for_idle(dmub, 100000); 353 - } while (status != DMUB_STATUS_OK); 354 - } else 355 - status = dmub_srv_wait_for_idle(dmub, 100000); 356 - 357 - if (status != DMUB_STATUS_OK) { 358 - DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 359 - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 360 - return false; 361 - } 362 - 363 - // Copy data back from ring buffer into command 364 - if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 365 - dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list); 366 - } 367 - 368 - return true; 230 + return dc_dmub_srv_wait_for_idle(dc_dmub_srv, wait_type, cmd_list); 369 231 } 370 232 371 233 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) ··· 937 927 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 938 928 } 939 929 940 - bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 930 + bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 941 931 { 942 - if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 932 + if (!dc_dmub_srv || !dc_dmub_srv->dmub) 943 933 return false; 944 - return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 934 + return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub); 945 935 } 946 936 947 937 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 948 938 { 949 - struct dmub_diagnostic_data diag_data = {0}; 950 939 uint32_t i; 951 940 952 941 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { ··· 955 946 956 947 DC_LOG_ERROR("%s: DMCUB error - collecting diagnostic data\n", __func__); 957 948 958 - if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 949 + if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv)) { 959 950 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 960 951 return; 961 952 } 962 953 963 954 DC_LOG_DEBUG("DMCUB STATE:"); 964 - DC_LOG_DEBUG(" dmcub_version : %08x", diag_data.dmcub_version); 965 - DC_LOG_DEBUG(" scratch [0] : %08x", diag_data.scratch[0]); 966 - DC_LOG_DEBUG(" scratch [1] : %08x", diag_data.scratch[1]); 967 - DC_LOG_DEBUG(" scratch [2] : %08x", diag_data.scratch[2]); 968 - DC_LOG_DEBUG(" scratch [3] : %08x", diag_data.scratch[3]); 969 - DC_LOG_DEBUG(" scratch [4] : %08x", diag_data.scratch[4]); 970 - DC_LOG_DEBUG(" scratch [5] : %08x", diag_data.scratch[5]); 971 - DC_LOG_DEBUG(" scratch [6] : %08x", diag_data.scratch[6]); 972 - DC_LOG_DEBUG(" scratch [7] : %08x", diag_data.scratch[7]); 973 - DC_LOG_DEBUG(" scratch [8] : %08x", diag_data.scratch[8]); 974 - DC_LOG_DEBUG(" scratch [9] : %08x", diag_data.scratch[9]); 975 - DC_LOG_DEBUG(" scratch [10] : %08x", diag_data.scratch[10]); 976 - DC_LOG_DEBUG(" scratch [11] : %08x", diag_data.scratch[11]); 977 - DC_LOG_DEBUG(" scratch [12] : %08x", diag_data.scratch[12]); 978 - DC_LOG_DEBUG(" scratch [13] : %08x", diag_data.scratch[13]); 979 - DC_LOG_DEBUG(" scratch [14] : %08x", diag_data.scratch[14]); 980 - DC_LOG_DEBUG(" scratch [15] : %08x", diag_data.scratch[15]); 955 + DC_LOG_DEBUG(" dmcub_version : %08x", dc_dmub_srv->dmub->debug.dmcub_version); 956 + DC_LOG_DEBUG(" scratch [0] : %08x", dc_dmub_srv->dmub->debug.scratch[0]); 957 + DC_LOG_DEBUG(" scratch [1] : %08x", dc_dmub_srv->dmub->debug.scratch[1]); 958 + DC_LOG_DEBUG(" scratch [2] : %08x", dc_dmub_srv->dmub->debug.scratch[2]); 959 + DC_LOG_DEBUG(" scratch [3] : %08x", dc_dmub_srv->dmub->debug.scratch[3]); 960 + DC_LOG_DEBUG(" scratch [4] : %08x", dc_dmub_srv->dmub->debug.scratch[4]); 961 + DC_LOG_DEBUG(" scratch [5] : %08x", dc_dmub_srv->dmub->debug.scratch[5]); 962 + DC_LOG_DEBUG(" scratch [6] : %08x", dc_dmub_srv->dmub->debug.scratch[6]); 963 + DC_LOG_DEBUG(" scratch [7] : %08x", dc_dmub_srv->dmub->debug.scratch[7]); 964 + DC_LOG_DEBUG(" scratch [8] : %08x", dc_dmub_srv->dmub->debug.scratch[8]); 965 + DC_LOG_DEBUG(" scratch [9] : %08x", dc_dmub_srv->dmub->debug.scratch[9]); 966 + DC_LOG_DEBUG(" scratch [10] : %08x", dc_dmub_srv->dmub->debug.scratch[10]); 967 + DC_LOG_DEBUG(" scratch [11] : %08x", dc_dmub_srv->dmub->debug.scratch[11]); 968 + DC_LOG_DEBUG(" scratch [12] : %08x", dc_dmub_srv->dmub->debug.scratch[12]); 969 + DC_LOG_DEBUG(" scratch [13] : %08x", dc_dmub_srv->dmub->debug.scratch[13]); 970 + DC_LOG_DEBUG(" scratch [14] : %08x", dc_dmub_srv->dmub->debug.scratch[14]); 971 + DC_LOG_DEBUG(" scratch [15] : %08x", dc_dmub_srv->dmub->debug.scratch[15]); 981 972 for (i = 0; i < DMUB_PC_SNAPSHOT_COUNT; i++) 982 - DC_LOG_DEBUG(" pc[%d] : %08x", i, diag_data.pc[i]); 983 - DC_LOG_DEBUG(" unk_fault_addr : %08x", diag_data.undefined_address_fault_addr); 984 - DC_LOG_DEBUG(" inst_fault_addr : %08x", diag_data.inst_fetch_fault_addr); 985 - DC_LOG_DEBUG(" data_fault_addr : %08x", diag_data.data_write_fault_addr); 986 - DC_LOG_DEBUG(" inbox1_rptr : %08x", diag_data.inbox1_rptr); 987 - DC_LOG_DEBUG(" inbox1_wptr : %08x", diag_data.inbox1_wptr); 988 - DC_LOG_DEBUG(" inbox1_size : %08x", diag_data.inbox1_size); 989 - DC_LOG_DEBUG(" inbox0_rptr : %08x", diag_data.inbox0_rptr); 990 - DC_LOG_DEBUG(" inbox0_wptr : %08x", diag_data.inbox0_wptr); 991 - DC_LOG_DEBUG(" inbox0_size : %08x", diag_data.inbox0_size); 992 - DC_LOG_DEBUG(" outbox1_rptr : %08x", diag_data.outbox1_rptr); 993 - DC_LOG_DEBUG(" outbox1_wptr : %08x", diag_data.outbox1_wptr); 994 - DC_LOG_DEBUG(" outbox1_size : %08x", diag_data.outbox1_size); 995 - DC_LOG_DEBUG(" is_enabled : %d", diag_data.is_dmcub_enabled); 996 - DC_LOG_DEBUG(" is_soft_reset : %d", diag_data.is_dmcub_soft_reset); 997 - DC_LOG_DEBUG(" is_secure_reset : %d", diag_data.is_dmcub_secure_reset); 998 - DC_LOG_DEBUG(" is_traceport_en : %d", diag_data.is_traceport_en); 999 - DC_LOG_DEBUG(" is_cw0_en : %d", diag_data.is_cw0_enabled); 1000 - DC_LOG_DEBUG(" is_cw6_en : %d", diag_data.is_cw6_enabled); 973 + DC_LOG_DEBUG(" pc[%d] : %08x", i, dc_dmub_srv->dmub->debug.pc[i]); 974 + DC_LOG_DEBUG(" unk_fault_addr : %08x", dc_dmub_srv->dmub->debug.undefined_address_fault_addr); 975 + DC_LOG_DEBUG(" inst_fault_addr : %08x", dc_dmub_srv->dmub->debug.inst_fetch_fault_addr); 976 + DC_LOG_DEBUG(" data_fault_addr : %08x", dc_dmub_srv->dmub->debug.data_write_fault_addr); 977 + DC_LOG_DEBUG(" inbox1_rptr : %08x", dc_dmub_srv->dmub->debug.inbox1_rptr); 978 + DC_LOG_DEBUG(" inbox1_wptr : %08x", dc_dmub_srv->dmub->debug.inbox1_wptr); 979 + DC_LOG_DEBUG(" inbox1_size : %08x", dc_dmub_srv->dmub->debug.inbox1_size); 980 + DC_LOG_DEBUG(" inbox0_rptr : %08x", dc_dmub_srv->dmub->debug.inbox0_rptr); 981 + DC_LOG_DEBUG(" inbox0_wptr : %08x", dc_dmub_srv->dmub->debug.inbox0_wptr); 982 + DC_LOG_DEBUG(" inbox0_size : %08x", dc_dmub_srv->dmub->debug.inbox0_size); 983 + DC_LOG_DEBUG(" outbox1_rptr : %08x", dc_dmub_srv->dmub->debug.outbox1_rptr); 984 + DC_LOG_DEBUG(" outbox1_wptr : %08x", dc_dmub_srv->dmub->debug.outbox1_wptr); 985 + DC_LOG_DEBUG(" outbox1_size : %08x", dc_dmub_srv->dmub->debug.outbox1_size); 986 + DC_LOG_DEBUG(" is_enabled : %d", dc_dmub_srv->dmub->debug.is_dmcub_enabled); 987 + DC_LOG_DEBUG(" is_soft_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_soft_reset); 988 + DC_LOG_DEBUG(" is_secure_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_secure_reset); 989 + DC_LOG_DEBUG(" is_traceport_en : %d", dc_dmub_srv->dmub->debug.is_traceport_en); 990 + DC_LOG_DEBUG(" is_cw0_en : %d", dc_dmub_srv->dmub->debug.is_cw0_enabled); 991 + DC_LOG_DEBUG(" is_cw6_en : %d", dc_dmub_srv->dmub->debug.is_cw6_enabled); 1001 992 } 1002 993 1003 994 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) ··· 1253 1244 ips_fw->signals.bits.ips1_commit, 1254 1245 ips_fw->signals.bits.ips2_commit); 1255 1246 1256 - dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 1247 + dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL); 1257 1248 1258 1249 memset(&new_signals, 0, sizeof(new_signals)); 1259 1250 ··· 1410 1401 ips_fw->signals.bits.ips1_commit, 1411 1402 ips_fw->signals.bits.ips2_commit); 1412 1403 1413 - dmub_srv_sync_inbox1(dc->ctx->dmub_srv->dmub); 1404 + dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub); 1414 1405 } 1415 1406 } 1416 1407 ··· 1664 1655 /* fill in generic command header */ 1665 1656 global_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1666 1657 global_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1667 - global_cmd->header.payload_bytes = sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1658 + global_cmd->header.payload_bytes = 1659 + sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1668 1660 1669 1661 if (enable) { 1670 1662 /* send global configuration parameters */ ··· 1684 1674 /* configure command header */ 1685 1675 stream_base_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1686 1676 stream_base_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1687 - stream_base_cmd->header.payload_bytes = sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1677 + stream_base_cmd->header.payload_bytes = 1678 + sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1688 1679 stream_base_cmd->header.multi_cmd_pending = 1; 1689 1680 stream_sub_state_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1690 1681 stream_sub_state_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1691 - stream_sub_state_cmd->header.payload_bytes = sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1682 + stream_sub_state_cmd->header.payload_bytes = 1683 + sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1692 1684 stream_sub_state_cmd->header.multi_cmd_pending = 1; 1693 1685 /* copy stream static base state */ 1694 1686 memcpy(&stream_base_cmd->config, ··· 1736 1724 cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid_frame_num = vtotal_mid_frame_num; 1737 1725 cmd.fams2_drr_update.dmub_optc_state_req.program_manual_trigger = program_manual_trigger; 1738 1726 1739 - cmd.fams2_drr_update.header.payload_bytes = sizeof(cmd.fams2_drr_update) - sizeof(cmd.fams2_drr_update.header); 1727 + cmd.fams2_drr_update.header.payload_bytes = 1728 + sizeof(cmd.fams2_drr_update) - sizeof(cmd.fams2_drr_update.header); 1740 1729 1741 1730 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1742 1731 } ··· 1773 1760 /* build command header */ 1774 1761 cmds[num_cmds].fams2_flip.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1775 1762 cmds[num_cmds].fams2_flip.header.sub_type = DMUB_CMD__FAMS2_FLIP; 1776 - cmds[num_cmds].fams2_flip.header.payload_bytes = sizeof(struct dmub_rb_cmd_fams2_flip); 1763 + cmds[num_cmds].fams2_flip.header.payload_bytes = 1764 + sizeof(struct dmub_rb_cmd_fams2_flip) - sizeof(struct dmub_cmd_header); 1777 1765 1778 1766 /* for chaining multiple commands, all but last command should set to 1 */ 1779 1767 cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1;

+2 -2

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

··· 58 58 bool needs_idle_wake; 59 59 }; 60 60 61 - void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv); 61 + bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv); 62 62 63 63 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv); 64 64 ··· 94 94 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv); 95 95 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data); 96 96 97 - bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *dmub_oca); 97 + bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv); 98 98 99 99 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable); 100 100 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);

+26 -1

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

··· 432 432 uint8_t BW_32Gbps:1; 433 433 uint8_t BW_40Gbps:1; 434 434 uint8_t BW_48Gbps:1; 435 - uint8_t RESERVED:1; // Bit 7 435 + uint8_t FRL_LINK_TRAINING_FINISHED:1; // Bit 7 436 + } bits; 437 + uint8_t raw; 438 + }; 439 + 440 + union hdmi_tx_link_status { 441 + struct { 442 + uint8_t HDMI_TX_LINK_ACTIVE_STATUS:1; 443 + uint8_t HDMI_TX_READY_STATUS:1; 444 + uint8_t RESERVED:6; 445 + } bits; 446 + uint8_t raw; 447 + }; 448 + 449 + union autonomous_mode_and_frl_link_status { 450 + struct { 451 + uint8_t FRL_LT_IN_PROGRESS_STATUS:1; 452 + uint8_t FRL_LT_LINK_CONFIG_IN_PROGRESS:3; 453 + uint8_t RESERVED:1; 454 + uint8_t FALLBACK_POLICY:1; 455 + uint8_t FALLBACK_POLICY_VALID:1; 456 + uint8_t REGULATED_AUTONOMOUS_MODE_SUPPORTED:1; 436 457 } bits; 437 458 uint8_t raw; 438 459 }; ··· 1187 1166 uint32_t dp_hdmi_max_bpc; 1188 1167 uint32_t dp_hdmi_max_pixel_clk_in_khz; 1189 1168 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 1169 + uint32_t dp_hdmi_regulated_autonomous_mode_support; 1190 1170 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 1191 1171 }; 1192 1172 ··· 1415 1393 #endif 1416 1394 #ifndef DP_LTTPR_ALPM_CAPABILITIES 1417 1395 #define DP_LTTPR_ALPM_CAPABILITIES 0xF0009 1396 + #endif 1397 + #ifndef DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 1398 + #define DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 0x303C 1418 1399 #endif 1419 1400 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 1420 1401 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50

+1 -1

drivers/gpu/drm/amd/display/dc/dc_helper.c

··· 682 682 if (offload && 683 683 ctx->dc->debug.dmub_offload_enabled && 684 684 !ctx->dc->debug.dmcub_emulation) { 685 - dc_dmub_srv_wait_idle(ctx->dmub_srv); 685 + dc_dmub_srv_wait_for_idle(ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL); 686 686 } 687 687 } 688 688

+1

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

··· 1017 1017 uint32_t v_total_mid; 1018 1018 uint32_t v_total_mid_frame_num; 1019 1019 uint32_t allow_otg_v_count_halt; 1020 + uint8_t timing_adjust_pending; 1020 1021 }; 1021 1022 1022 1023

+2 -1

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

··· 240 240 cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; 241 241 cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask; 242 242 243 - cmd.abm_save_restore.header.payload_bytes = sizeof(struct dmub_rb_cmd_abm_save_restore); 243 + cmd.abm_save_restore.header.payload_bytes = 244 + sizeof(struct dmub_rb_cmd_abm_save_restore) - sizeof(struct dmub_cmd_header); 244 245 245 246 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 246 247

+4

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

··· 63 63 64 64 bool should_use_dmub_lock(struct dc_link *link) 65 65 { 66 + /* ASIC doesn't support DMUB */ 67 + if (!link->ctx->dmub_srv) 68 + return false; 69 + 66 70 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) 67 71 return true; 68 72

+13 -6

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

··· 280 280 memset(&cmd, 0, sizeof(cmd)); 281 281 pCmd->header.type = DMUB_CMD__REPLAY; 282 282 pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL; 283 - pCmd->header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal); 283 + pCmd->header.payload_bytes = 284 + sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal) - 285 + sizeof(struct dmub_cmd_header); 284 286 pCmd->replay_set_power_opt_data.power_opt = power_opt; 285 287 pCmd->replay_set_power_opt_data.panel_inst = panel_inst; 286 288 pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF); ··· 321 319 cmd.replay_set_timing_sync.header.sub_type = 322 320 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED; 323 321 cmd.replay_set_timing_sync.header.payload_bytes = 324 - sizeof(struct dmub_rb_cmd_replay_set_timing_sync); 322 + sizeof(struct dmub_rb_cmd_replay_set_timing_sync) - 323 + sizeof(struct dmub_cmd_header); 325 324 //Cmd Body 326 325 cmd.replay_set_timing_sync.replay_set_timing_sync_data.panel_inst = 327 326 cmd_element->sync_data.panel_inst; ··· 334 331 cmd.replay_set_frameupdate_timer.header.sub_type = 335 332 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER; 336 333 cmd.replay_set_frameupdate_timer.header.payload_bytes = 337 - sizeof(struct dmub_rb_cmd_replay_set_frameupdate_timer); 334 + sizeof(struct dmub_rb_cmd_replay_set_frameupdate_timer) - 335 + sizeof(struct dmub_cmd_header); 338 336 //Cmd Body 339 337 cmd.replay_set_frameupdate_timer.data.panel_inst = 340 338 cmd_element->panel_inst; ··· 349 345 cmd.replay_set_pseudo_vtotal.header.sub_type = 350 346 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL; 351 347 cmd.replay_set_pseudo_vtotal.header.payload_bytes = 352 - sizeof(struct dmub_rb_cmd_replay_set_pseudo_vtotal); 348 + sizeof(struct dmub_rb_cmd_replay_set_pseudo_vtotal) - 349 + sizeof(struct dmub_cmd_header); 353 350 //Cmd Body 354 351 cmd.replay_set_pseudo_vtotal.data.panel_inst = 355 352 cmd_element->pseudo_vtotal_data.panel_inst; ··· 362 357 cmd.replay_disabled_adaptive_sync_sdp.header.sub_type = 363 358 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP; 364 359 cmd.replay_disabled_adaptive_sync_sdp.header.payload_bytes = 365 - sizeof(struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp); 360 + sizeof(struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp) - 361 + sizeof(struct dmub_cmd_header); 366 362 //Cmd Body 367 363 cmd.replay_disabled_adaptive_sync_sdp.data.panel_inst = 368 364 cmd_element->disabled_adaptive_sync_sdp_data.panel_inst; ··· 375 369 cmd.replay_set_general_cmd.header.sub_type = 376 370 DMUB_CMD__REPLAY_SET_GENERAL_CMD; 377 371 cmd.replay_set_general_cmd.header.payload_bytes = 378 - sizeof(struct dmub_rb_cmd_replay_set_general_cmd); 372 + sizeof(struct dmub_rb_cmd_replay_set_general_cmd) - 373 + sizeof(struct dmub_cmd_header); 379 374 //Cmd Body 380 375 cmd.replay_set_general_cmd.data.panel_inst = 381 376 cmd_element->set_general_cmd_data.panel_inst;

+2

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

··· 15 15 //#define DML_MODE_SUPPORT_USE_DPM_DRAM_BW 16 16 //#define DML_GLOBAL_PREFETCH_CHECK 17 17 #define ALLOW_SDPIF_RATE_LIMIT_PRE_CSTATE 18 + #define DML_MAX_VSTARTUP_START 1023 18 19 19 20 const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type) 20 21 { ··· 3738 3737 dml2_printf("DML::%s: vblank_avail = %u\n", __func__, vblank_avail); 3739 3738 dml2_printf("DML::%s: max_vstartup_lines = %u\n", __func__, max_vstartup_lines); 3740 3739 #endif 3740 + max_vstartup_lines = (unsigned int)math_min2(max_vstartup_lines, DML_MAX_VSTARTUP_START); 3741 3741 return max_vstartup_lines; 3742 3742 } 3743 3743

+7 -10

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

··· 1066 1066 DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1067 1067 } 1068 1068 1069 - if (!enable && link->dpcd_sink_ext_caps.bits.oled) { 1069 + if (!enable) { 1070 + /*follow oem panel config's requirement*/ 1070 1071 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms; 1071 1072 msleep(pre_T11_delay); 1072 1073 } ··· 1659 1658 1660 1659 params.vertical_total_min = stream->adjust.v_total_min; 1661 1660 params.vertical_total_max = stream->adjust.v_total_max; 1662 - if (pipe_ctx->stream_res.tg->funcs->set_drr) 1663 - pipe_ctx->stream_res.tg->funcs->set_drr( 1664 - pipe_ctx->stream_res.tg, &params); 1661 + set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params); 1665 1662 1666 1663 // DRR should set trigger event to monitor surface update event 1667 1664 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) ··· 1837 1838 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; 1838 1839 int i; 1839 1840 1840 - if (dc->ctx->dce_version != DCN_VERSION_3_5 && 1841 - dc->ctx->dce_version != DCN_VERSION_3_6 && 1842 - dc->ctx->dce_version != DCN_VERSION_3_51) 1841 + if (!dc->caps.is_apu || 1842 + dc->ctx->dce_version < DCN_VERSION_3_15) 1843 1843 return; 1844 - 1844 + /*VBIOS supports dsc starts from dcn315*/ 1845 1845 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1846 1846 struct dcn_dsc_state s = {0}; 1847 1847 ··· 2107 2109 struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; 2108 2110 2109 2111 if ((tg != NULL) && tg->funcs) { 2110 - if (tg->funcs->set_drr) 2111 - tg->funcs->set_drr(tg, &params); 2112 + set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params); 2112 2113 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 2113 2114 if (tg->funcs->set_static_screen_control) 2114 2115 tg->funcs->set_static_screen_control(

+2 -5

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

··· 1113 1113 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 1114 1114 1115 1115 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 1116 - if (pipe_ctx->stream_res.tg->funcs->set_drr) 1117 - pipe_ctx->stream_res.tg->funcs->set_drr( 1118 - pipe_ctx->stream_res.tg, NULL); 1116 + set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL); 1119 1117 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 1120 1118 pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0; 1121 1119 } ··· 3216 3218 struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; 3217 3219 3218 3220 if ((tg != NULL) && tg->funcs) { 3219 - if (tg->funcs->set_drr) 3220 - tg->funcs->set_drr(tg, &params); 3221 + set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params); 3221 3222 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 3222 3223 if (tg->funcs->set_static_screen_control) 3223 3224 tg->funcs->set_static_screen_control(

+2 -6

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

··· 952 952 params.vertical_total_max = stream->adjust.v_total_max; 953 953 params.vertical_total_mid = stream->adjust.v_total_mid; 954 954 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 955 - if (pipe_ctx->stream_res.tg->funcs->set_drr) 956 - pipe_ctx->stream_res.tg->funcs->set_drr( 957 - pipe_ctx->stream_res.tg, &params); 955 + set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params); 958 956 959 957 // DRR should set trigger event to monitor surface update event 960 958 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) ··· 2854 2856 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2855 2857 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2856 2858 2857 - if (pipe_ctx->stream_res.tg->funcs->set_drr) 2858 - pipe_ctx->stream_res.tg->funcs->set_drr( 2859 - pipe_ctx->stream_res.tg, NULL); 2859 + set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL); 2860 2860 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2861 2861 * the case where the same symclk is shared across multiple otg 2862 2862 * instances

+1 -3

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

··· 543 543 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 544 544 pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0; 545 545 546 - if (pipe_ctx->stream_res.tg->funcs->set_drr) 547 - pipe_ctx->stream_res.tg->funcs->set_drr( 548 - pipe_ctx->stream_res.tg, NULL); 546 + set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL); 549 547 550 548 /* DPMS may already disable or */ 551 549 /* dpms_off status is incorrect due to fastboot

+1 -2

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

··· 1473 1473 num_frames = 2 * (frame_rate % 60); 1474 1474 } 1475 1475 } 1476 - if (tg->funcs->set_drr) 1477 - tg->funcs->set_drr(tg, &params); 1476 + set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params); 1478 1477 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 1479 1478 if (tg->funcs->set_static_screen_control) 1480 1479 tg->funcs->set_static_screen_control(

+3 -7

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

··· 830 830 } 831 831 832 832 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 833 - 834 - if (pipe_ctx->stream_res.tg->funcs->set_drr) 835 - pipe_ctx->stream_res.tg->funcs->set_drr( 836 - pipe_ctx->stream_res.tg, &params); 833 + set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params); 837 834 838 835 /* Event triggers and num frames initialized for DRR, but can be 839 836 * later updated for PSR use. Note DRR trigger events are generated ··· 1817 1820 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1818 1821 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1819 1822 1820 - if (pipe_ctx->stream_res.tg->funcs->set_drr) 1821 - pipe_ctx->stream_res.tg->funcs->set_drr( 1822 - pipe_ctx->stream_res.tg, NULL); 1823 + set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL); 1824 + 1823 1825 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 1824 1826 * the case where the same symclk is shared across multiple otg 1825 1827 * instances

+6

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

··· 46 46 struct link_resource; 47 47 struct dc_dmub_cmd; 48 48 struct pg_block_update; 49 + struct drr_params; 49 50 50 51 struct subvp_pipe_control_lock_fast_params { 51 52 struct dc *dc; ··· 527 526 struct dc *dc, 528 527 struct dc_state *context, 529 528 struct pipe_ctx *pipe_ctx); 529 + 530 + void set_drr_and_clear_adjust_pending( 531 + struct pipe_ctx *pipe_ctx, 532 + struct dc_stream_state *stream, 533 + struct drr_params *params); 530 534 531 535 void hwss_execute_sequence(struct dc *dc, 532 536 struct block_sequence block_sequence[],

+45 -10

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

··· 265 265 supported_bw_in_kbps = 18000000; 266 266 else if (hdmi_encoded_link_bw.bits.BW_9Gbps) 267 267 supported_bw_in_kbps = 9000000; 268 + else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED) 269 + supported_bw_in_kbps = 0; /* This case should only get hit in regulated autonomous mode. */ 268 270 269 271 return supported_bw_in_kbps; 270 272 } ··· 1077 1075 return DC_OK; 1078 1076 } 1079 1077 1078 + static void read_and_intersect_post_frl_lt_status( 1079 + struct dc_link *link) 1080 + { 1081 + union autonomous_mode_and_frl_link_status autonomous_mode_caps = {0}; 1082 + union hdmi_tx_link_status hdmi_tx_link_status = {0}; 1083 + union hdmi_encoded_link_bw hdmi_encoded_link_bw = {0}; 1084 + 1085 + /* Check if dongle supports regulated autonomous mode. */ 1086 + core_link_read_dpcd(link, DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS, 1087 + &autonomous_mode_caps.raw, sizeof(autonomous_mode_caps)); 1088 + 1089 + link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support = 1090 + autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED; 1091 + 1092 + if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support) { 1093 + DC_LOG_DC("%s: PCON supports regulated autonomous mode.\n", __func__); 1094 + 1095 + core_link_read_dpcd(link, DP_PCON_HDMI_TX_LINK_STATUS, 1096 + &hdmi_tx_link_status.raw, sizeof(hdmi_tx_link_status)); 1097 + } 1098 + 1099 + // Intersect reported max link bw support with the supported link rate post FRL link training 1100 + if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS, 1101 + &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) { 1102 + 1103 + if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support && 1104 + (!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS || 1105 + !hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) { 1106 + DC_LOG_WARNING("%s: PCON TX link training has not finished.\n", __func__); 1107 + 1108 + /* Link training not finished, ignore values from this DPCD reg. */ 1109 + return; 1110 + } 1111 + 1112 + link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support( 1113 + link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps, 1114 + hdmi_encoded_link_bw); 1115 + DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__, 1116 + link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps); 1117 + } 1118 + } 1119 + 1080 1120 static void get_active_converter_info( 1081 1121 uint8_t data, struct dc_link *link) 1082 1122 { ··· 1207 1163 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); 1208 1164 1209 1165 if (link->dc->caps.dp_hdmi21_pcon_support) { 1210 - union hdmi_encoded_link_bw hdmi_encoded_link_bw; 1211 1166 1212 1167 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = 1213 1168 link_bw_kbps_from_raw_frl_link_rate_data( 1214 1169 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT); 1215 1170 1216 - // Intersect reported max link bw support with the supported link rate post FRL link training 1217 - if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS, 1218 - &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) { 1219 - link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support( 1220 - link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps, 1221 - hdmi_encoded_link_bw); 1222 - DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__, 1223 - link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps); 1224 - } 1171 + read_and_intersect_post_frl_lt_status(link); 1225 1172 1226 1173 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) 1227 1174 link->dpcd_caps.dongle_caps.extendedCapValid = true;

+1

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

··· 92 92 93 93 /* prepare QUERY_HPD command */ 94 94 cmd.query_hpd.header.type = DMUB_CMD__QUERY_HPD_STATE; 95 + cmd.query_hpd.header.payload_bytes = sizeof(cmd.query_hpd.data); 95 96 cmd.query_hpd.data.instance = link->link_id.enum_id - ENUM_ID_1; 96 97 cmd.query_hpd.data.ch_type = AUX_CHANNEL_DPIA; 97 98

+1 -4

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

··· 1789 1789 is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) && 1790 1790 (cur_link_settings.lane_count <= LANE_COUNT_ONE)); 1791 1791 1792 - if (is_link_bw_low) { 1792 + if (is_link_bw_low) 1793 1793 DC_LOG_WARNING( 1794 1794 "%s: Link(%d) bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n", 1795 1795 __func__, link->link_index, req_bw, link_bw); 1796 - 1797 - return false; 1798 - } 1799 1796 } 1800 1797 1801 1798 msleep(delay_between_attempts);

+22 -3

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

··· 675 675 if (!link) 676 676 return false; 677 677 678 + //Clear PSR cfg 679 + memset(&psr_configuration, 0, sizeof(psr_configuration)); 680 + dm_helpers_dp_write_dpcd( 681 + link->ctx, 682 + link, 683 + DP_PSR_EN_CFG, 684 + &psr_configuration.raw, 685 + sizeof(psr_configuration.raw)); 686 + 687 + if (link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) 688 + return false; 689 + 678 690 dc = link->ctx->dc; 679 691 dmcu = dc->res_pool->dmcu; 680 692 psr = dc->res_pool->psr; ··· 696 684 697 685 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) 698 686 return false; 699 - 700 - 701 - memset(&psr_configuration, 0, sizeof(psr_configuration)); 702 687 703 688 psr_configuration.bits.ENABLE = 1; 704 689 psr_configuration.bits.CRC_VERIFICATION = 1; ··· 958 949 959 950 if (!link) 960 951 return false; 952 + 953 + //Clear Replay config 954 + dm_helpers_dp_write_dpcd(link->ctx, link, 955 + DP_SINK_PR_ENABLE_AND_CONFIGURATION, 956 + (uint8_t *)&(replay_config.raw), sizeof(uint8_t)); 957 + 958 + if (!(link->replay_settings.config.replay_supported)) 959 + return false; 960 + 961 + link->replay_settings.config.replay_error_status.raw = 0; 961 962 962 963 dc = link->ctx->dc; 963 964

+2 -1

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

··· 2047 2047 2048 2048 int vlevel = 0; 2049 2049 int pipe_cnt = 0; 2050 - display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2050 + display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count, 2051 + sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2051 2052 DC_LOGGER_INIT(dc->ctx->logger); 2052 2053 2053 2054 BW_VAL_TRACE_COUNT();

+2 -1

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

··· 1768 1768 1769 1769 int vlevel = 0; 1770 1770 int pipe_cnt = 0; 1771 - display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1771 + display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count, 1772 + sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1772 1773 DC_LOGGER_INIT(dc->ctx->logger); 1773 1774 1774 1775 BW_VAL_TRACE_COUNT();

+2 -1

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

··· 1704 1704 1705 1705 int vlevel = 0; 1706 1706 int pipe_cnt = 0; 1707 - display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1707 + display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count, 1708 + sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1708 1709 DC_LOGGER_INIT(dc->ctx->logger); 1709 1710 1710 1711 BW_VAL_TRACE_COUNT();

+19 -21

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

··· 1698 1698 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1699 1699 DC_FP_START(); 1700 1700 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1701 - if (pixel_rate_crb && !pipe->top_pipe && !pipe->prev_odm_pipe) { 1701 + if (pixel_rate_crb) { 1702 1702 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); 1703 1703 /* Ceil to crb segment size */ 1704 1704 int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate( ··· 1755 1755 continue; 1756 1756 } 1757 1757 1758 - if (!pipe->top_pipe && !pipe->prev_odm_pipe) { 1759 - bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) 1760 - || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1758 + bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) 1759 + || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1761 1760 1762 - if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0) 1763 - pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes + 1764 - (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0); 1765 - if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) { 1766 - /* Clamp to 2 pipe split max det segments */ 1767 - remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS); 1768 - pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS; 1769 - } 1770 - if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) { 1771 - /* If we are splitting we must have an even number of segments */ 1772 - remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2; 1773 - pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2; 1774 - } 1775 - /* Convert segments into size for DML use */ 1776 - pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB; 1777 - 1778 - crb_idx++; 1761 + if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0) 1762 + pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes + 1763 + (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0); 1764 + if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) { 1765 + /* Clamp to 2 pipe split max det segments */ 1766 + remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS); 1767 + pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS; 1779 1768 } 1769 + if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) { 1770 + /* If we are splitting we must have an even number of segments */ 1771 + remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2; 1772 + pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2; 1773 + } 1774 + /* Convert segments into size for DML use */ 1775 + pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB; 1776 + 1777 + crb_idx++; 1780 1778 pipe_cnt++; 1781 1779 } 1782 1780 }

+2 -1

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

··· 1749 1749 1750 1750 int vlevel = 0; 1751 1751 int pipe_cnt = 0; 1752 - display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1752 + display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count, 1753 + sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1753 1754 1754 1755 /* To handle Freesync properly, setting FreeSync DML parameters 1755 1756 * to its default state for the first stage of validation

-3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h

··· 17 17 #define SPL_EXPAND(a, b) SPL_EXPAND2(a, b) 18 18 #define SPL_NAMESPACE(symbol) SPL_EXPAND(SPL_PFX_, symbol) 19 19 20 - #ifdef __cplusplus 21 - extern "C" { 22 - #endif 23 20 24 21 /* SPL interfaces */ 25 22

+94 -49

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

··· 51 51 * for the cache windows. 52 52 * 53 53 * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare 54 - * for command submission. Commands can be queued via dmub_srv_cmd_queue() 55 - * and executed via dmub_srv_cmd_execute(). 54 + * for command submission. Commands can be queued via dmub_srv_fb_cmd_queue() 55 + * and executed via dmub_srv_fb_cmd_execute(). 56 56 * 57 57 * If the queue is full the dmub_srv_wait_for_idle() call can be used to 58 58 * wait until the queue has been cleared. ··· 168 168 DMUB_POWER_STATE_UNDEFINED = 0, 169 169 DMUB_POWER_STATE_D0 = 1, 170 170 DMUB_POWER_STATE_D3 = 8 171 + }; 172 + 173 + /* enum dmub_inbox_cmd_interface type - defines default interface for host->dmub commands */ 174 + enum dmub_inbox_cmd_interface_type { 175 + DMUB_CMD_INTERFACE_DEFAULT = 0, 176 + DMUB_CMD_INTERFACE_FB = 1, 177 + DMUB_CMD_INTERFACE_REG = 2, 171 178 }; 172 179 173 180 /** ··· 320 313 * @timeout_occured: Indicates a timeout occured on any message from driver to dmub 321 314 * @timeout_cmd: first cmd sent from driver that timed out - subsequent timeouts are not stored 322 315 */ 323 - struct dmub_srv_debug { 316 + struct dmub_timeout_info { 324 317 bool timeout_occured; 325 318 union dmub_rb_cmd timeout_cmd; 326 319 unsigned long long timestamp; ··· 347 340 uint32_t outbox1_wptr; 348 341 uint32_t outbox1_size; 349 342 uint32_t gpint_datain0; 350 - struct dmub_srv_debug timeout_info; 343 + struct dmub_timeout_info timeout_info; 351 344 uint8_t is_dmcub_enabled : 1; 352 345 uint8_t is_dmcub_soft_reset : 1; 353 346 uint8_t is_dmcub_secure_reset : 1; 354 347 uint8_t is_traceport_en : 1; 355 348 uint8_t is_cw0_enabled : 1; 356 349 uint8_t is_cw6_enabled : 1; 350 + }; 351 + 352 + struct dmub_srv_inbox { 353 + /* generic status */ 354 + uint64_t num_submitted; 355 + uint64_t num_reported; 356 + union { 357 + /* frame buffer mailbox status */ 358 + struct dmub_rb rb; 359 + /* register mailbox status */ 360 + struct { 361 + bool is_pending; 362 + bool is_multi_pending; 363 + }; 364 + }; 357 365 }; 358 366 359 367 /** ··· 478 456 void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 479 457 uint32_t (*get_current_time)(struct dmub_srv *dmub); 480 458 481 - void (*get_diagnostic_data)(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca); 459 + void (*get_diagnostic_data)(struct dmub_srv *dmub); 482 460 483 461 bool (*should_detect)(struct dmub_srv *dmub); 484 462 void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx); 485 463 486 464 void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 465 + 487 466 void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub, 488 467 union dmub_rb_cmd *cmd); 489 468 uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub); 490 469 void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub, 491 470 union dmub_rb_cmd *cmd); 492 471 void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 472 + void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 473 + void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable); 474 + 493 475 uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub); 494 476 void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub); 495 477 void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg); 496 478 void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp); 497 479 uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub); 498 - void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable); 499 480 void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable); 500 481 }; 501 482 ··· 518 493 enum dmub_asic asic; 519 494 uint32_t fw_version; 520 495 bool is_virtual; 496 + enum dmub_inbox_cmd_interface_type inbox_type; 521 497 }; 522 498 523 499 /** ··· 545 519 struct dmub_srv_dcn32_regs *regs_dcn32; 546 520 struct dmub_srv_dcn35_regs *regs_dcn35; 547 521 const struct dmub_srv_dcn401_regs *regs_dcn401; 548 - 549 522 struct dmub_srv_base_funcs funcs; 550 523 struct dmub_srv_hw_funcs hw_funcs; 551 - struct dmub_rb inbox1_rb; 524 + struct dmub_srv_inbox inbox1; 552 525 uint32_t inbox1_last_wptr; 526 + struct dmub_srv_inbox reg_inbox0; 553 527 /** 554 528 * outbox1_rb is accessed without locks (dal & dc) 555 529 * and to be used only in dmub_srv_stat_get_notification() ··· 569 543 struct dmub_fw_meta_info meta_info; 570 544 struct dmub_feature_caps feature_caps; 571 545 struct dmub_visual_confirm_color visual_confirm_color; 546 + enum dmub_inbox_cmd_interface_type inbox_type; 572 547 573 548 enum dmub_srv_power_state_type power_state; 574 - struct dmub_srv_debug debug; 549 + struct dmub_diagnostic_data debug; 575 550 }; 576 551 577 552 /** ··· 727 700 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub); 728 701 729 702 /** 730 - * dmub_srv_sync_inbox1() - sync sw state with hw state 731 - * @dmub: the dmub service 732 - * 733 - * Sync sw state with hw state when resume from S0i3 734 - * 735 - * Return: 736 - * DMUB_STATUS_OK - success 737 - * DMUB_STATUS_INVALID - unspecified error 738 - */ 739 - enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub); 740 - 741 - /** 742 - * dmub_srv_cmd_queue() - queues a command to the DMUB 703 + * dmub_srv_fb_cmd_queue() - queues a command to the DMUB 743 704 * @dmub: the dmub service 744 705 * @cmd: the command to queue 745 706 * ··· 739 724 * DMUB_STATUS_QUEUE_FULL - no remaining room in queue 740 725 * DMUB_STATUS_INVALID - unspecified error 741 726 */ 742 - enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 727 + enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 743 728 const union dmub_rb_cmd *cmd); 744 729 745 730 /** 746 - * dmub_srv_cmd_execute() - Executes a queued sequence to the dmub 731 + * dmub_srv_fb_cmd_execute() - Executes a queued sequence to the dmub 747 732 * @dmub: the dmub service 748 733 * 749 734 * Begins execution of queued commands on the dmub. ··· 752 737 * DMUB_STATUS_OK - success 753 738 * DMUB_STATUS_INVALID - unspecified error 754 739 */ 755 - enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub); 740 + enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub); 756 741 757 742 /** 758 743 * dmub_srv_wait_for_hw_pwr_up() - Waits for firmware hardware power up is completed ··· 809 794 */ 810 795 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 811 796 uint32_t timeout_us); 797 + 798 + /** 799 + * dmub_srv_wait_for_pending() - Re-entrant wait for messages currently pending 800 + * @dmub: the dmub service 801 + * @timeout_us: the maximum number of microseconds to wait 802 + * 803 + * Waits until the commands queued prior to this call are complete. 804 + * If interfaces remain busy due to additional work being submitted 805 + * concurrently, this function will not continue to wait. 806 + * 807 + * Return: 808 + * DMUB_STATUS_OK - success 809 + * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 810 + * DMUB_STATUS_INVALID - unspecified error 811 + */ 812 + enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 813 + uint32_t timeout_us); 812 814 813 815 /** 814 816 * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle ··· 925 893 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 926 894 union dmub_fw_boot_options *option); 927 895 928 - enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 929 - union dmub_rb_cmd *cmd); 930 - 931 896 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 932 897 bool skip); 933 898 934 899 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); 935 900 936 - bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); 901 + bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub); 937 902 938 903 bool dmub_srv_should_detect(struct dmub_srv *dmub); 939 904 ··· 989 960 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 990 961 991 962 /** 992 - * dmub_srv_send_reg_inbox0_cmd() - send a dmub command and wait for the command 993 - * being processed by DMUB. 994 - * @dmub: The dmub service 995 - * @cmd: The dmub command being sent. If with_replay is true, the function will 996 - * update cmd with replied data. 997 - * @with_reply: true if DMUB reply needs to be copied back to cmd. false if the 998 - * cmd doesn't need to be replied. 999 - * @timeout_us: timeout in microseconds. 1000 - * 1001 - * Return: 1002 - * DMUB_STATUS_OK - success 1003 - * DMUB_STATUS_TIMEOUT - DMUB fails to process the command within the timeout 1004 - * interval. 1005 - */ 1006 - enum dmub_status dmub_srv_send_reg_inbox0_cmd( 1007 - struct dmub_srv *dmub, 1008 - union dmub_rb_cmd *cmd, 1009 - bool with_reply, uint32_t timeout_us); 1010 - 1011 - /** 1012 963 * dmub_srv_set_power_state() - Track DC power state in dmub_srv 1013 964 * @dmub: The dmub service 1014 965 * @power_state: DC power state setting ··· 999 990 * void 1000 991 */ 1001 992 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state); 993 + 994 + /** 995 + * dmub_srv_reg_cmd_execute() - Executes provided command to the dmub 996 + * @dmub: the dmub service 997 + * @cmd: the command packet to be executed 998 + * 999 + * Executes a single command for the dmub. 1000 + * 1001 + * Return: 1002 + * DMUB_STATUS_OK - success 1003 + * DMUB_STATUS_INVALID - unspecified error 1004 + */ 1005 + enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 1006 + 1007 + 1008 + /** 1009 + * dmub_srv_cmd_get_response() - Copies return data for command into buffer 1010 + * @dmub: the dmub service 1011 + * @cmd_rsp: response buffer 1012 + * 1013 + * Copies return data for command into buffer 1014 + */ 1015 + void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1016 + union dmub_rb_cmd *cmd_rsp); 1017 + 1018 + /** 1019 + * dmub_srv_sync_inboxes() - Sync inbox state 1020 + * @dmub: the dmub service 1021 + * 1022 + * Sync inbox state 1023 + * 1024 + * Return: 1025 + * DMUB_STATUS_OK - success 1026 + * DMUB_STATUS_INVALID - unspecified error 1027 + */ 1028 + enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub); 1002 1029 1003 1030 #endif /* _DMUB_SRV_H_ */

+48 -1

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

··· 1332 1332 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1333 1333 1334 1334 /** 1335 + * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1336 + */ 1337 + #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1338 + 1339 + /** 1340 + * Ringbuffer size in bytes. 1341 + */ 1342 + #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1343 + 1344 + /** 1335 1345 * REG_SET mask for reg offload. 1336 1346 */ 1337 1347 #define REG_SET_MASK 0xFFFF ··· 1543 1533 unsigned int sub_type : 8; /**< command sub type */ 1544 1534 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1545 1535 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1546 - unsigned int reserved0 : 6; /**< reserved bits */ 1536 + unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1537 + unsigned int reserved0 : 5; /**< reserved bits */ 1547 1538 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1548 1539 unsigned int reserved1 : 2; /**< reserved bits */ 1549 1540 }; ··· 5899 5888 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5900 5889 { 5901 5890 return (rb->wrpt == rb->rptr); 5891 + } 5892 + 5893 + /** 5894 + * @brief gets number of outstanding requests in the RB 5895 + * 5896 + * @param rb DMUB Ringbuffer 5897 + * @return true if full 5898 + */ 5899 + static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 5900 + { 5901 + uint32_t data_count; 5902 + 5903 + if (rb->wrpt >= rb->rptr) 5904 + data_count = rb->wrpt - rb->rptr; 5905 + else 5906 + data_count = rb->capacity - (rb->rptr - rb->wrpt); 5907 + 5908 + return data_count / DMUB_RB_CMD_SIZE; 5909 + } 5910 + 5911 + /** 5912 + * @brief gets number of free buffers in the RB 5913 + * 5914 + * @param rb DMUB Ringbuffer 5915 + * @return true if full 5916 + */ 5917 + static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 5918 + { 5919 + uint32_t data_count; 5920 + 5921 + if (rb->wrpt >= rb->rptr) 5922 + data_count = rb->wrpt - rb->rptr; 5923 + else 5924 + data_count = rb->capacity - (rb->rptr - rb->wrpt); 5925 + 5926 + return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 5902 5927 } 5903 5928 5904 5929 /**

+39 -36

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

··· 414 414 return REG_READ(DMCUB_TIMER_CURRENT); 415 415 } 416 416 417 - void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 417 + void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub) 418 418 { 419 419 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; 420 420 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 421 + struct dmub_timeout_info timeout = {0}; 421 422 422 - if (!dmub || !diag_data) 423 + if (!dmub) 423 424 return; 424 425 425 - memset(diag_data, 0, sizeof(*diag_data)); 426 + /* timeout data filled externally, cache before resetting memory */ 427 + timeout = dmub->debug.timeout_info; 428 + memset(&dmub->debug, 0, sizeof(dmub->debug)); 429 + dmub->debug.timeout_info = timeout; 426 430 427 - diag_data->dmcub_version = dmub->fw_version; 431 + dmub->debug.dmcub_version = dmub->fw_version; 428 432 429 - diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); 430 - diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); 431 - diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); 432 - diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); 433 - diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); 434 - diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); 435 - diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); 436 - diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); 437 - diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); 438 - diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); 439 - diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); 440 - diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); 441 - diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); 442 - diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); 443 - diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); 444 - diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); 433 + dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 434 + dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 435 + dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 436 + dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 437 + dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 438 + dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 439 + dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 440 + dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 441 + dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 442 + dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 443 + dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 444 + dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 445 + dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 446 + dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 447 + dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 448 + dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 445 449 446 - diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 447 - diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 448 - diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 450 + dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 451 + dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 452 + dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 449 453 450 - diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 451 - diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 452 - diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 454 + dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 455 + dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 456 + dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 453 457 454 - diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 455 - diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 456 - diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 458 + dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 459 + dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 460 + dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 457 461 458 462 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 459 - diag_data->is_dmcub_enabled = is_dmub_enabled; 463 + dmub->debug.is_dmcub_enabled = is_dmub_enabled; 460 464 461 465 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset); 462 - diag_data->is_dmcub_soft_reset = is_soft_reset; 466 + dmub->debug.is_dmcub_soft_reset = is_soft_reset; 463 467 464 468 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 465 - diag_data->is_dmcub_secure_reset = is_sec_reset; 469 + dmub->debug.is_dmcub_secure_reset = is_sec_reset; 466 470 467 471 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 468 - diag_data->is_traceport_en = is_traceport_enabled; 472 + dmub->debug.is_traceport_en = is_traceport_enabled; 469 473 470 474 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 471 - diag_data->is_cw0_enabled = is_cw0_enabled; 475 + dmub->debug.is_cw0_enabled = is_cw0_enabled; 472 476 473 477 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 474 - diag_data->is_cw6_enabled = is_cw6_enabled; 475 - diag_data->timeout_info = dmub->debug; 478 + dmub->debug.is_cw6_enabled = is_cw6_enabled; 476 479 }

+1 -1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

··· 247 247 248 248 uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub); 249 249 250 - void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca); 250 + void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub); 251 251 252 252 #endif /* _DMUB_DCN20_H_ */

+42 -39

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

··· 414 414 return REG_READ(DMCUB_TIMER_CURRENT); 415 415 } 416 416 417 - void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 417 + void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub) 418 418 { 419 419 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; 420 420 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 421 + struct dmub_timeout_info timeout = {0}; 421 422 422 - if (!dmub || !diag_data) 423 + if (!dmub) 423 424 return; 424 425 425 - memset(diag_data, 0, sizeof(*diag_data)); 426 + /* timeout data filled externally, cache before resetting memory */ 427 + timeout = dmub->debug.timeout_info; 428 + memset(&dmub->debug, 0, sizeof(dmub->debug)); 429 + dmub->debug.timeout_info = timeout; 426 430 427 - diag_data->dmcub_version = dmub->fw_version; 431 + dmub->debug.dmcub_version = dmub->fw_version; 428 432 429 - diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); 430 - diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); 431 - diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); 432 - diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); 433 - diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); 434 - diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); 435 - diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); 436 - diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); 437 - diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); 438 - diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); 439 - diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); 440 - diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); 441 - diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); 442 - diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); 443 - diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); 444 - diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); 433 + dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 434 + dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 435 + dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 436 + dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 437 + dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 438 + dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 439 + dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 440 + dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 441 + dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 442 + dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 443 + dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 444 + dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 445 + dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 446 + dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 447 + dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 448 + dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 445 449 446 - diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 447 - diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 448 - diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 450 + dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 451 + dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 452 + dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 449 453 450 - diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 451 - diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 452 - diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 454 + dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 455 + dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 456 + dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 453 457 454 - diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 455 - diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 456 - diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 458 + dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 459 + dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 460 + dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 457 461 458 - diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 459 - diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 460 - diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 462 + dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 463 + dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 464 + dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 461 465 462 466 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 463 - diag_data->is_dmcub_enabled = is_dmub_enabled; 467 + dmub->debug.is_dmcub_enabled = is_dmub_enabled; 464 468 465 469 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 466 - diag_data->is_dmcub_soft_reset = is_soft_reset; 470 + dmub->debug.is_dmcub_soft_reset = is_soft_reset; 467 471 468 472 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 469 - diag_data->is_dmcub_secure_reset = is_sec_reset; 473 + dmub->debug.is_dmcub_secure_reset = is_sec_reset; 470 474 471 475 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 472 - diag_data->is_traceport_en = is_traceport_enabled; 476 + dmub->debug.is_traceport_en = is_traceport_enabled; 473 477 474 478 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 475 - diag_data->is_cw0_enabled = is_cw0_enabled; 479 + dmub->debug.is_cw0_enabled = is_cw0_enabled; 476 480 477 481 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 478 - diag_data->is_cw6_enabled = is_cw6_enabled; 479 - diag_data->timeout_info = dmub->debug; 482 + dmub->debug.is_cw6_enabled = is_cw6_enabled; 480 483 } 481 484 482 485 bool dmub_dcn31_should_detect(struct dmub_srv *dmub)

+1 -1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

··· 251 251 252 252 uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub); 253 253 254 - void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); 254 + void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub); 255 255 256 256 bool dmub_dcn31_should_detect(struct dmub_srv *dmub); 257 257

+44 -42

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

··· 417 417 return REG_READ(DMCUB_TIMER_CURRENT); 418 418 } 419 419 420 - void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 420 + void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub) 421 421 { 422 422 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; 423 423 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 424 + struct dmub_timeout_info timeout = {0}; 424 425 425 - if (!dmub || !diag_data) 426 + if (!dmub) 426 427 return; 427 428 428 - memset(diag_data, 0, sizeof(*diag_data)); 429 + /* timeout data filled externally, cache before resetting memory */ 430 + timeout = dmub->debug.timeout_info; 431 + memset(&dmub->debug, 0, sizeof(dmub->debug)); 432 + dmub->debug.timeout_info = timeout; 429 433 430 - diag_data->dmcub_version = dmub->fw_version; 434 + dmub->debug.dmcub_version = dmub->fw_version; 431 435 432 - diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); 433 - diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); 434 - diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); 435 - diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); 436 - diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); 437 - diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); 438 - diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); 439 - diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); 440 - diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); 441 - diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); 442 - diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); 443 - diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); 444 - diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); 445 - diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); 446 - diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); 447 - diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); 448 - diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16); 436 + dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 437 + dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 438 + dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 439 + dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 440 + dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 441 + dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 442 + dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 443 + dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 444 + dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 445 + dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 446 + dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 447 + dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 448 + dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 449 + dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 450 + dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 451 + dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 452 + dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); 449 453 450 - diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 451 - diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 452 - diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 454 + dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 455 + dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 456 + dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 453 457 454 - diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 455 - diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 456 - diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 458 + dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 459 + dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 460 + dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 457 461 458 - diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 459 - diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 460 - diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 462 + dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 463 + dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 464 + dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 461 465 462 - diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 463 - diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 464 - diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 466 + dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 467 + dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 468 + dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 465 469 466 470 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 467 - diag_data->is_dmcub_enabled = is_dmub_enabled; 471 + dmub->debug.is_dmcub_enabled = is_dmub_enabled; 468 472 469 473 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 470 - diag_data->is_dmcub_soft_reset = is_soft_reset; 474 + dmub->debug.is_dmcub_soft_reset = is_soft_reset; 471 475 472 476 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 473 - diag_data->is_dmcub_secure_reset = is_sec_reset; 477 + dmub->debug.is_dmcub_secure_reset = is_sec_reset; 474 478 475 479 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 476 - diag_data->is_traceport_en = is_traceport_enabled; 480 + dmub->debug.is_traceport_en = is_traceport_enabled; 477 481 478 482 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 479 - diag_data->is_cw0_enabled = is_cw0_enabled; 483 + dmub->debug.is_cw0_enabled = is_cw0_enabled; 480 484 481 485 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 482 - diag_data->is_cw6_enabled = is_cw6_enabled; 486 + dmub->debug.is_cw6_enabled = is_cw6_enabled; 483 487 484 - diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 485 - 486 - diag_data->timeout_info = dmub->debug; 488 + dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 487 489 } 488 490 void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub) 489 491 {

+1 -1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

··· 254 254 255 255 uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub); 256 256 257 - void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); 257 + void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub); 258 258 259 259 void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub); 260 260 void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

+42 -39

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

··· 462 462 return REG_READ(DMCUB_TIMER_CURRENT); 463 463 } 464 464 465 - void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 465 + void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub) 466 466 { 467 467 uint32_t is_dmub_enabled, is_soft_reset; 468 468 uint32_t is_traceport_enabled, is_cw6_enabled; 469 + struct dmub_timeout_info timeout = {0}; 469 470 470 - if (!dmub || !diag_data) 471 + if (!dmub) 471 472 return; 472 473 473 - memset(diag_data, 0, sizeof(*diag_data)); 474 + /* timeout data filled externally, cache before resetting memory */ 475 + timeout = dmub->debug.timeout_info; 476 + memset(&dmub->debug, 0, sizeof(dmub->debug)); 477 + dmub->debug.timeout_info = timeout; 474 478 475 - diag_data->dmcub_version = dmub->fw_version; 479 + dmub->debug.dmcub_version = dmub->fw_version; 476 480 477 - diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); 478 - diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); 479 - diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); 480 - diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); 481 - diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); 482 - diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); 483 - diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); 484 - diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); 485 - diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); 486 - diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); 487 - diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); 488 - diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); 489 - diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); 490 - diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); 491 - diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); 492 - diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); 493 - diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16); 481 + dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 482 + dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 483 + dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 484 + dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 485 + dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 486 + dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 487 + dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 488 + dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 489 + dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 490 + dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 491 + dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 492 + dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 493 + dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 494 + dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 495 + dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 496 + dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 497 + dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); 494 498 495 - diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 496 - diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 497 - diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 499 + dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 500 + dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 501 + dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 498 502 499 - diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 500 - diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 501 - diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 503 + dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 504 + dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 505 + dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 502 506 503 - diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 504 - diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 505 - diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 507 + dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 508 + dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 509 + dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 506 510 507 - diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 508 - diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 509 - diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 511 + dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 512 + dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 513 + dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 510 514 511 515 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 512 - diag_data->is_dmcub_enabled = is_dmub_enabled; 516 + dmub->debug.is_dmcub_enabled = is_dmub_enabled; 513 517 514 518 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 515 - diag_data->is_dmcub_soft_reset = is_soft_reset; 519 + dmub->debug.is_dmcub_soft_reset = is_soft_reset; 516 520 517 521 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 518 - diag_data->is_traceport_en = is_traceport_enabled; 522 + dmub->debug.is_traceport_en = is_traceport_enabled; 519 523 520 524 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 521 - diag_data->is_cw6_enabled = is_cw6_enabled; 525 + dmub->debug.is_cw6_enabled = is_cw6_enabled; 522 526 523 - diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 524 - diag_data->timeout_info = dmub->debug; 527 + dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 525 528 } 526 529 void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub) 527 530 {

+1 -1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

··· 269 269 270 270 uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub); 271 271 272 - void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); 272 + void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub); 273 273 274 274 void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub); 275 275

+127 -79

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

··· 415 415 return REG_READ(DMCUB_TIMER_CURRENT); 416 416 } 417 417 418 - void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 418 + void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub) 419 419 { 420 420 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; 421 421 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 422 + struct dmub_timeout_info timeout = {0}; 422 423 423 - if (!dmub || !diag_data) 424 + if (!dmub) 424 425 return; 425 426 426 - memset(diag_data, 0, sizeof(*diag_data)); 427 + /* timeout data filled externally, cache before resetting memory */ 428 + timeout = dmub->debug.timeout_info; 429 + memset(&dmub->debug, 0, sizeof(dmub->debug)); 430 + dmub->debug.timeout_info = timeout; 427 431 428 - diag_data->dmcub_version = dmub->fw_version; 432 + dmub->debug.dmcub_version = dmub->fw_version; 429 433 430 - diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); 431 - diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); 432 - diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); 433 - diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); 434 - diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); 435 - diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); 436 - diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); 437 - diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); 438 - diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); 439 - diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); 440 - diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); 441 - diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); 442 - diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); 443 - diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); 444 - diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); 445 - diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); 446 - diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16); 434 + dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 435 + dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 436 + dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 437 + dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 438 + dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 439 + dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 440 + dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 441 + dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 442 + dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 443 + dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 444 + dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 445 + dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 446 + dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 447 + dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 448 + dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 449 + dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 450 + dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); 447 451 448 - diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 449 - diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 450 - diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 452 + dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 453 + dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 454 + dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 451 455 452 - diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 453 - diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 454 - diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 456 + dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 457 + dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 458 + dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 455 459 456 - diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 457 - diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 458 - diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 460 + dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 461 + dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 462 + dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 459 463 460 - diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 461 - diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 462 - diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 464 + dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 465 + dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 466 + dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 463 467 464 468 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 465 - diag_data->is_dmcub_enabled = is_dmub_enabled; 469 + dmub->debug.is_dmcub_enabled = is_dmub_enabled; 466 470 467 471 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 468 - diag_data->is_dmcub_soft_reset = is_soft_reset; 472 + dmub->debug.is_dmcub_soft_reset = is_soft_reset; 469 473 470 474 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 471 - diag_data->is_dmcub_secure_reset = is_sec_reset; 475 + dmub->debug.is_dmcub_secure_reset = is_sec_reset; 472 476 473 477 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 474 - diag_data->is_traceport_en = is_traceport_enabled; 478 + dmub->debug.is_traceport_en = is_traceport_enabled; 475 479 476 480 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 477 - diag_data->is_cw0_enabled = is_cw0_enabled; 481 + dmub->debug.is_cw0_enabled = is_cw0_enabled; 478 482 479 483 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 480 - diag_data->is_cw6_enabled = is_cw6_enabled; 484 + dmub->debug.is_cw6_enabled = is_cw6_enabled; 481 485 482 - diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 483 - diag_data->timeout_info = dmub->debug; 486 + dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 484 487 } 485 488 void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub) 486 489 { ··· 517 514 union dmub_rb_cmd *cmd) 518 515 { 519 516 uint32_t *dwords = (uint32_t *)cmd; 520 - 517 + int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; 518 + uint32_t msg_index; 521 519 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); 522 520 523 - REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[0]); 524 - REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[1]); 525 - REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[2]); 526 - REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[3]); 527 - REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[4]); 528 - REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[5]); 529 - REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[6]); 530 - REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[7]); 531 - REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[8]); 532 - REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[9]); 533 - REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[10]); 534 - REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[11]); 535 - REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[12]); 536 - REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[13]); 537 - REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[14]); 521 + /* read remaining data based on payload size */ 522 + for (msg_index = 0; msg_index < 15; msg_index++) { 523 + if (payload_size_bytes <= msg_index * 4) { 524 + break; 525 + } 526 + 527 + switch (msg_index) { 528 + case 0: 529 + REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]); 530 + break; 531 + case 1: 532 + REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]); 533 + break; 534 + case 2: 535 + REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]); 536 + break; 537 + case 3: 538 + REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]); 539 + break; 540 + case 4: 541 + REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]); 542 + break; 543 + case 5: 544 + REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]); 545 + break; 546 + case 6: 547 + REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]); 548 + break; 549 + case 7: 550 + REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]); 551 + break; 552 + case 8: 553 + REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]); 554 + break; 555 + case 9: 556 + REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]); 557 + break; 558 + case 10: 559 + REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]); 560 + break; 561 + case 11: 562 + REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]); 563 + break; 564 + case 12: 565 + REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]); 566 + break; 567 + case 13: 568 + REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]); 569 + break; 570 + case 14: 571 + REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]); 572 + break; 573 + } 574 + } 575 + 538 576 /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY 539 577 * interrupt. 540 578 */ 541 - REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[15]); 579 + REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]); 542 580 } 543 581 544 582 uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub) ··· 597 553 598 554 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); 599 555 600 - dwords[0] = REG_READ(DMCUB_REG_INBOX0_MSG0); 601 - dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG1); 602 - dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG2); 603 - dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG3); 604 - dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG4); 605 - dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG5); 606 - dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG6); 607 - dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG7); 608 - dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG8); 609 - dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG9); 610 - dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG10); 611 - dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG11); 612 - dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG12); 613 - dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG13); 614 - dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG14); 615 - dwords[15] = REG_READ(DMCUB_REG_INBOX0_RSP); 556 + dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP); 557 + dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0); 558 + dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1); 559 + dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2); 560 + dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3); 561 + dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4); 562 + dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5); 563 + dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6); 564 + dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7); 565 + dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8); 566 + dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9); 567 + dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10); 568 + dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11); 569 + dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12); 570 + dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13); 571 + dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14); 616 572 } 617 573 618 574 void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) 619 575 { 620 576 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1); 577 + } 578 + 579 + void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) 580 + { 621 581 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0); 582 + } 583 + 584 + void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable) 585 + { 586 + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0); 622 587 } 623 588 624 589 void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub) ··· 652 599 653 600 REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status); 654 601 return status; 655 - } 656 - 657 - void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable) 658 - { 659 - REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0); 660 602 } 661 603 662 604 void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)

+4 -2

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

··· 264 264 265 265 uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub); 266 266 267 - void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); 267 + void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub); 268 268 269 269 void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub); 270 270 void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); ··· 277 277 void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, 278 278 union dmub_rb_cmd *cmd); 279 279 void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); 280 + void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); 281 + void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable); 282 + 280 283 void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub); 281 284 void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg); 282 285 void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *msg); 283 286 uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub); 284 - void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable); 285 287 void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable); 286 288 uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub); 287 289

+218 -108

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

··· 157 157 { 158 158 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 159 159 160 + /* default to specifying now inbox type */ 161 + enum dmub_inbox_cmd_interface_type default_inbox_type = DMUB_CMD_INTERFACE_DEFAULT; 162 + 160 163 switch (asic) { 161 164 case DMUB_ASIC_DCN20: 162 165 case DMUB_ASIC_DCN21: ··· 356 353 357 354 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 358 355 if (asic == DMUB_ASIC_DCN351) 359 - funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 356 + funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 360 357 if (asic == DMUB_ASIC_DCN36) 361 358 funcs->init_reg_offsets = dmub_srv_dcn36_regs_init; 362 359 ··· 398 395 399 396 funcs->get_current_time = dmub_dcn401_get_current_time; 400 397 funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data; 398 + 401 399 funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg; 402 400 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status; 403 401 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp; 404 402 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack; 403 + funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack; 404 + funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 405 + default_inbox_type = DMUB_CMD_INTERFACE_FB; // still default to FB for now 406 + 405 407 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack; 406 408 funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg; 407 409 funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp; ··· 417 409 break; 418 410 default: 419 411 return false; 412 + } 413 + 414 + /* set default inbox type if not overriden */ 415 + if (dmub->inbox_type == DMUB_CMD_INTERFACE_DEFAULT) { 416 + if (default_inbox_type != DMUB_CMD_INTERFACE_DEFAULT) { 417 + /* use default inbox type as specified by DCN rev */ 418 + dmub->inbox_type = default_inbox_type; 419 + } else if (funcs->send_reg_inbox0_cmd_msg) { 420 + /* prefer reg as default inbox type if present */ 421 + dmub->inbox_type = DMUB_CMD_INTERFACE_REG; 422 + } else { 423 + /* use fb as fallback */ 424 + dmub->inbox_type = DMUB_CMD_INTERFACE_FB; 425 + } 420 426 } 421 427 422 428 return true; ··· 448 426 dmub->asic = params->asic; 449 427 dmub->fw_version = params->fw_version; 450 428 dmub->is_virtual = params->is_virtual; 429 + dmub->inbox_type = params->inbox_type; 451 430 452 431 /* Setup asic dependent hardware funcs. */ 453 432 if (!dmub_srv_hw_setup(dmub, params->asic)) { ··· 718 695 inbox1.base = cw4.region.base; 719 696 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 720 697 outbox1.base = inbox1.top; 721 - outbox1.top = cw4.region.top; 698 + outbox1.top = inbox1.top + DMUB_RB_SIZE; 722 699 723 700 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 724 701 cw5.region.base = DMUB_CW5_BASE; ··· 760 737 rb_params.ctx = dmub; 761 738 rb_params.base_address = mail_fb->cpu_addr; 762 739 rb_params.capacity = DMUB_RB_SIZE; 763 - dmub_rb_init(&dmub->inbox1_rb, &rb_params); 740 + dmub_rb_init(&dmub->inbox1.rb, &rb_params); 764 741 765 742 // Initialize outbox1 ring buffer 766 743 rb_params.ctx = dmub; ··· 791 768 return DMUB_STATUS_OK; 792 769 } 793 770 794 - enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 795 - { 796 - if (!dmub->sw_init) 797 - return DMUB_STATUS_INVALID; 798 - 799 - if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 800 - uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 801 - uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 802 - 803 - if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) { 804 - return DMUB_STATUS_HW_FAILURE; 805 - } else { 806 - dmub->inbox1_rb.rptr = rptr; 807 - dmub->inbox1_rb.wrpt = wptr; 808 - dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 809 - } 810 - } 811 - 812 - return DMUB_STATUS_OK; 813 - } 814 - 815 771 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 816 772 { 817 773 if (!dmub->sw_init) ··· 801 799 802 800 /* mailboxes have been reset in hw, so reset the sw state as well */ 803 801 dmub->inbox1_last_wptr = 0; 804 - dmub->inbox1_rb.wrpt = 0; 805 - dmub->inbox1_rb.rptr = 0; 802 + dmub->inbox1.rb.wrpt = 0; 803 + dmub->inbox1.rb.rptr = 0; 804 + dmub->inbox1.num_reported = 0; 805 + dmub->inbox1.num_submitted = 0; 806 + dmub->reg_inbox0.num_reported = 0; 807 + dmub->reg_inbox0.num_submitted = 0; 808 + dmub->reg_inbox0.is_pending = 0; 806 809 dmub->outbox0_rb.wrpt = 0; 807 810 dmub->outbox0_rb.rptr = 0; 808 811 dmub->outbox1_rb.wrpt = 0; ··· 818 811 return DMUB_STATUS_OK; 819 812 } 820 813 821 - enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 814 + enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 822 815 const union dmub_rb_cmd *cmd) 823 816 { 824 817 if (!dmub->hw_init) ··· 827 820 if (dmub->power_state != DMUB_POWER_STATE_D0) 828 821 return DMUB_STATUS_POWER_STATE_D3; 829 822 830 - if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity || 831 - dmub->inbox1_rb.wrpt > dmub->inbox1_rb.capacity) { 823 + if (dmub->inbox1.rb.rptr > dmub->inbox1.rb.capacity || 824 + dmub->inbox1.rb.wrpt > dmub->inbox1.rb.capacity) { 832 825 return DMUB_STATUS_HW_FAILURE; 833 826 } 834 827 835 - if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 828 + if (dmub_rb_push_front(&dmub->inbox1.rb, cmd)) { 829 + dmub->inbox1.num_submitted++; 836 830 return DMUB_STATUS_OK; 831 + } 837 832 838 833 return DMUB_STATUS_QUEUE_FULL; 839 834 } 840 835 841 - enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 836 + enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub) 842 837 { 843 838 struct dmub_rb flush_rb; 844 839 ··· 855 846 * been flushed to framebuffer memory. Otherwise DMCUB might 856 847 * read back stale, fully invalid or partially invalid data. 857 848 */ 858 - flush_rb = dmub->inbox1_rb; 849 + flush_rb = dmub->inbox1.rb; 859 850 flush_rb.rptr = dmub->inbox1_last_wptr; 860 851 dmub_rb_flush_pending(&flush_rb); 861 852 862 - dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 853 + dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1.rb.wrpt); 863 854 864 - dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 855 + dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 865 856 866 857 return DMUB_STATUS_OK; 867 858 } ··· 919 910 return DMUB_STATUS_TIMEOUT; 920 911 } 921 912 913 + static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub) 914 + { 915 + if (dmub->reg_inbox0.is_pending) { 916 + dmub->reg_inbox0.is_pending = dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 917 + !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 918 + 919 + if (!dmub->reg_inbox0.is_pending) { 920 + /* ack the rsp interrupt */ 921 + if (dmub->hw_funcs.write_reg_inbox0_rsp_int_ack) 922 + dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 923 + 924 + /* only update the reported count if commands aren't being batched */ 925 + if (!dmub->reg_inbox0.is_pending && !dmub->reg_inbox0.is_multi_pending) { 926 + dmub->reg_inbox0.num_reported = dmub->reg_inbox0.num_submitted; 927 + } 928 + } 929 + } 930 + } 931 + 932 + enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 933 + uint32_t timeout_us) 934 + { 935 + uint32_t i; 936 + const uint32_t polling_interval_us = 1; 937 + struct dmub_srv_inbox scratch_reg_inbox0 = dmub->reg_inbox0; 938 + struct dmub_srv_inbox scratch_inbox1 = dmub->inbox1; 939 + const volatile struct dmub_srv_inbox *reg_inbox0 = &dmub->reg_inbox0; 940 + const volatile struct dmub_srv_inbox *inbox1 = &dmub->inbox1; 941 + 942 + if (!dmub->hw_init || 943 + !dmub->hw_funcs.get_inbox1_wptr) 944 + return DMUB_STATUS_INVALID; 945 + 946 + /* take a snapshot of the required mailbox state */ 947 + scratch_inbox1.rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 948 + 949 + for (i = 0; i <= timeout_us; i += polling_interval_us) { 950 + scratch_inbox1.rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 951 + 952 + scratch_reg_inbox0.is_pending = scratch_reg_inbox0.is_pending && 953 + dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 954 + !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 955 + 956 + if (scratch_inbox1.rb.rptr > dmub->inbox1.rb.capacity) 957 + return DMUB_STATUS_HW_FAILURE; 958 + 959 + /* check current HW state first, but use command submission vs reported as a fallback */ 960 + if ((dmub_rb_empty(&scratch_inbox1.rb) || 961 + inbox1->num_reported >= scratch_inbox1.num_submitted) && 962 + (!scratch_reg_inbox0.is_pending || 963 + reg_inbox0->num_reported >= scratch_reg_inbox0.num_submitted)) 964 + return DMUB_STATUS_OK; 965 + 966 + udelay(polling_interval_us); 967 + } 968 + 969 + return DMUB_STATUS_TIMEOUT; 970 + } 971 + 922 972 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 923 973 uint32_t timeout_us) 924 974 { 925 975 uint32_t i, rptr; 976 + const uint32_t polling_interval_us = 1; 926 977 927 978 if (!dmub->hw_init) 928 979 return DMUB_STATUS_INVALID; 929 980 930 - for (i = 0; i <= timeout_us; ++i) { 931 - rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 981 + for (i = 0; i < timeout_us; i += polling_interval_us) { 982 + /* update inbox1 state */ 983 + rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 932 984 933 - if (rptr > dmub->inbox1_rb.capacity) 985 + if (rptr > dmub->inbox1.rb.capacity) 934 986 return DMUB_STATUS_HW_FAILURE; 935 987 936 - dmub->inbox1_rb.rptr = rptr; 988 + if (dmub->inbox1.rb.rptr > rptr) { 989 + /* rb wrapped */ 990 + dmub->inbox1.num_reported += (rptr + dmub->inbox1.rb.capacity - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 991 + } else { 992 + dmub->inbox1.num_reported += (rptr - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 993 + } 994 + dmub->inbox1.rb.rptr = rptr; 937 995 938 - if (dmub_rb_empty(&dmub->inbox1_rb)) 996 + /* update reg_inbox0 */ 997 + dmub_srv_update_reg_inbox0_status(dmub); 998 + 999 + /* check for idle */ 1000 + if (dmub_rb_empty(&dmub->inbox1.rb) && !dmub->reg_inbox0.is_pending) 939 1001 return DMUB_STATUS_OK; 940 1002 941 - udelay(1); 1003 + udelay(polling_interval_us); 942 1004 } 943 1005 944 1006 return DMUB_STATUS_TIMEOUT; ··· 1120 1040 return DMUB_STATUS_OK; 1121 1041 } 1122 1042 1123 - enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 1124 - union dmub_rb_cmd *cmd) 1125 - { 1126 - enum dmub_status status = DMUB_STATUS_OK; 1127 - 1128 - // Queue command 1129 - status = dmub_srv_cmd_queue(dmub, cmd); 1130 - 1131 - if (status != DMUB_STATUS_OK) 1132 - return status; 1133 - 1134 - // Execute command 1135 - status = dmub_srv_cmd_execute(dmub); 1136 - 1137 - if (status != DMUB_STATUS_OK) 1138 - return status; 1139 - 1140 - // Wait for DMUB to process command 1141 - status = dmub_srv_wait_for_idle(dmub, 100000); 1142 - 1143 - if (status != DMUB_STATUS_OK) 1144 - return status; 1145 - 1146 - // Copy data back from ring buffer into command 1147 - dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 1148 - 1149 - return status; 1150 - } 1151 - 1152 1043 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1153 1044 void *entry) 1154 1045 { ··· 1150 1099 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1151 1100 } 1152 1101 1153 - bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 1102 + bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub) 1154 1103 { 1155 - if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 1104 + if (!dmub || !dmub->hw_funcs.get_diagnostic_data) 1156 1105 return false; 1157 - dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 1106 + dmub->hw_funcs.get_diagnostic_data(dmub); 1158 1107 return true; 1159 1108 } 1160 1109 ··· 1211 1160 } 1212 1161 } 1213 1162 1214 - enum dmub_status dmub_srv_send_reg_inbox0_cmd( 1215 - struct dmub_srv *dmub, 1216 - union dmub_rb_cmd *cmd, 1217 - bool with_reply, uint32_t timeout_us) 1218 - { 1219 - uint32_t rsp_ready = 0; 1220 - uint32_t i; 1221 - 1222 - dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1223 - 1224 - for (i = 0; i < timeout_us; i++) { 1225 - rsp_ready = dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 1226 - if (rsp_ready) 1227 - break; 1228 - udelay(1); 1229 - } 1230 - if (rsp_ready == 0) 1231 - return DMUB_STATUS_TIMEOUT; 1232 - 1233 - if (with_reply) 1234 - dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd); 1235 - 1236 - dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 1237 - 1238 - /* wait for rsp int status is cleared to initial state before exit */ 1239 - for (; i <= timeout_us; i++) { 1240 - rsp_ready = dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 1241 - if (rsp_ready == 0) 1242 - break; 1243 - udelay(1); 1244 - } 1245 - ASSERT(rsp_ready == 0); 1246 - 1247 - return DMUB_STATUS_OK; 1248 - } 1249 - 1250 1163 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1251 1164 { 1252 1165 if (!dmub || !dmub->hw_init) 1253 1166 return; 1254 1167 1255 1168 dmub->power_state = dmub_srv_power_state; 1169 + } 1170 + 1171 + enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) 1172 + { 1173 + uint32_t num_pending = 0; 1174 + 1175 + if (!dmub->hw_init) 1176 + return DMUB_STATUS_INVALID; 1177 + 1178 + if (dmub->power_state != DMUB_POWER_STATE_D0) 1179 + return DMUB_STATUS_POWER_STATE_D3; 1180 + 1181 + if (!dmub->hw_funcs.send_reg_inbox0_cmd_msg || 1182 + !dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack) 1183 + return DMUB_STATUS_INVALID; 1184 + 1185 + if (dmub->reg_inbox0.num_submitted >= dmub->reg_inbox0.num_reported) 1186 + num_pending = dmub->reg_inbox0.num_submitted - dmub->reg_inbox0.num_reported; 1187 + else 1188 + /* num_submitted wrapped */ 1189 + num_pending = DMUB_REG_INBOX0_RB_MAX_ENTRY - 1190 + (dmub->reg_inbox0.num_reported - dmub->reg_inbox0.num_submitted); 1191 + 1192 + if (num_pending >= DMUB_REG_INBOX0_RB_MAX_ENTRY) 1193 + return DMUB_STATUS_QUEUE_FULL; 1194 + 1195 + /* clear last rsp ack and send message */ 1196 + dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack(dmub); 1197 + dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1198 + 1199 + dmub->reg_inbox0.num_submitted++; 1200 + dmub->reg_inbox0.is_pending = true; 1201 + dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending; 1202 + 1203 + return DMUB_STATUS_OK; 1204 + } 1205 + 1206 + void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1207 + union dmub_rb_cmd *cmd_rsp) 1208 + { 1209 + if (dmub) { 1210 + if (dmub->inbox_type == DMUB_CMD_INTERFACE_REG && 1211 + dmub->hw_funcs.read_reg_inbox0_cmd_rsp) { 1212 + dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd_rsp); 1213 + } else { 1214 + dmub_rb_get_return_data(&dmub->inbox1.rb, cmd_rsp); 1215 + } 1216 + } 1217 + } 1218 + 1219 + static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub) 1220 + { 1221 + if (!dmub || !dmub->sw_init) 1222 + return DMUB_STATUS_INVALID; 1223 + 1224 + dmub->reg_inbox0.is_pending = 0; 1225 + dmub->reg_inbox0.is_multi_pending = 0; 1226 + 1227 + return DMUB_STATUS_OK; 1228 + } 1229 + 1230 + static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 1231 + { 1232 + if (!dmub->sw_init) 1233 + return DMUB_STATUS_INVALID; 1234 + 1235 + if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 1236 + uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1237 + uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 1238 + 1239 + if (rptr > dmub->inbox1.rb.capacity || wptr > dmub->inbox1.rb.capacity) { 1240 + return DMUB_STATUS_HW_FAILURE; 1241 + } else { 1242 + dmub->inbox1.rb.rptr = rptr; 1243 + dmub->inbox1.rb.wrpt = wptr; 1244 + dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 1245 + } 1246 + } 1247 + 1248 + return DMUB_STATUS_OK; 1249 + } 1250 + 1251 + enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub) 1252 + { 1253 + enum dmub_status status; 1254 + 1255 + status = dmub_srv_sync_reg_inbox0(dmub); 1256 + if (status != DMUB_STATUS_OK) 1257 + return status; 1258 + 1259 + status = dmub_srv_sync_inbox1(dmub); 1260 + if (status != DMUB_STATUS_OK) 1261 + return status; 1262 + 1263 + return DMUB_STATUS_OK; 1256 1264 }

+3 -2

drivers/gpu/drm/amd/include/kgd_kfd_interface.h

··· 313 313 void (*get_iq_wait_times)(struct amdgpu_device *adev, 314 314 uint32_t *wait_times, 315 315 uint32_t inst); 316 - void (*build_grace_period_packet_info)(struct amdgpu_device *adev, 316 + void (*build_dequeue_wait_counts_packet_info)(struct amdgpu_device *adev, 317 317 uint32_t wait_times, 318 - uint32_t grace_period, 318 + uint32_t sch_wave, 319 + uint32_t que_sleep, 319 320 uint32_t *reg_offset, 320 321 uint32_t *reg_data); 321 322 void (*get_cu_occupancy)(struct amdgpu_device *adev,

+20 -9

drivers/gpu/drm/amd/pm/amdgpu_pm.c

··· 1936 1936 if (gc_ver == IP_VERSION(9, 4, 3) || 1937 1937 gc_ver == IP_VERSION(9, 4, 4) || 1938 1938 gc_ver == IP_VERSION(9, 5, 0)) { 1939 - if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1939 + if (amdgpu_sriov_multi_vf_mode(adev)) 1940 1940 *states = ATTR_STATE_UNSUPPORTED; 1941 1941 return 0; 1942 1942 } ··· 1971 1971 * setting should not be allowed from VF if not in one VF mode. 1972 1972 */ 1973 1973 if (gc_ver >= IP_VERSION(10, 0, 0) || 1974 - (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))) { 1974 + (amdgpu_sriov_multi_vf_mode(adev))) { 1975 1975 dev_attr->attr.mode &= ~S_IWUGO; 1976 1976 dev_attr->store = NULL; 1977 1977 } ··· 2314 2314 gc_ver == IP_VERSION(9, 0, 1)) 2315 2315 *states = ATTR_STATE_UNSUPPORTED; 2316 2316 } else if (DEVICE_ATTR_IS(vcn_busy_percent)) { 2317 - if (!(gc_ver == IP_VERSION(10, 3, 1) || 2318 - gc_ver == IP_VERSION(10, 3, 3) || 2319 - gc_ver == IP_VERSION(10, 3, 6) || 2320 - gc_ver == IP_VERSION(10, 3, 7) || 2321 - gc_ver == IP_VERSION(11, 0, 1) || 2322 - gc_ver == IP_VERSION(11, 0, 4) || 2323 - gc_ver == IP_VERSION(11, 5, 0))) 2317 + if (!(gc_ver == IP_VERSION(9, 3, 0) || 2318 + gc_ver == IP_VERSION(10, 3, 1) || 2319 + gc_ver == IP_VERSION(10, 3, 3) || 2320 + gc_ver == IP_VERSION(10, 3, 6) || 2321 + gc_ver == IP_VERSION(10, 3, 7) || 2322 + gc_ver == IP_VERSION(11, 0, 0) || 2323 + gc_ver == IP_VERSION(11, 0, 1) || 2324 + gc_ver == IP_VERSION(11, 0, 2) || 2325 + gc_ver == IP_VERSION(11, 0, 3) || 2326 + gc_ver == IP_VERSION(11, 0, 4) || 2327 + gc_ver == IP_VERSION(11, 5, 0) || 2328 + gc_ver == IP_VERSION(11, 5, 1) || 2329 + gc_ver == IP_VERSION(11, 5, 2) || 2330 + gc_ver == IP_VERSION(11, 5, 3) || 2331 + gc_ver == IP_VERSION(12, 0, 0) || 2332 + gc_ver == IP_VERSION(12, 0, 1))) 2324 2333 *states = ATTR_STATE_UNSUPPORTED; 2325 2334 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2326 2335 /* PCIe Perf counters won't work on APU nodes */ ··· 2350 2341 case IP_VERSION(11, 0, 1): 2351 2342 case IP_VERSION(11, 0, 2): 2352 2343 case IP_VERSION(11, 0, 3): 2344 + case IP_VERSION(12, 0, 0): 2345 + case IP_VERSION(12, 0, 1): 2353 2346 *states = ATTR_STATE_SUPPORTED; 2354 2347 break; 2355 2348 default:

+4 -4

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

··· 1814 1814 struct amdgpu_device *adev = ip_block->adev; 1815 1815 struct smu_context *smu = adev->powerplay.pp_handle; 1816 1816 1817 - if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1817 + if (amdgpu_sriov_multi_vf_mode(adev)) { 1818 1818 smu->pm_enabled = false; 1819 1819 return 0; 1820 1820 } ··· 2038 2038 struct smu_context *smu = adev->powerplay.pp_handle; 2039 2039 int i, ret; 2040 2040 2041 - if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2041 + if (amdgpu_sriov_multi_vf_mode(adev)) 2042 2042 return 0; 2043 2043 2044 2044 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { ··· 2106 2106 int ret; 2107 2107 uint64_t count; 2108 2108 2109 - if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2109 + if (amdgpu_sriov_multi_vf_mode(adev)) 2110 2110 return 0; 2111 2111 2112 2112 if (!smu->pm_enabled) ··· 2142 2142 struct amdgpu_device *adev = ip_block->adev; 2143 2143 struct smu_context *smu = adev->powerplay.pp_handle; 2144 2144 2145 - if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2145 + if (amdgpu_sriov_multi_vf_mode(adev)) 2146 2146 return 0; 2147 2147 2148 2148 if (!smu->pm_enabled)

+3 -1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

··· 356 356 __SMU_DUMMY_MAP(DS_FCLK), \ 357 357 __SMU_DUMMY_MAP(DS_MP1CLK), \ 358 358 __SMU_DUMMY_MAP(DS_MP0CLK), \ 359 + __SMU_DUMMY_MAP(DS_MPIOCLK), \ 359 360 __SMU_DUMMY_MAP(XGMI_PER_LINK_PWR_DWN), \ 360 361 __SMU_DUMMY_MAP(DPM_GFX_PACE), \ 361 362 __SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \ ··· 453 452 __SMU_DUMMY_MAP(APT_PF_DCS), \ 454 453 __SMU_DUMMY_MAP(GFX_EDC_XVMIN), \ 455 454 __SMU_DUMMY_MAP(GFX_DIDT_XVMIN), \ 456 - __SMU_DUMMY_MAP(FAN_ABNORMAL), 455 + __SMU_DUMMY_MAP(FAN_ABNORMAL), \ 456 + __SMU_DUMMY_MAP(PIT), 457 457 458 458 #undef __SMU_DUMMY_MAP 459 459 #define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT

+6

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

··· 1285 1285 (uint32_t *)data); 1286 1286 *size = 4; 1287 1287 break; 1288 + case AMDGPU_PP_SENSOR_VCN_LOAD: 1289 + ret = renoir_get_smu_metrics_data(smu, 1290 + METRICS_AVERAGE_VCNACTIVITY, 1291 + (uint32_t *)data); 1292 + *size = 4; 1293 + break; 1288 1294 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1289 1295 ret = renoir_get_smu_metrics_data(smu, 1290 1296 METRICS_TEMPERATURE_EDGE,

+10

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

··· 836 836 case METRICS_AVERAGE_MEMACTIVITY: 837 837 *value = metrics->AverageUclkActivity; 838 838 break; 839 + case METRICS_AVERAGE_VCNACTIVITY: 840 + *value = max(metrics->Vcn0ActivityPercentage, 841 + metrics->Vcn1ActivityPercentage); 842 + break; 839 843 case METRICS_AVERAGE_SOCKETPOWER: 840 844 *value = metrics->AverageSocketPower << 8; 841 845 break; ··· 963 959 case AMDGPU_PP_SENSOR_GPU_LOAD: 964 960 ret = smu_v13_0_0_get_smu_metrics_data(smu, 965 961 METRICS_AVERAGE_GFXACTIVITY, 962 + (uint32_t *)data); 963 + *size = 4; 964 + break; 965 + case AMDGPU_PP_SENSOR_VCN_LOAD: 966 + ret = smu_v13_0_0_get_smu_metrics_data(smu, 967 + METRICS_AVERAGE_VCNACTIVITY, 966 968 (uint32_t *)data); 967 969 *size = 4; 968 970 break;

+5

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

··· 76 76 SMU_13_0_12_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL), 77 77 SMU_13_0_12_FEA_MAP(SMU_FEATURE_SOC_PCC_BIT, FEATURE_SOC_PCC), 78 78 SMU_13_0_12_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN), 79 + SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN), 80 + SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK), 81 + SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK), 82 + SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK), 83 + SMU_13_0_12_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_PIT), 79 84 }; 80 85 81 86 // clang-format off

+10

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

··· 807 807 else 808 808 *value = metrics->AverageMemclkFrequencyPreDs; 809 809 break; 810 + case METRICS_AVERAGE_VCNACTIVITY: 811 + *value = max(metrics->Vcn0ActivityPercentage, 812 + metrics->Vcn1ActivityPercentage); 813 + break; 810 814 case METRICS_AVERAGE_VCLK: 811 815 *value = metrics->AverageVclk0Frequency; 812 816 break; ··· 952 948 case AMDGPU_PP_SENSOR_GPU_LOAD: 953 949 ret = smu_v13_0_7_get_smu_metrics_data(smu, 954 950 METRICS_AVERAGE_GFXACTIVITY, 951 + (uint32_t *)data); 952 + *size = 4; 953 + break; 954 + case AMDGPU_PP_SENSOR_VCN_LOAD: 955 + ret = smu_v13_0_7_get_smu_metrics_data(smu, 956 + METRICS_AVERAGE_VCNACTIVITY, 955 957 (uint32_t *)data); 956 958 *size = 4; 957 959 break;

+45

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

··· 756 756 case METRICS_AVERAGE_MEMACTIVITY: 757 757 *value = metrics->AverageUclkActivity; 758 758 break; 759 + case METRICS_AVERAGE_VCNACTIVITY: 760 + *value = max(metrics->AverageVcn0ActivityPercentage, 761 + metrics->Vcn1ActivityPercentage); 762 + break; 759 763 case METRICS_AVERAGE_SOCKETPOWER: 760 764 *value = metrics->AverageSocketPower << 8; 761 765 break; ··· 883 879 case AMDGPU_PP_SENSOR_GPU_LOAD: 884 880 ret = smu_v14_0_2_get_smu_metrics_data(smu, 885 881 METRICS_AVERAGE_GFXACTIVITY, 882 + (uint32_t *)data); 883 + *size = 4; 884 + break; 885 + case AMDGPU_PP_SENSOR_VCN_LOAD: 886 + ret = smu_v14_0_2_get_smu_metrics_data(smu, 887 + METRICS_AVERAGE_VCNACTIVITY, 886 888 (uint32_t *)data); 887 889 *size = 4; 888 890 break; ··· 1635 1625 1636 1626 out: 1637 1627 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1628 + } 1629 + 1630 + static int smu_v14_0_2_get_fan_speed_pwm(struct smu_context *smu, 1631 + uint32_t *speed) 1632 + { 1633 + int ret; 1634 + 1635 + if (!speed) 1636 + return -EINVAL; 1637 + 1638 + ret = smu_v14_0_2_get_smu_metrics_data(smu, 1639 + METRICS_CURR_FANPWM, 1640 + speed); 1641 + if (ret) { 1642 + dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!"); 1643 + return ret; 1644 + } 1645 + 1646 + /* Convert the PMFW output which is in percent to pwm(255) based */ 1647 + *speed = min(*speed * 255 / 100, (uint32_t)255); 1648 + 1649 + return 0; 1650 + } 1651 + 1652 + static int smu_v14_0_2_get_fan_speed_rpm(struct smu_context *smu, 1653 + uint32_t *speed) 1654 + { 1655 + if (!speed) 1656 + return -EINVAL; 1657 + 1658 + return smu_v14_0_2_get_smu_metrics_data(smu, 1659 + METRICS_CURR_FANSPEED, 1660 + speed); 1638 1661 } 1639 1662 1640 1663 static int smu_v14_0_2_get_power_limit(struct smu_context *smu, ··· 2847 2804 .set_performance_level = smu_v14_0_set_performance_level, 2848 2805 .gfx_off_control = smu_v14_0_gfx_off_control, 2849 2806 .get_unique_id = smu_v14_0_2_get_unique_id, 2807 + .get_fan_speed_pwm = smu_v14_0_2_get_fan_speed_pwm, 2808 + .get_fan_speed_rpm = smu_v14_0_2_get_fan_speed_rpm, 2850 2809 .get_power_limit = smu_v14_0_2_get_power_limit, 2851 2810 .set_power_limit = smu_v14_0_2_set_power_limit, 2852 2811 .get_power_profile_mode = smu_v14_0_2_get_power_profile_mode,

+1 -1

drivers/gpu/drm/radeon/radeon_vce.c

··· 557 557 { 558 558 int session_idx = -1; 559 559 bool destroyed = false, created = false, allocated = false; 560 - uint32_t tmp, handle = 0; 560 + uint32_t tmp = 0, handle = 0; 561 561 uint32_t *size = &tmp; 562 562 int i, r = 0; 563 563

Configure Feed

Configure Feed