tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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crypto: hisilicon/qm - add a function to set qm algs

Extract a public function to set qm algs and remove
the similar code for setting qm algs in each module.

Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com>
Signed-off-by: Hao Fang <fanghao11@huawei.com>
Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Wenkai Lin and committed by
Herbert Xu f76f0d7f 78aafb38

+62 -120
+4 -38
drivers/crypto/hisilicon/hpre/hpre_main.c
··· 118 118 #define HPRE_DFX_COMMON2_LEN 0xE 119 119 #define HPRE_DFX_CORE_LEN 0x43 120 120 121 - #define HPRE_DEV_ALG_MAX_LEN 256 122 - 123 121 static const char hpre_name[] = "hisi_hpre"; 124 122 static struct dentry *hpre_debugfs_root; 125 123 static const struct pci_device_id hpre_dev_ids[] = { ··· 133 135 const char *msg; 134 136 }; 135 137 136 - struct hpre_dev_alg { 137 - u32 alg_msk; 138 - const char *alg; 139 - }; 140 - 141 - static const struct hpre_dev_alg hpre_dev_algs[] = { 138 + static const struct qm_dev_alg hpre_dev_algs[] = { 142 139 { 143 140 .alg_msk = BIT(0), 144 141 .alg = "rsa\n" ··· 353 360 return true; 354 361 355 362 return false; 356 - } 357 - 358 - static int hpre_set_qm_algs(struct hisi_qm *qm) 359 - { 360 - struct device *dev = &qm->pdev->dev; 361 - char *algs, *ptr; 362 - u32 alg_msk; 363 - int i; 364 - 365 - if (!qm->use_sva) 366 - return 0; 367 - 368 - algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 369 - if (!algs) 370 - return -ENOMEM; 371 - 372 - alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); 373 - 374 - for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++) 375 - if (alg_msk & hpre_dev_algs[i].alg_msk) 376 - strcat(algs, hpre_dev_algs[i].alg); 377 - 378 - ptr = strrchr(algs, '\n'); 379 - if (ptr) 380 - *ptr = '\0'; 381 - 382 - qm->uacce->algs = algs; 383 - 384 - return 0; 385 363 } 386 364 387 365 static int hpre_diff_regs_show(struct seq_file *s, void *unused) ··· 1105 1141 1106 1142 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1107 1143 { 1144 + u64 alg_msk; 1108 1145 int ret; 1109 1146 1110 1147 if (pdev->revision == QM_HW_V1) { ··· 1136 1171 return ret; 1137 1172 } 1138 1173 1139 - ret = hpre_set_qm_algs(qm); 1174 + alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); 1175 + ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs)); 1140 1176 if (ret) { 1141 1177 pci_err(pdev, "Failed to set hpre algs!\n"); 1142 1178 hisi_qm_uninit(qm);
+36
drivers/crypto/hisilicon/qm.c
··· 234 234 #define QM_QOS_MAX_CIR_U 6 235 235 #define QM_AUTOSUSPEND_DELAY 3000 236 236 237 + #define QM_DEV_ALG_MAX_LEN 256 238 + 237 239 #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \ 238 240 (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \ 239 241 ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \ ··· 750 748 *low_bits = depth & QM_XQ_DEPTH_MASK; 751 749 *high_bits = (depth >> QM_XQ_DEPTH_SHIFT) & QM_XQ_DEPTH_MASK; 752 750 } 751 + 752 + int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, 753 + u32 dev_algs_size) 754 + { 755 + struct device *dev = &qm->pdev->dev; 756 + char *algs, *ptr; 757 + int i; 758 + 759 + if (!qm->uacce) 760 + return 0; 761 + 762 + if (dev_algs_size >= QM_DEV_ALG_MAX_LEN) { 763 + dev_err(dev, "algs size %u is equal or larger than %d.\n", 764 + dev_algs_size, QM_DEV_ALG_MAX_LEN); 765 + return -EINVAL; 766 + } 767 + 768 + algs = devm_kzalloc(dev, QM_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 769 + if (!algs) 770 + return -ENOMEM; 771 + 772 + for (i = 0; i < dev_algs_size; i++) 773 + if (alg_msk & dev_algs[i].alg_msk) 774 + strcat(algs, dev_algs[i].alg); 775 + 776 + ptr = strrchr(algs, '\n'); 777 + if (ptr) { 778 + *ptr = '\0'; 779 + qm->uacce->algs = algs; 780 + } 781 + 782 + return 0; 783 + } 784 + EXPORT_SYMBOL_GPL(hisi_qm_set_algs); 753 785 754 786 static u32 qm_get_irq_num(struct hisi_qm *qm) 755 787 {
+7 -40
drivers/crypto/hisilicon/sec2/sec_main.c
··· 120 120 GENMASK_ULL(42, 25)) 121 121 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \ 122 122 GENMASK_ULL(45, 43)) 123 - #define SEC_DEV_ALG_MAX_LEN 256 124 123 125 124 struct sec_hw_error { 126 125 u32 int_msk; ··· 129 130 struct sec_dfx_item { 130 131 const char *name; 131 132 u32 offset; 132 - }; 133 - 134 - struct sec_dev_alg { 135 - u64 alg_msk; 136 - const char *algs; 137 133 }; 138 134 139 135 static const char sec_name[] = "hisi_sec2"; ··· 167 173 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 168 174 }; 169 175 170 - static const struct sec_dev_alg sec_dev_algs[] = { { 176 + static const struct qm_dev_alg sec_dev_algs[] = { { 171 177 .alg_msk = SEC_CIPHER_BITMAP, 172 - .algs = "cipher\n", 178 + .alg = "cipher\n", 173 179 }, { 174 180 .alg_msk = SEC_DIGEST_BITMAP, 175 - .algs = "digest\n", 181 + .alg = "digest\n", 176 182 }, { 177 183 .alg_msk = SEC_AEAD_BITMAP, 178 - .algs = "aead\n", 184 + .alg = "aead\n", 179 185 }, 180 186 }; 181 187 ··· 1071 1077 return ret; 1072 1078 } 1073 1079 1074 - static int sec_set_qm_algs(struct hisi_qm *qm) 1075 - { 1076 - struct device *dev = &qm->pdev->dev; 1077 - char *algs, *ptr; 1078 - u64 alg_mask; 1079 - int i; 1080 - 1081 - if (!qm->use_sva) 1082 - return 0; 1083 - 1084 - algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 1085 - if (!algs) 1086 - return -ENOMEM; 1087 - 1088 - alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); 1089 - 1090 - for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++) 1091 - if (alg_mask & sec_dev_algs[i].alg_msk) 1092 - strcat(algs, sec_dev_algs[i].algs); 1093 - 1094 - ptr = strrchr(algs, '\n'); 1095 - if (ptr) 1096 - *ptr = '\0'; 1097 - 1098 - qm->uacce->algs = algs; 1099 - 1100 - return 0; 1101 - } 1102 - 1103 1080 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1104 1081 { 1082 + u64 alg_msk; 1105 1083 int ret; 1106 1084 1107 1085 qm->pdev = pdev; ··· 1108 1142 return ret; 1109 1143 } 1110 1144 1111 - ret = sec_set_qm_algs(qm); 1145 + alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); 1146 + ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); 1112 1147 if (ret) { 1113 1148 pci_err(qm->pdev, "Failed to set sec algs!\n"); 1114 1149 hisi_qm_uninit(qm);
+8 -41
drivers/crypto/hisilicon/zip/zip_main.c
··· 74 74 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 75 75 #define HZIP_WR_PORT BIT(11) 76 76 77 - #define HZIP_DEV_ALG_MAX_LEN 256 78 77 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 79 78 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 80 79 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) ··· 127 128 u32 offset; 128 129 }; 129 130 130 - struct zip_dev_alg { 131 - u32 alg_msk; 132 - const char *algs; 133 - }; 134 - 135 - static const struct zip_dev_alg zip_dev_algs[] = { { 131 + static const struct qm_dev_alg zip_dev_algs[] = { { 136 132 .alg_msk = HZIP_ALG_ZLIB_BIT, 137 - .algs = "zlib\n", 133 + .alg = "zlib\n", 138 134 }, { 139 135 .alg_msk = HZIP_ALG_GZIP_BIT, 140 - .algs = "gzip\n", 136 + .alg = "gzip\n", 141 137 }, { 142 138 .alg_msk = HZIP_ALG_DEFLATE_BIT, 143 - .algs = "deflate\n", 139 + .alg = "deflate\n", 144 140 }, { 145 141 .alg_msk = HZIP_ALG_LZ77_BIT, 146 - .algs = "lz77_zstd\n", 142 + .alg = "lz77_zstd\n", 147 143 }, 148 144 }; 149 145 ··· 470 476 pci_err(qm->pdev, "failed to set perf mode\n"); 471 477 472 478 return ret; 473 - } 474 - 475 - static int hisi_zip_set_qm_algs(struct hisi_qm *qm) 476 - { 477 - struct device *dev = &qm->pdev->dev; 478 - char *algs, *ptr; 479 - u32 alg_mask; 480 - int i; 481 - 482 - if (!qm->use_sva) 483 - return 0; 484 - 485 - algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 486 - if (!algs) 487 - return -ENOMEM; 488 - 489 - alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 490 - 491 - for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) 492 - if (alg_mask & zip_dev_algs[i].alg_msk) 493 - strcat(algs, zip_dev_algs[i].algs); 494 - 495 - ptr = strrchr(algs, '\n'); 496 - if (ptr) 497 - *ptr = '\0'; 498 - 499 - qm->uacce->algs = algs; 500 - 501 - return 0; 502 479 } 503 480 504 481 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) ··· 1158 1193 1159 1194 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1160 1195 { 1196 + u64 alg_msk; 1161 1197 int ret; 1162 1198 1163 1199 qm->pdev = pdev; ··· 1194 1228 return ret; 1195 1229 } 1196 1230 1197 - ret = hisi_zip_set_qm_algs(qm); 1231 + alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 1232 + ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); 1198 1233 if (ret) { 1199 1234 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1200 1235 hisi_qm_uninit(qm);
+7 -1
include/linux/hisi_acc_qm.h
··· 156 156 QM_SUPPORT_RPM, 157 157 }; 158 158 159 + struct qm_dev_alg { 160 + u64 alg_msk; 161 + const char *alg; 162 + }; 163 + 159 164 struct dfx_diff_registers { 160 165 u32 *regs; 161 166 u32 reg_offset; ··· 366 361 struct work_struct rst_work; 367 362 struct work_struct cmd_process; 368 363 369 - const char *algs; 370 364 bool use_sva; 371 365 372 366 resource_size_t phys_base; ··· 563 559 u32 hisi_qm_get_hw_info(struct hisi_qm *qm, 564 560 const struct hisi_qm_cap_info *info_table, 565 561 u32 index, bool is_read); 562 + int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, 563 + u32 dev_algs_size); 566 564 567 565 /* Used by VFIO ACC live migration driver */ 568 566 struct pci_driver *hisi_sec_get_pf_driver(void);