tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/bridge: dw-hdmi-qp: Fixup timer base setup

Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed
value as initially found in vendor driver code supporting the RK3588
SoC. As a matter of fact the value matches the rate of the HDMI TX
reference clock, which is roughly 428.57 MHz.

However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and
the incorrect register configuration breaks CEC functionality.

Set the timer base according to the actual reference clock rate that
shall be provided by the platform driver. Otherwise fallback to the
vendor default.

While at it, also drop the unnecessary empty lines in
dw_hdmi_qp_init_hw().

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250903-rk3588-hdmi-cec-v4-2-fa25163c4b08@collabora.com

authored by

Cristian Ciocaltea and committed by
Heiko Stuebner f7a1de0d e4a2d54a

+10 -3
+9 -3
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
··· 161 161 void *data; 162 162 } phy; 163 163 164 + unsigned long ref_clk_rate; 164 165 struct regmap *regm; 165 166 166 167 unsigned long tmds_char_rate; ··· 1211 1210 { 1212 1211 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1213 1212 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1214 - dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); 1213 + dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); 1215 1214 1216 1215 /* Software reset */ 1217 1216 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 1218 - 1219 1217 dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 1220 - 1221 1218 dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 1222 1219 1223 1220 /* Clear DONE and ERROR interrupts */ ··· 1260 1261 1261 1262 hdmi->phy.ops = plat_data->phy_ops; 1262 1263 hdmi->phy.data = plat_data->phy_data; 1264 + 1265 + if (plat_data->ref_clk_rate) { 1266 + hdmi->ref_clk_rate = plat_data->ref_clk_rate; 1267 + } else { 1268 + hdmi->ref_clk_rate = 428571429; 1269 + dev_warn(dev, "Set ref_clk_rate to vendor default\n"); 1270 + } 1263 1271 1264 1272 dw_hdmi_qp_init_hw(hdmi); 1265 1273
+1
include/drm/bridge/dw_hdmi_qp.h
··· 24 24 void *phy_data; 25 25 int main_irq; 26 26 int cec_irq; 27 + unsigned long ref_clk_rate; 27 28 }; 28 29 29 30 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,