+38 -24

arch/arm/Kconfig

reviewed

··· 114 114 bool 115 115 default y 116 116 117 117 - config GENERIC_BUST_SPINLOCK 118 118 - bool 119 119 - 120 117 config ARCH_MAY_HAVE_PC_FDC 121 118 bool 122 119 ··· 244 247 help 245 248 Support for Motorola's i.MX family of processors (MX1, MXL). 246 249 250 250 + config ARCH_IOP13XX 251 251 + bool "IOP13xx-based" 252 252 + depends on MMU 253 253 + select PLAT_IOP 254 254 + select PCI 255 255 + select ARCH_SUPPORTS_MSI 256 256 + help 257 257 + Support for Intel's IOP13XX (XScale) family of processors. 258 258 + 247 259 config ARCH_IOP32X 248 260 bool "IOP32x-based" 249 261 depends on MMU ··· 270 264 help 271 265 Support for Intel's IOP33X (XScale) family of processors. 272 266 273 273 - config ARCH_IOP13XX 274 274 - bool "IOP13xx-based" 267 267 + config ARCH_IXP23XX 268 268 + bool "IXP23XX-based" 275 269 depends on MMU 276 276 - select PLAT_IOP 277 277 - select PCI 278 278 - select ARCH_SUPPORTS_MSI 270 270 + select PCI 279 271 help 280 280 - Support for Intel's IOP13XX (XScale) family of processors. 281 281 - 282 282 - config ARCH_IXP4XX 283 283 - bool "IXP4xx-based" 284 284 - depends on MMU 285 285 - select GENERIC_TIME 286 286 - select GENERIC_CLOCKEVENTS 287 287 - help 288 288 - Support for Intel's IXP4XX (XScale) family of processors. 272 272 + Support for Intel's IXP23xx (XScale) family of processors. 289 273 290 274 config ARCH_IXP2000 291 275 bool "IXP2400/2800-based" ··· 284 288 help 285 289 Support for Intel's IXP2400/2800 (XScale) family of processors. 286 290 287 287 - config ARCH_IXP23XX 288 288 - bool "IXP23XX-based" 291 291 + config ARCH_IXP4XX 292 292 + bool "IXP4xx-based" 289 293 depends on MMU 290 290 - select PCI 294 294 + select GENERIC_TIME 295 295 + select GENERIC_CLOCKEVENTS 291 296 help 292 292 - Support for Intel's IXP23xx (XScale) family of processors. 297 297 + Support for Intel's IXP4XX (XScale) family of processors. 293 298 294 299 config ARCH_L7200 295 300 bool "LinkUp-L7200" ··· 304 307 305 308 If you have any questions or comments about the Linux kernel port 306 309 to this board, send e-mail to <sjhill@cotw.com>. 310 310 + 311 311 + config ARCH_KS8695 312 312 + bool "Micrel/Kendin KS8695" 313 313 + help 314 314 + Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 315 315 + System-on-Chip devices. 307 316 308 317 config ARCH_NS9XXX 309 318 bool "NetSilicon NS9xxx" ··· 357 354 config ARCH_S3C2410 358 355 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" 359 356 select GENERIC_GPIO 360 360 - select GENERIC_TIME 361 357 help 362 358 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 363 359 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or ··· 378 376 System on a Chip processors. These CPUs include an ARM922T 379 377 core with a wide array of integrated devices for 380 378 hand-held and low-power applications. 379 379 + 380 380 + config ARCH_DAVINCI 381 381 + bool "TI DaVinci" 382 382 + select GENERIC_TIME 383 383 + select GENERIC_CLOCKEVENTS 384 384 + help 385 385 + Support for TI's DaVinci platform. 381 386 382 387 config ARCH_OMAP 383 388 bool "TI OMAP" ··· 454 445 455 446 source "arch/arm/mach-ns9xxx/Kconfig" 456 447 448 448 + source "arch/arm/mach-davinci/Kconfig" 449 449 + 450 450 + source "arch/arm/mach-ks8695/Kconfig" 451 451 + 457 452 # Definitions to make life easier 458 453 config ARCH_ACORN 459 454 bool ··· 518 505 bool 519 506 520 507 config PCI 521 521 - bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX 508 508 + bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 522 509 help 523 510 Find out whether you have a PCI motherboard. PCI is the name of a 524 511 bus system, i.e. the way the CPU talks to the other stuff inside ··· 687 674 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 688 675 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 689 676 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 690 690 - ARCH_AT91 || MACH_TRIZEPS4 677 677 + ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \ 678 678 + ARCH_KS8695 691 679 help 692 680 If you say Y here, the LEDs on your machine will be used 693 681 to provide useful information about your current system status.

+2

arch/arm/Makefile

reviewed

··· 135 135 machine-$(CONFIG_ARCH_NETX) := netx 136 136 machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx 137 137 textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 138 138 + machine-$(CONFIG_ARCH_DAVINCI) := davinci 139 139 + machine-$(CONFIG_ARCH_KS8695) := ks8695 138 140 139 141 ifeq ($(CONFIG_ARCH_EBSA110),y) 140 142 # This is what happens if you forget the IOCS16 line.

+957

arch/arm/configs/at91sam9rlek_defconfig

reviewed

··· 1 1 + # 2 2 + # Automatically generated make config: don't edit 3 3 + # Linux kernel version: 2.6.21 4 4 + # Mon May 7 16:30:40 2007 5 5 + # 6 6 + CONFIG_ARM=y 7 7 + CONFIG_SYS_SUPPORTS_APM_EMULATION=y 8 8 + CONFIG_GENERIC_GPIO=y 9 9 + # CONFIG_GENERIC_TIME is not set 10 10 + CONFIG_MMU=y 11 11 + # CONFIG_NO_IOPORT is not set 12 12 + CONFIG_GENERIC_HARDIRQS=y 13 13 + CONFIG_TRACE_IRQFLAGS_SUPPORT=y 14 14 + CONFIG_HARDIRQS_SW_RESEND=y 15 15 + CONFIG_GENERIC_IRQ_PROBE=y 16 16 + CONFIG_RWSEM_GENERIC_SPINLOCK=y 17 17 + # CONFIG_ARCH_HAS_ILOG2_U32 is not set 18 18 + # CONFIG_ARCH_HAS_ILOG2_U64 is not set 19 19 + CONFIG_GENERIC_HWEIGHT=y 20 20 + CONFIG_GENERIC_CALIBRATE_DELAY=y 21 21 + CONFIG_ZONE_DMA=y 22 22 + CONFIG_VECTORS_BASE=0xffff0000 23 23 + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 24 24 + 25 25 + # 26 26 + # Code maturity level options 27 27 + # 28 28 + CONFIG_EXPERIMENTAL=y 29 29 + CONFIG_BROKEN_ON_SMP=y 30 30 + CONFIG_INIT_ENV_ARG_LIMIT=32 31 31 + 32 32 + # 33 33 + # General setup 34 34 + # 35 35 + CONFIG_LOCALVERSION="" 36 36 + # CONFIG_LOCALVERSION_AUTO is not set 37 37 + # CONFIG_SWAP is not set 38 38 + CONFIG_SYSVIPC=y 39 39 + # CONFIG_IPC_NS is not set 40 40 + CONFIG_SYSVIPC_SYSCTL=y 41 41 + # CONFIG_POSIX_MQUEUE is not set 42 42 + # CONFIG_BSD_PROCESS_ACCT is not set 43 43 + # CONFIG_TASKSTATS is not set 44 44 + # CONFIG_UTS_NS is not set 45 45 + # CONFIG_AUDIT is not set 46 46 + # CONFIG_IKCONFIG is not set 47 47 + CONFIG_SYSFS_DEPRECATED=y 48 48 + # CONFIG_RELAY is not set 49 49 + CONFIG_BLK_DEV_INITRD=y 50 50 + CONFIG_INITRAMFS_SOURCE="" 51 51 + CONFIG_CC_OPTIMIZE_FOR_SIZE=y 52 52 + CONFIG_SYSCTL=y 53 53 + # CONFIG_EMBEDDED is not set 54 54 + CONFIG_UID16=y 55 55 + CONFIG_SYSCTL_SYSCALL=y 56 56 + CONFIG_KALLSYMS=y 57 57 + # CONFIG_KALLSYMS_ALL is not set 58 58 + # CONFIG_KALLSYMS_EXTRA_PASS is not set 59 59 + CONFIG_HOTPLUG=y 60 60 + CONFIG_PRINTK=y 61 61 + CONFIG_BUG=y 62 62 + CONFIG_ELF_CORE=y 63 63 + CONFIG_BASE_FULL=y 64 64 + CONFIG_FUTEX=y 65 65 + CONFIG_EPOLL=y 66 66 + CONFIG_SHMEM=y 67 67 + CONFIG_SLAB=y 68 68 + CONFIG_VM_EVENT_COUNTERS=y 69 69 + CONFIG_RT_MUTEXES=y 70 70 + # CONFIG_TINY_SHMEM is not set 71 71 + CONFIG_BASE_SMALL=0 72 72 + # CONFIG_SLOB is not set 73 73 + 74 74 + # 75 75 + # Loadable module support 76 76 + # 77 77 + CONFIG_MODULES=y 78 78 + CONFIG_MODULE_UNLOAD=y 79 79 + # CONFIG_MODULE_FORCE_UNLOAD is not set 80 80 + # CONFIG_MODVERSIONS is not set 81 81 + # CONFIG_MODULE_SRCVERSION_ALL is not set 82 82 + CONFIG_KMOD=y 83 83 + 84 84 + # 85 85 + # Block layer 86 86 + # 87 87 + CONFIG_BLOCK=y 88 88 + # CONFIG_LBD is not set 89 89 + # CONFIG_BLK_DEV_IO_TRACE is not set 90 90 + # CONFIG_LSF is not set 91 91 + 92 92 + # 93 93 + # IO Schedulers 94 94 + # 95 95 + CONFIG_IOSCHED_NOOP=y 96 96 + CONFIG_IOSCHED_AS=y 97 97 + # CONFIG_IOSCHED_DEADLINE is not set 98 98 + # CONFIG_IOSCHED_CFQ is not set 99 99 + CONFIG_DEFAULT_AS=y 100 100 + # CONFIG_DEFAULT_DEADLINE is not set 101 101 + # CONFIG_DEFAULT_CFQ is not set 102 102 + # CONFIG_DEFAULT_NOOP is not set 103 103 + CONFIG_DEFAULT_IOSCHED="anticipatory" 104 104 + 105 105 + # 106 106 + # System Type 107 107 + # 108 108 + # CONFIG_ARCH_AAEC2000 is not set 109 109 + # CONFIG_ARCH_INTEGRATOR is not set 110 110 + # CONFIG_ARCH_REALVIEW is not set 111 111 + # CONFIG_ARCH_VERSATILE is not set 112 112 + CONFIG_ARCH_AT91=y 113 113 + # CONFIG_ARCH_CLPS7500 is not set 114 114 + # CONFIG_ARCH_CLPS711X is not set 115 115 + # CONFIG_ARCH_CO285 is not set 116 116 + # CONFIG_ARCH_EBSA110 is not set 117 117 + # CONFIG_ARCH_EP93XX is not set 118 118 + # CONFIG_ARCH_FOOTBRIDGE is not set 119 119 + # CONFIG_ARCH_NETX is not set 120 120 + # CONFIG_ARCH_H720X is not set 121 121 + # CONFIG_ARCH_IMX is not set 122 122 + # CONFIG_ARCH_IOP32X is not set 123 123 + # CONFIG_ARCH_IOP33X is not set 124 124 + # CONFIG_ARCH_IOP13XX is not set 125 125 + # CONFIG_ARCH_IXP4XX is not set 126 126 + # CONFIG_ARCH_IXP2000 is not set 127 127 + # CONFIG_ARCH_IXP23XX is not set 128 128 + # CONFIG_ARCH_L7200 is not set 129 129 + # CONFIG_ARCH_NS9XXX is not set 130 130 + # CONFIG_ARCH_PNX4008 is not set 131 131 + # CONFIG_ARCH_PXA is not set 132 132 + # CONFIG_ARCH_RPC is not set 133 133 + # CONFIG_ARCH_SA1100 is not set 134 134 + # CONFIG_ARCH_S3C2410 is not set 135 135 + # CONFIG_ARCH_SHARK is not set 136 136 + # CONFIG_ARCH_LH7A40X is not set 137 137 + # CONFIG_ARCH_OMAP is not set 138 138 + 139 139 + # 140 140 + # Atmel AT91 System-on-Chip 141 141 + # 142 142 + # CONFIG_ARCH_AT91RM9200 is not set 143 143 + # CONFIG_ARCH_AT91SAM9260 is not set 144 144 + # CONFIG_ARCH_AT91SAM9261 is not set 145 145 + # CONFIG_ARCH_AT91SAM9263 is not set 146 146 + CONFIG_ARCH_AT91SAM9RL=y 147 147 + 148 148 + # 149 149 + # AT91SAM9RL Board Type 150 150 + # 151 151 + CONFIG_MACH_AT91SAM9RLEK=y 152 152 + 153 153 + # 154 154 + # AT91 Board Options 155 155 + # 156 156 + 157 157 + # 158 158 + # AT91 Feature Selections 159 159 + # 160 160 + # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set 161 161 + 162 162 + # 163 163 + # Processor Type 164 164 + # 165 165 + CONFIG_CPU_32=y 166 166 + CONFIG_CPU_ARM926T=y 167 167 + CONFIG_CPU_32v5=y 168 168 + CONFIG_CPU_ABRT_EV5TJ=y 169 169 + CONFIG_CPU_CACHE_VIVT=y 170 170 + CONFIG_CPU_COPY_V4WB=y 171 171 + CONFIG_CPU_TLB_V4WBI=y 172 172 + CONFIG_CPU_CP15=y 173 173 + CONFIG_CPU_CP15_MMU=y 174 174 + 175 175 + # 176 176 + # Processor Features 177 177 + # 178 178 + # CONFIG_ARM_THUMB is not set 179 179 + # CONFIG_CPU_ICACHE_DISABLE is not set 180 180 + # CONFIG_CPU_DCACHE_DISABLE is not set 181 181 + # CONFIG_CPU_DCACHE_WRITETHROUGH is not set 182 182 + # CONFIG_CPU_CACHE_ROUND_ROBIN is not set 183 183 + # CONFIG_OUTER_CACHE is not set 184 184 + 185 185 + # 186 186 + # Bus support 187 187 + # 188 188 + 189 189 + # 190 190 + # PCCARD (PCMCIA/CardBus) support 191 191 + # 192 192 + # CONFIG_PCCARD is not set 193 193 + 194 194 + # 195 195 + # Kernel Features 196 196 + # 197 197 + # CONFIG_PREEMPT is not set 198 198 + # CONFIG_NO_IDLE_HZ is not set 199 199 + CONFIG_HZ=100 200 200 + # CONFIG_AEABI is not set 201 201 + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 202 202 + CONFIG_SELECT_MEMORY_MODEL=y 203 203 + CONFIG_FLATMEM_MANUAL=y 204 204 + # CONFIG_DISCONTIGMEM_MANUAL is not set 205 205 + # CONFIG_SPARSEMEM_MANUAL is not set 206 206 + CONFIG_FLATMEM=y 207 207 + CONFIG_FLAT_NODE_MEM_MAP=y 208 208 + # CONFIG_SPARSEMEM_STATIC is not set 209 209 + CONFIG_SPLIT_PTLOCK_CPUS=4096 210 210 + # CONFIG_RESOURCES_64BIT is not set 211 211 + CONFIG_ZONE_DMA_FLAG=1 212 212 + # CONFIG_LEDS is not set 213 213 + CONFIG_ALIGNMENT_TRAP=y 214 214 + 215 215 + # 216 216 + # Boot options 217 217 + # 218 218 + CONFIG_ZBOOT_ROM_TEXT=0x0 219 219 + CONFIG_ZBOOT_ROM_BSS=0x0 220 220 + CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw" 221 221 + # CONFIG_XIP_KERNEL is not set 222 222 + # CONFIG_KEXEC is not set 223 223 + 224 224 + # 225 225 + # Floating point emulation 226 226 + # 227 227 + 228 228 + # 229 229 + # At least one emulation must be selected 230 230 + # 231 231 + CONFIG_FPE_NWFPE=y 232 232 + # CONFIG_FPE_NWFPE_XP is not set 233 233 + # CONFIG_FPE_FASTFPE is not set 234 234 + # CONFIG_VFP is not set 235 235 + 236 236 + # 237 237 + # Userspace binary formats 238 238 + # 239 239 + CONFIG_BINFMT_ELF=y 240 240 + # CONFIG_BINFMT_AOUT is not set 241 241 + # CONFIG_BINFMT_MISC is not set 242 242 + # CONFIG_ARTHUR is not set 243 243 + 244 244 + # 245 245 + # Power management options 246 246 + # 247 247 + # CONFIG_PM is not set 248 248 + 249 249 + # 250 250 + # Networking 251 251 + # 252 252 + CONFIG_NET=y 253 253 + 254 254 + # 255 255 + # Networking options 256 256 + # 257 257 + # CONFIG_NETDEBUG is not set 258 258 + # CONFIG_PACKET is not set 259 259 + CONFIG_UNIX=y 260 260 + # CONFIG_NET_KEY is not set 261 261 + # CONFIG_INET is not set 262 262 + # CONFIG_NETWORK_SECMARK is not set 263 263 + # CONFIG_NETFILTER is not set 264 264 + # CONFIG_ATM is not set 265 265 + # CONFIG_BRIDGE is not set 266 266 + # CONFIG_VLAN_8021Q is not set 267 267 + # CONFIG_DECNET is not set 268 268 + # CONFIG_LLC2 is not set 269 269 + # CONFIG_IPX is not set 270 270 + # CONFIG_ATALK is not set 271 271 + # CONFIG_X25 is not set 272 272 + # CONFIG_LAPB is not set 273 273 + # CONFIG_WAN_ROUTER is not set 274 274 + 275 275 + # 276 276 + # QoS and/or fair queueing 277 277 + # 278 278 + # CONFIG_NET_SCHED is not set 279 279 + 280 280 + # 281 281 + # Network testing 282 282 + # 283 283 + # CONFIG_NET_PKTGEN is not set 284 284 + # CONFIG_HAMRADIO is not set 285 285 + # CONFIG_IRDA is not set 286 286 + # CONFIG_BT is not set 287 287 + # CONFIG_IEEE80211 is not set 288 288 + 289 289 + # 290 290 + # Device Drivers 291 291 + # 292 292 + 293 293 + # 294 294 + # Generic Driver Options 295 295 + # 296 296 + CONFIG_STANDALONE=y 297 297 + CONFIG_PREVENT_FIRMWARE_BUILD=y 298 298 + # CONFIG_FW_LOADER is not set 299 299 + # CONFIG_DEBUG_DRIVER is not set 300 300 + # CONFIG_DEBUG_DEVRES is not set 301 301 + # CONFIG_SYS_HYPERVISOR is not set 302 302 + 303 303 + # 304 304 + # Connector - unified userspace <-> kernelspace linker 305 305 + # 306 306 + # CONFIG_CONNECTOR is not set 307 307 + 308 308 + # 309 309 + # Memory Technology Devices (MTD) 310 310 + # 311 311 + CONFIG_MTD=y 312 312 + # CONFIG_MTD_DEBUG is not set 313 313 + CONFIG_MTD_CONCAT=y 314 314 + CONFIG_MTD_PARTITIONS=y 315 315 + # CONFIG_MTD_REDBOOT_PARTS is not set 316 316 + CONFIG_MTD_CMDLINE_PARTS=y 317 317 + # CONFIG_MTD_AFS_PARTS is not set 318 318 + 319 319 + # 320 320 + # User Modules And Translation Layers 321 321 + # 322 322 + CONFIG_MTD_CHAR=y 323 323 + CONFIG_MTD_BLKDEVS=y 324 324 + CONFIG_MTD_BLOCK=y 325 325 + # CONFIG_FTL is not set 326 326 + # CONFIG_NFTL is not set 327 327 + # CONFIG_INFTL is not set 328 328 + # CONFIG_RFD_FTL is not set 329 329 + # CONFIG_SSFDC is not set 330 330 + 331 331 + # 332 332 + # RAM/ROM/Flash chip drivers 333 333 + # 334 334 + # CONFIG_MTD_CFI is not set 335 335 + # CONFIG_MTD_JEDECPROBE is not set 336 336 + CONFIG_MTD_MAP_BANK_WIDTH_1=y 337 337 + CONFIG_MTD_MAP_BANK_WIDTH_2=y 338 338 + CONFIG_MTD_MAP_BANK_WIDTH_4=y 339 339 + # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set 340 340 + # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set 341 341 + # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set 342 342 + CONFIG_MTD_CFI_I1=y 343 343 + CONFIG_MTD_CFI_I2=y 344 344 + # CONFIG_MTD_CFI_I4 is not set 345 345 + # CONFIG_MTD_CFI_I8 is not set 346 346 + # CONFIG_MTD_RAM is not set 347 347 + # CONFIG_MTD_ROM is not set 348 348 + # CONFIG_MTD_ABSENT is not set 349 349 + # CONFIG_MTD_OBSOLETE_CHIPS is not set 350 350 + 351 351 + # 352 352 + # Mapping drivers for chip access 353 353 + # 354 354 + # CONFIG_MTD_COMPLEX_MAPPINGS is not set 355 355 + # CONFIG_MTD_PLATRAM is not set 356 356 + 357 357 + # 358 358 + # Self-contained MTD device drivers 359 359 + # 360 360 + CONFIG_MTD_DATAFLASH=y 361 361 + # CONFIG_MTD_M25P80 is not set 362 362 + # CONFIG_MTD_SLRAM is not set 363 363 + # CONFIG_MTD_PHRAM is not set 364 364 + # CONFIG_MTD_MTDRAM is not set 365 365 + # CONFIG_MTD_BLOCK2MTD is not set 366 366 + 367 367 + # 368 368 + # Disk-On-Chip Device Drivers 369 369 + # 370 370 + # CONFIG_MTD_DOC2000 is not set 371 371 + # CONFIG_MTD_DOC2001 is not set 372 372 + # CONFIG_MTD_DOC2001PLUS is not set 373 373 + 374 374 + # 375 375 + # NAND Flash Device Drivers 376 376 + # 377 377 + CONFIG_MTD_NAND=y 378 378 + # CONFIG_MTD_NAND_VERIFY_WRITE is not set 379 379 + # CONFIG_MTD_NAND_ECC_SMC is not set 380 380 + CONFIG_MTD_NAND_IDS=y 381 381 + # CONFIG_MTD_NAND_DISKONCHIP is not set 382 382 + CONFIG_MTD_NAND_AT91=y 383 383 + # CONFIG_MTD_NAND_NANDSIM is not set 384 384 + 385 385 + # 386 386 + # OneNAND Flash Device Drivers 387 387 + # 388 388 + # CONFIG_MTD_ONENAND is not set 389 389 + 390 390 + # 391 391 + # Parallel port support 392 392 + # 393 393 + # CONFIG_PARPORT is not set 394 394 + 395 395 + # 396 396 + # Plug and Play support 397 397 + # 398 398 + # CONFIG_PNPACPI is not set 399 399 + 400 400 + # 401 401 + # Block devices 402 402 + # 403 403 + # CONFIG_BLK_DEV_COW_COMMON is not set 404 404 + CONFIG_BLK_DEV_LOOP=y 405 405 + # CONFIG_BLK_DEV_CRYPTOLOOP is not set 406 406 + # CONFIG_BLK_DEV_NBD is not set 407 407 + CONFIG_BLK_DEV_RAM=y 408 408 + CONFIG_BLK_DEV_RAM_COUNT=4 409 409 + CONFIG_BLK_DEV_RAM_SIZE=24576 410 410 + CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 411 411 + # CONFIG_CDROM_PKTCDVD is not set 412 412 + # CONFIG_ATA_OVER_ETH is not set 413 413 + 414 414 + # 415 415 + # SCSI device support 416 416 + # 417 417 + # CONFIG_RAID_ATTRS is not set 418 418 + CONFIG_SCSI=y 419 419 + # CONFIG_SCSI_TGT is not set 420 420 + # CONFIG_SCSI_NETLINK is not set 421 421 + CONFIG_SCSI_PROC_FS=y 422 422 + 423 423 + # 424 424 + # SCSI support type (disk, tape, CD-ROM) 425 425 + # 426 426 + CONFIG_BLK_DEV_SD=y 427 427 + # CONFIG_CHR_DEV_ST is not set 428 428 + # CONFIG_CHR_DEV_OSST is not set 429 429 + # CONFIG_BLK_DEV_SR is not set 430 430 + # CONFIG_CHR_DEV_SG is not set 431 431 + # CONFIG_CHR_DEV_SCH is not set 432 432 + 433 433 + # 434 434 + # Some SCSI devices (e.g. CD jukebox) support multiple LUNs 435 435 + # 436 436 + CONFIG_SCSI_MULTI_LUN=y 437 437 + # CONFIG_SCSI_CONSTANTS is not set 438 438 + # CONFIG_SCSI_LOGGING is not set 439 439 + # CONFIG_SCSI_SCAN_ASYNC is not set 440 440 + 441 441 + # 442 442 + # SCSI Transports 443 443 + # 444 444 + # CONFIG_SCSI_SPI_ATTRS is not set 445 445 + # CONFIG_SCSI_FC_ATTRS is not set 446 446 + # CONFIG_SCSI_ISCSI_ATTRS is not set 447 447 + # CONFIG_SCSI_SAS_ATTRS is not set 448 448 + # CONFIG_SCSI_SAS_LIBSAS is not set 449 449 + 450 450 + # 451 451 + # SCSI low-level drivers 452 452 + # 453 453 + # CONFIG_SCSI_DEBUG is not set 454 454 + 455 455 + # 456 456 + # Serial ATA (prod) and Parallel ATA (experimental) drivers 457 457 + # 458 458 + # CONFIG_ATA is not set 459 459 + 460 460 + # 461 461 + # Multi-device support (RAID and LVM) 462 462 + # 463 463 + # CONFIG_MD is not set 464 464 + 465 465 + # 466 466 + # Fusion MPT device support 467 467 + # 468 468 + # CONFIG_FUSION is not set 469 469 + 470 470 + # 471 471 + # IEEE 1394 (FireWire) support 472 472 + # 473 473 + 474 474 + # 475 475 + # I2O device support 476 476 + # 477 477 + 478 478 + # 479 479 + # Network device support 480 480 + # 481 481 + # CONFIG_NETDEVICES is not set 482 482 + # CONFIG_NETPOLL is not set 483 483 + # CONFIG_NET_POLL_CONTROLLER is not set 484 484 + 485 485 + # 486 486 + # ISDN subsystem 487 487 + # 488 488 + # CONFIG_ISDN is not set 489 489 + 490 490 + # 491 491 + # Input device support 492 492 + # 493 493 + CONFIG_INPUT=y 494 494 + # CONFIG_INPUT_FF_MEMLESS is not set 495 495 + 496 496 + # 497 497 + # Userland interfaces 498 498 + # 499 499 + CONFIG_INPUT_MOUSEDEV=y 500 500 + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set 501 501 + CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 502 502 + CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 503 503 + # CONFIG_INPUT_JOYDEV is not set 504 504 + # CONFIG_INPUT_TSDEV is not set 505 505 + CONFIG_INPUT_EVDEV=y 506 506 + # CONFIG_INPUT_EVBUG is not set 507 507 + 508 508 + # 509 509 + # Input Device Drivers 510 510 + # 511 511 + # CONFIG_INPUT_KEYBOARD is not set 512 512 + # CONFIG_INPUT_MOUSE is not set 513 513 + # CONFIG_INPUT_JOYSTICK is not set 514 514 + CONFIG_INPUT_TOUCHSCREEN=y 515 515 + # CONFIG_TOUCHSCREEN_ADS7846 is not set 516 516 + # CONFIG_TOUCHSCREEN_GUNZE is not set 517 517 + # CONFIG_TOUCHSCREEN_ELO is not set 518 518 + # CONFIG_TOUCHSCREEN_MTOUCH is not set 519 519 + # CONFIG_TOUCHSCREEN_MK712 is not set 520 520 + # CONFIG_TOUCHSCREEN_PENMOUNT is not set 521 521 + # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set 522 522 + # CONFIG_TOUCHSCREEN_TOUCHWIN is not set 523 523 + # CONFIG_TOUCHSCREEN_UCB1400 is not set 524 524 + # CONFIG_INPUT_MISC is not set 525 525 + 526 526 + # 527 527 + # Hardware I/O ports 528 528 + # 529 529 + # CONFIG_SERIO is not set 530 530 + # CONFIG_GAMEPORT is not set 531 531 + 532 532 + # 533 533 + # Character devices 534 534 + # 535 535 + CONFIG_VT=y 536 536 + CONFIG_VT_CONSOLE=y 537 537 + CONFIG_HW_CONSOLE=y 538 538 + # CONFIG_VT_HW_CONSOLE_BINDING is not set 539 539 + # CONFIG_SERIAL_NONSTANDARD is not set 540 540 + 541 541 + # 542 542 + # Serial drivers 543 543 + # 544 544 + # CONFIG_SERIAL_8250 is not set 545 545 + 546 546 + # 547 547 + # Non-8250 serial port support 548 548 + # 549 549 + CONFIG_SERIAL_ATMEL=y 550 550 + CONFIG_SERIAL_ATMEL_CONSOLE=y 551 551 + # CONFIG_SERIAL_ATMEL_TTYAT is not set 552 552 + CONFIG_SERIAL_CORE=y 553 553 + CONFIG_SERIAL_CORE_CONSOLE=y 554 554 + CONFIG_UNIX98_PTYS=y 555 555 + CONFIG_LEGACY_PTYS=y 556 556 + CONFIG_LEGACY_PTY_COUNT=256 557 557 + 558 558 + # 559 559 + # IPMI 560 560 + # 561 561 + # CONFIG_IPMI_HANDLER is not set 562 562 + 563 563 + # 564 564 + # Watchdog Cards 565 565 + # 566 566 + CONFIG_WATCHDOG=y 567 567 + CONFIG_WATCHDOG_NOWAYOUT=y 568 568 + 569 569 + # 570 570 + # Watchdog Device Drivers 571 571 + # 572 572 + # CONFIG_SOFT_WATCHDOG is not set 573 573 + CONFIG_HW_RANDOM=y 574 574 + # CONFIG_NVRAM is not set 575 575 + # CONFIG_DTLK is not set 576 576 + # CONFIG_R3964 is not set 577 577 + # CONFIG_RAW_DRIVER is not set 578 578 + 579 579 + # 580 580 + # TPM devices 581 581 + # 582 582 + # CONFIG_TCG_TPM is not set 583 583 + 584 584 + # 585 585 + # I2C support 586 586 + # 587 587 + # CONFIG_I2C is not set 588 588 + 589 589 + # 590 590 + # SPI support 591 591 + # 592 592 + CONFIG_SPI=y 593 593 + # CONFIG_SPI_DEBUG is not set 594 594 + CONFIG_SPI_MASTER=y 595 595 + 596 596 + # 597 597 + # SPI Master Controller Drivers 598 598 + # 599 599 + CONFIG_SPI_ATMEL=y 600 600 + # CONFIG_SPI_BITBANG is not set 601 601 + 602 602 + # 603 603 + # SPI Protocol Masters 604 604 + # 605 605 + # CONFIG_SPI_AT25 is not set 606 606 + 607 607 + # 608 608 + # Dallas's 1-wire bus 609 609 + # 610 610 + # CONFIG_W1 is not set 611 611 + 612 612 + # 613 613 + # Hardware Monitoring support 614 614 + # 615 615 + # CONFIG_HWMON is not set 616 616 + # CONFIG_HWMON_VID is not set 617 617 + 618 618 + # 619 619 + # Misc devices 620 620 + # 621 621 + 622 622 + # 623 623 + # Multifunction device drivers 624 624 + # 625 625 + # CONFIG_MFD_SM501 is not set 626 626 + 627 627 + # 628 628 + # LED devices 629 629 + # 630 630 + # CONFIG_NEW_LEDS is not set 631 631 + 632 632 + # 633 633 + # LED drivers 634 634 + # 635 635 + 636 636 + # 637 637 + # LED Triggers 638 638 + # 639 639 + 640 640 + # 641 641 + # Multimedia devices 642 642 + # 643 643 + # CONFIG_VIDEO_DEV is not set 644 644 + 645 645 + # 646 646 + # Digital Video Broadcasting Devices 647 647 + # 648 648 + 649 649 + # 650 650 + # Graphics support 651 651 + # 652 652 + # CONFIG_BACKLIGHT_LCD_SUPPORT is not set 653 653 + CONFIG_FB=y 654 654 + # CONFIG_FIRMWARE_EDID is not set 655 655 + # CONFIG_FB_DDC is not set 656 656 + CONFIG_FB_CFB_FILLRECT=y 657 657 + CONFIG_FB_CFB_COPYAREA=y 658 658 + CONFIG_FB_CFB_IMAGEBLIT=y 659 659 + # CONFIG_FB_SVGALIB is not set 660 660 + # CONFIG_FB_MACMODES is not set 661 661 + # CONFIG_FB_BACKLIGHT is not set 662 662 + # CONFIG_FB_MODE_HELPERS is not set 663 663 + # CONFIG_FB_TILEBLITTING is not set 664 664 + 665 665 + # 666 666 + # Frame buffer hardware drivers 667 667 + # 668 668 + # CONFIG_FB_S1D13XXX is not set 669 669 + CONFIG_FB_ATMEL=y 670 670 + # CONFIG_FB_VIRTUAL is not set 671 671 + 672 672 + # 673 673 + # Console display driver support 674 674 + # 675 675 + # CONFIG_VGA_CONSOLE is not set 676 676 + CONFIG_DUMMY_CONSOLE=y 677 677 + # CONFIG_FRAMEBUFFER_CONSOLE is not set 678 678 + 679 679 + # 680 680 + # Logo configuration 681 681 + # 682 682 + # CONFIG_LOGO is not set 683 683 + 684 684 + # 685 685 + # Sound 686 686 + # 687 687 + CONFIG_SOUND=y 688 688 + 689 689 + # 690 690 + # Advanced Linux Sound Architecture 691 691 + # 692 692 + CONFIG_SND=y 693 693 + CONFIG_SND_TIMER=y 694 694 + CONFIG_SND_PCM=y 695 695 + CONFIG_SND_SEQUENCER=y 696 696 + CONFIG_SND_SEQ_DUMMY=y 697 697 + CONFIG_SND_OSSEMUL=y 698 698 + CONFIG_SND_MIXER_OSS=y 699 699 + CONFIG_SND_PCM_OSS=y 700 700 + CONFIG_SND_PCM_OSS_PLUGINS=y 701 701 + CONFIG_SND_SEQUENCER_OSS=y 702 702 + # CONFIG_SND_DYNAMIC_MINORS is not set 703 703 + CONFIG_SND_SUPPORT_OLD_API=y 704 704 + CONFIG_SND_VERBOSE_PROCFS=y 705 705 + CONFIG_SND_VERBOSE_PRINTK=y 706 706 + CONFIG_SND_DEBUG=y 707 707 + CONFIG_SND_DEBUG_DETECT=y 708 708 + # CONFIG_SND_PCM_XRUN_DEBUG is not set 709 709 + 710 710 + # 711 711 + # Generic devices 712 712 + # 713 713 + # CONFIG_SND_DUMMY is not set 714 714 + # CONFIG_SND_VIRMIDI is not set 715 715 + # CONFIG_SND_MTPAV is not set 716 716 + # CONFIG_SND_SERIAL_U16550 is not set 717 717 + # CONFIG_SND_MPU401 is not set 718 718 + 719 719 + # 720 720 + # ALSA ARM devices 721 721 + # 722 722 + 723 723 + # 724 724 + # SoC audio support 725 725 + # 726 726 + # CONFIG_SND_SOC is not set 727 727 + 728 728 + # 729 729 + # Open Sound System 730 730 + # 731 731 + # CONFIG_SOUND_PRIME is not set 732 732 + 733 733 + # 734 734 + # HID Devices 735 735 + # 736 736 + CONFIG_HID=y 737 737 + # CONFIG_HID_DEBUG is not set 738 738 + 739 739 + # 740 740 + # USB support 741 741 + # 742 742 + CONFIG_USB_ARCH_HAS_HCD=y 743 743 + CONFIG_USB_ARCH_HAS_OHCI=y 744 744 + # CONFIG_USB_ARCH_HAS_EHCI is not set 745 745 + # CONFIG_USB is not set 746 746 + 747 747 + # 748 748 + # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 749 749 + # 750 750 + 751 751 + # 752 752 + # USB Gadget Support 753 753 + # 754 754 + # CONFIG_USB_GADGET is not set 755 755 + 756 756 + # 757 757 + # MMC/SD Card support 758 758 + # 759 759 + CONFIG_MMC=y 760 760 + # CONFIG_MMC_DEBUG is not set 761 761 + CONFIG_MMC_BLOCK=y 762 762 + CONFIG_MMC_AT91=y 763 763 + 764 764 + # 765 765 + # Real Time Clock 766 766 + # 767 767 + CONFIG_RTC_LIB=y 768 768 + # CONFIG_RTC_CLASS is not set 769 769 + 770 770 + # 771 771 + # File systems 772 772 + # 773 773 + CONFIG_EXT2_FS=y 774 774 + # CONFIG_EXT2_FS_XATTR is not set 775 775 + # CONFIG_EXT2_FS_XIP is not set 776 776 + # CONFIG_EXT3_FS is not set 777 777 + # CONFIG_EXT4DEV_FS is not set 778 778 + # CONFIG_REISERFS_FS is not set 779 779 + # CONFIG_JFS_FS is not set 780 780 + # CONFIG_FS_POSIX_ACL is not set 781 781 + # CONFIG_XFS_FS is not set 782 782 + # CONFIG_GFS2_FS is not set 783 783 + # CONFIG_OCFS2_FS is not set 784 784 + # CONFIG_MINIX_FS is not set 785 785 + # CONFIG_ROMFS_FS is not set 786 786 + CONFIG_INOTIFY=y 787 787 + CONFIG_INOTIFY_USER=y 788 788 + # CONFIG_QUOTA is not set 789 789 + CONFIG_DNOTIFY=y 790 790 + # CONFIG_AUTOFS_FS is not set 791 791 + # CONFIG_AUTOFS4_FS is not set 792 792 + # CONFIG_FUSE_FS is not set 793 793 + 794 794 + # 795 795 + # CD-ROM/DVD Filesystems 796 796 + # 797 797 + # CONFIG_ISO9660_FS is not set 798 798 + # CONFIG_UDF_FS is not set 799 799 + 800 800 + # 801 801 + # DOS/FAT/NT Filesystems 802 802 + # 803 803 + CONFIG_FAT_FS=y 804 804 + CONFIG_MSDOS_FS=y 805 805 + CONFIG_VFAT_FS=y 806 806 + CONFIG_FAT_DEFAULT_CODEPAGE=437 807 807 + CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" 808 808 + # CONFIG_NTFS_FS is not set 809 809 + 810 810 + # 811 811 + # Pseudo filesystems 812 812 + # 813 813 + CONFIG_PROC_FS=y 814 814 + CONFIG_PROC_SYSCTL=y 815 815 + CONFIG_SYSFS=y 816 816 + CONFIG_TMPFS=y 817 817 + # CONFIG_TMPFS_POSIX_ACL is not set 818 818 + # CONFIG_HUGETLB_PAGE is not set 819 819 + CONFIG_RAMFS=y 820 820 + # CONFIG_CONFIGFS_FS is not set 821 821 + 822 822 + # 823 823 + # Miscellaneous filesystems 824 824 + # 825 825 + # CONFIG_ADFS_FS is not set 826 826 + # CONFIG_AFFS_FS is not set 827 827 + # CONFIG_HFS_FS is not set 828 828 + # CONFIG_HFSPLUS_FS is not set 829 829 + # CONFIG_BEFS_FS is not set 830 830 + # CONFIG_BFS_FS is not set 831 831 + # CONFIG_EFS_FS is not set 832 832 + # CONFIG_JFFS2_FS is not set 833 833 + CONFIG_CRAMFS=y 834 834 + # CONFIG_VXFS_FS is not set 835 835 + # CONFIG_HPFS_FS is not set 836 836 + # CONFIG_QNX4FS_FS is not set 837 837 + # CONFIG_SYSV_FS is not set 838 838 + # CONFIG_UFS_FS is not set 839 839 + 840 840 + # 841 841 + # Network File Systems 842 842 + # 843 843 + 844 844 + # 845 845 + # Partition Types 846 846 + # 847 847 + # CONFIG_PARTITION_ADVANCED is not set 848 848 + CONFIG_MSDOS_PARTITION=y 849 849 + 850 850 + # 851 851 + # Native Language Support 852 852 + # 853 853 + CONFIG_NLS=y 854 854 + CONFIG_NLS_DEFAULT="iso8859-1" 855 855 + CONFIG_NLS_CODEPAGE_437=y 856 856 + # CONFIG_NLS_CODEPAGE_737 is not set 857 857 + # CONFIG_NLS_CODEPAGE_775 is not set 858 858 + CONFIG_NLS_CODEPAGE_850=y 859 859 + # CONFIG_NLS_CODEPAGE_852 is not set 860 860 + # CONFIG_NLS_CODEPAGE_855 is not set 861 861 + # CONFIG_NLS_CODEPAGE_857 is not set 862 862 + # CONFIG_NLS_CODEPAGE_860 is not set 863 863 + # CONFIG_NLS_CODEPAGE_861 is not set 864 864 + # CONFIG_NLS_CODEPAGE_862 is not set 865 865 + # CONFIG_NLS_CODEPAGE_863 is not set 866 866 + # CONFIG_NLS_CODEPAGE_864 is not set 867 867 + # CONFIG_NLS_CODEPAGE_865 is not set 868 868 + # CONFIG_NLS_CODEPAGE_866 is not set 869 869 + # CONFIG_NLS_CODEPAGE_869 is not set 870 870 + # CONFIG_NLS_CODEPAGE_936 is not set 871 871 + # CONFIG_NLS_CODEPAGE_950 is not set 872 872 + # CONFIG_NLS_CODEPAGE_932 is not set 873 873 + # CONFIG_NLS_CODEPAGE_949 is not set 874 874 + # CONFIG_NLS_CODEPAGE_874 is not set 875 875 + # CONFIG_NLS_ISO8859_8 is not set 876 876 + # CONFIG_NLS_CODEPAGE_1250 is not set 877 877 + # CONFIG_NLS_CODEPAGE_1251 is not set 878 878 + # CONFIG_NLS_ASCII is not set 879 879 + CONFIG_NLS_ISO8859_1=y 880 880 + # CONFIG_NLS_ISO8859_2 is not set 881 881 + # CONFIG_NLS_ISO8859_3 is not set 882 882 + # CONFIG_NLS_ISO8859_4 is not set 883 883 + # CONFIG_NLS_ISO8859_5 is not set 884 884 + # CONFIG_NLS_ISO8859_6 is not set 885 885 + # CONFIG_NLS_ISO8859_7 is not set 886 886 + # CONFIG_NLS_ISO8859_9 is not set 887 887 + # CONFIG_NLS_ISO8859_13 is not set 888 888 + # CONFIG_NLS_ISO8859_14 is not set 889 889 + CONFIG_NLS_ISO8859_15=y 890 890 + # CONFIG_NLS_KOI8_R is not set 891 891 + # CONFIG_NLS_KOI8_U is not set 892 892 + CONFIG_NLS_UTF8=y 893 893 + 894 894 + # 895 895 + # Profiling support 896 896 + # 897 897 + # CONFIG_PROFILING is not set 898 898 + 899 899 + # 900 900 + # Kernel hacking 901 901 + # 902 902 + # CONFIG_PRINTK_TIME is not set 903 903 + CONFIG_ENABLE_MUST_CHECK=y 904 904 + # CONFIG_MAGIC_SYSRQ is not set 905 905 + # CONFIG_UNUSED_SYMBOLS is not set 906 906 + # CONFIG_DEBUG_FS is not set 907 907 + # CONFIG_HEADERS_CHECK is not set 908 908 + CONFIG_DEBUG_KERNEL=y 909 909 + # CONFIG_DEBUG_SHIRQ is not set 910 910 + CONFIG_LOG_BUF_SHIFT=14 911 911 + CONFIG_DETECT_SOFTLOCKUP=y 912 912 + # CONFIG_SCHEDSTATS is not set 913 913 + # CONFIG_TIMER_STATS is not set 914 914 + # CONFIG_DEBUG_SLAB is not set 915 915 + # CONFIG_DEBUG_RT_MUTEXES is not set 916 916 + # CONFIG_RT_MUTEX_TESTER is not set 917 917 + # CONFIG_DEBUG_SPINLOCK is not set 918 918 + # CONFIG_DEBUG_MUTEXES is not set 919 919 + # CONFIG_DEBUG_SPINLOCK_SLEEP is not set 920 920 + # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 921 921 + # CONFIG_DEBUG_KOBJECT is not set 922 922 + CONFIG_DEBUG_BUGVERBOSE=y 923 923 + CONFIG_DEBUG_INFO=y 924 924 + # CONFIG_DEBUG_VM is not set 925 925 + # CONFIG_DEBUG_LIST is not set 926 926 + CONFIG_FRAME_POINTER=y 927 927 + CONFIG_FORCED_INLINING=y 928 928 + # CONFIG_RCU_TORTURE_TEST is not set 929 929 + # CONFIG_FAULT_INJECTION is not set 930 930 + CONFIG_DEBUG_USER=y 931 931 + # CONFIG_DEBUG_ERRORS is not set 932 932 + CONFIG_DEBUG_LL=y 933 933 + # CONFIG_DEBUG_ICEDCC is not set 934 934 + 935 935 + # 936 936 + # Security options 937 937 + # 938 938 + # CONFIG_KEYS is not set 939 939 + # CONFIG_SECURITY is not set 940 940 + 941 941 + # 942 942 + # Cryptographic options 943 943 + # 944 944 + # CONFIG_CRYPTO is not set 945 945 + 946 946 + # 947 947 + # Library routines 948 948 + # 949 949 + CONFIG_BITREVERSE=y 950 950 + # CONFIG_CRC_CCITT is not set 951 951 + # CONFIG_CRC16 is not set 952 952 + CONFIG_CRC32=y 953 953 + # CONFIG_LIBCRC32C is not set 954 954 + CONFIG_ZLIB_INFLATE=y 955 955 + CONFIG_PLIST=y 956 956 + CONFIG_HAS_IOMEM=y 957 957 + CONFIG_HAS_IOPORT=y

+880

arch/arm/configs/ks8695_defconfig

reviewed

··· 1 1 + # 2 2 + # Automatically generated make config: don't edit 3 3 + # Linux kernel version: 2.6.17-rc4 4 4 + # Thu May 25 15:42:51 2006 5 5 + # 6 6 + CONFIG_ARM=y 7 7 + CONFIG_MMU=y 8 8 + CONFIG_RWSEM_GENERIC_SPINLOCK=y 9 9 + CONFIG_GENERIC_HWEIGHT=y 10 10 + CONFIG_GENERIC_CALIBRATE_DELAY=y 11 11 + CONFIG_VECTORS_BASE=0xffff0000 12 12 + 13 13 + # 14 14 + # Code maturity level options 15 15 + # 16 16 + CONFIG_EXPERIMENTAL=y 17 17 + CONFIG_BROKEN_ON_SMP=y 18 18 + CONFIG_INIT_ENV_ARG_LIMIT=32 19 19 + 20 20 + # 21 21 + # General setup 22 22 + # 23 23 + CONFIG_LOCALVERSION="" 24 24 + CONFIG_LOCALVERSION_AUTO=y 25 25 + # CONFIG_SWAP is not set 26 26 + CONFIG_SYSVIPC=y 27 27 + # CONFIG_POSIX_MQUEUE is not set 28 28 + # CONFIG_BSD_PROCESS_ACCT is not set 29 29 + CONFIG_SYSCTL=y 30 30 + # CONFIG_AUDIT is not set 31 31 + # CONFIG_IKCONFIG is not set 32 32 + # CONFIG_RELAY is not set 33 33 + CONFIG_INITRAMFS_SOURCE="" 34 34 + CONFIG_UID16=y 35 35 + CONFIG_CC_OPTIMIZE_FOR_SIZE=y 36 36 + # CONFIG_EMBEDDED is not set 37 37 + CONFIG_KALLSYMS=y 38 38 + # CONFIG_KALLSYMS_ALL is not set 39 39 + # CONFIG_KALLSYMS_EXTRA_PASS is not set 40 40 + CONFIG_HOTPLUG=y 41 41 + CONFIG_PRINTK=y 42 42 + CONFIG_BUG=y 43 43 + CONFIG_ELF_CORE=y 44 44 + CONFIG_BASE_FULL=y 45 45 + CONFIG_FUTEX=y 46 46 + CONFIG_EPOLL=y 47 47 + CONFIG_SHMEM=y 48 48 + CONFIG_SLAB=y 49 49 + # CONFIG_TINY_SHMEM is not set 50 50 + CONFIG_BASE_SMALL=0 51 51 + # CONFIG_SLOB is not set 52 52 + CONFIG_OBSOLETE_INTERMODULE=y 53 53 + 54 54 + # 55 55 + # Loadable module support 56 56 + # 57 57 + CONFIG_MODULES=y 58 58 + CONFIG_MODULE_UNLOAD=y 59 59 + # CONFIG_MODULE_FORCE_UNLOAD is not set 60 60 + # CONFIG_MODVERSIONS is not set 61 61 + # CONFIG_MODULE_SRCVERSION_ALL is not set 62 62 + CONFIG_KMOD=y 63 63 + 64 64 + # 65 65 + # Block layer 66 66 + # 67 67 + # CONFIG_BLK_DEV_IO_TRACE is not set 68 68 + 69 69 + # 70 70 + # IO Schedulers 71 71 + # 72 72 + CONFIG_IOSCHED_NOOP=y 73 73 + CONFIG_IOSCHED_AS=y 74 74 + # CONFIG_IOSCHED_DEADLINE is not set 75 75 + # CONFIG_IOSCHED_CFQ is not set 76 76 + CONFIG_DEFAULT_AS=y 77 77 + # CONFIG_DEFAULT_DEADLINE is not set 78 78 + # CONFIG_DEFAULT_CFQ is not set 79 79 + # CONFIG_DEFAULT_NOOP is not set 80 80 + CONFIG_DEFAULT_IOSCHED="anticipatory" 81 81 + 82 82 + # 83 83 + # System Type 84 84 + # 85 85 + # CONFIG_ARCH_CLPS7500 is not set 86 86 + # CONFIG_ARCH_CLPS711X is not set 87 87 + # CONFIG_ARCH_CO285 is not set 88 88 + # CONFIG_ARCH_EBSA110 is not set 89 89 + # CONFIG_ARCH_EP93XX is not set 90 90 + # CONFIG_ARCH_FOOTBRIDGE is not set 91 91 + # CONFIG_ARCH_INTEGRATOR is not set 92 92 + # CONFIG_ARCH_IOP3XX is not set 93 93 + # CONFIG_ARCH_IXP4XX is not set 94 94 + # CONFIG_ARCH_IXP2000 is not set 95 95 + # CONFIG_ARCH_IXP23XX is not set 96 96 + # CONFIG_ARCH_L7200 is not set 97 97 + # CONFIG_ARCH_PXA is not set 98 98 + # CONFIG_ARCH_RPC is not set 99 99 + # CONFIG_ARCH_SA1100 is not set 100 100 + # CONFIG_ARCH_S3C2410 is not set 101 101 + # CONFIG_ARCH_SHARK is not set 102 102 + # CONFIG_ARCH_LH7A40X is not set 103 103 + # CONFIG_ARCH_OMAP is not set 104 104 + # CONFIG_ARCH_VERSATILE is not set 105 105 + # CONFIG_ARCH_REALVIEW is not set 106 106 + # CONFIG_ARCH_IMX is not set 107 107 + # CONFIG_ARCH_H720X is not set 108 108 + # CONFIG_ARCH_AAEC2000 is not set 109 109 + # CONFIG_ARCH_AT91 is not set 110 110 + CONFIG_ARCH_KS8695=y 111 111 + 112 112 + # 113 113 + # Kendin/Micrel KS8695 Implementations 114 114 + # 115 115 + CONFIG_MACH_KS8695=y 116 116 + # CONFIG_MACH_DSM320 is not set 117 117 + # CONFIG_MACH_CM4002 is not set 118 118 + # CONFIG_MACH_CM4008 is not set 119 119 + # CONFIG_MACH_CM40xx is not set 120 120 + # CONFIG_MACH_LITE300 is not set 121 121 + # CONFIG_MACH_SE4200 is not set 122 122 + # CONFIG_MACH_MANGA_KS8695 is not set 123 123 + 124 124 + # 125 125 + # Processor Type 126 126 + # 127 127 + CONFIG_CPU_32=y 128 128 + CONFIG_CPU_ARM922T=y 129 129 + CONFIG_CPU_32v4=y 130 130 + CONFIG_CPU_ABRT_EV4T=y 131 131 + CONFIG_CPU_CACHE_V4WT=y 132 132 + CONFIG_CPU_CACHE_VIVT=y 133 133 + CONFIG_CPU_COPY_V4WB=y 134 134 + CONFIG_CPU_TLB_V4WBI=y 135 135 + 136 136 + # 137 137 + # Processor Features 138 138 + # 139 139 + # CONFIG_ARM_THUMB is not set 140 140 + # CONFIG_CPU_ICACHE_DISABLE is not set 141 141 + # CONFIG_CPU_DCACHE_DISABLE is not set 142 142 + # CONFIG_CPU_DCACHE_WRITETHROUGH is not set 143 143 + 144 144 + # 145 145 + # Bus support 146 146 + # 147 147 + CONFIG_PCI=y 148 148 + CONFIG_PCI_DEBUG=y 149 149 + 150 150 + # 151 151 + # PCCARD (PCMCIA/CardBus) support 152 152 + # 153 153 + CONFIG_PCCARD=y 154 154 + # CONFIG_PCMCIA_DEBUG is not set 155 155 + CONFIG_PCMCIA=y 156 156 + CONFIG_PCMCIA_LOAD_CIS=y 157 157 + CONFIG_PCMCIA_IOCTL=y 158 158 + CONFIG_CARDBUS=y 159 159 + 160 160 + # 161 161 + # PC-card bridges 162 162 + # 163 163 + CONFIG_YENTA=y 164 164 + CONFIG_YENTA_O2=y 165 165 + CONFIG_YENTA_RICOH=y 166 166 + CONFIG_YENTA_TI=y 167 167 + CONFIG_YENTA_ENE_TUNE=y 168 168 + CONFIG_YENTA_TOSHIBA=y 169 169 + # CONFIG_PD6729 is not set 170 170 + # CONFIG_I82092 is not set 171 171 + CONFIG_PCCARD_NONSTATIC=y 172 172 + 173 173 + # 174 174 + # Kernel Features 175 175 + # 176 176 + # CONFIG_PREEMPT is not set 177 177 + # CONFIG_NO_IDLE_HZ is not set 178 178 + CONFIG_HZ=100 179 179 + # CONFIG_AEABI is not set 180 180 + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 181 181 + CONFIG_SELECT_MEMORY_MODEL=y 182 182 + CONFIG_FLATMEM_MANUAL=y 183 183 + # CONFIG_DISCONTIGMEM_MANUAL is not set 184 184 + # CONFIG_SPARSEMEM_MANUAL is not set 185 185 + CONFIG_FLATMEM=y 186 186 + CONFIG_FLAT_NODE_MEM_MAP=y 187 187 + # CONFIG_SPARSEMEM_STATIC is not set 188 188 + CONFIG_SPLIT_PTLOCK_CPUS=4096 189 189 + CONFIG_ALIGNMENT_TRAP=y 190 190 + 191 191 + # 192 192 + # Boot options 193 193 + # 194 194 + CONFIG_ZBOOT_ROM_TEXT=0x0 195 195 + CONFIG_ZBOOT_ROM_BSS=0x0 196 196 + CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" 197 197 + # CONFIG_XIP_KERNEL is not set 198 198 + 199 199 + # 200 200 + # Floating point emulation 201 201 + # 202 202 + 203 203 + # 204 204 + # At least one emulation must be selected 205 205 + # 206 206 + CONFIG_FPE_NWFPE=y 207 207 + # CONFIG_FPE_NWFPE_XP is not set 208 208 + # CONFIG_FPE_FASTFPE is not set 209 209 + 210 210 + # 211 211 + # Userspace binary formats 212 212 + # 213 213 + CONFIG_BINFMT_ELF=y 214 214 + # CONFIG_BINFMT_AOUT is not set 215 215 + # CONFIG_BINFMT_MISC is not set 216 216 + # CONFIG_ARTHUR is not set 217 217 + 218 218 + # 219 219 + # Power management options 220 220 + # 221 221 + # CONFIG_PM is not set 222 222 + # CONFIG_APM is not set 223 223 + 224 224 + # 225 225 + # Networking 226 226 + # 227 227 + CONFIG_NET=y 228 228 + 229 229 + # 230 230 + # Networking options 231 231 + # 232 232 + # CONFIG_NETDEBUG is not set 233 233 + CONFIG_PACKET=y 234 234 + # CONFIG_PACKET_MMAP is not set 235 235 + CONFIG_UNIX=y 236 236 + # CONFIG_NET_KEY is not set 237 237 + CONFIG_INET=y 238 238 + # CONFIG_IP_MULTICAST is not set 239 239 + # CONFIG_IP_ADVANCED_ROUTER is not set 240 240 + CONFIG_IP_FIB_HASH=y 241 241 + CONFIG_IP_PNP=y 242 242 + # CONFIG_IP_PNP_DHCP is not set 243 243 + CONFIG_IP_PNP_BOOTP=y 244 244 + # CONFIG_IP_PNP_RARP is not set 245 245 + # CONFIG_NET_IPIP is not set 246 246 + # CONFIG_NET_IPGRE is not set 247 247 + # CONFIG_ARPD is not set 248 248 + # CONFIG_SYN_COOKIES is not set 249 249 + # CONFIG_INET_AH is not set 250 250 + # CONFIG_INET_ESP is not set 251 251 + # CONFIG_INET_IPCOMP is not set 252 252 + # CONFIG_INET_XFRM_TUNNEL is not set 253 253 + # CONFIG_INET_TUNNEL is not set 254 254 + CONFIG_INET_DIAG=y 255 255 + CONFIG_INET_TCP_DIAG=y 256 256 + # CONFIG_TCP_CONG_ADVANCED is not set 257 257 + CONFIG_TCP_CONG_BIC=y 258 258 + # CONFIG_IPV6 is not set 259 259 + # CONFIG_INET6_XFRM_TUNNEL is not set 260 260 + # CONFIG_INET6_TUNNEL is not set 261 261 + # CONFIG_NETFILTER is not set 262 262 + 263 263 + # 264 264 + # DCCP Configuration (EXPERIMENTAL) 265 265 + # 266 266 + # CONFIG_IP_DCCP is not set 267 267 + 268 268 + # 269 269 + # SCTP Configuration (EXPERIMENTAL) 270 270 + # 271 271 + # CONFIG_IP_SCTP is not set 272 272 + 273 273 + # 274 274 + # TIPC Configuration (EXPERIMENTAL) 275 275 + # 276 276 + # CONFIG_TIPC is not set 277 277 + # CONFIG_ATM is not set 278 278 + # CONFIG_BRIDGE is not set 279 279 + # CONFIG_VLAN_8021Q is not set 280 280 + # CONFIG_DECNET is not set 281 281 + # CONFIG_LLC2 is not set 282 282 + # CONFIG_IPX is not set 283 283 + # CONFIG_ATALK is not set 284 284 + # CONFIG_X25 is not set 285 285 + # CONFIG_LAPB is not set 286 286 + # CONFIG_NET_DIVERT is not set 287 287 + # CONFIG_ECONET is not set 288 288 + # CONFIG_WAN_ROUTER is not set 289 289 + 290 290 + # 291 291 + # QoS and/or fair queueing 292 292 + # 293 293 + # CONFIG_NET_SCHED is not set 294 294 + 295 295 + # 296 296 + # Network testing 297 297 + # 298 298 + # CONFIG_NET_PKTGEN is not set 299 299 + # CONFIG_HAMRADIO is not set 300 300 + # CONFIG_IRDA is not set 301 301 + # CONFIG_BT is not set 302 302 + # CONFIG_IEEE80211 is not set 303 303 + 304 304 + # 305 305 + # Device Drivers 306 306 + # 307 307 + 308 308 + # 309 309 + # Generic Driver Options 310 310 + # 311 311 + CONFIG_STANDALONE=y 312 312 + CONFIG_PREVENT_FIRMWARE_BUILD=y 313 313 + CONFIG_FW_LOADER=y 314 314 + # CONFIG_DEBUG_DRIVER is not set 315 315 + 316 316 + # 317 317 + # Connector - unified userspace <-> kernelspace linker 318 318 + # 319 319 + # CONFIG_CONNECTOR is not set 320 320 + 321 321 + # 322 322 + # Memory Technology Devices (MTD) 323 323 + # 324 324 + CONFIG_MTD=y 325 325 + # CONFIG_MTD_DEBUG is not set 326 326 + # CONFIG_MTD_CONCAT is not set 327 327 + CONFIG_MTD_PARTITIONS=y 328 328 + # CONFIG_MTD_REDBOOT_PARTS is not set 329 329 + CONFIG_MTD_CMDLINE_PARTS=y 330 330 + # CONFIG_MTD_AFS_PARTS is not set 331 331 + 332 332 + # 333 333 + # User Modules And Translation Layers 334 334 + # 335 335 + CONFIG_MTD_CHAR=y 336 336 + CONFIG_MTD_BLOCK=y 337 337 + # CONFIG_FTL is not set 338 338 + # CONFIG_NFTL is not set 339 339 + # CONFIG_INFTL is not set 340 340 + # CONFIG_RFD_FTL is not set 341 341 + 342 342 + # 343 343 + # RAM/ROM/Flash chip drivers 344 344 + # 345 345 + CONFIG_MTD_CFI=y 346 346 + CONFIG_MTD_JEDECPROBE=y 347 347 + CONFIG_MTD_GEN_PROBE=y 348 348 + # CONFIG_MTD_CFI_ADV_OPTIONS is not set 349 349 + CONFIG_MTD_MAP_BANK_WIDTH_1=y 350 350 + CONFIG_MTD_MAP_BANK_WIDTH_2=y 351 351 + CONFIG_MTD_MAP_BANK_WIDTH_4=y 352 352 + # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set 353 353 + # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set 354 354 + # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set 355 355 + CONFIG_MTD_CFI_I1=y 356 356 + CONFIG_MTD_CFI_I2=y 357 357 + # CONFIG_MTD_CFI_I4 is not set 358 358 + # CONFIG_MTD_CFI_I8 is not set 359 359 + # CONFIG_MTD_CFI_INTELEXT is not set 360 360 + CONFIG_MTD_CFI_AMDSTD=y 361 361 + # CONFIG_MTD_CFI_STAA is not set 362 362 + CONFIG_MTD_CFI_UTIL=y 363 363 + # CONFIG_MTD_RAM is not set 364 364 + # CONFIG_MTD_ROM is not set 365 365 + # CONFIG_MTD_ABSENT is not set 366 366 + # CONFIG_MTD_OBSOLETE_CHIPS is not set 367 367 + 368 368 + # 369 369 + # Mapping drivers for chip access 370 370 + # 371 371 + # CONFIG_MTD_COMPLEX_MAPPINGS is not set 372 372 + # CONFIG_MTD_PHYSMAP is not set 373 373 + # CONFIG_MTD_ARM_INTEGRATOR is not set 374 374 + # CONFIG_MTD_IMPA7 is not set 375 375 + # CONFIG_MTD_PLATRAM is not set 376 376 + 377 377 + # 378 378 + # Self-contained MTD device drivers 379 379 + # 380 380 + # CONFIG_MTD_PMC551 is not set 381 381 + # CONFIG_MTD_SLRAM is not set 382 382 + # CONFIG_MTD_PHRAM is not set 383 383 + # CONFIG_MTD_MTDRAM is not set 384 384 + # CONFIG_MTD_BLOCK2MTD is not set 385 385 + 386 386 + # 387 387 + # Disk-On-Chip Device Drivers 388 388 + # 389 389 + # CONFIG_MTD_DOC2000 is not set 390 390 + # CONFIG_MTD_DOC2001 is not set 391 391 + # CONFIG_MTD_DOC2001PLUS is not set 392 392 + 393 393 + # 394 394 + # NAND Flash Device Drivers 395 395 + # 396 396 + # CONFIG_MTD_NAND is not set 397 397 + 398 398 + # 399 399 + # OneNAND Flash Device Drivers 400 400 + # 401 401 + # CONFIG_MTD_ONENAND is not set 402 402 + 403 403 + # 404 404 + # Parallel port support 405 405 + # 406 406 + # CONFIG_PARPORT is not set 407 407 + 408 408 + # 409 409 + # Plug and Play support 410 410 + # 411 411 + 412 412 + # 413 413 + # Block devices 414 414 + # 415 415 + # CONFIG_BLK_CPQ_DA is not set 416 416 + # CONFIG_BLK_CPQ_CISS_DA is not set 417 417 + # CONFIG_BLK_DEV_DAC960 is not set 418 418 + # CONFIG_BLK_DEV_UMEM is not set 419 419 + # CONFIG_BLK_DEV_COW_COMMON is not set 420 420 + # CONFIG_BLK_DEV_LOOP is not set 421 421 + # CONFIG_BLK_DEV_NBD is not set 422 422 + # CONFIG_BLK_DEV_SX8 is not set 423 423 + CONFIG_BLK_DEV_RAM=y 424 424 + CONFIG_BLK_DEV_RAM_COUNT=16 425 425 + CONFIG_BLK_DEV_RAM_SIZE=8192 426 426 + CONFIG_BLK_DEV_INITRD=y 427 427 + # CONFIG_CDROM_PKTCDVD is not set 428 428 + # CONFIG_ATA_OVER_ETH is not set 429 429 + 430 430 + # 431 431 + # ATA/ATAPI/MFM/RLL support 432 432 + # 433 433 + # CONFIG_IDE is not set 434 434 + 435 435 + # 436 436 + # SCSI device support 437 437 + # 438 438 + # CONFIG_RAID_ATTRS is not set 439 439 + # CONFIG_SCSI is not set 440 440 + 441 441 + # 442 442 + # Multi-device support (RAID and LVM) 443 443 + # 444 444 + # CONFIG_MD is not set 445 445 + 446 446 + # 447 447 + # Fusion MPT device support 448 448 + # 449 449 + # CONFIG_FUSION is not set 450 450 + 451 451 + # 452 452 + # IEEE 1394 (FireWire) support 453 453 + # 454 454 + # CONFIG_IEEE1394 is not set 455 455 + 456 456 + # 457 457 + # I2O device support 458 458 + # 459 459 + # CONFIG_I2O is not set 460 460 + 461 461 + # 462 462 + # Network device support 463 463 + # 464 464 + CONFIG_NETDEVICES=y 465 465 + # CONFIG_DUMMY is not set 466 466 + # CONFIG_BONDING is not set 467 467 + # CONFIG_EQUALIZER is not set 468 468 + # CONFIG_TUN is not set 469 469 + 470 470 + # 471 471 + # ARCnet devices 472 472 + # 473 473 + # CONFIG_ARCNET is not set 474 474 + 475 475 + # 476 476 + # PHY device support 477 477 + # 478 478 + # CONFIG_PHYLIB is not set 479 479 + 480 480 + # 481 481 + # Ethernet (10 or 100Mbit) 482 482 + # 483 483 + CONFIG_NET_ETHERNET=y 484 484 + # CONFIG_MII is not set 485 485 + CONFIG_ARM_KS8695_ETHER=y 486 486 + # CONFIG_HAPPYMEAL is not set 487 487 + # CONFIG_SUNGEM is not set 488 488 + # CONFIG_CASSINI is not set 489 489 + # CONFIG_NET_VENDOR_3COM is not set 490 490 + # CONFIG_SMC91X is not set 491 491 + # CONFIG_DM9000 is not set 492 492 + 493 493 + # 494 494 + # Tulip family network device support 495 495 + # 496 496 + # CONFIG_NET_TULIP is not set 497 497 + # CONFIG_HP100 is not set 498 498 + # CONFIG_NET_PCI is not set 499 499 + 500 500 + # 501 501 + # Ethernet (1000 Mbit) 502 502 + # 503 503 + # CONFIG_ACENIC is not set 504 504 + # CONFIG_DL2K is not set 505 505 + # CONFIG_E1000 is not set 506 506 + # CONFIG_NS83820 is not set 507 507 + # CONFIG_HAMACHI is not set 508 508 + # CONFIG_YELLOWFIN is not set 509 509 + # CONFIG_R8169 is not set 510 510 + # CONFIG_SIS190 is not set 511 511 + # CONFIG_SKGE is not set 512 512 + # CONFIG_SKY2 is not set 513 513 + # CONFIG_SK98LIN is not set 514 514 + # CONFIG_TIGON3 is not set 515 515 + # CONFIG_BNX2 is not set 516 516 + 517 517 + # 518 518 + # Ethernet (10000 Mbit) 519 519 + # 520 520 + # CONFIG_CHELSIO_T1 is not set 521 521 + # CONFIG_IXGB is not set 522 522 + # CONFIG_S2IO is not set 523 523 + 524 524 + # 525 525 + # Token Ring devices 526 526 + # 527 527 + # CONFIG_TR is not set 528 528 + 529 529 + # 530 530 + # Wireless LAN (non-hamradio) 531 531 + # 532 532 + # CONFIG_NET_RADIO is not set 533 533 + 534 534 + # 535 535 + # PCMCIA network device support 536 536 + # 537 537 + # CONFIG_NET_PCMCIA is not set 538 538 + 539 539 + # 540 540 + # Wan interfaces 541 541 + # 542 542 + # CONFIG_WAN is not set 543 543 + # CONFIG_FDDI is not set 544 544 + # CONFIG_HIPPI is not set 545 545 + # CONFIG_PPP is not set 546 546 + # CONFIG_SLIP is not set 547 547 + # CONFIG_SHAPER is not set 548 548 + # CONFIG_NETCONSOLE is not set 549 549 + # CONFIG_NETPOLL is not set 550 550 + # CONFIG_NET_POLL_CONTROLLER is not set 551 551 + 552 552 + # 553 553 + # ISDN subsystem 554 554 + # 555 555 + # CONFIG_ISDN is not set 556 556 + 557 557 + # 558 558 + # Input device support 559 559 + # 560 560 + CONFIG_INPUT=y 561 561 + 562 562 + # 563 563 + # Userland interfaces 564 564 + # 565 565 + CONFIG_INPUT_MOUSEDEV=y 566 566 + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set 567 567 + CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 568 568 + CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 569 569 + # CONFIG_INPUT_JOYDEV is not set 570 570 + # CONFIG_INPUT_TSDEV is not set 571 571 + # CONFIG_INPUT_EVDEV is not set 572 572 + # CONFIG_INPUT_EVBUG is not set 573 573 + 574 574 + # 575 575 + # Input Device Drivers 576 576 + # 577 577 + # CONFIG_INPUT_KEYBOARD is not set 578 578 + # CONFIG_INPUT_MOUSE is not set 579 579 + # CONFIG_INPUT_JOYSTICK is not set 580 580 + # CONFIG_INPUT_TOUCHSCREEN is not set 581 581 + # CONFIG_INPUT_MISC is not set 582 582 + 583 583 + # 584 584 + # Hardware I/O ports 585 585 + # 586 586 + # CONFIG_SERIO is not set 587 587 + # CONFIG_GAMEPORT is not set 588 588 + 589 589 + # 590 590 + # Character devices 591 591 + # 592 592 + CONFIG_VT=y 593 593 + CONFIG_VT_CONSOLE=y 594 594 + CONFIG_HW_CONSOLE=y 595 595 + # CONFIG_SERIAL_NONSTANDARD is not set 596 596 + 597 597 + # 598 598 + # Serial drivers 599 599 + # 600 600 + # CONFIG_SERIAL_8250 is not set 601 601 + 602 602 + # 603 603 + # Non-8250 serial port support 604 604 + # 605 605 + CONFIG_SERIAL_KS8695=y 606 606 + CONFIG_SERIAL_KS8695_CONSOLE=y 607 607 + CONFIG_SERIAL_CORE=y 608 608 + CONFIG_SERIAL_CORE_CONSOLE=y 609 609 + # CONFIG_SERIAL_JSM is not set 610 610 + CONFIG_UNIX98_PTYS=y 611 611 + CONFIG_LEGACY_PTYS=y 612 612 + CONFIG_LEGACY_PTY_COUNT=256 613 613 + 614 614 + # 615 615 + # IPMI 616 616 + # 617 617 + # CONFIG_IPMI_HANDLER is not set 618 618 + 619 619 + # 620 620 + # Watchdog Cards 621 621 + # 622 622 + # CONFIG_WATCHDOG is not set 623 623 + # CONFIG_NVRAM is not set 624 624 + # CONFIG_DTLK is not set 625 625 + # CONFIG_R3964 is not set 626 626 + # CONFIG_APPLICOM is not set 627 627 + 628 628 + # 629 629 + # Ftape, the floppy tape device driver 630 630 + # 631 631 + # CONFIG_DRM is not set 632 632 + 633 633 + # 634 634 + # PCMCIA character devices 635 635 + # 636 636 + # CONFIG_SYNCLINK_CS is not set 637 637 + # CONFIG_CARDMAN_4000 is not set 638 638 + # CONFIG_CARDMAN_4040 is not set 639 639 + # CONFIG_RAW_DRIVER is not set 640 640 + 641 641 + # 642 642 + # TPM devices 643 643 + # 644 644 + # CONFIG_TCG_TPM is not set 645 645 + # CONFIG_TELCLOCK is not set 646 646 + 647 647 + # 648 648 + # I2C support 649 649 + # 650 650 + # CONFIG_I2C is not set 651 651 + 652 652 + # 653 653 + # SPI support 654 654 + # 655 655 + # CONFIG_SPI is not set 656 656 + # CONFIG_SPI_MASTER is not set 657 657 + 658 658 + # 659 659 + # Dallas's 1-wire bus 660 660 + # 661 661 + # CONFIG_W1 is not set 662 662 + 663 663 + # 664 664 + # Hardware Monitoring support 665 665 + # 666 666 + # CONFIG_HWMON is not set 667 667 + # CONFIG_HWMON_VID is not set 668 668 + 669 669 + # 670 670 + # Misc devices 671 671 + # 672 672 + 673 673 + # 674 674 + # LED devices 675 675 + # 676 676 + # CONFIG_NEW_LEDS is not set 677 677 + 678 678 + # 679 679 + # LED drivers 680 680 + # 681 681 + 682 682 + # 683 683 + # LED Triggers 684 684 + # 685 685 + 686 686 + # 687 687 + # Multimedia devices 688 688 + # 689 689 + # CONFIG_VIDEO_DEV is not set 690 690 + 691 691 + # 692 692 + # Digital Video Broadcasting Devices 693 693 + # 694 694 + # CONFIG_DVB is not set 695 695 + 696 696 + # 697 697 + # Graphics support 698 698 + # 699 699 + # CONFIG_FB is not set 700 700 + 701 701 + # 702 702 + # Console display driver support 703 703 + # 704 704 + # CONFIG_VGA_CONSOLE is not set 705 705 + CONFIG_DUMMY_CONSOLE=y 706 706 + 707 707 + # 708 708 + # Sound 709 709 + # 710 710 + # CONFIG_SOUND is not set 711 711 + 712 712 + # 713 713 + # USB support 714 714 + # 715 715 + CONFIG_USB_ARCH_HAS_HCD=y 716 716 + CONFIG_USB_ARCH_HAS_OHCI=y 717 717 + CONFIG_USB_ARCH_HAS_EHCI=y 718 718 + # CONFIG_USB is not set 719 719 + 720 720 + # 721 721 + # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 722 722 + # 723 723 + 724 724 + # 725 725 + # USB Gadget Support 726 726 + # 727 727 + # CONFIG_USB_GADGET is not set 728 728 + 729 729 + # 730 730 + # MMC/SD Card support 731 731 + # 732 732 + # CONFIG_MMC is not set 733 733 + 734 734 + # 735 735 + # Real Time Clock 736 736 + # 737 737 + CONFIG_RTC_LIB=y 738 738 + # CONFIG_RTC_CLASS is not set 739 739 + 740 740 + # 741 741 + # File systems 742 742 + # 743 743 + CONFIG_EXT2_FS=y 744 744 + # CONFIG_EXT2_FS_XATTR is not set 745 745 + # CONFIG_EXT2_FS_XIP is not set 746 746 + # CONFIG_EXT3_FS is not set 747 747 + # CONFIG_REISERFS_FS is not set 748 748 + # CONFIG_JFS_FS is not set 749 749 + # CONFIG_FS_POSIX_ACL is not set 750 750 + # CONFIG_XFS_FS is not set 751 751 + # CONFIG_OCFS2_FS is not set 752 752 + # CONFIG_MINIX_FS is not set 753 753 + # CONFIG_ROMFS_FS is not set 754 754 + CONFIG_INOTIFY=y 755 755 + # CONFIG_QUOTA is not set 756 756 + CONFIG_DNOTIFY=y 757 757 + # CONFIG_AUTOFS_FS is not set 758 758 + # CONFIG_AUTOFS4_FS is not set 759 759 + # CONFIG_FUSE_FS is not set 760 760 + 761 761 + # 762 762 + # CD-ROM/DVD Filesystems 763 763 + # 764 764 + # CONFIG_ISO9660_FS is not set 765 765 + # CONFIG_UDF_FS is not set 766 766 + 767 767 + # 768 768 + # DOS/FAT/NT Filesystems 769 769 + # 770 770 + # CONFIG_MSDOS_FS is not set 771 771 + # CONFIG_VFAT_FS is not set 772 772 + # CONFIG_NTFS_FS is not set 773 773 + 774 774 + # 775 775 + # Pseudo filesystems 776 776 + # 777 777 + CONFIG_PROC_FS=y 778 778 + CONFIG_SYSFS=y 779 779 + CONFIG_TMPFS=y 780 780 + # CONFIG_HUGETLB_PAGE is not set 781 781 + CONFIG_RAMFS=y 782 782 + # CONFIG_CONFIGFS_FS is not set 783 783 + 784 784 + # 785 785 + # Miscellaneous filesystems 786 786 + # 787 787 + # CONFIG_ADFS_FS is not set 788 788 + # CONFIG_AFFS_FS is not set 789 789 + # CONFIG_HFS_FS is not set 790 790 + # CONFIG_HFSPLUS_FS is not set 791 791 + # CONFIG_BEFS_FS is not set 792 792 + # CONFIG_BFS_FS is not set 793 793 + # CONFIG_EFS_FS is not set 794 794 + # CONFIG_JFFS_FS is not set 795 795 + # CONFIG_JFFS2_FS is not set 796 796 + CONFIG_CRAMFS=y 797 797 + # CONFIG_VXFS_FS is not set 798 798 + # CONFIG_HPFS_FS is not set 799 799 + # CONFIG_QNX4FS_FS is not set 800 800 + # CONFIG_SYSV_FS is not set 801 801 + # CONFIG_UFS_FS is not set 802 802 + 803 803 + # 804 804 + # Network File Systems 805 805 + # 806 806 + # CONFIG_NFS_FS is not set 807 807 + # CONFIG_NFSD is not set 808 808 + # CONFIG_SMB_FS is not set 809 809 + # CONFIG_CIFS is not set 810 810 + # CONFIG_NCP_FS is not set 811 811 + # CONFIG_CODA_FS is not set 812 812 + # CONFIG_AFS_FS is not set 813 813 + # CONFIG_9P_FS is not set 814 814 + 815 815 + # 816 816 + # Partition Types 817 817 + # 818 818 + # CONFIG_PARTITION_ADVANCED is not set 819 819 + CONFIG_MSDOS_PARTITION=y 820 820 + 821 821 + # 822 822 + # Native Language Support 823 823 + # 824 824 + # CONFIG_NLS is not set 825 825 + 826 826 + # 827 827 + # Profiling support 828 828 + # 829 829 + # CONFIG_PROFILING is not set 830 830 + 831 831 + # 832 832 + # Kernel hacking 833 833 + # 834 834 + # CONFIG_PRINTK_TIME is not set 835 835 + # CONFIG_MAGIC_SYSRQ is not set 836 836 + CONFIG_DEBUG_KERNEL=y 837 837 + CONFIG_LOG_BUF_SHIFT=14 838 838 + CONFIG_DETECT_SOFTLOCKUP=y 839 839 + # CONFIG_SCHEDSTATS is not set 840 840 + # CONFIG_DEBUG_SLAB is not set 841 841 + CONFIG_DEBUG_MUTEXES=y 842 842 + # CONFIG_DEBUG_SPINLOCK is not set 843 843 + # CONFIG_DEBUG_SPINLOCK_SLEEP is not set 844 844 + # CONFIG_DEBUG_KOBJECT is not set 845 845 + CONFIG_DEBUG_BUGVERBOSE=y 846 846 + # CONFIG_DEBUG_INFO is not set 847 847 + # CONFIG_DEBUG_FS is not set 848 848 + # CONFIG_DEBUG_VM is not set 849 849 + CONFIG_FRAME_POINTER=y 850 850 + # CONFIG_UNWIND_INFO is not set 851 851 + CONFIG_FORCED_INLINING=y 852 852 + # CONFIG_RCU_TORTURE_TEST is not set 853 853 + CONFIG_DEBUG_USER=y 854 854 + # CONFIG_DEBUG_ERRORS is not set 855 855 + CONFIG_DEBUG_LL=y 856 856 + # CONFIG_DEBUG_ICEDCC is not set 857 857 + 858 858 + # 859 859 + # Security options 860 860 + # 861 861 + # CONFIG_KEYS is not set 862 862 + # CONFIG_SECURITY is not set 863 863 + 864 864 + # 865 865 + # Cryptographic options 866 866 + # 867 867 + # CONFIG_CRYPTO is not set 868 868 + 869 869 + # 870 870 + # Hardware crypto devices 871 871 + # 872 872 + 873 873 + # 874 874 + # Library routines 875 875 + # 876 876 + # CONFIG_CRC_CCITT is not set 877 877 + # CONFIG_CRC16 is not set 878 878 + CONFIG_CRC32=y 879 879 + # CONFIG_LIBCRC32C is not set 880 880 + CONFIG_ZLIB_INFLATE=y

+329 -203

arch/arm/configs/trizeps4_defconfig

reviewed

··· 1 1 # 2 2 # Automatically generated make config: don't edit 3 3 - # Linux kernel version: 2.6.17 4 4 - # Sat Jun 24 22:45:14 2006 3 3 + # Linux kernel version: 2.6.21 4 4 + # Mon Apr 30 21:23:20 2007 5 5 # 6 6 CONFIG_ARM=y 7 7 + CONFIG_SYS_SUPPORTS_APM_EMULATION=y 8 8 + CONFIG_GENERIC_GPIO=y 9 9 + CONFIG_GENERIC_TIME=y 7 10 CONFIG_MMU=y 11 11 + # CONFIG_NO_IOPORT is not set 12 12 + CONFIG_GENERIC_HARDIRQS=y 13 13 + CONFIG_TRACE_IRQFLAGS_SUPPORT=y 14 14 + CONFIG_HARDIRQS_SW_RESEND=y 15 15 + CONFIG_GENERIC_IRQ_PROBE=y 8 16 CONFIG_RWSEM_GENERIC_SPINLOCK=y 17 17 + # CONFIG_ARCH_HAS_ILOG2_U32 is not set 18 18 + # CONFIG_ARCH_HAS_ILOG2_U64 is not set 9 19 CONFIG_GENERIC_HWEIGHT=y 10 20 CONFIG_GENERIC_CALIBRATE_DELAY=y 21 21 + CONFIG_ZONE_DMA=y 11 22 CONFIG_ARCH_MTD_XIP=y 12 23 CONFIG_VECTORS_BASE=0xffff0000 24 24 + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 13 25 14 26 # 15 27 # Code maturity level options ··· 38 26 CONFIG_LOCALVERSION_AUTO=y 39 27 CONFIG_SWAP=y 40 28 CONFIG_SYSVIPC=y 29 29 + # CONFIG_IPC_NS is not set 30 30 + CONFIG_SYSVIPC_SYSCTL=y 41 31 CONFIG_POSIX_MQUEUE=y 42 32 CONFIG_BSD_PROCESS_ACCT=y 43 33 CONFIG_BSD_PROCESS_ACCT_V3=y 44 44 - CONFIG_SYSCTL=y 45 45 - CONFIG_AUDIT=y 34 34 + # CONFIG_TASKSTATS is not set 35 35 + # CONFIG_UTS_NS is not set 36 36 + # CONFIG_AUDIT is not set 46 37 CONFIG_IKCONFIG=y 47 38 CONFIG_IKCONFIG_PROC=y 39 39 + CONFIG_SYSFS_DEPRECATED=y 48 40 # CONFIG_RELAY is not set 41 41 + CONFIG_BLK_DEV_INITRD=y 49 42 CONFIG_INITRAMFS_SOURCE="" 50 50 - CONFIG_UID16=y 51 43 CONFIG_CC_OPTIMIZE_FOR_SIZE=y 44 44 + CONFIG_SYSCTL=y 52 45 CONFIG_EMBEDDED=y 46 46 + CONFIG_UID16=y 47 47 + CONFIG_SYSCTL_SYSCALL=y 53 48 CONFIG_KALLSYMS=y 54 49 CONFIG_KALLSYMS_EXTRA_PASS=y 55 50 CONFIG_HOTPLUG=y ··· 68 49 CONFIG_EPOLL=y 69 50 CONFIG_SHMEM=y 70 51 CONFIG_SLAB=y 52 52 + CONFIG_VM_EVENT_COUNTERS=y 53 53 + CONFIG_RT_MUTEXES=y 71 54 # CONFIG_TINY_SHMEM is not set 72 55 CONFIG_BASE_SMALL=0 73 56 # CONFIG_SLOB is not set 74 74 - CONFIG_OBSOLETE_INTERMODULE=y 75 57 76 58 # 77 59 # Loadable module support ··· 80 60 CONFIG_MODULES=y 81 61 CONFIG_MODULE_UNLOAD=y 82 62 CONFIG_MODULE_FORCE_UNLOAD=y 83 83 - # CONFIG_MODVERSIONS is not set 63 63 + CONFIG_MODVERSIONS=y 84 64 CONFIG_MODULE_SRCVERSION_ALL=y 85 65 CONFIG_KMOD=y 86 66 87 67 # 88 68 # Block layer 89 69 # 70 70 + CONFIG_BLOCK=y 71 71 + CONFIG_LBD=y 90 72 # CONFIG_BLK_DEV_IO_TRACE is not set 73 73 + CONFIG_LSF=y 91 74 92 75 # 93 76 # IO Schedulers ··· 108 85 # 109 86 # System Type 110 87 # 88 88 + # CONFIG_ARCH_AAEC2000 is not set 89 89 + # CONFIG_ARCH_INTEGRATOR is not set 90 90 + # CONFIG_ARCH_REALVIEW is not set 91 91 + # CONFIG_ARCH_VERSATILE is not set 92 92 + # CONFIG_ARCH_AT91 is not set 111 93 # CONFIG_ARCH_CLPS7500 is not set 112 94 # CONFIG_ARCH_CLPS711X is not set 113 95 # CONFIG_ARCH_CO285 is not set 114 96 # CONFIG_ARCH_EBSA110 is not set 115 97 # CONFIG_ARCH_EP93XX is not set 116 98 # CONFIG_ARCH_FOOTBRIDGE is not set 117 117 - # CONFIG_ARCH_INTEGRATOR is not set 118 118 - # CONFIG_ARCH_IOP3XX is not set 99 99 + # CONFIG_ARCH_NETX is not set 100 100 + # CONFIG_ARCH_H720X is not set 101 101 + # CONFIG_ARCH_IMX is not set 102 102 + # CONFIG_ARCH_IOP32X is not set 103 103 + # CONFIG_ARCH_IOP33X is not set 104 104 + # CONFIG_ARCH_IOP13XX is not set 119 105 # CONFIG_ARCH_IXP4XX is not set 120 106 # CONFIG_ARCH_IXP2000 is not set 121 107 # CONFIG_ARCH_IXP23XX is not set 122 108 # CONFIG_ARCH_L7200 is not set 109 109 + # CONFIG_ARCH_NS9XXX is not set 110 110 + # CONFIG_ARCH_PNX4008 is not set 123 111 CONFIG_ARCH_PXA=y 124 112 # CONFIG_ARCH_RPC is not set 125 113 # CONFIG_ARCH_SA1100 is not set ··· 138 104 # CONFIG_ARCH_SHARK is not set 139 105 # CONFIG_ARCH_LH7A40X is not set 140 106 # CONFIG_ARCH_OMAP is not set 141 141 - # CONFIG_ARCH_VERSATILE is not set 142 142 - # CONFIG_ARCH_REALVIEW is not set 143 143 - # CONFIG_ARCH_IMX is not set 144 144 - # CONFIG_ARCH_H720X is not set 145 145 - # CONFIG_ARCH_AAEC2000 is not set 146 146 - # CONFIG_ARCH_AT91RM9200 is not set 147 107 148 108 # 149 109 # Intel PXA2xx Implementations ··· 161 133 CONFIG_CPU_ABRT_EV5T=y 162 134 CONFIG_CPU_CACHE_VIVT=y 163 135 CONFIG_CPU_TLB_V4WBI=y 136 136 + CONFIG_CPU_CP15=y 137 137 + CONFIG_CPU_CP15_MMU=y 164 138 165 139 # 166 140 # Processor Features 167 141 # 168 142 CONFIG_ARM_THUMB=y 143 143 + # CONFIG_CPU_DCACHE_DISABLE is not set 144 144 + # CONFIG_OUTER_CACHE is not set 145 145 + CONFIG_IWMMXT=y 169 146 CONFIG_XSCALE_PMU=y 170 147 171 148 # ··· 180 147 # 181 148 # PCCARD (PCMCIA/CardBus) support 182 149 # 183 183 - CONFIG_PCCARD=m 150 150 + CONFIG_PCCARD=y 184 151 # CONFIG_PCMCIA_DEBUG is not set 185 185 - CONFIG_PCMCIA=m 186 186 - CONFIG_PCMCIA_LOAD_CIS=y 152 152 + CONFIG_PCMCIA=y 153 153 + # CONFIG_PCMCIA_LOAD_CIS is not set 187 154 CONFIG_PCMCIA_IOCTL=y 188 155 189 156 # 190 157 # PC-card bridges 191 158 # 192 192 - CONFIG_PCMCIA_PXA2XX=m 159 159 + CONFIG_PCMCIA_PXA2XX=y 193 160 194 161 # 195 162 # Kernel Features ··· 197 164 CONFIG_PREEMPT=y 198 165 # CONFIG_NO_IDLE_HZ is not set 199 166 CONFIG_HZ=100 200 200 - # CONFIG_AEABI is not set 167 167 + CONFIG_AEABI=y 168 168 + CONFIG_OABI_COMPAT=y 201 169 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 202 170 CONFIG_SELECT_MEMORY_MODEL=y 203 171 CONFIG_FLATMEM_MANUAL=y ··· 208 174 CONFIG_FLAT_NODE_MEM_MAP=y 209 175 # CONFIG_SPARSEMEM_STATIC is not set 210 176 CONFIG_SPLIT_PTLOCK_CPUS=4096 177 177 + # CONFIG_RESOURCES_64BIT is not set 178 178 + CONFIG_ZONE_DMA_FLAG=1 211 179 CONFIG_LEDS=y 212 180 CONFIG_LEDS_TIMER=y 213 181 CONFIG_LEDS_CPU=y ··· 220 184 # 221 185 CONFIG_ZBOOT_ROM_TEXT=0 222 186 CONFIG_ZBOOT_ROM_BSS=0 223 223 - CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200n8" 187 187 + CONFIG_CMDLINE="root=fe01 console=ttyS0,38400n8 loglevel=5" 224 188 # CONFIG_XIP_KERNEL is not set 189 189 + # CONFIG_KEXEC is not set 225 190 226 191 # 227 192 # Floating point emulation ··· 240 203 # 241 204 CONFIG_BINFMT_ELF=y 242 205 # CONFIG_BINFMT_AOUT is not set 243 243 - CONFIG_BINFMT_MISC=m 244 244 - # CONFIG_ARTHUR is not set 206 206 + # CONFIG_BINFMT_MISC is not set 245 207 246 208 # 247 209 # Power management options 248 210 # 249 211 CONFIG_PM=y 250 250 - CONFIG_PM_LEGACY=y 212 212 + # CONFIG_PM_LEGACY is not set 251 213 # CONFIG_PM_DEBUG is not set 252 252 - CONFIG_APM=y 214 214 + # CONFIG_PM_SYSFS_DEPRECATED is not set 215 215 + # CONFIG_APM_EMULATION is not set 253 216 254 217 # 255 218 # Networking ··· 259 222 # 260 223 # Networking options 261 224 # 262 262 - # CONFIG_NETDEBUG is not set 263 225 CONFIG_PACKET=y 264 226 CONFIG_PACKET_MMAP=y 265 227 CONFIG_UNIX=y 266 228 CONFIG_XFRM=y 267 229 CONFIG_XFRM_USER=m 230 230 + # CONFIG_XFRM_SUB_POLICY is not set 231 231 + # CONFIG_XFRM_MIGRATE is not set 268 232 CONFIG_NET_KEY=y 233 233 + # CONFIG_NET_KEY_MIGRATE is not set 269 234 CONFIG_INET=y 270 235 # CONFIG_IP_MULTICAST is not set 271 236 # CONFIG_IP_ADVANCED_ROUTER is not set ··· 285 246 # CONFIG_INET_IPCOMP is not set 286 247 # CONFIG_INET_XFRM_TUNNEL is not set 287 248 # CONFIG_INET_TUNNEL is not set 249 249 + CONFIG_INET_XFRM_MODE_TRANSPORT=y 250 250 + CONFIG_INET_XFRM_MODE_TUNNEL=y 251 251 + CONFIG_INET_XFRM_MODE_BEET=y 288 252 CONFIG_INET_DIAG=y 289 253 CONFIG_INET_TCP_DIAG=y 290 254 # CONFIG_TCP_CONG_ADVANCED is not set 291 291 - CONFIG_TCP_CONG_BIC=y 255 255 + CONFIG_TCP_CONG_CUBIC=y 256 256 + CONFIG_DEFAULT_TCP_CONG="cubic" 257 257 + # CONFIG_TCP_MD5SIG is not set 292 258 293 259 # 294 260 # IP: Virtual Server Configuration 295 261 # 296 262 # CONFIG_IP_VS is not set 297 297 - CONFIG_IPV6=m 298 298 - # CONFIG_IPV6_PRIVACY is not set 299 299 - # CONFIG_IPV6_ROUTER_PREF is not set 300 300 - # CONFIG_INET6_AH is not set 301 301 - # CONFIG_INET6_ESP is not set 302 302 - # CONFIG_INET6_IPCOMP is not set 263 263 + # CONFIG_IPV6 is not set 303 264 # CONFIG_INET6_XFRM_TUNNEL is not set 304 265 # CONFIG_INET6_TUNNEL is not set 305 305 - # CONFIG_IPV6_TUNNEL is not set 266 266 + # CONFIG_NETLABEL is not set 267 267 + # CONFIG_NETWORK_SECMARK is not set 306 268 CONFIG_NETFILTER=y 307 269 # CONFIG_NETFILTER_DEBUG is not set 308 270 ··· 311 271 # Core Netfilter Configuration 312 272 # 313 273 # CONFIG_NETFILTER_NETLINK is not set 274 274 + # CONFIG_NF_CONNTRACK_ENABLED is not set 275 275 + # CONFIG_NF_CONNTRACK is not set 314 276 # CONFIG_NETFILTER_XTABLES is not set 315 277 316 278 # 317 279 # IP: Netfilter Configuration 318 280 # 319 319 - CONFIG_IP_NF_CONNTRACK=m 320 320 - CONFIG_IP_NF_CT_ACCT=y 321 321 - CONFIG_IP_NF_CONNTRACK_MARK=y 322 322 - # CONFIG_IP_NF_CONNTRACK_EVENTS is not set 323 323 - # CONFIG_IP_NF_CT_PROTO_SCTP is not set 324 324 - CONFIG_IP_NF_FTP=m 325 325 - CONFIG_IP_NF_IRC=m 326 326 - # CONFIG_IP_NF_NETBIOS_NS is not set 327 327 - CONFIG_IP_NF_TFTP=m 328 328 - CONFIG_IP_NF_AMANDA=m 329 329 - # CONFIG_IP_NF_PPTP is not set 330 330 - # CONFIG_IP_NF_H323 is not set 331 281 CONFIG_IP_NF_QUEUE=m 332 332 - 333 333 - # 334 334 - # IPv6: Netfilter Configuration (EXPERIMENTAL) 335 335 - # 336 336 - # CONFIG_IP6_NF_QUEUE is not set 282 282 + # CONFIG_IP_NF_IPTABLES is not set 283 283 + # CONFIG_IP_NF_ARPTABLES is not set 337 284 338 285 # 339 286 # DCCP Configuration (EXPERIMENTAL) ··· 345 318 # CONFIG_ATALK is not set 346 319 # CONFIG_X25 is not set 347 320 # CONFIG_LAPB is not set 348 348 - # CONFIG_NET_DIVERT is not set 349 321 # CONFIG_ECONET is not set 350 322 # CONFIG_WAN_ROUTER is not set 351 323 ··· 404 378 # CONFIG_USB_IRDA is not set 405 379 # CONFIG_SIGMATEL_FIR is not set 406 380 # CONFIG_PXA_FICP is not set 381 381 + # CONFIG_MCS_FIR is not set 407 382 CONFIG_BT=m 408 383 CONFIG_BT_L2CAP=m 409 384 CONFIG_BT_SCO=m ··· 428 401 # CONFIG_BT_HCIBLUECARD is not set 429 402 # CONFIG_BT_HCIBTUART is not set 430 403 # CONFIG_BT_HCIVHCI is not set 431 431 - CONFIG_IEEE80211=m 404 404 + # CONFIG_AF_RXRPC is not set 405 405 + 406 406 + # 407 407 + # Wireless 408 408 + # 409 409 + CONFIG_CFG80211=y 410 410 + CONFIG_WIRELESS_EXT=y 411 411 + CONFIG_IEEE80211=y 432 412 # CONFIG_IEEE80211_DEBUG is not set 433 433 - CONFIG_IEEE80211_CRYPT_WEP=m 413 413 + CONFIG_IEEE80211_CRYPT_WEP=y 434 414 CONFIG_IEEE80211_CRYPT_CCMP=m 435 415 CONFIG_IEEE80211_CRYPT_TKIP=m 436 416 CONFIG_IEEE80211_SOFTMAC=m 437 417 # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set 438 438 - CONFIG_WIRELESS_EXT=y 439 418 440 419 # 441 420 # Device Drivers ··· 453 420 CONFIG_STANDALONE=y 454 421 CONFIG_PREVENT_FIRMWARE_BUILD=y 455 422 CONFIG_FW_LOADER=y 423 423 + # CONFIG_SYS_HYPERVISOR is not set 456 424 457 425 # 458 426 # Connector - unified userspace <-> kernelspace linker 459 427 # 460 428 CONFIG_CONNECTOR=y 461 429 CONFIG_PROC_EVENTS=y 462 462 - 463 463 - # 464 464 - # Memory Technology Devices (MTD) 465 465 - # 466 430 CONFIG_MTD=y 467 431 # CONFIG_MTD_DEBUG is not set 468 432 CONFIG_MTD_CONCAT=y ··· 475 445 # User Modules And Translation Layers 476 446 # 477 447 CONFIG_MTD_CHAR=y 448 448 + CONFIG_MTD_BLKDEVS=y 478 449 CONFIG_MTD_BLOCK=y 479 450 # CONFIG_FTL is not set 480 480 - CONFIG_NFTL=y 481 481 - CONFIG_NFTL_RW=y 482 482 - CONFIG_INFTL=y 451 451 + # CONFIG_NFTL is not set 452 452 + # CONFIG_INFTL is not set 483 453 # CONFIG_RFD_FTL is not set 454 454 + # CONFIG_SSFDC is not set 484 455 485 456 # 486 457 # RAM/ROM/Flash chip drivers ··· 521 490 CONFIG_MTD_COMPLEX_MAPPINGS=y 522 491 CONFIG_MTD_PHYSMAP=y 523 492 CONFIG_MTD_PHYSMAP_START=0x0 524 524 - CONFIG_MTD_PHYSMAP_LEN=0x4000000 493 493 + CONFIG_MTD_PHYSMAP_LEN=0x0 525 494 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 526 526 - # CONFIG_MTD_TRIZEPS4 is not set 527 495 # CONFIG_MTD_ARM_INTEGRATOR is not set 528 496 # CONFIG_MTD_IMPA7 is not set 529 497 # CONFIG_MTD_SHARP_SL is not set ··· 531 501 # 532 502 # Self-contained MTD device drivers 533 503 # 534 534 - # CONFIG_MTD_DATAFLASH is not set 535 535 - # CONFIG_MTD_M25P80 is not set 536 504 # CONFIG_MTD_SLRAM is not set 537 505 # CONFIG_MTD_PHRAM is not set 538 506 # CONFIG_MTD_MTDRAM is not set 539 539 - # CONFIG_MTD_BLOCK2MTD is not set 507 507 + CONFIG_MTD_BLOCK2MTD=y 540 508 541 509 # 542 510 # Disk-On-Chip Device Drivers 543 511 # 544 544 - # CONFIG_MTD_DOC2000 is not set 545 545 - # CONFIG_MTD_DOC2001 is not set 512 512 + CONFIG_MTD_DOC2000=y 513 513 + CONFIG_MTD_DOC2001=y 546 514 CONFIG_MTD_DOC2001PLUS=y 547 515 CONFIG_MTD_DOCPROBE=y 548 516 CONFIG_MTD_DOCECC=y 549 549 - # CONFIG_MTD_DOCPROBE_ADVANCED is not set 550 550 - CONFIG_MTD_DOCPROBE_ADDRESS=0 551 551 - 552 552 - # 553 553 - # NAND Flash Device Drivers 554 554 - # 517 517 + CONFIG_MTD_DOCPROBE_ADVANCED=y 518 518 + CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000 519 519 + CONFIG_MTD_DOCPROBE_HIGH=y 520 520 + # CONFIG_MTD_DOCPROBE_55AA is not set 555 521 CONFIG_MTD_NAND=y 556 522 # CONFIG_MTD_NAND_VERIFY_WRITE is not set 523 523 + # CONFIG_MTD_NAND_ECC_SMC is not set 524 524 + # CONFIG_MTD_NAND_MUSEUM_IDS is not set 557 525 # CONFIG_MTD_NAND_H1900 is not set 558 526 CONFIG_MTD_NAND_IDS=y 559 527 CONFIG_MTD_NAND_DISKONCHIP=y 560 560 - # CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set 561 561 - CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 562 562 - # CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set 528 528 + CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y 529 529 + CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000 530 530 + CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y 531 531 + CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y 563 532 # CONFIG_MTD_NAND_SHARPSL is not set 564 533 # CONFIG_MTD_NAND_NANDSIM is not set 534 534 + CONFIG_MTD_ONENAND=y 535 535 + # CONFIG_MTD_ONENAND_VERIFY_WRITE is not set 536 536 + # CONFIG_MTD_ONENAND_GENERIC is not set 537 537 + # CONFIG_MTD_ONENAND_OTP is not set 565 538 566 539 # 567 567 - # OneNAND Flash Device Drivers 540 540 + # UBI - Unsorted block images 568 541 # 569 569 - # CONFIG_MTD_ONENAND is not set 542 542 + # CONFIG_MTD_UBI is not set 570 543 571 544 # 572 545 # Parallel port support ··· 579 546 # 580 547 # Plug and Play support 581 548 # 549 549 + # CONFIG_PNPACPI is not set 582 550 583 551 # 584 552 # Block devices ··· 590 556 CONFIG_BLK_DEV_NBD=y 591 557 # CONFIG_BLK_DEV_UB is not set 592 558 CONFIG_BLK_DEV_RAM=y 593 593 - CONFIG_BLK_DEV_RAM_COUNT=4 559 559 + CONFIG_BLK_DEV_RAM_COUNT=8 594 560 CONFIG_BLK_DEV_RAM_SIZE=4096 595 595 - CONFIG_BLK_DEV_INITRD=y 561 561 + CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 596 562 # CONFIG_CDROM_PKTCDVD is not set 597 563 # CONFIG_ATA_OVER_ETH is not set 598 564 ··· 600 566 # ATA/ATAPI/MFM/RLL support 601 567 # 602 568 CONFIG_IDE=y 569 569 + CONFIG_IDE_MAX_HWIFS=4 603 570 CONFIG_BLK_DEV_IDE=y 604 571 605 572 # ··· 620 585 # IDE chipset support/bugfixes 621 586 # 622 587 CONFIG_IDE_GENERIC=y 623 623 - CONFIG_IDE_PXA_CF=y 624 624 - CONFIG_IDE_ARM=y 588 588 + # CONFIG_IDE_ARM is not set 625 589 # CONFIG_BLK_DEV_IDEDMA is not set 626 626 - # CONFIG_IDEDMA_AUTO is not set 627 590 # CONFIG_BLK_DEV_HD is not set 628 591 629 592 # 630 593 # SCSI device support 631 594 # 632 595 # CONFIG_RAID_ATTRS is not set 633 633 - CONFIG_SCSI=m 596 596 + CONFIG_SCSI=y 597 597 + # CONFIG_SCSI_TGT is not set 598 598 + # CONFIG_SCSI_NETLINK is not set 634 599 CONFIG_SCSI_PROC_FS=y 635 600 636 601 # 637 602 # SCSI support type (disk, tape, CD-ROM) 638 603 # 639 639 - CONFIG_BLK_DEV_SD=m 604 604 + CONFIG_BLK_DEV_SD=y 640 605 # CONFIG_CHR_DEV_ST is not set 641 606 # CONFIG_CHR_DEV_OSST is not set 642 607 # CONFIG_BLK_DEV_SR is not set 643 643 - CONFIG_CHR_DEV_SG=m 608 608 + CONFIG_CHR_DEV_SG=y 644 609 # CONFIG_CHR_DEV_SCH is not set 645 610 646 611 # ··· 649 614 CONFIG_SCSI_MULTI_LUN=y 650 615 # CONFIG_SCSI_CONSTANTS is not set 651 616 # CONFIG_SCSI_LOGGING is not set 617 617 + # CONFIG_SCSI_SCAN_ASYNC is not set 652 618 653 619 # 654 654 - # SCSI Transport Attributes 620 620 + # SCSI Transports 655 621 # 656 622 # CONFIG_SCSI_SPI_ATTRS is not set 657 623 # CONFIG_SCSI_FC_ATTRS is not set 658 624 # CONFIG_SCSI_ISCSI_ATTRS is not set 659 625 # CONFIG_SCSI_SAS_ATTRS is not set 626 626 + # CONFIG_SCSI_SAS_LIBSAS is not set 660 627 661 628 # 662 629 # SCSI low-level drivers 663 630 # 664 631 # CONFIG_ISCSI_TCP is not set 665 665 - # CONFIG_SCSI_SATA is not set 666 632 # CONFIG_SCSI_DEBUG is not set 633 633 + # CONFIG_SCSI_ESP_CORE is not set 667 634 668 635 # 669 636 # PCMCIA SCSI adapter support ··· 675 638 # CONFIG_PCMCIA_NINJA_SCSI is not set 676 639 # CONFIG_PCMCIA_QLOGIC is not set 677 640 # CONFIG_PCMCIA_SYM53C500 is not set 641 641 + 642 642 + # 643 643 + # Serial ATA (prod) and Parallel ATA (experimental) drivers 644 644 + # 645 645 + CONFIG_ATA=m 646 646 + # CONFIG_ATA_NONSTANDARD is not set 647 647 + CONFIG_PATA_PCMCIA=m 648 648 + CONFIG_PATA_PLATFORM=m 678 649 679 650 # 680 651 # Multi-device support (RAID and LVM) ··· 720 675 # MII PHY device drivers 721 676 # 722 677 # CONFIG_MARVELL_PHY is not set 723 723 - CONFIG_DAVICOM_PHY=y 678 678 + # CONFIG_DAVICOM_PHY is not set 724 679 # CONFIG_QSEMI_PHY is not set 725 680 # CONFIG_LXT_PHY is not set 726 681 # CONFIG_CICADA_PHY is not set 682 682 + # CONFIG_VITESSE_PHY is not set 683 683 + # CONFIG_SMSC_PHY is not set 684 684 + # CONFIG_BROADCOM_PHY is not set 685 685 + # CONFIG_FIXED_PHY is not set 727 686 728 687 # 729 688 # Ethernet (10 or 100Mbit) ··· 736 687 CONFIG_MII=y 737 688 # CONFIG_SMC91X is not set 738 689 CONFIG_DM9000=y 690 690 + # CONFIG_SMC911X is not set 739 691 740 692 # 741 693 # Ethernet (1000 Mbit) ··· 751 701 # 752 702 753 703 # 754 754 - # Wireless LAN (non-hamradio) 704 704 + # Wireless LAN 755 705 # 756 756 - CONFIG_NET_RADIO=y 757 757 - # CONFIG_NET_WIRELESS_RTNETLINK is not set 758 758 - 759 759 - # 760 760 - # Obsolete Wireless cards support (pre-802.11) 761 761 - # 762 762 - # CONFIG_STRIP is not set 763 763 - # CONFIG_PCMCIA_WAVELAN is not set 764 764 - # CONFIG_PCMCIA_NETWAVE is not set 765 765 - 766 766 - # 767 767 - # Wireless 802.11 Frequency Hopping cards support 768 768 - # 706 706 + # CONFIG_WLAN_PRE80211 is not set 707 707 + CONFIG_WLAN_80211=y 769 708 # CONFIG_PCMCIA_RAYCS is not set 770 770 - 771 771 - # 772 772 - # Wireless 802.11b ISA/PCI cards support 773 773 - # 774 774 - CONFIG_HERMES=m 709 709 + CONFIG_HERMES=y 775 710 # CONFIG_ATMEL is not set 776 776 - 777 777 - # 778 778 - # Wireless 802.11b Pcmcia/Cardbus cards support 779 779 - # 780 780 - CONFIG_PCMCIA_HERMES=m 781 781 - # CONFIG_PCMCIA_SPECTRUM is not set 782 782 - CONFIG_AIRO_CS=m 711 711 + CONFIG_PCMCIA_HERMES=y 712 712 + CONFIG_PCMCIA_SPECTRUM=y 713 713 + # CONFIG_AIRO_CS is not set 783 714 # CONFIG_PCMCIA_WL3501 is not set 784 784 - CONFIG_HOSTAP=m 715 715 + # CONFIG_USB_ZD1201 is not set 716 716 + CONFIG_HOSTAP=y 785 717 CONFIG_HOSTAP_FIRMWARE=y 786 718 CONFIG_HOSTAP_FIRMWARE_NVRAM=y 787 787 - CONFIG_HOSTAP_CS=m 788 788 - CONFIG_NET_WIRELESS=y 719 719 + CONFIG_HOSTAP_CS=y 720 720 + # CONFIG_ZD1211RW is not set 789 721 790 722 # 791 723 # PCMCIA network device support ··· 788 756 CONFIG_PPP_MPPE=m 789 757 # CONFIG_PPPOE is not set 790 758 # CONFIG_SLIP is not set 759 759 + CONFIG_SLHC=m 791 760 # CONFIG_SHAPER is not set 792 761 # CONFIG_NETCONSOLE is not set 793 762 # CONFIG_NETPOLL is not set ··· 803 770 # Input device support 804 771 # 805 772 CONFIG_INPUT=y 773 773 + # CONFIG_INPUT_FF_MEMLESS is not set 806 774 807 775 # 808 776 # Userland interfaces ··· 823 789 # Input Device Drivers 824 790 # 825 791 CONFIG_INPUT_KEYBOARD=y 826 826 - CONFIG_KEYBOARD_ATKBD=y 792 792 + CONFIG_KEYBOARD_ATKBD=m 827 793 # CONFIG_KEYBOARD_SUNKBD is not set 828 794 # CONFIG_KEYBOARD_LKKBD is not set 829 795 # CONFIG_KEYBOARD_XTKBD is not set 830 796 # CONFIG_KEYBOARD_NEWTON is not set 797 797 + # CONFIG_KEYBOARD_STOWAWAY is not set 798 798 + # CONFIG_KEYBOARD_GPIO is not set 831 799 CONFIG_INPUT_MOUSE=y 832 800 # CONFIG_MOUSE_PS2 is not set 833 833 - CONFIG_MOUSE_SERIAL=y 801 801 + CONFIG_MOUSE_SERIAL=m 834 802 # CONFIG_MOUSE_VSXXXAA is not set 835 803 # CONFIG_INPUT_JOYSTICK is not set 836 804 CONFIG_INPUT_TOUCHSCREEN=y 837 837 - # CONFIG_TOUCHSCREEN_ADS7846 is not set 838 805 # CONFIG_TOUCHSCREEN_GUNZE is not set 839 806 # CONFIG_TOUCHSCREEN_ELO is not set 840 807 # CONFIG_TOUCHSCREEN_MTOUCH is not set 841 808 # CONFIG_TOUCHSCREEN_MK712 is not set 809 809 + # CONFIG_TOUCHSCREEN_PENMOUNT is not set 810 810 + # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set 811 811 + # CONFIG_TOUCHSCREEN_TOUCHWIN is not set 812 812 + CONFIG_TOUCHSCREEN_UCB1400=y 842 813 CONFIG_INPUT_MISC=y 843 814 CONFIG_INPUT_UINPUT=m 844 815 ··· 862 823 CONFIG_VT=y 863 824 CONFIG_VT_CONSOLE=y 864 825 CONFIG_HW_CONSOLE=y 826 826 + # CONFIG_VT_HW_CONSOLE_BINDING is not set 865 827 # CONFIG_SERIAL_NONSTANDARD is not set 866 828 867 829 # ··· 902 862 # USB-based Watchdog Cards 903 863 # 904 864 # CONFIG_USBPCWATCHDOG is not set 865 865 + CONFIG_HW_RANDOM=y 905 866 # CONFIG_NVRAM is not set 906 867 # CONFIG_DTLK is not set 907 868 # CONFIG_R3964 is not set 908 908 - 909 909 - # 910 910 - # Ftape, the floppy tape device driver 911 911 - # 912 869 913 870 # 914 871 # PCMCIA character devices ··· 919 882 # TPM devices 920 883 # 921 884 # CONFIG_TCG_TPM is not set 922 922 - # CONFIG_TELCLOCK is not set 923 885 924 886 # 925 887 # I2C support ··· 938 902 # 939 903 CONFIG_I2C_PXA=y 940 904 CONFIG_I2C_PXA_SLAVE=y 905 905 + # CONFIG_I2C_OCORES is not set 941 906 # CONFIG_I2C_PARPORT_LIGHT is not set 942 907 # CONFIG_I2C_STUB is not set 943 908 # CONFIG_I2C_PCA_ISA is not set ··· 948 911 # 949 912 # CONFIG_SENSORS_DS1337 is not set 950 913 # CONFIG_SENSORS_DS1374 is not set 951 951 - CONFIG_SENSORS_EEPROM=m 914 914 + # CONFIG_SENSORS_EEPROM is not set 952 915 # CONFIG_SENSORS_PCF8574 is not set 953 916 # CONFIG_SENSORS_PCA9539 is not set 954 917 # CONFIG_SENSORS_PCF8591 is not set ··· 961 924 # 962 925 # SPI support 963 926 # 964 964 - CONFIG_SPI=y 965 965 - CONFIG_SPI_MASTER=y 966 966 - 967 967 - # 968 968 - # SPI Master Controller Drivers 969 969 - # 970 970 - # CONFIG_SPI_BITBANG is not set 971 971 - CONFIG_SPI_PXA2XX=m 972 972 - 973 973 - # 974 974 - # SPI Protocol Masters 975 975 - # 927 927 + # CONFIG_SPI is not set 928 928 + # CONFIG_SPI_MASTER is not set 976 929 977 930 # 978 931 # Dallas's 1-wire bus ··· 974 947 # 975 948 CONFIG_HWMON=y 976 949 # CONFIG_HWMON_VID is not set 950 950 + # CONFIG_SENSORS_ABITUGURU is not set 977 951 # CONFIG_SENSORS_ADM1021 is not set 978 952 # CONFIG_SENSORS_ADM1025 is not set 979 953 # CONFIG_SENSORS_ADM1026 is not set 954 954 + # CONFIG_SENSORS_ADM1029 is not set 980 955 # CONFIG_SENSORS_ADM1031 is not set 981 956 # CONFIG_SENSORS_ADM9240 is not set 982 957 # CONFIG_SENSORS_ASB100 is not set ··· 1002 973 # CONFIG_SENSORS_LM92 is not set 1003 974 # CONFIG_SENSORS_MAX1619 is not set 1004 975 # CONFIG_SENSORS_PC87360 is not set 976 976 + # CONFIG_SENSORS_PC87427 is not set 1005 977 # CONFIG_SENSORS_SMSC47M1 is not set 978 978 + # CONFIG_SENSORS_SMSC47M192 is not set 1006 979 # CONFIG_SENSORS_SMSC47B397 is not set 980 980 + # CONFIG_SENSORS_VT1211 is not set 1007 981 # CONFIG_SENSORS_W83781D is not set 982 982 + # CONFIG_SENSORS_W83791D is not set 1008 983 # CONFIG_SENSORS_W83792D is not set 984 984 + # CONFIG_SENSORS_W83793 is not set 1009 985 # CONFIG_SENSORS_W83L785TS is not set 1010 986 # CONFIG_SENSORS_W83627HF is not set 1011 987 # CONFIG_SENSORS_W83627EHF is not set ··· 1021 987 # 1022 988 1023 989 # 1024 1024 - # Multimedia Capabilities Port drivers 990 990 + # Multifunction device drivers 1025 991 # 1026 1026 - CONFIG_UCB1400=y 1027 1027 - CONFIG_UCB1400_TS=y 992 992 + # CONFIG_MFD_SM501 is not set 1028 993 1029 994 # 1030 995 # LED devices 1031 996 # 1032 997 CONFIG_NEW_LEDS=y 1033 1033 - CONFIG_LEDS_CLASS=y 998 998 + # CONFIG_LEDS_CLASS is not set 1034 999 1035 1000 # 1036 1001 # LED drivers ··· 1040 1007 # 1041 1008 CONFIG_LEDS_TRIGGERS=y 1042 1009 CONFIG_LEDS_TRIGGER_TIMER=y 1043 1043 - CONFIG_LEDS_TRIGGER_IDE_DISK=y 1010 1010 + # CONFIG_LEDS_TRIGGER_IDE_DISK is not set 1011 1011 + CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1044 1012 1045 1013 # 1046 1014 # Multimedia devices 1047 1015 # 1048 1016 # CONFIG_VIDEO_DEV is not set 1049 1049 - CONFIG_VIDEO_V4L2=y 1050 1017 1051 1018 # 1052 1019 # Digital Video Broadcasting Devices ··· 1057 1024 # 1058 1025 # Graphics support 1059 1026 # 1027 1027 + CONFIG_BACKLIGHT_LCD_SUPPORT=y 1028 1028 + CONFIG_BACKLIGHT_CLASS_DEVICE=y 1029 1029 + CONFIG_LCD_CLASS_DEVICE=y 1060 1030 CONFIG_FB=y 1031 1031 + CONFIG_FIRMWARE_EDID=y 1032 1032 + # CONFIG_FB_DDC is not set 1061 1033 CONFIG_FB_CFB_FILLRECT=y 1062 1034 CONFIG_FB_CFB_COPYAREA=y 1063 1035 CONFIG_FB_CFB_IMAGEBLIT=y 1036 1036 + # CONFIG_FB_SVGALIB is not set 1064 1037 # CONFIG_FB_MACMODES is not set 1065 1065 - CONFIG_FB_FIRMWARE_EDID=y 1038 1038 + # CONFIG_FB_BACKLIGHT is not set 1066 1039 # CONFIG_FB_MODE_HELPERS is not set 1067 1040 # CONFIG_FB_TILEBLITTING is not set 1041 1041 + 1042 1042 + # 1043 1043 + # Frame buffer hardware drivers 1044 1044 + # 1068 1045 # CONFIG_FB_S1D13XXX is not set 1069 1046 CONFIG_FB_PXA=y 1070 1047 # CONFIG_FB_PXA_PARAMETERS is not set 1048 1048 + # CONFIG_FB_MBX is not set 1071 1049 # CONFIG_FB_VIRTUAL is not set 1072 1050 1073 1051 # ··· 1107 1063 CONFIG_LOGO_LINUX_MONO=y 1108 1064 CONFIG_LOGO_LINUX_VGA16=y 1109 1065 CONFIG_LOGO_LINUX_CLUT224=y 1110 1110 - CONFIG_BACKLIGHT_LCD_SUPPORT=y 1111 1111 - CONFIG_BACKLIGHT_CLASS_DEVICE=y 1112 1112 - CONFIG_BACKLIGHT_DEVICE=y 1113 1113 - CONFIG_LCD_CLASS_DEVICE=y 1114 1114 - CONFIG_LCD_DEVICE=y 1115 1066 1116 1067 # 1117 1068 # Sound ··· 1121 1082 CONFIG_SND_PCM=y 1122 1083 CONFIG_SND_HWDEP=m 1123 1084 CONFIG_SND_RAWMIDI=m 1124 1124 - CONFIG_SND_SEQUENCER=m 1085 1085 + CONFIG_SND_SEQUENCER=y 1125 1086 # CONFIG_SND_SEQ_DUMMY is not set 1126 1087 CONFIG_SND_OSSEMUL=y 1127 1088 CONFIG_SND_MIXER_OSS=y ··· 1132 1093 CONFIG_SND_SUPPORT_OLD_API=y 1133 1094 CONFIG_SND_VERBOSE_PROCFS=y 1134 1095 CONFIG_SND_VERBOSE_PRINTK=y 1135 1135 - # CONFIG_SND_DEBUG is not set 1096 1096 + CONFIG_SND_DEBUG=y 1097 1097 + CONFIG_SND_DEBUG_DETECT=y 1098 1098 + # CONFIG_SND_PCM_XRUN_DEBUG is not set 1136 1099 1137 1100 # 1138 1101 # Generic devices 1139 1102 # 1140 1103 CONFIG_SND_AC97_CODEC=y 1141 1141 - CONFIG_SND_AC97_BUS=y 1142 1104 # CONFIG_SND_DUMMY is not set 1143 1105 # CONFIG_SND_VIRMIDI is not set 1144 1106 # CONFIG_SND_MTPAV is not set ··· 1164 1124 # CONFIG_SND_PDAUDIOCF is not set 1165 1125 1166 1126 # 1127 1127 + # SoC audio support 1128 1128 + # 1129 1129 + # CONFIG_SND_SOC is not set 1130 1130 + 1131 1131 + # 1167 1132 # Open Sound System 1168 1133 # 1169 1134 # CONFIG_SOUND_PRIME is not set 1135 1135 + CONFIG_AC97_BUS=y 1136 1136 + 1137 1137 + # 1138 1138 + # HID Devices 1139 1139 + # 1140 1140 + CONFIG_HID=y 1141 1141 + # CONFIG_HID_DEBUG is not set 1142 1142 + 1143 1143 + # 1144 1144 + # USB Input Devices 1145 1145 + # 1146 1146 + # CONFIG_USB_HID is not set 1147 1147 + 1148 1148 + # 1149 1149 + # USB HID Boot Protocol drivers 1150 1150 + # 1151 1151 + # CONFIG_USB_KBD is not set 1152 1152 + # CONFIG_USB_MOUSE is not set 1170 1153 1171 1154 # 1172 1155 # USB support ··· 1204 1141 # Miscellaneous USB options 1205 1142 # 1206 1143 CONFIG_USB_DEVICEFS=y 1207 1207 - # CONFIG_USB_BANDWIDTH is not set 1144 1144 + # CONFIG_USB_DEVICE_CLASS is not set 1208 1145 # CONFIG_USB_DYNAMIC_MINORS is not set 1209 1146 # CONFIG_USB_SUSPEND is not set 1210 1147 # CONFIG_USB_OTG is not set ··· 1214 1151 # 1215 1152 # CONFIG_USB_ISP116X_HCD is not set 1216 1153 CONFIG_USB_OHCI_HCD=y 1217 1217 - # CONFIG_USB_OHCI_BIG_ENDIAN is not set 1154 1154 + # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 1155 1155 + # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1218 1156 CONFIG_USB_OHCI_LITTLE_ENDIAN=y 1219 1157 # CONFIG_USB_SL811_HCD is not set 1220 1158 ··· 1243 1179 # CONFIG_USB_STORAGE_SDDR55 is not set 1244 1180 # CONFIG_USB_STORAGE_JUMPSHOT is not set 1245 1181 # CONFIG_USB_STORAGE_ALAUDA is not set 1182 1182 + # CONFIG_USB_STORAGE_KARMA is not set 1246 1183 # CONFIG_USB_LIBUSUAL is not set 1247 1184 1248 1185 # 1249 1186 # USB Input Devices 1250 1187 # 1251 1251 - CONFIG_USB_HID=m 1252 1252 - CONFIG_USB_HIDINPUT=y 1253 1253 - # CONFIG_USB_HIDINPUT_POWERBOOK is not set 1254 1254 - # CONFIG_HID_FF is not set 1255 1255 - # CONFIG_USB_HIDDEV is not set 1256 1256 - 1257 1257 - # 1258 1258 - # USB HID Boot Protocol drivers 1259 1259 - # 1260 1260 - # CONFIG_USB_KBD is not set 1261 1261 - # CONFIG_USB_MOUSE is not set 1262 1188 # CONFIG_USB_AIPTEK is not set 1263 1189 # CONFIG_USB_WACOM is not set 1264 1190 # CONFIG_USB_ACECAD is not set 1265 1191 # CONFIG_USB_KBTAB is not set 1266 1192 # CONFIG_USB_POWERMATE is not set 1267 1267 - CONFIG_USB_TOUCHSCREEN=m 1268 1268 - # CONFIG_USB_TOUCHSCREEN_EGALAX is not set 1269 1269 - # CONFIG_USB_TOUCHSCREEN_PANJIT is not set 1270 1270 - # CONFIG_USB_TOUCHSCREEN_3M is not set 1271 1271 - # CONFIG_USB_TOUCHSCREEN_ITM is not set 1193 1193 + # CONFIG_USB_TOUCHSCREEN is not set 1272 1194 # CONFIG_USB_YEALINK is not set 1273 1195 # CONFIG_USB_XPAD is not set 1274 1196 # CONFIG_USB_ATI_REMOTE is not set 1275 1197 # CONFIG_USB_ATI_REMOTE2 is not set 1276 1198 # CONFIG_USB_KEYSPAN_REMOTE is not set 1277 1199 # CONFIG_USB_APPLETOUCH is not set 1200 1200 + # CONFIG_USB_GTCO is not set 1278 1201 1279 1202 # 1280 1203 # USB Imaging devices ··· 1276 1225 # CONFIG_USB_KAWETH is not set 1277 1226 # CONFIG_USB_PEGASUS is not set 1278 1227 # CONFIG_USB_RTL8150 is not set 1228 1228 + # CONFIG_USB_USBNET_MII is not set 1279 1229 # CONFIG_USB_USBNET is not set 1280 1280 - # CONFIG_USB_ZD1201 is not set 1281 1281 - CONFIG_USB_MON=y 1230 1230 + # CONFIG_USB_MON is not set 1282 1231 1283 1232 # 1284 1233 # USB port drivers ··· 1287 1236 # 1288 1237 # USB Serial Converter support 1289 1238 # 1290 1290 - # CONFIG_USB_SERIAL is not set 1239 1239 + CONFIG_USB_SERIAL=m 1240 1240 + # CONFIG_USB_SERIAL_GENERIC is not set 1241 1241 + # CONFIG_USB_SERIAL_AIRCABLE is not set 1242 1242 + # CONFIG_USB_SERIAL_AIRPRIME is not set 1243 1243 + # CONFIG_USB_SERIAL_ARK3116 is not set 1244 1244 + # CONFIG_USB_SERIAL_BELKIN is not set 1245 1245 + # CONFIG_USB_SERIAL_WHITEHEAT is not set 1246 1246 + # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set 1247 1247 + # CONFIG_USB_SERIAL_CP2101 is not set 1248 1248 + # CONFIG_USB_SERIAL_CYPRESS_M8 is not set 1249 1249 + # CONFIG_USB_SERIAL_EMPEG is not set 1250 1250 + # CONFIG_USB_SERIAL_FTDI_SIO is not set 1251 1251 + # CONFIG_USB_SERIAL_FUNSOFT is not set 1252 1252 + # CONFIG_USB_SERIAL_VISOR is not set 1253 1253 + # CONFIG_USB_SERIAL_IPAQ is not set 1254 1254 + # CONFIG_USB_SERIAL_IR is not set 1255 1255 + # CONFIG_USB_SERIAL_EDGEPORT is not set 1256 1256 + # CONFIG_USB_SERIAL_EDGEPORT_TI is not set 1257 1257 + # CONFIG_USB_SERIAL_GARMIN is not set 1258 1258 + # CONFIG_USB_SERIAL_IPW is not set 1259 1259 + # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set 1260 1260 + # CONFIG_USB_SERIAL_KEYSPAN is not set 1261 1261 + # CONFIG_USB_SERIAL_KLSI is not set 1262 1262 + # CONFIG_USB_SERIAL_KOBIL_SCT is not set 1263 1263 + # CONFIG_USB_SERIAL_MCT_U232 is not set 1264 1264 + # CONFIG_USB_SERIAL_MOS7720 is not set 1265 1265 + # CONFIG_USB_SERIAL_MOS7840 is not set 1266 1266 + # CONFIG_USB_SERIAL_NAVMAN is not set 1267 1267 + # CONFIG_USB_SERIAL_PL2303 is not set 1268 1268 + # CONFIG_USB_SERIAL_HP4X is not set 1269 1269 + # CONFIG_USB_SERIAL_SAFE is not set 1270 1270 + # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set 1271 1271 + # CONFIG_USB_SERIAL_TI is not set 1272 1272 + # CONFIG_USB_SERIAL_CYBERJACK is not set 1273 1273 + # CONFIG_USB_SERIAL_XIRCOM is not set 1274 1274 + # CONFIG_USB_SERIAL_OPTION is not set 1275 1275 + # CONFIG_USB_SERIAL_OMNINET is not set 1276 1276 + # CONFIG_USB_SERIAL_DEBUG is not set 1291 1277 1292 1278 # 1293 1279 # USB Miscellaneous drivers 1294 1280 # 1295 1281 # CONFIG_USB_EMI62 is not set 1296 1282 # CONFIG_USB_EMI26 is not set 1283 1283 + # CONFIG_USB_ADUTUX is not set 1297 1284 # CONFIG_USB_AUERSWALD is not set 1298 1285 # CONFIG_USB_RIO500 is not set 1299 1286 # CONFIG_USB_LEGOTOWER is not set 1300 1287 # CONFIG_USB_LCD is not set 1288 1288 + # CONFIG_USB_BERRY_CHARGE is not set 1301 1289 # CONFIG_USB_LED is not set 1290 1290 + # CONFIG_USB_CYPRESS_CY7C63 is not set 1302 1291 # CONFIG_USB_CYTHERM is not set 1303 1303 - # CONFIG_USB_PHIDGETKIT is not set 1304 1304 - # CONFIG_USB_PHIDGETSERVO is not set 1292 1292 + # CONFIG_USB_PHIDGET is not set 1305 1293 # CONFIG_USB_IDMOUSE is not set 1294 1294 + # CONFIG_USB_FTDI_ELAN is not set 1295 1295 + # CONFIG_USB_APPLEDISPLAY is not set 1306 1296 # CONFIG_USB_LD is not set 1297 1297 + # CONFIG_USB_TRANCEVIBRATOR is not set 1298 1298 + # CONFIG_USB_IOWARRIOR is not set 1307 1299 # CONFIG_USB_TEST is not set 1308 1300 1309 1301 # ··· 1356 1262 # 1357 1263 # USB Gadget Support 1358 1264 # 1359 1359 - CONFIG_USB_GADGET=y 1265 1265 + CONFIG_USB_GADGET=m 1360 1266 # CONFIG_USB_GADGET_DEBUG_FILES is not set 1361 1267 CONFIG_USB_GADGET_SELECTED=y 1268 1268 + # CONFIG_USB_GADGET_FSL_USB2 is not set 1362 1269 # CONFIG_USB_GADGET_NET2280 is not set 1363 1270 # CONFIG_USB_GADGET_PXA2XX is not set 1364 1271 # CONFIG_USB_GADGET_GOKU is not set ··· 1367 1272 # CONFIG_USB_GADGET_OMAP is not set 1368 1273 # CONFIG_USB_GADGET_AT91 is not set 1369 1274 CONFIG_USB_GADGET_DUMMY_HCD=y 1370 1370 - CONFIG_USB_DUMMY_HCD=y 1275 1275 + CONFIG_USB_DUMMY_HCD=m 1371 1276 CONFIG_USB_GADGET_DUALSPEED=y 1372 1277 # CONFIG_USB_ZERO is not set 1373 1373 - CONFIG_USB_ETH=m 1374 1374 - CONFIG_USB_ETH_RNDIS=y 1375 1375 - CONFIG_USB_GADGETFS=m 1376 1376 - CONFIG_USB_FILE_STORAGE=m 1377 1377 - # CONFIG_USB_FILE_STORAGE_TEST is not set 1378 1378 - CONFIG_USB_G_SERIAL=m 1278 1278 + # CONFIG_USB_ETH is not set 1279 1279 + # CONFIG_USB_GADGETFS is not set 1280 1280 + # CONFIG_USB_FILE_STORAGE is not set 1281 1281 + # CONFIG_USB_G_SERIAL is not set 1282 1282 + # CONFIG_USB_MIDI_GADGET is not set 1379 1283 1380 1284 # 1381 1285 # MMC/SD Card support ··· 1389 1295 # 1390 1296 CONFIG_RTC_LIB=y 1391 1297 CONFIG_RTC_CLASS=y 1392 1392 - CONFIG_RTC_HCTOSYS=y 1393 1393 - CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 1298 1298 + # CONFIG_RTC_HCTOSYS is not set 1299 1299 + # CONFIG_RTC_DEBUG is not set 1394 1300 1395 1301 # 1396 1302 # RTC interfaces ··· 1398 1304 CONFIG_RTC_INTF_SYSFS=y 1399 1305 CONFIG_RTC_INTF_PROC=y 1400 1306 CONFIG_RTC_INTF_DEV=y 1307 1307 + # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 1401 1308 1402 1309 # 1403 1310 # RTC drivers 1404 1311 # 1312 1312 + # CONFIG_RTC_DRV_CMOS is not set 1405 1313 # CONFIG_RTC_DRV_X1205 is not set 1314 1314 + # CONFIG_RTC_DRV_DS1307 is not set 1315 1315 + # CONFIG_RTC_DRV_DS1553 is not set 1316 1316 + # CONFIG_RTC_DRV_ISL1208 is not set 1406 1317 # CONFIG_RTC_DRV_DS1672 is not set 1318 1318 + # CONFIG_RTC_DRV_DS1742 is not set 1407 1319 # CONFIG_RTC_DRV_PCF8563 is not set 1320 1320 + CONFIG_RTC_DRV_PCF8583=m 1408 1321 # CONFIG_RTC_DRV_RS5C372 is not set 1409 1322 # CONFIG_RTC_DRV_M48T86 is not set 1410 1323 CONFIG_RTC_DRV_SA1100=y 1411 1324 # CONFIG_RTC_DRV_TEST is not set 1325 1325 + # CONFIG_RTC_DRV_V3020 is not set 1412 1326 1413 1327 # 1414 1328 # File systems ··· 1430 1328 CONFIG_EXT3_FS_XATTR=y 1431 1329 CONFIG_EXT3_FS_POSIX_ACL=y 1432 1330 CONFIG_EXT3_FS_SECURITY=y 1331 1331 + # CONFIG_EXT4DEV_FS is not set 1433 1332 CONFIG_JBD=y 1434 1333 # CONFIG_JBD_DEBUG is not set 1435 1334 CONFIG_FS_MBCACHE=y ··· 1438 1335 # CONFIG_JFS_FS is not set 1439 1336 CONFIG_FS_POSIX_ACL=y 1440 1337 # CONFIG_XFS_FS is not set 1338 1338 + # CONFIG_GFS2_FS is not set 1441 1339 # CONFIG_OCFS2_FS is not set 1442 1340 # CONFIG_MINIX_FS is not set 1443 1341 # CONFIG_ROMFS_FS is not set 1444 1342 CONFIG_INOTIFY=y 1343 1343 + CONFIG_INOTIFY_USER=y 1445 1344 # CONFIG_QUOTA is not set 1446 1345 CONFIG_DNOTIFY=y 1447 1346 # CONFIG_AUTOFS_FS is not set ··· 1470 1365 # Pseudo filesystems 1471 1366 # 1472 1367 CONFIG_PROC_FS=y 1368 1368 + CONFIG_PROC_SYSCTL=y 1473 1369 CONFIG_SYSFS=y 1474 1370 CONFIG_TMPFS=y 1371 1371 + # CONFIG_TMPFS_POSIX_ACL is not set 1475 1372 # CONFIG_HUGETLB_PAGE is not set 1476 1373 CONFIG_RAMFS=y 1477 1374 # CONFIG_CONFIGFS_FS is not set ··· 1483 1376 # 1484 1377 # CONFIG_ADFS_FS is not set 1485 1378 # CONFIG_AFFS_FS is not set 1379 1379 + # CONFIG_ECRYPT_FS is not set 1486 1380 # CONFIG_HFS_FS is not set 1487 1381 # CONFIG_HFSPLUS_FS is not set 1488 1382 # CONFIG_BEFS_FS is not set 1489 1383 # CONFIG_BFS_FS is not set 1490 1384 # CONFIG_EFS_FS is not set 1491 1491 - CONFIG_JFFS_FS=y 1492 1492 - CONFIG_JFFS_FS_VERBOSE=0 1493 1493 - CONFIG_JFFS_PROC_FS=y 1494 1385 CONFIG_JFFS2_FS=y 1495 1386 CONFIG_JFFS2_FS_DEBUG=0 1496 1387 CONFIG_JFFS2_FS_WRITEBUFFER=y 1497 1388 # CONFIG_JFFS2_SUMMARY is not set 1389 1389 + # CONFIG_JFFS2_FS_XATTR is not set 1498 1390 CONFIG_JFFS2_COMPRESSION_OPTIONS=y 1499 1391 CONFIG_JFFS2_ZLIB=y 1500 1392 CONFIG_JFFS2_RTIME=y ··· 1513 1407 # 1514 1408 CONFIG_NFS_FS=y 1515 1409 CONFIG_NFS_V3=y 1516 1516 - CONFIG_NFS_V3_ACL=y 1410 1410 + # CONFIG_NFS_V3_ACL is not set 1517 1411 CONFIG_NFS_V4=y 1518 1412 # CONFIG_NFS_DIRECTIO is not set 1519 1413 CONFIG_NFSD=y 1520 1520 - CONFIG_NFSD_V2_ACL=y 1521 1414 CONFIG_NFSD_V3=y 1522 1522 - CONFIG_NFSD_V3_ACL=y 1415 1415 + # CONFIG_NFSD_V3_ACL is not set 1523 1416 CONFIG_NFSD_V4=y 1524 1417 CONFIG_NFSD_TCP=y 1525 1418 CONFIG_ROOT_NFS=y 1526 1419 CONFIG_LOCKD=y 1527 1420 CONFIG_LOCKD_V4=y 1528 1421 CONFIG_EXPORTFS=y 1529 1529 - CONFIG_NFS_ACL_SUPPORT=y 1530 1422 CONFIG_NFS_COMMON=y 1531 1423 CONFIG_SUNRPC=y 1532 1424 CONFIG_SUNRPC_GSS=y ··· 1534 1430 # CONFIG_SMB_NLS_DEFAULT is not set 1535 1431 CONFIG_CIFS=m 1536 1432 # CONFIG_CIFS_STATS is not set 1433 1433 + # CONFIG_CIFS_WEAK_PW_HASH is not set 1537 1434 # CONFIG_CIFS_XATTR is not set 1435 1435 + # CONFIG_CIFS_DEBUG2 is not set 1538 1436 # CONFIG_CIFS_EXPERIMENTAL is not set 1539 1437 # CONFIG_NCP_FS is not set 1540 1438 # CONFIG_CODA_FS is not set ··· 1610 1504 CONFIG_NLS_UTF8=m 1611 1505 1612 1506 # 1507 1507 + # Distributed Lock Manager 1508 1508 + # 1509 1509 + # CONFIG_DLM is not set 1510 1510 + 1511 1511 + # 1613 1512 # Profiling support 1614 1513 # 1615 1615 - CONFIG_PROFILING=y 1616 1616 - CONFIG_OPROFILE=y 1514 1514 + # CONFIG_PROFILING is not set 1617 1515 1618 1516 # 1619 1517 # Kernel hacking 1620 1518 # 1621 1519 # CONFIG_PRINTK_TIME is not set 1520 1520 + CONFIG_ENABLE_MUST_CHECK=y 1622 1521 CONFIG_MAGIC_SYSRQ=y 1522 1522 + # CONFIG_UNUSED_SYMBOLS is not set 1523 1523 + CONFIG_DEBUG_FS=y 1524 1524 + # CONFIG_HEADERS_CHECK is not set 1623 1525 # CONFIG_DEBUG_KERNEL is not set 1624 1526 CONFIG_LOG_BUF_SHIFT=14 1625 1527 # CONFIG_DEBUG_BUGVERBOSE is not set 1626 1626 - # CONFIG_DEBUG_FS is not set 1627 1528 CONFIG_FRAME_POINTER=y 1628 1628 - # CONFIG_UNWIND_INFO is not set 1629 1529 CONFIG_DEBUG_USER=y 1630 1530 1631 1531 # ··· 1643 1531 # CONFIG_SECURITY_NETWORK is not set 1644 1532 CONFIG_SECURITY_CAPABILITIES=y 1645 1533 # CONFIG_SECURITY_ROOTPLUG is not set 1646 1646 - # CONFIG_SECURITY_SECLVL is not set 1647 1534 1648 1535 # 1649 1536 # Cryptographic options 1650 1537 # 1651 1538 CONFIG_CRYPTO=y 1539 1539 + CONFIG_CRYPTO_ALGAPI=y 1540 1540 + CONFIG_CRYPTO_BLKCIPHER=y 1541 1541 + CONFIG_CRYPTO_MANAGER=y 1652 1542 # CONFIG_CRYPTO_HMAC is not set 1543 1543 + # CONFIG_CRYPTO_XCBC is not set 1653 1544 # CONFIG_CRYPTO_NULL is not set 1654 1654 - CONFIG_CRYPTO_MD4=y 1545 1545 + # CONFIG_CRYPTO_MD4 is not set 1655 1546 CONFIG_CRYPTO_MD5=y 1656 1547 CONFIG_CRYPTO_SHA1=m 1657 1548 CONFIG_CRYPTO_SHA256=m 1658 1549 CONFIG_CRYPTO_SHA512=m 1659 1550 # CONFIG_CRYPTO_WP512 is not set 1660 1551 # CONFIG_CRYPTO_TGR192 is not set 1552 1552 + # CONFIG_CRYPTO_GF128MUL is not set 1553 1553 + CONFIG_CRYPTO_ECB=y 1554 1554 + CONFIG_CRYPTO_CBC=y 1555 1555 + CONFIG_CRYPTO_PCBC=m 1556 1556 + # CONFIG_CRYPTO_LRW is not set 1661 1557 CONFIG_CRYPTO_DES=y 1558 1558 + # CONFIG_CRYPTO_FCRYPT is not set 1662 1559 # CONFIG_CRYPTO_BLOWFISH is not set 1663 1560 # CONFIG_CRYPTO_TWOFISH is not set 1664 1561 # CONFIG_CRYPTO_SERPENT is not set ··· 1675 1554 # CONFIG_CRYPTO_CAST5 is not set 1676 1555 # CONFIG_CRYPTO_CAST6 is not set 1677 1556 # CONFIG_CRYPTO_TEA is not set 1678 1678 - CONFIG_CRYPTO_ARC4=m 1557 1557 + CONFIG_CRYPTO_ARC4=y 1679 1558 # CONFIG_CRYPTO_KHAZAD is not set 1680 1559 # CONFIG_CRYPTO_ANUBIS is not set 1681 1560 CONFIG_CRYPTO_DEFLATE=m 1682 1561 CONFIG_CRYPTO_MICHAEL_MIC=m 1683 1562 CONFIG_CRYPTO_CRC32C=y 1563 1563 + # CONFIG_CRYPTO_CAMELLIA is not set 1684 1564 # CONFIG_CRYPTO_TEST is not set 1685 1565 1686 1566 # ··· 1691 1569 # 1692 1570 # Library routines 1693 1571 # 1572 1572 + CONFIG_BITREVERSE=y 1694 1573 CONFIG_CRC_CCITT=y 1695 1574 CONFIG_CRC16=y 1696 1575 CONFIG_CRC32=y ··· 1700 1577 CONFIG_ZLIB_DEFLATE=y 1701 1578 CONFIG_REED_SOLOMON=y 1702 1579 CONFIG_REED_SOLOMON_DEC16=y 1580 1580 + CONFIG_PLIST=y 1581 1581 + CONFIG_HAS_IOMEM=y 1582 1582 + CONFIG_HAS_IOPORT=y

+1

arch/arm/kernel/armksyms.c

reviewed

··· 76 76 77 77 /* networking */ 78 78 EXPORT_SYMBOL(csum_partial); 79 79 + EXPORT_SYMBOL(csum_partial_copy_from_user); 79 80 EXPORT_SYMBOL(csum_partial_copy_nocheck); 80 81 EXPORT_SYMBOL(__csum_ipv6_magic); 81 82

+34 -1

arch/arm/kernel/ecard.c

reviewed

··· 41 41 #include <linux/init.h> 42 42 #include <linux/mutex.h> 43 43 #include <linux/kthread.h> 44 44 + #include <linux/io.h> 44 45 45 46 #include <asm/dma.h> 46 47 #include <asm/ecard.h> 47 48 #include <asm/hardware.h> 48 48 - #include <asm/io.h> 49 49 #include <asm/irq.h> 50 50 #include <asm/mmu_context.h> 51 51 #include <asm/mach/irq.h> ··· 958 958 } 959 959 EXPORT_SYMBOL(ecard_release_resources); 960 960 961 961 + void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data) 962 962 + { 963 963 + ec->irq_data = irq_data; 964 964 + barrier(); 965 965 + ec->ops = ops; 966 966 + } 967 967 + EXPORT_SYMBOL(ecard_setirq); 968 968 + 969 969 + void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, 970 970 + unsigned long offset, unsigned long maxsize) 971 971 + { 972 972 + unsigned long start = ecard_resource_start(ec, res); 973 973 + unsigned long end = ecard_resource_end(ec, res); 974 974 + 975 975 + if (offset > (end - start)) 976 976 + return NULL; 977 977 + 978 978 + start += offset; 979 979 + if (maxsize && end - start > maxsize) 980 980 + end = start + maxsize; 981 981 + 982 982 + return devm_ioremap(&ec->dev, start, end - start); 983 983 + } 984 984 + EXPORT_SYMBOL(ecardm_iomap); 985 985 + 961 986 /* 962 987 * Probe for an expansion card. 963 988 * ··· 1157 1132 1158 1133 drv->remove(ec); 1159 1134 ecard_release(ec); 1135 1135 + 1136 1136 + /* 1137 1137 + * Restore the default operations. We ensure that the 1138 1138 + * ops are set before we change the data. 1139 1139 + */ 1140 1140 + ec->ops = &ecard_default_ops; 1141 1141 + barrier(); 1142 1142 + ec->irq_data = NULL; 1160 1143 1161 1144 return 0; 1162 1145 }

+3 -9

arch/arm/kernel/stacktrace.c

reviewed

··· 52 52 return trace->nr_entries >= trace->max_entries; 53 53 } 54 54 55 55 - void save_stack_trace(struct stack_trace *trace, struct task_struct *task) 55 55 + void save_stack_trace(struct stack_trace *trace) 56 56 { 57 57 struct stack_trace_data data; 58 58 unsigned long fp, base; 59 59 60 60 data.trace = trace; 61 61 data.skip = trace->skip; 62 62 - 63 63 - if (task) { 64 64 - base = (unsigned long)task_stack_page(task); 65 65 - fp = 0; /* FIXME */ 66 66 - } else { 67 67 - base = (unsigned long)task_stack_page(current); 68 68 - asm("mov %0, fp" : "=r" (fp)); 69 69 - } 62 62 + base = (unsigned long)task_stack_page(current); 63 63 + asm("mov %0, fp" : "=r" (fp)); 70 64 71 65 walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data); 72 66 }

+1 -1

arch/arm/kernel/time.c

reviewed

··· 512 512 513 513 #ifdef CONFIG_NO_IDLE_HZ 514 514 if (system_timer->dyn_tick) 515 515 - system_timer->dyn_tick->lock = SPIN_LOCK_UNLOCKED; 515 515 + spin_lock_init(&system_timer->dyn_tick->lock); 516 516 #endif 517 517 } 518 518

+17

arch/arm/mach-at91/Kconfig

reviewed

··· 17 17 config ARCH_AT91SAM9263 18 18 bool "AT91SAM9263" 19 19 20 20 + config ARCH_AT91SAM9RL 21 21 + bool "AT91SAM9RL" 22 22 + 20 23 endchoice 21 24 22 25 # ---------------------------------------------------------- ··· 150 147 help 151 148 Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. 152 149 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> 150 150 + 151 151 + endif 152 152 + 153 153 + # ---------------------------------------------------------- 154 154 + 155 155 + if ARCH_AT91SAM9RL 156 156 + 157 157 + comment "AT91SAM9RL Board Type" 158 158 + 159 159 + config MACH_AT91SAM9RLEK 160 160 + bool "Atmel AT91SAM9RL-EK Evaluation Kit" 161 161 + depends on ARCH_AT91SAM9RL 162 162 + help 163 163 + Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. 153 164 154 165 endif 155 166

+5

arch/arm/mach-at91/Makefile

reviewed

··· 14 14 obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o 15 15 obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o 16 16 obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o 17 17 + obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o 17 18 18 19 # AT91RM9200 board-specific support 19 20 obj-$(CONFIG_MACH_ONEARM) += board-1arm.o ··· 37 36 # AT91SAM9263 board-specific support 38 37 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o 39 38 39 39 + # AT91SAM9RL board-specific support 40 40 + obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o 41 41 + 40 42 # LEDs support 41 43 led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o 42 44 led-$(CONFIG_MACH_AT91RM9200EK) += leds.o 45 45 + led-$(CONFIG_MACH_AT91SAM9261EK)+= leds.o 43 46 led-$(CONFIG_MACH_CSB337) += leds.o 44 47 led-$(CONFIG_MACH_CSB637) += leds.o 45 48 led-$(CONFIG_MACH_KB9200) += leds.o

-3

arch/arm/mach-at91/at91rm9200_devices.c

reviewed

··· 22 22 23 23 #include "generic.h" 24 24 25 25 - #define SZ_512 0x00000200 26 26 - #define SZ_256 0x00000100 27 27 - #define SZ_16 0x00000010 28 25 29 26 /* -------------------------------------------------------------------- 30 27 * USB Host

-3

arch/arm/mach-at91/at91sam9260_devices.c

reviewed

··· 22 22 23 23 #include "generic.h" 24 24 25 25 - #define SZ_512 0x00000200 26 26 - #define SZ_256 0x00000100 27 27 - #define SZ_16 0x00000010 28 25 29 26 /* -------------------------------------------------------------------- 30 27 * USB Host

-3

arch/arm/mach-at91/at91sam9261_devices.c

reviewed

··· 23 23 24 24 #include "generic.h" 25 25 26 26 - #define SZ_512 0x00000200 27 27 - #define SZ_256 0x00000100 28 28 - #define SZ_16 0x00000010 29 26 30 27 /* -------------------------------------------------------------------- 31 28 * USB Host

-3

arch/arm/mach-at91/at91sam9263_devices.c

reviewed

··· 22 22 23 23 #include "generic.h" 24 24 25 25 - #define SZ_512 0x00000200 26 26 - #define SZ_256 0x00000100 27 27 - #define SZ_16 0x00000010 28 25 29 26 /* -------------------------------------------------------------------- 30 27 * USB Host

+341

arch/arm/mach-at91/at91sam9rl.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-at91/at91sam9rl.c 3 3 + * 4 4 + * Copyright (C) 2005 SAN People 5 5 + * Copyright (C) 2007 Atmel Corporation 6 6 + * 7 7 + * This file is subject to the terms and conditions of the GNU General Public 8 8 + * License. See the file COPYING in the main directory of this archive for 9 9 + * more details. 10 10 + */ 11 11 + 12 12 + #include <linux/module.h> 13 13 + 14 14 + #include <asm/mach/arch.h> 15 15 + #include <asm/mach/map.h> 16 16 + #include <asm/arch/cpu.h> 17 17 + #include <asm/arch/at91sam9rl.h> 18 18 + #include <asm/arch/at91_pmc.h> 19 19 + #include <asm/arch/at91_rstc.h> 20 20 + 21 21 + #include "generic.h" 22 22 + #include "clock.h" 23 23 + 24 24 + static struct map_desc at91sam9rl_io_desc[] __initdata = { 25 25 + { 26 26 + .virtual = AT91_VA_BASE_SYS, 27 27 + .pfn = __phys_to_pfn(AT91_BASE_SYS), 28 28 + .length = SZ_16K, 29 29 + .type = MT_DEVICE, 30 30 + }, 31 31 + }; 32 32 + 33 33 + static struct map_desc at91sam9rl_sram_desc[] __initdata = { 34 34 + { 35 35 + .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE), 36 36 + .type = MT_DEVICE, 37 37 + } 38 38 + }; 39 39 + 40 40 + /* -------------------------------------------------------------------- 41 41 + * Clocks 42 42 + * -------------------------------------------------------------------- */ 43 43 + 44 44 + /* 45 45 + * The peripheral clocks. 46 46 + */ 47 47 + static struct clk pioA_clk = { 48 48 + .name = "pioA_clk", 49 49 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOA, 50 50 + .type = CLK_TYPE_PERIPHERAL, 51 51 + }; 52 52 + static struct clk pioB_clk = { 53 53 + .name = "pioB_clk", 54 54 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOB, 55 55 + .type = CLK_TYPE_PERIPHERAL, 56 56 + }; 57 57 + static struct clk pioC_clk = { 58 58 + .name = "pioC_clk", 59 59 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOC, 60 60 + .type = CLK_TYPE_PERIPHERAL, 61 61 + }; 62 62 + static struct clk pioD_clk = { 63 63 + .name = "pioD_clk", 64 64 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOD, 65 65 + .type = CLK_TYPE_PERIPHERAL, 66 66 + }; 67 67 + static struct clk usart0_clk = { 68 68 + .name = "usart0_clk", 69 69 + .pmc_mask = 1 << AT91SAM9RL_ID_US0, 70 70 + .type = CLK_TYPE_PERIPHERAL, 71 71 + }; 72 72 + static struct clk usart1_clk = { 73 73 + .name = "usart1_clk", 74 74 + .pmc_mask = 1 << AT91SAM9RL_ID_US1, 75 75 + .type = CLK_TYPE_PERIPHERAL, 76 76 + }; 77 77 + static struct clk usart2_clk = { 78 78 + .name = "usart2_clk", 79 79 + .pmc_mask = 1 << AT91SAM9RL_ID_US2, 80 80 + .type = CLK_TYPE_PERIPHERAL, 81 81 + }; 82 82 + static struct clk usart3_clk = { 83 83 + .name = "usart3_clk", 84 84 + .pmc_mask = 1 << AT91SAM9RL_ID_US3, 85 85 + .type = CLK_TYPE_PERIPHERAL, 86 86 + }; 87 87 + static struct clk mmc_clk = { 88 88 + .name = "mci_clk", 89 89 + .pmc_mask = 1 << AT91SAM9RL_ID_MCI, 90 90 + .type = CLK_TYPE_PERIPHERAL, 91 91 + }; 92 92 + static struct clk twi0_clk = { 93 93 + .name = "twi0_clk", 94 94 + .pmc_mask = 1 << AT91SAM9RL_ID_TWI0, 95 95 + .type = CLK_TYPE_PERIPHERAL, 96 96 + }; 97 97 + static struct clk twi1_clk = { 98 98 + .name = "twi1_clk", 99 99 + .pmc_mask = 1 << AT91SAM9RL_ID_TWI1, 100 100 + .type = CLK_TYPE_PERIPHERAL, 101 101 + }; 102 102 + static struct clk spi_clk = { 103 103 + .name = "spi_clk", 104 104 + .pmc_mask = 1 << AT91SAM9RL_ID_SPI, 105 105 + .type = CLK_TYPE_PERIPHERAL, 106 106 + }; 107 107 + static struct clk ssc0_clk = { 108 108 + .name = "ssc0_clk", 109 109 + .pmc_mask = 1 << AT91SAM9RL_ID_SSC0, 110 110 + .type = CLK_TYPE_PERIPHERAL, 111 111 + }; 112 112 + static struct clk ssc1_clk = { 113 113 + .name = "ssc1_clk", 114 114 + .pmc_mask = 1 << AT91SAM9RL_ID_SSC1, 115 115 + .type = CLK_TYPE_PERIPHERAL, 116 116 + }; 117 117 + static struct clk tc0_clk = { 118 118 + .name = "tc0_clk", 119 119 + .pmc_mask = 1 << AT91SAM9RL_ID_TC0, 120 120 + .type = CLK_TYPE_PERIPHERAL, 121 121 + }; 122 122 + static struct clk tc1_clk = { 123 123 + .name = "tc1_clk", 124 124 + .pmc_mask = 1 << AT91SAM9RL_ID_TC1, 125 125 + .type = CLK_TYPE_PERIPHERAL, 126 126 + }; 127 127 + static struct clk tc2_clk = { 128 128 + .name = "tc2_clk", 129 129 + .pmc_mask = 1 << AT91SAM9RL_ID_TC2, 130 130 + .type = CLK_TYPE_PERIPHERAL, 131 131 + }; 132 132 + static struct clk pwmc_clk = { 133 133 + .name = "pwmc_clk", 134 134 + .pmc_mask = 1 << AT91SAM9RL_ID_PWMC, 135 135 + .type = CLK_TYPE_PERIPHERAL, 136 136 + }; 137 137 + static struct clk tsc_clk = { 138 138 + .name = "tsc_clk", 139 139 + .pmc_mask = 1 << AT91SAM9RL_ID_TSC, 140 140 + .type = CLK_TYPE_PERIPHERAL, 141 141 + }; 142 142 + static struct clk dma_clk = { 143 143 + .name = "dma_clk", 144 144 + .pmc_mask = 1 << AT91SAM9RL_ID_DMA, 145 145 + .type = CLK_TYPE_PERIPHERAL, 146 146 + }; 147 147 + static struct clk udphs_clk = { 148 148 + .name = "udphs_clk", 149 149 + .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS, 150 150 + .type = CLK_TYPE_PERIPHERAL, 151 151 + }; 152 152 + static struct clk lcdc_clk = { 153 153 + .name = "lcdc_clk", 154 154 + .pmc_mask = 1 << AT91SAM9RL_ID_LCDC, 155 155 + .type = CLK_TYPE_PERIPHERAL, 156 156 + }; 157 157 + static struct clk ac97_clk = { 158 158 + .name = "ac97_clk", 159 159 + .pmc_mask = 1 << AT91SAM9RL_ID_AC97C, 160 160 + .type = CLK_TYPE_PERIPHERAL, 161 161 + }; 162 162 + 163 163 + static struct clk *periph_clocks[] __initdata = { 164 164 + &pioA_clk, 165 165 + &pioB_clk, 166 166 + &pioC_clk, 167 167 + &pioD_clk, 168 168 + &usart0_clk, 169 169 + &usart1_clk, 170 170 + &usart2_clk, 171 171 + &usart3_clk, 172 172 + &mmc_clk, 173 173 + &twi0_clk, 174 174 + &twi1_clk, 175 175 + &spi_clk, 176 176 + &ssc0_clk, 177 177 + &ssc1_clk, 178 178 + &tc0_clk, 179 179 + &tc1_clk, 180 180 + &tc2_clk, 181 181 + &pwmc_clk, 182 182 + &tsc_clk, 183 183 + &dma_clk, 184 184 + &udphs_clk, 185 185 + &lcdc_clk, 186 186 + &ac97_clk, 187 187 + // irq0 188 188 + }; 189 189 + 190 190 + /* 191 191 + * The two programmable clocks. 192 192 + * You must configure pin multiplexing to bring these signals out. 193 193 + */ 194 194 + static struct clk pck0 = { 195 195 + .name = "pck0", 196 196 + .pmc_mask = AT91_PMC_PCK0, 197 197 + .type = CLK_TYPE_PROGRAMMABLE, 198 198 + .id = 0, 199 199 + }; 200 200 + static struct clk pck1 = { 201 201 + .name = "pck1", 202 202 + .pmc_mask = AT91_PMC_PCK1, 203 203 + .type = CLK_TYPE_PROGRAMMABLE, 204 204 + .id = 1, 205 205 + }; 206 206 + 207 207 + static void __init at91sam9rl_register_clocks(void) 208 208 + { 209 209 + int i; 210 210 + 211 211 + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) 212 212 + clk_register(periph_clocks[i]); 213 213 + 214 214 + clk_register(&pck0); 215 215 + clk_register(&pck1); 216 216 + } 217 217 + 218 218 + /* -------------------------------------------------------------------- 219 219 + * GPIO 220 220 + * -------------------------------------------------------------------- */ 221 221 + 222 222 + static struct at91_gpio_bank at91sam9rl_gpio[] = { 223 223 + { 224 224 + .id = AT91SAM9RL_ID_PIOA, 225 225 + .offset = AT91_PIOA, 226 226 + .clock = &pioA_clk, 227 227 + }, { 228 228 + .id = AT91SAM9RL_ID_PIOB, 229 229 + .offset = AT91_PIOB, 230 230 + .clock = &pioB_clk, 231 231 + }, { 232 232 + .id = AT91SAM9RL_ID_PIOC, 233 233 + .offset = AT91_PIOC, 234 234 + .clock = &pioC_clk, 235 235 + }, { 236 236 + .id = AT91SAM9RL_ID_PIOD, 237 237 + .offset = AT91_PIOD, 238 238 + .clock = &pioD_clk, 239 239 + } 240 240 + }; 241 241 + 242 242 + static void at91sam9rl_reset(void) 243 243 + { 244 244 + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); 245 245 + } 246 246 + 247 247 + 248 248 + /* -------------------------------------------------------------------- 249 249 + * AT91SAM9RL processor initialization 250 250 + * -------------------------------------------------------------------- */ 251 251 + 252 252 + void __init at91sam9rl_initialize(unsigned long main_clock) 253 253 + { 254 254 + unsigned long cidr, sram_size; 255 255 + 256 256 + /* Map peripherals */ 257 257 + iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc)); 258 258 + 259 259 + cidr = at91_sys_read(AT91_DBGU_CIDR); 260 260 + 261 261 + switch (cidr & AT91_CIDR_SRAMSIZ) { 262 262 + case AT91_CIDR_SRAMSIZ_32K: 263 263 + sram_size = 2 * SZ_16K; 264 264 + break; 265 265 + case AT91_CIDR_SRAMSIZ_16K: 266 266 + default: 267 267 + sram_size = SZ_16K; 268 268 + } 269 269 + 270 270 + at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; 271 271 + at91sam9rl_sram_desc->length = sram_size; 272 272 + 273 273 + /* Map SRAM */ 274 274 + iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); 275 275 + 276 276 + at91_arch_reset = at91sam9rl_reset; 277 277 + at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); 278 278 + 279 279 + /* Init clock subsystem */ 280 280 + at91_clock_init(main_clock); 281 281 + 282 282 + /* Register the processor-specific clocks */ 283 283 + at91sam9rl_register_clocks(); 284 284 + 285 285 + /* Register GPIO subsystem */ 286 286 + at91_gpio_init(at91sam9rl_gpio, 4); 287 287 + } 288 288 + 289 289 + /* -------------------------------------------------------------------- 290 290 + * Interrupt initialization 291 291 + * -------------------------------------------------------------------- */ 292 292 + 293 293 + /* 294 294 + * The default interrupt priority levels (0 = lowest, 7 = highest). 295 295 + */ 296 296 + static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { 297 297 + 7, /* Advanced Interrupt Controller */ 298 298 + 7, /* System Peripherals */ 299 299 + 1, /* Parallel IO Controller A */ 300 300 + 1, /* Parallel IO Controller B */ 301 301 + 1, /* Parallel IO Controller C */ 302 302 + 1, /* Parallel IO Controller D */ 303 303 + 5, /* USART 0 */ 304 304 + 5, /* USART 1 */ 305 305 + 5, /* USART 2 */ 306 306 + 5, /* USART 3 */ 307 307 + 0, /* Multimedia Card Interface */ 308 308 + 6, /* Two-Wire Interface 0 */ 309 309 + 6, /* Two-Wire Interface 1 */ 310 310 + 5, /* Serial Peripheral Interface */ 311 311 + 4, /* Serial Synchronous Controller 0 */ 312 312 + 4, /* Serial Synchronous Controller 1 */ 313 313 + 0, /* Timer Counter 0 */ 314 314 + 0, /* Timer Counter 1 */ 315 315 + 0, /* Timer Counter 2 */ 316 316 + 0, 317 317 + 0, /* Touch Screen Controller */ 318 318 + 0, /* DMA Controller */ 319 319 + 2, /* USB Device High speed port */ 320 320 + 2, /* LCD Controller */ 321 321 + 6, /* AC97 Controller */ 322 322 + 0, 323 323 + 0, 324 324 + 0, 325 325 + 0, 326 326 + 0, 327 327 + 0, 328 328 + 0, /* Advanced Interrupt Controller */ 329 329 + }; 330 330 + 331 331 + void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS]) 332 332 + { 333 333 + if (!priority) 334 334 + priority = at91sam9rl_default_irq_priority; 335 335 + 336 336 + /* Initialize the AIC interrupt controller */ 337 337 + at91_aic_init(priority); 338 338 + 339 339 + /* Enable GPIO interrupts */ 340 340 + at91_gpio_irq_setup(); 341 341 + }

+630

arch/arm/mach-at91/at91sam9rl_devices.c

reviewed

··· 1 1 + /* 2 2 + * Copyright (C) 2007 Atmel Corporation 3 3 + * 4 4 + * This file is subject to the terms and conditions of the GNU General Public 5 5 + * License. See the file COPYING in the main directory of this archive for 6 6 + * more details. 7 7 + */ 8 8 + 9 9 + #include <asm/mach/arch.h> 10 10 + #include <asm/mach/map.h> 11 11 + 12 12 + #include <linux/platform_device.h> 13 13 + #include <linux/fb.h> 14 14 + 15 15 + #include <video/atmel_lcdc.h> 16 16 + 17 17 + #include <asm/arch/board.h> 18 18 + #include <asm/arch/gpio.h> 19 19 + #include <asm/arch/at91sam9rl.h> 20 20 + #include <asm/arch/at91sam9rl_matrix.h> 21 21 + #include <asm/arch/at91sam926x_mc.h> 22 22 + 23 23 + #include "generic.h" 24 24 + 25 25 + 26 26 + /* -------------------------------------------------------------------- 27 27 + * MMC / SD 28 28 + * -------------------------------------------------------------------- */ 29 29 + 30 30 + #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) 31 31 + static u64 mmc_dmamask = 0xffffffffUL; 32 32 + static struct at91_mmc_data mmc_data; 33 33 + 34 34 + static struct resource mmc_resources[] = { 35 35 + [0] = { 36 36 + .start = AT91SAM9RL_BASE_MCI, 37 37 + .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1, 38 38 + .flags = IORESOURCE_MEM, 39 39 + }, 40 40 + [1] = { 41 41 + .start = AT91SAM9RL_ID_MCI, 42 42 + .end = AT91SAM9RL_ID_MCI, 43 43 + .flags = IORESOURCE_IRQ, 44 44 + }, 45 45 + }; 46 46 + 47 47 + static struct platform_device at91sam9rl_mmc_device = { 48 48 + .name = "at91_mci", 49 49 + .id = -1, 50 50 + .dev = { 51 51 + .dma_mask = &mmc_dmamask, 52 52 + .coherent_dma_mask = 0xffffffff, 53 53 + .platform_data = &mmc_data, 54 54 + }, 55 55 + .resource = mmc_resources, 56 56 + .num_resources = ARRAY_SIZE(mmc_resources), 57 57 + }; 58 58 + 59 59 + void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) 60 60 + { 61 61 + if (!data) 62 62 + return; 63 63 + 64 64 + /* input/irq */ 65 65 + if (data->det_pin) { 66 66 + at91_set_gpio_input(data->det_pin, 1); 67 67 + at91_set_deglitch(data->det_pin, 1); 68 68 + } 69 69 + if (data->wp_pin) 70 70 + at91_set_gpio_input(data->wp_pin, 1); 71 71 + if (data->vcc_pin) 72 72 + at91_set_gpio_output(data->vcc_pin, 0); 73 73 + 74 74 + /* CLK */ 75 75 + at91_set_A_periph(AT91_PIN_PA2, 0); 76 76 + 77 77 + /* CMD */ 78 78 + at91_set_A_periph(AT91_PIN_PA1, 1); 79 79 + 80 80 + /* DAT0, maybe DAT1..DAT3 */ 81 81 + at91_set_A_periph(AT91_PIN_PA0, 1); 82 82 + if (data->wire4) { 83 83 + at91_set_A_periph(AT91_PIN_PA3, 1); 84 84 + at91_set_A_periph(AT91_PIN_PA4, 1); 85 85 + at91_set_A_periph(AT91_PIN_PA5, 1); 86 86 + } 87 87 + 88 88 + mmc_data = *data; 89 89 + platform_device_register(&at91sam9rl_mmc_device); 90 90 + } 91 91 + #else 92 92 + void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 93 93 + #endif 94 94 + 95 95 + 96 96 + /* -------------------------------------------------------------------- 97 97 + * NAND / SmartMedia 98 98 + * -------------------------------------------------------------------- */ 99 99 + 100 100 + #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) 101 101 + static struct at91_nand_data nand_data; 102 102 + 103 103 + #define NAND_BASE AT91_CHIPSELECT_3 104 104 + 105 105 + static struct resource nand_resources[] = { 106 106 + { 107 107 + .start = NAND_BASE, 108 108 + .end = NAND_BASE + SZ_256M - 1, 109 109 + .flags = IORESOURCE_MEM, 110 110 + } 111 111 + }; 112 112 + 113 113 + static struct platform_device at91_nand_device = { 114 114 + .name = "at91_nand", 115 115 + .id = -1, 116 116 + .dev = { 117 117 + .platform_data = &nand_data, 118 118 + }, 119 119 + .resource = nand_resources, 120 120 + .num_resources = ARRAY_SIZE(nand_resources), 121 121 + }; 122 122 + 123 123 + void __init at91_add_device_nand(struct at91_nand_data *data) 124 124 + { 125 125 + unsigned long csa; 126 126 + 127 127 + if (!data) 128 128 + return; 129 129 + 130 130 + csa = at91_sys_read(AT91_MATRIX_EBICSA); 131 131 + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 132 132 + 133 133 + /* set the bus interface characteristics */ 134 134 + at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) 135 135 + | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 136 136 + 137 137 + at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) 138 138 + | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); 139 139 + 140 140 + at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); 141 141 + 142 142 + at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); 143 143 + 144 144 + /* enable pin */ 145 145 + if (data->enable_pin) 146 146 + at91_set_gpio_output(data->enable_pin, 1); 147 147 + 148 148 + /* ready/busy pin */ 149 149 + if (data->rdy_pin) 150 150 + at91_set_gpio_input(data->rdy_pin, 1); 151 151 + 152 152 + /* card detect pin */ 153 153 + if (data->det_pin) 154 154 + at91_set_gpio_input(data->det_pin, 1); 155 155 + 156 156 + at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ 157 157 + at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ 158 158 + 159 159 + nand_data = *data; 160 160 + platform_device_register(&at91_nand_device); 161 161 + } 162 162 + 163 163 + #else 164 164 + void __init at91_add_device_nand(struct at91_nand_data *data) {} 165 165 + #endif 166 166 + 167 167 + 168 168 + /* -------------------------------------------------------------------- 169 169 + * TWI (i2c) 170 170 + * -------------------------------------------------------------------- */ 171 171 + 172 172 + #if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 173 173 + 174 174 + static struct resource twi_resources[] = { 175 175 + [0] = { 176 176 + .start = AT91SAM9RL_BASE_TWI0, 177 177 + .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1, 178 178 + .flags = IORESOURCE_MEM, 179 179 + }, 180 180 + [1] = { 181 181 + .start = AT91SAM9RL_ID_TWI0, 182 182 + .end = AT91SAM9RL_ID_TWI0, 183 183 + .flags = IORESOURCE_IRQ, 184 184 + }, 185 185 + }; 186 186 + 187 187 + static struct platform_device at91sam9rl_twi_device = { 188 188 + .name = "at91_i2c", 189 189 + .id = -1, 190 190 + .resource = twi_resources, 191 191 + .num_resources = ARRAY_SIZE(twi_resources), 192 192 + }; 193 193 + 194 194 + void __init at91_add_device_i2c(void) 195 195 + { 196 196 + /* pins used for TWI interface */ 197 197 + at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ 198 198 + at91_set_multi_drive(AT91_PIN_PA23, 1); 199 199 + 200 200 + at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */ 201 201 + at91_set_multi_drive(AT91_PIN_PA24, 1); 202 202 + 203 203 + platform_device_register(&at91sam9rl_twi_device); 204 204 + } 205 205 + #else 206 206 + void __init at91_add_device_i2c(void) {} 207 207 + #endif 208 208 + 209 209 + 210 210 + /* -------------------------------------------------------------------- 211 211 + * SPI 212 212 + * -------------------------------------------------------------------- */ 213 213 + 214 214 + #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) 215 215 + static u64 spi_dmamask = 0xffffffffUL; 216 216 + 217 217 + static struct resource spi_resources[] = { 218 218 + [0] = { 219 219 + .start = AT91SAM9RL_BASE_SPI, 220 220 + .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1, 221 221 + .flags = IORESOURCE_MEM, 222 222 + }, 223 223 + [1] = { 224 224 + .start = AT91SAM9RL_ID_SPI, 225 225 + .end = AT91SAM9RL_ID_SPI, 226 226 + .flags = IORESOURCE_IRQ, 227 227 + }, 228 228 + }; 229 229 + 230 230 + static struct platform_device at91sam9rl_spi_device = { 231 231 + .name = "atmel_spi", 232 232 + .id = 0, 233 233 + .dev = { 234 234 + .dma_mask = &spi_dmamask, 235 235 + .coherent_dma_mask = 0xffffffff, 236 236 + }, 237 237 + .resource = spi_resources, 238 238 + .num_resources = ARRAY_SIZE(spi_resources), 239 239 + }; 240 240 + 241 241 + static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 }; 242 242 + 243 243 + 244 244 + void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 245 245 + { 246 246 + int i; 247 247 + unsigned long cs_pin; 248 248 + 249 249 + at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */ 250 250 + at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */ 251 251 + at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */ 252 252 + 253 253 + /* Enable SPI chip-selects */ 254 254 + for (i = 0; i < nr_devices; i++) { 255 255 + if (devices[i].controller_data) 256 256 + cs_pin = (unsigned long) devices[i].controller_data; 257 257 + else 258 258 + cs_pin = spi_standard_cs[devices[i].chip_select]; 259 259 + 260 260 + /* enable chip-select pin */ 261 261 + at91_set_gpio_output(cs_pin, 1); 262 262 + 263 263 + /* pass chip-select pin to driver */ 264 264 + devices[i].controller_data = (void *) cs_pin; 265 265 + } 266 266 + 267 267 + spi_register_board_info(devices, nr_devices); 268 268 + platform_device_register(&at91sam9rl_spi_device); 269 269 + } 270 270 + #else 271 271 + void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} 272 272 + #endif 273 273 + 274 274 + 275 275 + /* -------------------------------------------------------------------- 276 276 + * LCD Controller 277 277 + * -------------------------------------------------------------------- */ 278 278 + 279 279 + #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) 280 280 + static u64 lcdc_dmamask = 0xffffffffUL; 281 281 + static struct atmel_lcdfb_info lcdc_data; 282 282 + 283 283 + static struct resource lcdc_resources[] = { 284 284 + [0] = { 285 285 + .start = AT91SAM9RL_LCDC_BASE, 286 286 + .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1, 287 287 + .flags = IORESOURCE_MEM, 288 288 + }, 289 289 + [1] = { 290 290 + .start = AT91SAM9RL_ID_LCDC, 291 291 + .end = AT91SAM9RL_ID_LCDC, 292 292 + .flags = IORESOURCE_IRQ, 293 293 + }, 294 294 + #if defined(CONFIG_FB_INTSRAM) 295 295 + [2] = { 296 296 + .start = AT91SAM9RL_SRAM_BASE, 297 297 + .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1, 298 298 + .flags = IORESOURCE_MEM, 299 299 + }, 300 300 + #endif 301 301 + }; 302 302 + 303 303 + static struct platform_device at91_lcdc_device = { 304 304 + .name = "atmel_lcdfb", 305 305 + .id = 0, 306 306 + .dev = { 307 307 + .dma_mask = &lcdc_dmamask, 308 308 + .coherent_dma_mask = 0xffffffff, 309 309 + .platform_data = &lcdc_data, 310 310 + }, 311 311 + .resource = lcdc_resources, 312 312 + .num_resources = ARRAY_SIZE(lcdc_resources), 313 313 + }; 314 314 + 315 315 + void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) 316 316 + { 317 317 + if (!data) { 318 318 + return; 319 319 + } 320 320 + 321 321 + at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ 322 322 + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ 323 323 + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ 324 324 + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ 325 325 + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ 326 326 + at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ 327 327 + at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ 328 328 + at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ 329 329 + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ 330 330 + at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ 331 331 + at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ 332 332 + at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ 333 333 + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ 334 334 + at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ 335 335 + at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ 336 336 + at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ 337 337 + at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ 338 338 + at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ 339 339 + at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ 340 340 + at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ 341 341 + at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ 342 342 + 343 343 + lcdc_data = *data; 344 344 + platform_device_register(&at91_lcdc_device); 345 345 + } 346 346 + #else 347 347 + void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} 348 348 + #endif 349 349 + 350 350 + 351 351 + /* -------------------------------------------------------------------- 352 352 + * LEDs 353 353 + * -------------------------------------------------------------------- */ 354 354 + 355 355 + #if defined(CONFIG_LEDS) 356 356 + u8 at91_leds_cpu; 357 357 + u8 at91_leds_timer; 358 358 + 359 359 + void __init at91_init_leds(u8 cpu_led, u8 timer_led) 360 360 + { 361 361 + /* Enable GPIO to access the LEDs */ 362 362 + at91_set_gpio_output(cpu_led, 1); 363 363 + at91_set_gpio_output(timer_led, 1); 364 364 + 365 365 + at91_leds_cpu = cpu_led; 366 366 + at91_leds_timer = timer_led; 367 367 + } 368 368 + #else 369 369 + void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} 370 370 + #endif 371 371 + 372 372 + 373 373 + /* -------------------------------------------------------------------- 374 374 + * UART 375 375 + * -------------------------------------------------------------------- */ 376 376 + 377 377 + #if defined(CONFIG_SERIAL_ATMEL) 378 378 + static struct resource dbgu_resources[] = { 379 379 + [0] = { 380 380 + .start = AT91_VA_BASE_SYS + AT91_DBGU, 381 381 + .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, 382 382 + .flags = IORESOURCE_MEM, 383 383 + }, 384 384 + [1] = { 385 385 + .start = AT91_ID_SYS, 386 386 + .end = AT91_ID_SYS, 387 387 + .flags = IORESOURCE_IRQ, 388 388 + }, 389 389 + }; 390 390 + 391 391 + static struct atmel_uart_data dbgu_data = { 392 392 + .use_dma_tx = 0, 393 393 + .use_dma_rx = 0, /* DBGU not capable of receive DMA */ 394 394 + .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), 395 395 + }; 396 396 + 397 397 + static struct platform_device at91sam9rl_dbgu_device = { 398 398 + .name = "atmel_usart", 399 399 + .id = 0, 400 400 + .dev = { 401 401 + .platform_data = &dbgu_data, 402 402 + .coherent_dma_mask = 0xffffffff, 403 403 + }, 404 404 + .resource = dbgu_resources, 405 405 + .num_resources = ARRAY_SIZE(dbgu_resources), 406 406 + }; 407 407 + 408 408 + static inline void configure_dbgu_pins(void) 409 409 + { 410 410 + at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ 411 411 + at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ 412 412 + } 413 413 + 414 414 + static struct resource uart0_resources[] = { 415 415 + [0] = { 416 416 + .start = AT91SAM9RL_BASE_US0, 417 417 + .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1, 418 418 + .flags = IORESOURCE_MEM, 419 419 + }, 420 420 + [1] = { 421 421 + .start = AT91SAM9RL_ID_US0, 422 422 + .end = AT91SAM9RL_ID_US0, 423 423 + .flags = IORESOURCE_IRQ, 424 424 + }, 425 425 + }; 426 426 + 427 427 + static struct atmel_uart_data uart0_data = { 428 428 + .use_dma_tx = 1, 429 429 + .use_dma_rx = 1, 430 430 + }; 431 431 + 432 432 + static struct platform_device at91sam9rl_uart0_device = { 433 433 + .name = "atmel_usart", 434 434 + .id = 1, 435 435 + .dev = { 436 436 + .platform_data = &uart0_data, 437 437 + .coherent_dma_mask = 0xffffffff, 438 438 + }, 439 439 + .resource = uart0_resources, 440 440 + .num_resources = ARRAY_SIZE(uart0_resources), 441 441 + }; 442 442 + 443 443 + static inline void configure_usart0_pins(void) 444 444 + { 445 445 + at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ 446 446 + at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ 447 447 + at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */ 448 448 + at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */ 449 449 + } 450 450 + 451 451 + static struct resource uart1_resources[] = { 452 452 + [0] = { 453 453 + .start = AT91SAM9RL_BASE_US1, 454 454 + .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1, 455 455 + .flags = IORESOURCE_MEM, 456 456 + }, 457 457 + [1] = { 458 458 + .start = AT91SAM9RL_ID_US1, 459 459 + .end = AT91SAM9RL_ID_US1, 460 460 + .flags = IORESOURCE_IRQ, 461 461 + }, 462 462 + }; 463 463 + 464 464 + static struct atmel_uart_data uart1_data = { 465 465 + .use_dma_tx = 1, 466 466 + .use_dma_rx = 1, 467 467 + }; 468 468 + 469 469 + static struct platform_device at91sam9rl_uart1_device = { 470 470 + .name = "atmel_usart", 471 471 + .id = 2, 472 472 + .dev = { 473 473 + .platform_data = &uart1_data, 474 474 + .coherent_dma_mask = 0xffffffff, 475 475 + }, 476 476 + .resource = uart1_resources, 477 477 + .num_resources = ARRAY_SIZE(uart1_resources), 478 478 + }; 479 479 + 480 480 + static inline void configure_usart1_pins(void) 481 481 + { 482 482 + at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ 483 483 + at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ 484 484 + } 485 485 + 486 486 + static struct resource uart2_resources[] = { 487 487 + [0] = { 488 488 + .start = AT91SAM9RL_BASE_US2, 489 489 + .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1, 490 490 + .flags = IORESOURCE_MEM, 491 491 + }, 492 492 + [1] = { 493 493 + .start = AT91SAM9RL_ID_US2, 494 494 + .end = AT91SAM9RL_ID_US2, 495 495 + .flags = IORESOURCE_IRQ, 496 496 + }, 497 497 + }; 498 498 + 499 499 + static struct atmel_uart_data uart2_data = { 500 500 + .use_dma_tx = 1, 501 501 + .use_dma_rx = 1, 502 502 + }; 503 503 + 504 504 + static struct platform_device at91sam9rl_uart2_device = { 505 505 + .name = "atmel_usart", 506 506 + .id = 3, 507 507 + .dev = { 508 508 + .platform_data = &uart2_data, 509 509 + .coherent_dma_mask = 0xffffffff, 510 510 + }, 511 511 + .resource = uart2_resources, 512 512 + .num_resources = ARRAY_SIZE(uart2_resources), 513 513 + }; 514 514 + 515 515 + static inline void configure_usart2_pins(void) 516 516 + { 517 517 + at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ 518 518 + at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ 519 519 + } 520 520 + 521 521 + static struct resource uart3_resources[] = { 522 522 + [0] = { 523 523 + .start = AT91SAM9RL_BASE_US3, 524 524 + .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1, 525 525 + .flags = IORESOURCE_MEM, 526 526 + }, 527 527 + [1] = { 528 528 + .start = AT91SAM9RL_ID_US3, 529 529 + .end = AT91SAM9RL_ID_US3, 530 530 + .flags = IORESOURCE_IRQ, 531 531 + }, 532 532 + }; 533 533 + 534 534 + static struct atmel_uart_data uart3_data = { 535 535 + .use_dma_tx = 1, 536 536 + .use_dma_rx = 1, 537 537 + }; 538 538 + 539 539 + static struct platform_device at91sam9rl_uart3_device = { 540 540 + .name = "atmel_usart", 541 541 + .id = 4, 542 542 + .dev = { 543 543 + .platform_data = &uart3_data, 544 544 + .coherent_dma_mask = 0xffffffff, 545 545 + }, 546 546 + .resource = uart3_resources, 547 547 + .num_resources = ARRAY_SIZE(uart3_resources), 548 548 + }; 549 549 + 550 550 + static inline void configure_usart3_pins(void) 551 551 + { 552 552 + at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */ 553 553 + at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */ 554 554 + } 555 555 + 556 556 + struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 557 557 + struct platform_device *atmel_default_console_device; /* the serial console device */ 558 558 + 559 559 + void __init at91_init_serial(struct at91_uart_config *config) 560 560 + { 561 561 + int i; 562 562 + 563 563 + /* Fill in list of supported UARTs */ 564 564 + for (i = 0; i < config->nr_tty; i++) { 565 565 + switch (config->tty_map[i]) { 566 566 + case 0: 567 567 + configure_usart0_pins(); 568 568 + at91_uarts[i] = &at91sam9rl_uart0_device; 569 569 + at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart"); 570 570 + break; 571 571 + case 1: 572 572 + configure_usart1_pins(); 573 573 + at91_uarts[i] = &at91sam9rl_uart1_device; 574 574 + at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart"); 575 575 + break; 576 576 + case 2: 577 577 + configure_usart2_pins(); 578 578 + at91_uarts[i] = &at91sam9rl_uart2_device; 579 579 + at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart"); 580 580 + break; 581 581 + case 3: 582 582 + configure_usart3_pins(); 583 583 + at91_uarts[i] = &at91sam9rl_uart3_device; 584 584 + at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart"); 585 585 + break; 586 586 + case 4: 587 587 + configure_dbgu_pins(); 588 588 + at91_uarts[i] = &at91sam9rl_dbgu_device; 589 589 + at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart"); 590 590 + break; 591 591 + default: 592 592 + continue; 593 593 + } 594 594 + at91_uarts[i]->id = i; /* update ID number to mapped ID */ 595 595 + } 596 596 + 597 597 + /* Set serial console device */ 598 598 + if (config->console_tty < ATMEL_MAX_UART) 599 599 + atmel_default_console_device = at91_uarts[config->console_tty]; 600 600 + if (!atmel_default_console_device) 601 601 + printk(KERN_INFO "AT91: No default serial console defined.\n"); 602 602 + } 603 603 + 604 604 + void __init at91_add_device_serial(void) 605 605 + { 606 606 + int i; 607 607 + 608 608 + for (i = 0; i < ATMEL_MAX_UART; i++) { 609 609 + if (at91_uarts[i]) 610 610 + platform_device_register(at91_uarts[i]); 611 611 + } 612 612 + } 613 613 + #else 614 614 + void __init at91_init_serial(struct at91_uart_config *config) {} 615 615 + void __init at91_add_device_serial(void) {} 616 616 + #endif 617 617 + 618 618 + 619 619 + /* -------------------------------------------------------------------- */ 620 620 + 621 621 + /* 622 622 + * These devices are always present and don't need any board-specific 623 623 + * setup. 624 624 + */ 625 625 + static int __init at91_add_standard_devices(void) 626 626 + { 627 627 + return 0; 628 628 + } 629 629 + 630 630 + arch_initcall(at91_add_standard_devices);

+3

arch/arm/mach-at91/board-sam9261ek.c

reviewed

··· 60 60 /* Initialize processor: 18.432 MHz crystal */ 61 61 at91sam9261_initialize(18432000); 62 62 63 63 + /* Setup the LEDs */ 64 64 + at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); 65 65 + 63 66 /* Setup the serial ports and console */ 64 67 at91_init_serial(&ek_uart_config); 65 68 }

+204

arch/arm/mach-at91/board-sam9rlek.c

reviewed

··· 1 1 + /* 2 2 + * Copyright (C) 2005 SAN People 3 3 + * Copyright (C) 2007 Atmel Corporation 4 4 + * 5 5 + * This file is subject to the terms and conditions of the GNU General Public 6 6 + * License. See the file COPYING in the main directory of this archive for 7 7 + * more details. 8 8 + */ 9 9 + 10 10 + #include <linux/types.h> 11 11 + #include <linux/init.h> 12 12 + #include <linux/mm.h> 13 13 + #include <linux/module.h> 14 14 + #include <linux/platform_device.h> 15 15 + #include <linux/spi/spi.h> 16 16 + #include <linux/fb.h> 17 17 + #include <linux/clk.h> 18 18 + 19 19 + #include <video/atmel_lcdc.h> 20 20 + 21 21 + #include <asm/hardware.h> 22 22 + #include <asm/setup.h> 23 23 + #include <asm/mach-types.h> 24 24 + #include <asm/irq.h> 25 25 + 26 26 + #include <asm/mach/arch.h> 27 27 + #include <asm/mach/map.h> 28 28 + #include <asm/mach/irq.h> 29 29 + 30 30 + #include <asm/arch/board.h> 31 31 + #include <asm/arch/gpio.h> 32 32 + #include <asm/arch/at91sam926x_mc.h> 33 33 + 34 34 + #include "generic.h" 35 35 + 36 36 + 37 37 + /* 38 38 + * Serial port configuration. 39 39 + * 0 .. 3 = USART0 .. USART3 40 40 + * 4 = DBGU 41 41 + */ 42 42 + static struct at91_uart_config __initdata ek_uart_config = { 43 43 + .console_tty = 0, /* ttyS0 */ 44 44 + .nr_tty = 2, 45 45 + .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ 46 46 + }; 47 47 + 48 48 + static void __init ek_map_io(void) 49 49 + { 50 50 + /* Initialize processor: 12.000 MHz crystal */ 51 51 + at91sam9rl_initialize(12000000); 52 52 + 53 53 + /* Setup the serial ports and console */ 54 54 + at91_init_serial(&ek_uart_config); 55 55 + } 56 56 + 57 57 + static void __init ek_init_irq(void) 58 58 + { 59 59 + at91sam9rl_init_interrupts(NULL); 60 60 + } 61 61 + 62 62 + 63 63 + /* 64 64 + * MCI (SD/MMC) 65 65 + */ 66 66 + static struct at91_mmc_data __initdata ek_mmc_data = { 67 67 + .wire4 = 1, 68 68 + .det_pin = AT91_PIN_PA15, 69 69 + // .wp_pin = ... not connected 70 70 + // .vcc_pin = ... not connected 71 71 + }; 72 72 + 73 73 + 74 74 + /* 75 75 + * NAND flash 76 76 + */ 77 77 + static struct mtd_partition __initdata ek_nand_partition[] = { 78 78 + { 79 79 + .name = "Partition 1", 80 80 + .offset = 0, 81 81 + .size = 256 * 1024, 82 82 + }, 83 83 + { 84 84 + .name = "Partition 2", 85 85 + .offset = 256 * 1024 , 86 86 + .size = MTDPART_SIZ_FULL, 87 87 + }, 88 88 + }; 89 89 + 90 90 + static struct mtd_partition *nand_partitions(int size, int *num_partitions) 91 91 + { 92 92 + *num_partitions = ARRAY_SIZE(ek_nand_partition); 93 93 + return ek_nand_partition; 94 94 + } 95 95 + 96 96 + static struct at91_nand_data __initdata ek_nand_data = { 97 97 + .ale = 21, 98 98 + .cle = 22, 99 99 + // .det_pin = ... not connected 100 100 + .rdy_pin = AT91_PIN_PD17, 101 101 + .enable_pin = AT91_PIN_PB6, 102 102 + .partition_info = nand_partitions, 103 103 + .bus_width_16 = 0, 104 104 + }; 105 105 + 106 106 + 107 107 + /* 108 108 + * SPI devices 109 109 + */ 110 110 + static struct spi_board_info ek_spi_devices[] = { 111 111 + { /* DataFlash chip */ 112 112 + .modalias = "mtd_dataflash", 113 113 + .chip_select = 0, 114 114 + .max_speed_hz = 15 * 1000 * 1000, 115 115 + .bus_num = 0, 116 116 + }, 117 117 + }; 118 118 + 119 119 + 120 120 + /* 121 121 + * LCD Controller 122 122 + */ 123 123 + #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) 124 124 + static struct fb_videomode at91_tft_vga_modes[] = { 125 125 + { 126 126 + .name = "TX09D50VM1CCA @ 60", 127 127 + .refresh = 60, 128 128 + .xres = 240, .yres = 320, 129 129 + .pixclock = KHZ2PICOS(4965), 130 130 + 131 131 + .left_margin = 1, .right_margin = 33, 132 132 + .upper_margin = 1, .lower_margin = 0, 133 133 + .hsync_len = 5, .vsync_len = 1, 134 134 + 135 135 + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 136 136 + .vmode = FB_VMODE_NONINTERLACED, 137 137 + }, 138 138 + }; 139 139 + 140 140 + static struct fb_monspecs at91fb_default_monspecs = { 141 141 + .manufacturer = "HIT", 142 142 + .monitor = "TX09D50VM1CCA", 143 143 + 144 144 + .modedb = at91_tft_vga_modes, 145 145 + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), 146 146 + .hfmin = 15000, 147 147 + .hfmax = 64000, 148 148 + .vfmin = 50, 149 149 + .vfmax = 150, 150 150 + }; 151 151 + 152 152 + #define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ 153 153 + | ATMEL_LCDC_DISTYPE_TFT \ 154 154 + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) 155 155 + 156 156 + static void at91_lcdc_power_control(int on) 157 157 + { 158 158 + if (on) 159 159 + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ 160 160 + else 161 161 + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ 162 162 + } 163 163 + 164 164 + /* Driver datas */ 165 165 + static struct atmel_lcdfb_info __initdata ek_lcdc_data = { 166 166 + .default_bpp = 16, 167 167 + .default_dmacon = ATMEL_LCDC_DMAEN, 168 168 + .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2, 169 169 + .default_monspecs = &at91fb_default_monspecs, 170 170 + .atmel_lcdfb_power_control = at91_lcdc_power_control, 171 171 + .guard_time = 1, 172 172 + }; 173 173 + 174 174 + #else 175 175 + static struct atmel_lcdfb_info __initdata ek_lcdc_data; 176 176 + #endif 177 177 + 178 178 + 179 179 + static void __init ek_board_init(void) 180 180 + { 181 181 + /* Serial */ 182 182 + at91_add_device_serial(); 183 183 + /* I2C */ 184 184 + at91_add_device_i2c(); 185 185 + /* NAND */ 186 186 + at91_add_device_nand(&ek_nand_data); 187 187 + /* SPI */ 188 188 + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); 189 189 + /* MMC */ 190 190 + at91_add_device_mmc(0, &ek_mmc_data); 191 191 + /* LCD Controller */ 192 192 + at91_add_device_lcdc(&ek_lcdc_data); 193 193 + } 194 194 + 195 195 + MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") 196 196 + /* Maintainer: Atmel */ 197 197 + .phys_io = AT91_BASE_SYS, 198 198 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, 199 199 + .boot_params = AT91_SDRAM_BASE + 0x100, 200 200 + .timer = &at91sam926x_timer, 201 201 + .map_io = ek_map_io, 202 202 + .init_irq = ek_init_irq, 203 203 + .init_machine = ek_board_init, 204 204 + MACHINE_END

+2

arch/arm/mach-at91/generic.h

reviewed

··· 13 13 extern void __init at91sam9260_initialize(unsigned long main_clock); 14 14 extern void __init at91sam9261_initialize(unsigned long main_clock); 15 15 extern void __init at91sam9263_initialize(unsigned long main_clock); 16 16 + extern void __init at91sam9rl_initialize(unsigned long main_clock); 16 17 17 18 /* Interrupts */ 18 19 extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 19 20 extern void __init at91sam9260_init_interrupts(unsigned int priority[]); 20 21 extern void __init at91sam9261_init_interrupts(unsigned int priority[]); 21 22 extern void __init at91sam9263_init_interrupts(unsigned int priority[]); 23 23 + extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); 22 24 extern void __init at91_aic_init(unsigned int priority[]); 23 25 24 26 /* Timer */

+23

arch/arm/mach-davinci/Kconfig

reviewed

··· 1 1 + if ARCH_DAVINCI 2 2 + 3 3 + menu "TI DaVinci Implementations" 4 4 + 5 5 + comment "DaVinci Core Type" 6 6 + 7 7 + config ARCH_DAVINCI644x 8 8 + default y 9 9 + bool "DaVinci 644x based system" 10 10 + 11 11 + comment "DaVinci Board Type" 12 12 + 13 13 + config MACH_DAVINCI_EVM 14 14 + bool "TI DaVinci EVM" 15 15 + default y 16 16 + depends on ARCH_DAVINCI644x 17 17 + help 18 18 + Configure this option to specify the whether the board used 19 19 + for development is a DaVinci EVM 20 20 + 21 21 + endmenu 22 22 + 23 23 + endif

+10

arch/arm/mach-davinci/Makefile

reviewed

··· 1 1 + # 2 2 + # Makefile for the linux kernel. 3 3 + # 4 4 + # 5 5 + 6 6 + # Common objects 7 7 + obj-y := time.o irq.o serial.o io.o id.o psc.o 8 8 + 9 9 + # Board specific 10 10 + obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o

+3

arch/arm/mach-davinci/Makefile.boot

reviewed

··· 1 1 + zreladdr-y := 0x80008000 2 2 + params_phys-y := 0x80000100 3 3 + initrd_phys-y := 0x80800000

+131

arch/arm/mach-davinci/board-evm.c

reviewed

··· 1 1 + /* 2 2 + * TI DaVinci EVM board support 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #include <linux/kernel.h> 12 12 + #include <linux/module.h> 13 13 + #include <linux/init.h> 14 14 + #include <linux/dma-mapping.h> 15 15 + #include <linux/platform_device.h> 16 16 + #include <linux/mtd/mtd.h> 17 17 + #include <linux/mtd/partitions.h> 18 18 + #include <linux/mtd/physmap.h> 19 19 + 20 20 + #include <asm/setup.h> 21 21 + #include <asm/io.h> 22 22 + #include <asm/mach-types.h> 23 23 + #include <asm/hardware.h> 24 24 + 25 25 + #include <asm/mach/arch.h> 26 26 + #include <asm/mach/map.h> 27 27 + #include <asm/mach/flash.h> 28 28 + 29 29 + #include <asm/arch/common.h> 30 30 + 31 31 + /* other misc. init functions */ 32 32 + void __init davinci_psc_init(void); 33 33 + void __init davinci_irq_init(void); 34 34 + void __init davinci_map_common_io(void); 35 35 + 36 36 + /* NOR Flash base address set to CS0 by default */ 37 37 + #define NOR_FLASH_PHYS 0x02000000 38 38 + 39 39 + static struct mtd_partition davinci_evm_partitions[] = { 40 40 + /* bootloader (U-Boot, etc) in first 4 sectors */ 41 41 + { 42 42 + .name = "bootloader", 43 43 + .offset = 0, 44 44 + .size = 4 * SZ_64K, 45 45 + .mask_flags = MTD_WRITEABLE, /* force read-only */ 46 46 + }, 47 47 + /* bootloader params in the next 1 sectors */ 48 48 + { 49 49 + .name = "params", 50 50 + .offset = MTDPART_OFS_APPEND, 51 51 + .size = SZ_64K, 52 52 + .mask_flags = 0, 53 53 + }, 54 54 + /* kernel */ 55 55 + { 56 56 + .name = "kernel", 57 57 + .offset = MTDPART_OFS_APPEND, 58 58 + .size = SZ_2M, 59 59 + .mask_flags = 0 60 60 + }, 61 61 + /* file system */ 62 62 + { 63 63 + .name = "filesystem", 64 64 + .offset = MTDPART_OFS_APPEND, 65 65 + .size = MTDPART_SIZ_FULL, 66 66 + .mask_flags = 0 67 67 + } 68 68 + }; 69 69 + 70 70 + static struct physmap_flash_data davinci_evm_flash_data = { 71 71 + .width = 2, 72 72 + .parts = davinci_evm_partitions, 73 73 + .nr_parts = ARRAY_SIZE(davinci_evm_partitions), 74 74 + }; 75 75 + 76 76 + /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF 77 77 + * limits addresses to 16M, so using addresses past 16M will wrap */ 78 78 + static struct resource davinci_evm_flash_resource = { 79 79 + .start = NOR_FLASH_PHYS, 80 80 + .end = NOR_FLASH_PHYS + SZ_16M - 1, 81 81 + .flags = IORESOURCE_MEM, 82 82 + }; 83 83 + 84 84 + static struct platform_device davinci_evm_flash_device = { 85 85 + .name = "physmap-flash", 86 86 + .id = 0, 87 87 + .dev = { 88 88 + .platform_data = &davinci_evm_flash_data, 89 89 + }, 90 90 + .num_resources = 1, 91 91 + .resource = &davinci_evm_flash_resource, 92 92 + }; 93 93 + 94 94 + static struct platform_device *davinci_evm_devices[] __initdata = { 95 95 + &davinci_evm_flash_device, 96 96 + }; 97 97 + 98 98 + static void __init 99 99 + davinci_evm_map_io(void) 100 100 + { 101 101 + davinci_map_common_io(); 102 102 + } 103 103 + 104 104 + static __init void davinci_evm_init(void) 105 105 + { 106 106 + davinci_psc_init(); 107 107 + 108 108 + #if defined(CONFIG_BLK_DEV_DAVINCI) || defined(CONFIG_BLK_DEV_DAVINCI_MODULE) 109 109 + printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " 110 110 + "but share pins.\n\t Disable IDE for NOR support.\n"); 111 111 + #endif 112 112 + 113 113 + platform_add_devices(davinci_evm_devices, 114 114 + ARRAY_SIZE(davinci_evm_devices)); 115 115 + } 116 116 + 117 117 + static __init void davinci_evm_irq_init(void) 118 118 + { 119 119 + davinci_irq_init(); 120 120 + } 121 121 + 122 122 + MACHINE_START(DAVINCI_EVM, "DaVinci EVM") 123 123 + /* Maintainer: MontaVista Software <source@mvista.com> */ 124 124 + .phys_io = IO_PHYS, 125 125 + .io_pg_offst = (io_p2v(IO_PHYS) >> 18) & 0xfffc, 126 126 + .boot_params = (DAVINCI_DDR_BASE + 0x100), 127 127 + .map_io = davinci_evm_map_io, 128 128 + .init_irq = davinci_evm_irq_init, 129 129 + .timer = &davinci_timer, 130 130 + .init_machine = davinci_evm_init, 131 131 + MACHINE_END

+94

arch/arm/mach-davinci/id.c

reviewed

··· 1 1 + /* 2 2 + * Davinci CPU identification code 3 3 + * 4 4 + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 5 5 + * 6 6 + * Derived from OMAP1 CPU identification code. 7 7 + * 8 8 + * This program is free software; you can redistribute it and/or modify 9 9 + * it under the terms of the GNU General Public License version 2 as 10 10 + * published by the Free Software Foundation. 11 11 + */ 12 12 + 13 13 + #include <linux/module.h> 14 14 + #include <linux/kernel.h> 15 15 + #include <linux/init.h> 16 16 + 17 17 + #include <asm/io.h> 18 18 + 19 19 + #define JTAG_ID_BASE 0x01c40028 20 20 + 21 21 + struct davinci_id { 22 22 + u8 variant; /* JTAG ID bits 31:28 */ 23 23 + u16 part_no; /* JTAG ID bits 27:12 */ 24 24 + u32 manufacturer; /* JTAG ID bits 11:1 */ 25 25 + u32 type; /* Cpu id bits [31:8], cpu class bits [7:0] */ 26 26 + }; 27 27 + 28 28 + /* Register values to detect the DaVinci version */ 29 29 + static struct davinci_id davinci_ids[] __initdata = { 30 30 + { 31 31 + /* DM6446 */ 32 32 + .part_no = 0xb700, 33 33 + .variant = 0x0, 34 34 + .manufacturer = 0x017, 35 35 + .type = 0x64460000, 36 36 + }, 37 37 + }; 38 38 + 39 39 + /* 40 40 + * Get Device Part No. from JTAG ID register 41 41 + */ 42 42 + static u16 __init davinci_get_part_no(void) 43 43 + { 44 44 + u32 dev_id, part_no; 45 45 + 46 46 + dev_id = davinci_readl(JTAG_ID_BASE); 47 47 + 48 48 + part_no = ((dev_id >> 12) & 0xffff); 49 49 + 50 50 + return part_no; 51 51 + } 52 52 + 53 53 + /* 54 54 + * Get Device Revision from JTAG ID register 55 55 + */ 56 56 + static u8 __init davinci_get_variant(void) 57 57 + { 58 58 + u32 variant; 59 59 + 60 60 + variant = davinci_readl(JTAG_ID_BASE); 61 61 + 62 62 + variant = (variant >> 28) & 0xf; 63 63 + 64 64 + return variant; 65 65 + } 66 66 + 67 67 + void __init davinci_check_revision(void) 68 68 + { 69 69 + int i; 70 70 + u16 part_no; 71 71 + u8 variant; 72 72 + 73 73 + part_no = davinci_get_part_no(); 74 74 + variant = davinci_get_variant(); 75 75 + 76 76 + /* First check only the major version in a safe way */ 77 77 + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { 78 78 + if (part_no == (davinci_ids[i].part_no)) { 79 79 + system_rev = davinci_ids[i].type; 80 80 + break; 81 81 + } 82 82 + } 83 83 + 84 84 + /* Check if we can find the dev revision */ 85 85 + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { 86 86 + if (part_no == davinci_ids[i].part_no && 87 87 + variant == davinci_ids[i].variant) { 88 88 + system_rev = davinci_ids[i].type; 89 89 + break; 90 90 + } 91 91 + } 92 92 + 93 93 + printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant); 94 94 + }

+51

arch/arm/mach-davinci/io.c

reviewed

··· 1 1 + /* 2 2 + * DaVinci I/O mapping code 3 3 + * 4 4 + * Copyright (C) 2005-2006 Texas Instruments 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License version 2 as 8 8 + * published by the Free Software Foundation. 9 9 + */ 10 10 + 11 11 + #include <linux/module.h> 12 12 + #include <linux/kernel.h> 13 13 + #include <linux/init.h> 14 14 + 15 15 + #include <asm/tlb.h> 16 16 + #include <asm/io.h> 17 17 + #include <asm/memory.h> 18 18 + 19 19 + #include <asm/mach/map.h> 20 20 + 21 21 + extern void davinci_check_revision(void); 22 22 + 23 23 + /* 24 24 + * The machine specific code may provide the extra mapping besides the 25 25 + * default mapping provided here. 26 26 + */ 27 27 + static struct map_desc davinci_io_desc[] __initdata = { 28 28 + { 29 29 + .virtual = IO_VIRT, 30 30 + .pfn = __phys_to_pfn(IO_PHYS), 31 31 + .length = IO_SIZE, 32 32 + .type = MT_DEVICE 33 33 + }, 34 34 + }; 35 35 + 36 36 + void __init davinci_map_common_io(void) 37 37 + { 38 38 + iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc)); 39 39 + 40 40 + /* Normally devicemaps_init() would flush caches and tlb after 41 41 + * mdesc->map_io(), but we must also do it here because of the CPU 42 42 + * revision check below. 43 43 + */ 44 44 + local_flush_tlb_all(); 45 45 + flush_cache_all(); 46 46 + 47 47 + /* We want to check CPU revision early for cpu_is_xxxx() macros. 48 48 + * IO space mapping must be initialized before we can do that. 49 49 + */ 50 50 + davinci_check_revision(); 51 51 + }

+226

arch/arm/mach-davinci/irq.c

reviewed

··· 1 1 + /* 2 2 + * Interrupt handler for DaVinci boards. 3 3 + * 4 4 + * Copyright (C) 2006 Texas Instruments. 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License as published by 8 8 + * the Free Software Foundation; either version 2 of the License, or 9 9 + * (at your option) any later version. 10 10 + * 11 11 + * This program is distributed in the hope that it will be useful, 12 12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 14 + * GNU General Public License for more details. 15 15 + * 16 16 + * You should have received a copy of the GNU General Public License 17 17 + * along with this program; if not, write to the Free Software 18 18 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 19 + * 20 20 + */ 21 21 + #include <linux/kernel.h> 22 22 + #include <linux/init.h> 23 23 + #include <linux/interrupt.h> 24 24 + #include <linux/irq.h> 25 25 + 26 26 + #include <asm/hardware.h> 27 27 + #include <asm/io.h> 28 28 + #include <asm/mach/irq.h> 29 29 + 30 30 + #define IRQ_BIT(irq) ((irq) & 0x1f) 31 31 + 32 32 + #define FIQ_REG0_OFFSET 0x0000 33 33 + #define FIQ_REG1_OFFSET 0x0004 34 34 + #define IRQ_REG0_OFFSET 0x0008 35 35 + #define IRQ_REG1_OFFSET 0x000C 36 36 + #define IRQ_ENT_REG0_OFFSET 0x0018 37 37 + #define IRQ_ENT_REG1_OFFSET 0x001C 38 38 + #define IRQ_INCTL_REG_OFFSET 0x0020 39 39 + #define IRQ_EABASE_REG_OFFSET 0x0024 40 40 + #define IRQ_INTPRI0_REG_OFFSET 0x0030 41 41 + #define IRQ_INTPRI7_REG_OFFSET 0x004C 42 42 + 43 43 + static inline unsigned int davinci_irq_readl(int offset) 44 44 + { 45 45 + return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); 46 46 + } 47 47 + 48 48 + static inline void davinci_irq_writel(unsigned long value, int offset) 49 49 + { 50 50 + davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); 51 51 + } 52 52 + 53 53 + /* Disable interrupt */ 54 54 + static void davinci_mask_irq(unsigned int irq) 55 55 + { 56 56 + unsigned int mask; 57 57 + u32 l; 58 58 + 59 59 + mask = 1 << IRQ_BIT(irq); 60 60 + 61 61 + if (irq > 31) { 62 62 + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); 63 63 + l &= ~mask; 64 64 + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); 65 65 + } else { 66 66 + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); 67 67 + l &= ~mask; 68 68 + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); 69 69 + } 70 70 + } 71 71 + 72 72 + /* Enable interrupt */ 73 73 + static void davinci_unmask_irq(unsigned int irq) 74 74 + { 75 75 + unsigned int mask; 76 76 + u32 l; 77 77 + 78 78 + mask = 1 << IRQ_BIT(irq); 79 79 + 80 80 + if (irq > 31) { 81 81 + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); 82 82 + l |= mask; 83 83 + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); 84 84 + } else { 85 85 + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); 86 86 + l |= mask; 87 87 + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); 88 88 + } 89 89 + } 90 90 + 91 91 + /* EOI interrupt */ 92 92 + static void davinci_ack_irq(unsigned int irq) 93 93 + { 94 94 + unsigned int mask; 95 95 + 96 96 + mask = 1 << IRQ_BIT(irq); 97 97 + 98 98 + if (irq > 31) 99 99 + davinci_irq_writel(mask, IRQ_REG1_OFFSET); 100 100 + else 101 101 + davinci_irq_writel(mask, IRQ_REG0_OFFSET); 102 102 + } 103 103 + 104 104 + static struct irq_chip davinci_irq_chip_0 = { 105 105 + .name = "AINTC", 106 106 + .ack = davinci_ack_irq, 107 107 + .mask = davinci_mask_irq, 108 108 + .unmask = davinci_unmask_irq, 109 109 + }; 110 110 + 111 111 + 112 112 + /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 113 113 + static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { 114 114 + [IRQ_VDINT0] = 2, 115 115 + [IRQ_VDINT1] = 6, 116 116 + [IRQ_VDINT2] = 6, 117 117 + [IRQ_HISTINT] = 6, 118 118 + [IRQ_H3AINT] = 6, 119 119 + [IRQ_PRVUINT] = 6, 120 120 + [IRQ_RSZINT] = 6, 121 121 + [7] = 7, 122 122 + [IRQ_VENCINT] = 6, 123 123 + [IRQ_ASQINT] = 6, 124 124 + [IRQ_IMXINT] = 6, 125 125 + [IRQ_VLCDINT] = 6, 126 126 + [IRQ_USBINT] = 4, 127 127 + [IRQ_EMACINT] = 4, 128 128 + [14] = 7, 129 129 + [15] = 7, 130 130 + [IRQ_CCINT0] = 5, /* dma */ 131 131 + [IRQ_CCERRINT] = 5, /* dma */ 132 132 + [IRQ_TCERRINT0] = 5, /* dma */ 133 133 + [IRQ_TCERRINT] = 5, /* dma */ 134 134 + [IRQ_PSCIN] = 7, 135 135 + [21] = 7, 136 136 + [IRQ_IDE] = 4, 137 137 + [23] = 7, 138 138 + [IRQ_MBXINT] = 7, 139 139 + [IRQ_MBRINT] = 7, 140 140 + [IRQ_MMCINT] = 7, 141 141 + [IRQ_SDIOINT] = 7, 142 142 + [28] = 7, 143 143 + [IRQ_DDRINT] = 7, 144 144 + [IRQ_AEMIFINT] = 7, 145 145 + [IRQ_VLQINT] = 4, 146 146 + [IRQ_TINT0_TINT12] = 2, /* clockevent */ 147 147 + [IRQ_TINT0_TINT34] = 2, /* clocksource */ 148 148 + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ 149 149 + [IRQ_TINT1_TINT34] = 7, /* system tick */ 150 150 + [IRQ_PWMINT0] = 7, 151 151 + [IRQ_PWMINT1] = 7, 152 152 + [IRQ_PWMINT2] = 7, 153 153 + [IRQ_I2C] = 3, 154 154 + [IRQ_UARTINT0] = 3, 155 155 + [IRQ_UARTINT1] = 3, 156 156 + [IRQ_UARTINT2] = 3, 157 157 + [IRQ_SPINT0] = 3, 158 158 + [IRQ_SPINT1] = 3, 159 159 + [45] = 7, 160 160 + [IRQ_DSP2ARM0] = 4, 161 161 + [IRQ_DSP2ARM1] = 4, 162 162 + [IRQ_GPIO0] = 7, 163 163 + [IRQ_GPIO1] = 7, 164 164 + [IRQ_GPIO2] = 7, 165 165 + [IRQ_GPIO3] = 7, 166 166 + [IRQ_GPIO4] = 7, 167 167 + [IRQ_GPIO5] = 7, 168 168 + [IRQ_GPIO6] = 7, 169 169 + [IRQ_GPIO7] = 7, 170 170 + [IRQ_GPIOBNK0] = 7, 171 171 + [IRQ_GPIOBNK1] = 7, 172 172 + [IRQ_GPIOBNK2] = 7, 173 173 + [IRQ_GPIOBNK3] = 7, 174 174 + [IRQ_GPIOBNK4] = 7, 175 175 + [IRQ_COMMTX] = 7, 176 176 + [IRQ_COMMRX] = 7, 177 177 + [IRQ_EMUINT] = 7, 178 178 + }; 179 179 + 180 180 + /* ARM Interrupt Controller Initialization */ 181 181 + void __init davinci_irq_init(void) 182 182 + { 183 183 + unsigned i; 184 184 + const u8 *priority = default_priorities; 185 185 + 186 186 + /* Clear all interrupt requests */ 187 187 + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 188 188 + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); 189 189 + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); 190 190 + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); 191 191 + 192 192 + /* Disable all interrupts */ 193 193 + davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); 194 194 + davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); 195 195 + 196 196 + /* Interrupts disabled immediately, IRQ entry reflects all */ 197 197 + davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); 198 198 + 199 199 + /* we don't use the hardware vector table, just its entry addresses */ 200 200 + davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); 201 201 + 202 202 + /* Clear all interrupt requests */ 203 203 + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 204 204 + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); 205 205 + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); 206 206 + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); 207 207 + 208 208 + for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { 209 209 + unsigned j; 210 210 + u32 pri; 211 211 + 212 212 + for (j = 0, pri = 0; j < 32; j += 4, priority++) 213 213 + pri |= (*priority & 0x07) << j; 214 214 + davinci_irq_writel(pri, i); 215 215 + } 216 216 + 217 217 + /* set up genirq dispatch for ARM INTC */ 218 218 + for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) { 219 219 + set_irq_chip(i, &davinci_irq_chip_0); 220 220 + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 221 221 + if (i != IRQ_TINT1_TINT34) 222 222 + set_irq_handler(i, handle_edge_irq); 223 223 + else 224 224 + set_irq_handler(i, handle_level_irq); 225 225 + } 226 226 + }

+113

arch/arm/mach-davinci/psc.c

reviewed

··· 1 1 + /* 2 2 + * TI DaVinci Power and Sleep Controller (PSC) 3 3 + * 4 4 + * Copyright (C) 2006 Texas Instruments. 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License as published by 8 8 + * the Free Software Foundation; either version 2 of the License, or 9 9 + * (at your option) any later version. 10 10 + * 11 11 + * This program is distributed in the hope that it will be useful, 12 12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 14 + * GNU General Public License for more details. 15 15 + * 16 16 + * You should have received a copy of the GNU General Public License 17 17 + * along with this program; if not, write to the Free Software 18 18 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 19 + * 20 20 + */ 21 21 + #include <linux/kernel.h> 22 22 + #include <linux/module.h> 23 23 + #include <linux/init.h> 24 24 + 25 25 + #include <asm/io.h> 26 26 + #include <asm/hardware.h> 27 27 + #include <asm/arch/psc.h> 28 28 + 29 29 + #define PTCMD __REG(0x01C41120) 30 30 + #define PDSTAT __REG(0x01C41200) 31 31 + #define PDCTL1 __REG(0x01C41304) 32 32 + #define EPCPR __REG(0x01C41070) 33 33 + #define PTSTAT __REG(0x01C41128) 34 34 + 35 35 + #define MDSTAT IO_ADDRESS(0x01C41800) 36 36 + #define MDCTL IO_ADDRESS(0x01C41A00) 37 37 + 38 38 + #define PINMUX0 __REG(0x01c40000) 39 39 + #define PINMUX1 __REG(0x01c40004) 40 40 + #define VDD3P3V_PWDN __REG(0x01C40048) 41 41 + 42 42 + static void davinci_psc_mux(unsigned int id) 43 43 + { 44 44 + switch (id) { 45 45 + case DAVINCI_LPSC_ATA: 46 46 + PINMUX0 |= (1 << 17) | (1 << 16); 47 47 + break; 48 48 + case DAVINCI_LPSC_MMC_SD: 49 49 + /* VDD power manupulations are done in U-Boot for CPMAC 50 50 + * so applies to MMC as well 51 51 + */ 52 52 + /*Set up the pull regiter for MMC */ 53 53 + VDD3P3V_PWDN = 0x0; 54 54 + PINMUX1 &= (~(1 << 9)); 55 55 + break; 56 56 + case DAVINCI_LPSC_I2C: 57 57 + PINMUX1 |= (1 << 7); 58 58 + break; 59 59 + case DAVINCI_LPSC_McBSP: 60 60 + PINMUX1 |= (1 << 10); 61 61 + break; 62 62 + default: 63 63 + break; 64 64 + } 65 65 + } 66 66 + 67 67 + /* Enable or disable a PSC domain */ 68 68 + void davinci_psc_config(unsigned int domain, unsigned int id, char enable) 69 69 + { 70 70 + volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id); 71 71 + volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id); 72 72 + 73 73 + if (id < 0) 74 74 + return; 75 75 + 76 76 + if (enable) 77 77 + *mdctl |= 0x00000003; /* Enable Module */ 78 78 + else 79 79 + *mdctl &= 0xFFFFFFF2; /* Disable Module */ 80 80 + 81 81 + if ((PDSTAT & 0x00000001) == 0) { 82 82 + PDCTL1 |= 0x1; 83 83 + PTCMD = (1 << domain); 84 84 + while ((((EPCPR >> domain) & 1) == 0)); 85 85 + 86 86 + PDCTL1 |= 0x100; 87 87 + while (!(((PTSTAT >> domain) & 1) == 0)); 88 88 + } else { 89 89 + PTCMD = (1 << domain); 90 90 + while (!(((PTSTAT >> domain) & 1) == 0)); 91 91 + } 92 92 + 93 93 + if (enable) 94 94 + while (!((*mdstat & 0x0000001F) == 0x3)); 95 95 + else 96 96 + while (!((*mdstat & 0x0000001F) == 0x2)); 97 97 + 98 98 + if (enable) 99 99 + davinci_psc_mux(id); 100 100 + } 101 101 + 102 102 + void __init davinci_psc_init(void) 103 103 + { 104 104 + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1); 105 105 + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1); 106 106 + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1); 107 107 + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1); 108 108 + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1); 109 109 + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1); 110 110 + 111 111 + /* Turn on WatchDog timer LPSC. Needed for RESET to work */ 112 112 + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1); 113 113 + }

+96

arch/arm/mach-davinci/serial.c

reviewed

··· 1 1 + /* 2 2 + * TI DaVinci serial driver 3 3 + * 4 4 + * Copyright (C) 2006 Texas Instruments. 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License as published by 8 8 + * the Free Software Foundation; either version 2 of the License, or 9 9 + * (at your option) any later version. 10 10 + * 11 11 + * This program is distributed in the hope that it will be useful, 12 12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 14 + * GNU General Public License for more details. 15 15 + * 16 16 + * You should have received a copy of the GNU General Public License 17 17 + * along with this program; if not, write to the Free Software 18 18 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 19 + * 20 20 + */ 21 21 + 22 22 + #include <linux/kernel.h> 23 23 + #include <linux/init.h> 24 24 + #include <linux/serial_8250.h> 25 25 + #include <linux/serial_reg.h> 26 26 + #include <linux/platform_device.h> 27 27 + #include <linux/delay.h> 28 28 + #include <linux/clk.h> 29 29 + 30 30 + #include <asm/io.h> 31 31 + #include <asm/irq.h> 32 32 + #include <asm/hardware.h> 33 33 + #include <asm/arch/serial.h> 34 34 + #include <asm/arch/irqs.h> 35 35 + 36 36 + #define UART_DAVINCI_PWREMU 0x0c 37 37 + 38 38 + static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up, 39 39 + int offset) 40 40 + { 41 41 + offset <<= up->regshift; 42 42 + return (unsigned int)__raw_readb(up->membase + offset); 43 43 + } 44 44 + 45 45 + static inline void davinci_serial_outp(struct plat_serial8250_port *p, 46 46 + int offset, int value) 47 47 + { 48 48 + offset <<= p->regshift; 49 49 + __raw_writeb(value, p->membase + offset); 50 50 + } 51 51 + 52 52 + static struct plat_serial8250_port serial_platform_data[] = { 53 53 + { 54 54 + .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE), 55 55 + .mapbase = (unsigned long)DAVINCI_UART0_BASE, 56 56 + .irq = IRQ_UARTINT0, 57 57 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 58 58 + .iotype = UPIO_MEM, 59 59 + .regshift = 2, 60 60 + .uartclk = 27000000, 61 61 + }, 62 62 + { 63 63 + .flags = 0 64 64 + }, 65 65 + }; 66 66 + 67 67 + static struct platform_device serial_device = { 68 68 + .name = "serial8250", 69 69 + .id = PLAT8250_DEV_PLATFORM, 70 70 + .dev = { 71 71 + .platform_data = serial_platform_data, 72 72 + }, 73 73 + }; 74 74 + 75 75 + static void __init davinci_serial_reset(struct plat_serial8250_port *p) 76 76 + { 77 77 + /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ 78 78 + unsigned int pwremu = 0; 79 79 + 80 80 + davinci_serial_outp(p, UART_IER, 0); /* disable all interrupts */ 81 81 + 82 82 + davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); 83 83 + mdelay(10); 84 84 + 85 85 + pwremu |= (0x3 << 13); 86 86 + pwremu |= 0x1; 87 87 + davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); 88 88 + } 89 89 + 90 90 + static int __init davinci_init(void) 91 91 + { 92 92 + davinci_serial_reset(&serial_platform_data[0]); 93 93 + return platform_device_register(&serial_device); 94 94 + } 95 95 + 96 96 + arch_initcall(davinci_init);

+372

arch/arm/mach-davinci/time.c

reviewed

··· 1 1 + /* 2 2 + * DaVinci timer subsystem 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #include <linux/kernel.h> 12 12 + #include <linux/init.h> 13 13 + #include <linux/types.h> 14 14 + #include <linux/interrupt.h> 15 15 + #include <linux/clocksource.h> 16 16 + #include <linux/clockchips.h> 17 17 + #include <linux/spinlock.h> 18 18 + 19 19 + #include <asm/io.h> 20 20 + #include <asm/hardware.h> 21 21 + #include <asm/system.h> 22 22 + #include <asm/irq.h> 23 23 + #include <asm/mach/irq.h> 24 24 + #include <asm/mach/time.h> 25 25 + #include <asm/errno.h> 26 26 + #include <asm/arch/io.h> 27 27 + 28 28 + static struct clock_event_device clockevent_davinci; 29 29 + 30 30 + #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) 31 31 + #define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) 32 32 + #define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) 33 33 + 34 34 + enum { 35 35 + T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS, 36 36 + }; 37 37 + 38 38 + #define IS_TIMER1(id) (id & 0x2) 39 39 + #define IS_TIMER0(id) (!IS_TIMER1(id)) 40 40 + #define IS_TIMER_TOP(id) ((id & 0x1)) 41 41 + #define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) 42 42 + 43 43 + static int timer_irqs[NUM_TIMERS] = { 44 44 + IRQ_TINT0_TINT12, 45 45 + IRQ_TINT0_TINT34, 46 46 + IRQ_TINT1_TINT12, 47 47 + IRQ_TINT1_TINT34, 48 48 + }; 49 49 + 50 50 + /* 51 51 + * This driver configures the 2 64-bit count-up timers as 4 independent 52 52 + * 32-bit count-up timers used as follows: 53 53 + * 54 54 + * T0_BOT: Timer 0, bottom: clockevent source for hrtimers 55 55 + * T0_TOP: Timer 0, top : clocksource for generic timekeeping 56 56 + * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) 57 57 + * T1_TOP: Timer 1, top : <unused> 58 58 + */ 59 59 + #define TID_CLOCKEVENT T0_BOT 60 60 + #define TID_CLOCKSOURCE T0_TOP 61 61 + 62 62 + /* Timer register offsets */ 63 63 + #define PID12 0x0 64 64 + #define TIM12 0x10 65 65 + #define TIM34 0x14 66 66 + #define PRD12 0x18 67 67 + #define PRD34 0x1c 68 68 + #define TCR 0x20 69 69 + #define TGCR 0x24 70 70 + #define WDTCR 0x28 71 71 + 72 72 + /* Timer register bitfields */ 73 73 + #define TCR_ENAMODE_DISABLE 0x0 74 74 + #define TCR_ENAMODE_ONESHOT 0x1 75 75 + #define TCR_ENAMODE_PERIODIC 0x2 76 76 + #define TCR_ENAMODE_MASK 0x3 77 77 + 78 78 + #define TGCR_TIMMODE_SHIFT 2 79 79 + #define TGCR_TIMMODE_64BIT_GP 0x0 80 80 + #define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 81 81 + #define TGCR_TIMMODE_64BIT_WDOG 0x2 82 82 + #define TGCR_TIMMODE_32BIT_CHAINED 0x3 83 83 + 84 84 + #define TGCR_TIM12RS_SHIFT 0 85 85 + #define TGCR_TIM34RS_SHIFT 1 86 86 + #define TGCR_RESET 0x0 87 87 + #define TGCR_UNRESET 0x1 88 88 + #define TGCR_RESET_MASK 0x3 89 89 + 90 90 + #define WDTCR_WDEN_SHIFT 14 91 91 + #define WDTCR_WDEN_DISABLE 0x0 92 92 + #define WDTCR_WDEN_ENABLE 0x1 93 93 + #define WDTCR_WDKEY_SHIFT 16 94 94 + #define WDTCR_WDKEY_SEQ0 0xa5c6 95 95 + #define WDTCR_WDKEY_SEQ1 0xda7e 96 96 + 97 97 + struct timer_s { 98 98 + char *name; 99 99 + unsigned int id; 100 100 + unsigned long period; 101 101 + unsigned long opts; 102 102 + unsigned long reg_base; 103 103 + unsigned long tim_reg; 104 104 + unsigned long prd_reg; 105 105 + unsigned long enamode_shift; 106 106 + struct irqaction irqaction; 107 107 + }; 108 108 + static struct timer_s timers[]; 109 109 + 110 110 + /* values for 'opts' field of struct timer_s */ 111 111 + #define TIMER_OPTS_DISABLED 0x00 112 112 + #define TIMER_OPTS_ONESHOT 0x01 113 113 + #define TIMER_OPTS_PERIODIC 0x02 114 114 + 115 115 + static int timer32_config(struct timer_s *t) 116 116 + { 117 117 + u32 tcr = davinci_readl(t->reg_base + TCR); 118 118 + 119 119 + /* disable timer */ 120 120 + tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); 121 121 + davinci_writel(tcr, t->reg_base + TCR); 122 122 + 123 123 + /* reset counter to zero, set new period */ 124 124 + davinci_writel(0, t->tim_reg); 125 125 + davinci_writel(t->period, t->prd_reg); 126 126 + 127 127 + /* Set enable mode */ 128 128 + if (t->opts & TIMER_OPTS_ONESHOT) { 129 129 + tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; 130 130 + } else if (t->opts & TIMER_OPTS_PERIODIC) { 131 131 + tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; 132 132 + } 133 133 + 134 134 + davinci_writel(tcr, t->reg_base + TCR); 135 135 + return 0; 136 136 + } 137 137 + 138 138 + static inline u32 timer32_read(struct timer_s *t) 139 139 + { 140 140 + return davinci_readl(t->tim_reg); 141 141 + } 142 142 + 143 143 + static irqreturn_t timer_interrupt(int irq, void *dev_id) 144 144 + { 145 145 + struct clock_event_device *evt = &clockevent_davinci; 146 146 + 147 147 + evt->event_handler(evt); 148 148 + return IRQ_HANDLED; 149 149 + } 150 150 + 151 151 + /* called when 32-bit counter wraps */ 152 152 + static irqreturn_t freerun_interrupt(int irq, void *dev_id) 153 153 + { 154 154 + return IRQ_HANDLED; 155 155 + } 156 156 + 157 157 + static struct timer_s timers[] = { 158 158 + [TID_CLOCKEVENT] = { 159 159 + .name = "clockevent", 160 160 + .opts = TIMER_OPTS_DISABLED, 161 161 + .irqaction = { 162 162 + .flags = IRQF_DISABLED | IRQF_TIMER, 163 163 + .handler = timer_interrupt, 164 164 + } 165 165 + }, 166 166 + [TID_CLOCKSOURCE] = { 167 167 + .name = "free-run counter", 168 168 + .period = ~0, 169 169 + .opts = TIMER_OPTS_PERIODIC, 170 170 + .irqaction = { 171 171 + .flags = IRQF_DISABLED | IRQF_TIMER, 172 172 + .handler = freerun_interrupt, 173 173 + } 174 174 + }, 175 175 + }; 176 176 + 177 177 + static void __init timer_init(void) 178 178 + { 179 179 + u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; 180 180 + int i; 181 181 + 182 182 + /* Global init of each 64-bit timer as a whole */ 183 183 + for(i=0; i<2; i++) { 184 184 + u32 tgcr, base = bases[i]; 185 185 + 186 186 + /* Disabled, Internal clock source */ 187 187 + davinci_writel(0, base + TCR); 188 188 + 189 189 + /* reset both timers, no pre-scaler for timer34 */ 190 190 + tgcr = 0; 191 191 + davinci_writel(tgcr, base + TGCR); 192 192 + 193 193 + /* Set both timers to unchained 32-bit */ 194 194 + tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; 195 195 + davinci_writel(tgcr, base + TGCR); 196 196 + 197 197 + /* Unreset timers */ 198 198 + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 199 199 + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 200 200 + davinci_writel(tgcr, base + TGCR); 201 201 + 202 202 + /* Init both counters to zero */ 203 203 + davinci_writel(0, base + TIM12); 204 204 + davinci_writel(0, base + TIM34); 205 205 + } 206 206 + 207 207 + /* Init of each timer as a 32-bit timer */ 208 208 + for (i=0; i< ARRAY_SIZE(timers); i++) { 209 209 + struct timer_s *t = &timers[i]; 210 210 + 211 211 + if (t->name) { 212 212 + t->id = i; 213 213 + t->reg_base = (IS_TIMER1(t->id) ? 214 214 + DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); 215 215 + 216 216 + if (IS_TIMER_BOT(t->id)) { 217 217 + t->enamode_shift = 6; 218 218 + t->tim_reg = t->reg_base + TIM12; 219 219 + t->prd_reg = t->reg_base + PRD12; 220 220 + } else { 221 221 + t->enamode_shift = 22; 222 222 + t->tim_reg = t->reg_base + TIM34; 223 223 + t->prd_reg = t->reg_base + PRD34; 224 224 + } 225 225 + 226 226 + /* Register interrupt */ 227 227 + t->irqaction.name = t->name; 228 228 + t->irqaction.dev_id = (void *)t; 229 229 + if (t->irqaction.handler != NULL) { 230 230 + setup_irq(timer_irqs[t->id], &t->irqaction); 231 231 + } 232 232 + 233 233 + timer32_config(&timers[i]); 234 234 + } 235 235 + } 236 236 + } 237 237 + 238 238 + /* 239 239 + * clocksource 240 240 + */ 241 241 + static cycle_t read_cycles(void) 242 242 + { 243 243 + struct timer_s *t = &timers[TID_CLOCKSOURCE]; 244 244 + 245 245 + return (cycles_t)timer32_read(t); 246 246 + } 247 247 + 248 248 + static struct clocksource clocksource_davinci = { 249 249 + .name = "timer0_1", 250 250 + .rating = 300, 251 251 + .read = read_cycles, 252 252 + .mask = CLOCKSOURCE_MASK(32), 253 253 + .shift = 24, 254 254 + .flags = CLOCK_SOURCE_IS_CONTINUOUS, 255 255 + }; 256 256 + 257 257 + /* 258 258 + * clockevent 259 259 + */ 260 260 + static int davinci_set_next_event(unsigned long cycles, 261 261 + struct clock_event_device *evt) 262 262 + { 263 263 + struct timer_s *t = &timers[TID_CLOCKEVENT]; 264 264 + 265 265 + t->period = cycles; 266 266 + timer32_config(t); 267 267 + return 0; 268 268 + } 269 269 + 270 270 + static void davinci_set_mode(enum clock_event_mode mode, 271 271 + struct clock_event_device *evt) 272 272 + { 273 273 + struct timer_s *t = &timers[TID_CLOCKEVENT]; 274 274 + 275 275 + switch (mode) { 276 276 + case CLOCK_EVT_MODE_PERIODIC: 277 277 + t->period = CLOCK_TICK_RATE / (HZ); 278 278 + t->opts = TIMER_OPTS_PERIODIC; 279 279 + timer32_config(t); 280 280 + break; 281 281 + case CLOCK_EVT_MODE_ONESHOT: 282 282 + t->opts = TIMER_OPTS_ONESHOT; 283 283 + break; 284 284 + case CLOCK_EVT_MODE_UNUSED: 285 285 + case CLOCK_EVT_MODE_SHUTDOWN: 286 286 + t->opts = TIMER_OPTS_DISABLED; 287 287 + break; 288 288 + } 289 289 + } 290 290 + 291 291 + static struct clock_event_device clockevent_davinci = { 292 292 + .name = "timer0_0", 293 293 + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 294 294 + .shift = 32, 295 295 + .set_next_event = davinci_set_next_event, 296 296 + .set_mode = davinci_set_mode, 297 297 + }; 298 298 + 299 299 + 300 300 + static void __init davinci_timer_init(void) 301 301 + { 302 302 + static char err[] __initdata = KERN_ERR 303 303 + "%s: can't register clocksource!\n"; 304 304 + 305 305 + /* init timer hw */ 306 306 + timer_init(); 307 307 + 308 308 + /* setup clocksource */ 309 309 + clocksource_davinci.mult = 310 310 + clocksource_khz2mult(CLOCK_TICK_RATE/1000, 311 311 + clocksource_davinci.shift); 312 312 + if (clocksource_register(&clocksource_davinci)) 313 313 + printk(err, clocksource_davinci.name); 314 314 + 315 315 + /* setup clockevent */ 316 316 + clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 317 317 + clockevent_davinci.shift); 318 318 + clockevent_davinci.max_delta_ns = 319 319 + clockevent_delta2ns(0xfffffffe, &clockevent_davinci); 320 320 + clockevent_davinci.min_delta_ns = 321 321 + clockevent_delta2ns(1, &clockevent_davinci); 322 322 + 323 323 + clockevent_davinci.cpumask = cpumask_of_cpu(0); 324 324 + clockevents_register_device(&clockevent_davinci); 325 325 + } 326 326 + 327 327 + struct sys_timer davinci_timer = { 328 328 + .init = davinci_timer_init, 329 329 + }; 330 330 + 331 331 + 332 332 + /* reset board using watchdog timer */ 333 333 + void davinci_watchdog_reset(void) { 334 334 + u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE; 335 335 + 336 336 + /* disable, internal clock source */ 337 337 + davinci_writel(0, base + TCR); 338 338 + 339 339 + /* reset timer, set mode to 64-bit watchdog, and unreset */ 340 340 + tgcr = 0; 341 341 + davinci_writel(tgcr, base + TCR); 342 342 + tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; 343 343 + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 344 344 + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 345 345 + davinci_writel(tgcr, base + TCR); 346 346 + 347 347 + /* clear counter and period regs */ 348 348 + davinci_writel(0, base + TIM12); 349 349 + davinci_writel(0, base + TIM34); 350 350 + davinci_writel(0, base + PRD12); 351 351 + davinci_writel(0, base + PRD34); 352 352 + 353 353 + /* enable */ 354 354 + wdtcr = davinci_readl(base + WDTCR); 355 355 + wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; 356 356 + davinci_writel(wdtcr, base + WDTCR); 357 357 + 358 358 + /* put watchdog in pre-active state */ 359 359 + wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | 360 360 + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); 361 361 + davinci_writel(wdtcr, base + WDTCR); 362 362 + 363 363 + /* put watchdog in active state */ 364 364 + wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | 365 365 + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); 366 366 + davinci_writel(wdtcr, base + WDTCR); 367 367 + 368 368 + /* write an invalid value to the WDKEY field to trigger 369 369 + * a watchdog reset */ 370 370 + wdtcr = 0x00004000; 371 371 + davinci_writel(wdtcr, base + WDTCR); 372 372 + }

+4 -4

arch/arm/mach-ebsa110/io.c

reviewed

··· 102 102 EXPORT_SYMBOL(__readw); 103 103 EXPORT_SYMBOL(__readl); 104 104 105 105 - void readsw(void __iomem *addr, void *data, int len) 105 105 + void readsw(const void __iomem *addr, void *data, int len) 106 106 { 107 107 void __iomem *a = __isamem_convert_addr(addr); 108 108 ··· 112 112 } 113 113 EXPORT_SYMBOL(readsw); 114 114 115 115 - void readsl(void __iomem *addr, void *data, int len) 115 115 + void readsl(const void __iomem *addr, void *data, int len) 116 116 { 117 117 void __iomem *a = __isamem_convert_addr(addr); 118 118 ··· 157 157 EXPORT_SYMBOL(__writew); 158 158 EXPORT_SYMBOL(__writel); 159 159 160 160 - void writesw(void __iomem *addr, void *data, int len) 160 160 + void writesw(void __iomem *addr, const void *data, int len) 161 161 { 162 162 void __iomem *a = __isamem_convert_addr(addr); 163 163 ··· 167 167 } 168 168 EXPORT_SYMBOL(writesw); 169 169 170 170 - void writesl(void __iomem *addr, void *data, int len) 170 170 + void writesl(void __iomem *addr, const void *data, int len) 171 171 { 172 172 void __iomem *a = __isamem_convert_addr(addr); 173 173

+1

arch/arm/mach-iop13xx/Makefile

reviewed

··· 10 10 obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o 11 11 obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o 12 12 obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o 13 13 + obj-$(CONFIG_PCI_MSI) += msi.o

+4 -1

arch/arm/mach-iop13xx/irq.c

reviewed

··· 26 26 #include <asm/hardware.h> 27 27 #include <asm/mach-types.h> 28 28 #include <asm/arch/irqs.h> 29 29 + #include <asm/arch/msi.h> 29 30 30 31 /* INTCTL0 CP6 R0 Page 4 31 32 */ ··· 259 258 write_intbase(INTBASE); 260 259 write_intsize(INTSIZE_4); 261 260 262 262 - for(i = 0; i < NR_IOP13XX_IRQS; i++) { 261 261 + for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { 263 262 if (i < 32) 264 263 set_irq_chip(i, &iop13xx_irqchip1); 265 264 else if (i < 64) ··· 272 271 set_irq_handler(i, handle_level_irq); 273 272 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 274 273 } 274 274 + 275 275 + iop13xx_msi_init(); 275 276 }

+194

arch/arm/mach-iop13xx/msi.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-iop13xx/msi.c 3 3 + * 4 4 + * PCI MSI support for the iop13xx processor 5 5 + * 6 6 + * Copyright (c) 2006, Intel Corporation. 7 7 + * 8 8 + * This program is free software; you can redistribute it and/or modify it 9 9 + * under the terms and conditions of the GNU General Public License, 10 10 + * version 2, as published by the Free Software Foundation. 11 11 + * 12 12 + * This program is distributed in the hope it will be useful, but WITHOUT 13 13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 15 + * more details. 16 16 + * 17 17 + * You should have received a copy of the GNU General Public License along with 18 18 + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 19 19 + * Place - Suite 330, Boston, MA 02111-1307 USA. 20 20 + * 21 21 + */ 22 22 + #include <linux/pci.h> 23 23 + #include <linux/msi.h> 24 24 + #include <asm/mach/irq.h> 25 25 + #include <asm/irq.h> 26 26 + 27 27 + 28 28 + #define IOP13XX_NUM_MSI_IRQS 128 29 29 + static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); 30 30 + 31 31 + /* IMIPR0 CP6 R8 Page 1 32 32 + */ 33 33 + static inline u32 read_imipr_0(void) 34 34 + { 35 35 + u32 val; 36 36 + asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); 37 37 + return val; 38 38 + } 39 39 + static inline void write_imipr_0(u32 val) 40 40 + { 41 41 + asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); 42 42 + } 43 43 + 44 44 + /* IMIPR1 CP6 R9 Page 1 45 45 + */ 46 46 + static inline u32 read_imipr_1(void) 47 47 + { 48 48 + u32 val; 49 49 + asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); 50 50 + return val; 51 51 + } 52 52 + static inline void write_imipr_1(u32 val) 53 53 + { 54 54 + asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); 55 55 + } 56 56 + 57 57 + /* IMIPR2 CP6 R10 Page 1 58 58 + */ 59 59 + static inline u32 read_imipr_2(void) 60 60 + { 61 61 + u32 val; 62 62 + asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); 63 63 + return val; 64 64 + } 65 65 + static inline void write_imipr_2(u32 val) 66 66 + { 67 67 + asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); 68 68 + } 69 69 + 70 70 + /* IMIPR3 CP6 R11 Page 1 71 71 + */ 72 72 + static inline u32 read_imipr_3(void) 73 73 + { 74 74 + u32 val; 75 75 + asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); 76 76 + return val; 77 77 + } 78 78 + static inline void write_imipr_3(u32 val) 79 79 + { 80 80 + asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); 81 81 + } 82 82 + 83 83 + static u32 (*read_imipr[])(void) = { 84 84 + read_imipr_0, 85 85 + read_imipr_1, 86 86 + read_imipr_2, 87 87 + read_imipr_3, 88 88 + }; 89 89 + 90 90 + static void (*write_imipr[])(u32) = { 91 91 + write_imipr_0, 92 92 + write_imipr_1, 93 93 + write_imipr_2, 94 94 + write_imipr_3, 95 95 + }; 96 96 + 97 97 + static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) 98 98 + { 99 99 + int i, j; 100 100 + unsigned long status; 101 101 + 102 102 + /* read IMIPR registers and find any active interrupts, 103 103 + * then call ISR for each active interrupt 104 104 + */ 105 105 + for (i = 0; i < ARRAY_SIZE(read_imipr); i++) { 106 106 + status = (read_imipr[i])(); 107 107 + if (!status) 108 108 + continue; 109 109 + 110 110 + do { 111 111 + j = find_first_bit(&status, 32); 112 112 + (write_imipr[i])(1 << j); /* write back to clear bit */ 113 113 + desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i); 114 114 + desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc); 115 115 + status = (read_imipr[i])(); 116 116 + } while (status); 117 117 + } 118 118 + } 119 119 + 120 120 + void __init iop13xx_msi_init(void) 121 121 + { 122 122 + set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); 123 123 + } 124 124 + 125 125 + /* 126 126 + * Dynamic irq allocate and deallocation 127 127 + */ 128 128 + int create_irq(void) 129 129 + { 130 130 + int irq, pos; 131 131 + 132 132 + again: 133 133 + pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); 134 134 + irq = IRQ_IOP13XX_MSI_0 + pos; 135 135 + if (irq > NR_IRQS) 136 136 + return -ENOSPC; 137 137 + /* test_and_set_bit operates on 32-bits at a time */ 138 138 + if (test_and_set_bit(pos, msi_irq_in_use)) 139 139 + goto again; 140 140 + 141 141 + dynamic_irq_init(irq); 142 142 + 143 143 + return irq; 144 144 + } 145 145 + 146 146 + void destroy_irq(unsigned int irq) 147 147 + { 148 148 + int pos = irq - IRQ_IOP13XX_MSI_0; 149 149 + 150 150 + dynamic_irq_cleanup(irq); 151 151 + 152 152 + clear_bit(pos, msi_irq_in_use); 153 153 + } 154 154 + 155 155 + void arch_teardown_msi_irq(unsigned int irq) 156 156 + { 157 157 + destroy_irq(irq); 158 158 + } 159 159 + 160 160 + static void iop13xx_msi_nop(unsigned int irq) 161 161 + { 162 162 + return; 163 163 + } 164 164 + 165 165 + static struct irq_chip iop13xx_msi_chip = { 166 166 + .name = "PCI-MSI", 167 167 + .ack = iop13xx_msi_nop, 168 168 + .enable = unmask_msi_irq, 169 169 + .disable = mask_msi_irq, 170 170 + .mask = mask_msi_irq, 171 171 + .unmask = unmask_msi_irq, 172 172 + }; 173 173 + 174 174 + int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 175 175 + { 176 176 + int id, irq = create_irq(); 177 177 + struct msi_msg msg; 178 178 + 179 179 + if (irq < 0) 180 180 + return irq; 181 181 + 182 182 + set_irq_msi(irq, desc); 183 183 + 184 184 + msg.address_hi = 0x0; 185 185 + msg.address_lo = IOP13XX_MU_MIMR_PCI; 186 186 + 187 187 + id = iop13xx_cpu_id(); 188 188 + msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); 189 189 + 190 190 + write_msi_msg(irq, &msg); 191 191 + set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); 192 192 + 193 193 + return irq; 194 194 + }

+16

arch/arm/mach-iop13xx/pci.c

reviewed

··· 559 559 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE); 560 560 u32 reg_val; 561 561 562 562 + #ifdef CONFIG_PCI_MSI 563 563 + /* BAR 0 (inbound msi window) */ 564 564 + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); 565 565 + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); 566 566 + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); 567 567 + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); 568 568 + #endif 569 569 + 562 570 /* BAR 1 (1:1 mapping with Physical RAM) */ 563 571 /* Set limit and enable */ 564 572 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, ··· 727 719 } 728 720 else 729 721 atux_trhfa_timeout = jiffies; 722 722 + 723 723 + #ifdef CONFIG_PCI_MSI 724 724 + /* BAR 0 (inbound msi window) */ 725 725 + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); 726 726 + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); 727 727 + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); 728 728 + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); 729 729 + #endif 730 730 731 731 /* BAR 1 (1:1 mapping with Physical RAM) */ 732 732 /* Set limit and enable */

+13

arch/arm/mach-ks8695/Kconfig

reviewed

··· 1 1 + if ARCH_KS8695 2 2 + 3 3 + menu "Kendin/Micrel KS8695 Implementations" 4 4 + 5 5 + config MACH_KS8695 6 6 + bool "KS8695 development board" 7 7 + help 8 8 + Say 'Y' here if you want your kernel to run on the original 9 9 + Kendin-Micrel KS8695 development board. 10 10 + 11 11 + endmenu 12 12 + 13 13 + endif

+15

arch/arm/mach-ks8695/Makefile

reviewed

··· 1 1 + # arch/arm/mach-ks8695/Makefile 2 2 + # 3 3 + # Makefile for KS8695 architecture support 4 4 + # 5 5 + 6 6 + obj-y := cpu.o irq.o time.o devices.o 7 7 + obj-m := 8 8 + obj-n := 9 9 + obj- := 10 10 + 11 11 + # PCI support is optional 12 12 + #obj-$(CONFIG_PCI) += pci.o 13 13 + 14 14 + # Board-specific support 15 15 + obj-$(CONFIG_MACH_KS8695) += board-micrel.o

+8

arch/arm/mach-ks8695/Makefile.boot

reviewed

··· 1 1 + # Note: the following conditions must always be true: 2 2 + # ZRELADDR == virt_to_phys(TEXTADDR) 3 3 + # PARAMS_PHYS must be within 4MB of ZRELADDR 4 4 + # INITRD_PHYS must be in RAM 5 5 + 6 6 + zreladdr-y := 0x00008000 7 7 + params_phys-y := 0x00000100 8 8 + initrd_phys-y := 0x00800000

+60

arch/arm/mach-ks8695/board-micrel.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-ks8695/board-micrel.c 3 3 + * 4 4 + * This program is free software; you can redistribute it and/or modify 5 5 + * it under the terms of the GNU General Public License version 2 as 6 6 + * published by the Free Software Foundation. 7 7 + */ 8 8 + 9 9 + #include <linux/kernel.h> 10 10 + #include <linux/types.h> 11 11 + #include <linux/interrupt.h> 12 12 + #include <linux/init.h> 13 13 + #include <linux/platform_device.h> 14 14 + 15 15 + #include <asm/mach-types.h> 16 16 + 17 17 + #include <asm/mach/arch.h> 18 18 + #include <asm/mach/map.h> 19 19 + #include <asm/mach/irq.h> 20 20 + 21 21 + #include <asm/arch/devices.h> 22 22 + 23 23 + #include "generic.h" 24 24 + 25 25 + #ifdef CONFIG_PCI 26 26 + static int __init micrel_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 27 27 + { 28 28 + return KS8695_IRQ_EXTERN0; 29 29 + } 30 30 + 31 31 + static struct ks8695_pci_cfg micrel_pci = { 32 32 + .mode = KS8695_MODE_MINIPCI, 33 33 + .map_irq = micrel_pci_map_irq, 34 34 + }; 35 35 + #endif 36 36 + 37 37 + 38 38 + static void micrel_init(void) 39 39 + { 40 40 + printk(KERN_INFO "Micrel KS8695 Development Board initializing\n"); 41 41 + 42 42 + #ifdef CONFIG_PCI 43 43 + ks8695_init_pci(&micrel_pci); 44 44 + #endif 45 45 + 46 46 + /* Add devices */ 47 47 + ks8695_add_device_wan(); /* eth0 = WAN */ 48 48 + ks8695_add_device_lan(); /* eth1 = LAN */ 49 49 + } 50 50 + 51 51 + MACHINE_START(KS8695, "KS8695 Centaur Development Board") 52 52 + /* Maintainer: Micrel Semiconductor Inc. */ 53 53 + .phys_io = KS8695_IO_PA, 54 54 + .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc, 55 55 + .boot_params = KS8695_SDRAM_PA + 0x100, 56 56 + .map_io = ks8695_map_io, 57 57 + .init_irq = ks8695_init_irq, 58 58 + .init_machine = micrel_init, 59 59 + .timer = &ks8695_timer, 60 60 + MACHINE_END

+73

arch/arm/mach-ks8695/cpu.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-ks8695/cpu.c 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 CPU support 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License as published by 11 11 + * the Free Software Foundation; either version 2 of the License, or 12 12 + * (at your option) any later version. 13 13 + * 14 14 + * This program is distributed in the hope that it will be useful, 15 15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 17 + * GNU General Public License for more details. 18 18 + * 19 19 + * You should have received a copy of the GNU General Public License 20 20 + * along with this program; if not, write to the Free Software 21 21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 22 + */ 23 23 + 24 24 + #include <linux/kernel.h> 25 25 + #include <linux/module.h> 26 26 + #include <linux/init.h> 27 27 + 28 28 + #include <asm/hardware.h> 29 29 + #include <asm/io.h> 30 30 + #include <asm/mach/arch.h> 31 31 + #include <asm/mach/map.h> 32 32 + 33 33 + #include <asm/arch/regs-sys.h> 34 34 + #include <asm/arch/regs-misc.h> 35 35 + 36 36 + 37 37 + static struct __initdata map_desc ks8695_io_desc[] = { 38 38 + { 39 39 + .virtual = KS8695_IO_VA, 40 40 + .pfn = __phys_to_pfn(KS8695_IO_PA), 41 41 + .length = KS8695_IO_SIZE, 42 42 + .type = MT_DEVICE, 43 43 + } 44 44 + }; 45 45 + 46 46 + static void __init ks8695_processor_info(void) 47 47 + { 48 48 + unsigned long id, rev; 49 49 + 50 50 + id = __raw_readl(KS8695_MISC_VA + KS8695_DID); 51 51 + rev = __raw_readl(KS8695_MISC_VA + KS8695_RID); 52 52 + 53 53 + printk("KS8695 ID=%04lx SubID=%02lx Revision=%02lx\n", (id & DID_ID), (rev & RID_SUBID), (rev & RID_REVISION)); 54 54 + } 55 55 + 56 56 + static unsigned int sysclk[8] = { 125000000, 100000000, 62500000, 50000000, 41700000, 33300000, 31300000, 25000000 }; 57 57 + static unsigned int cpuclk[8] = { 166000000, 166000000, 83000000, 83000000, 55300000, 55300000, 41500000, 41500000 }; 58 58 + 59 59 + static void __init ks8695_clock_info(void) 60 60 + { 61 61 + unsigned int scdc = __raw_readl(KS8695_SYS_VA + KS8695_CLKCON) & CLKCON_SCDC; 62 62 + 63 63 + printk("Clocks: System %u MHz, CPU %u MHz\n", 64 64 + sysclk[scdc] / 1000000, cpuclk[scdc] / 1000000); 65 65 + } 66 66 + 67 67 + void __init ks8695_map_io(void) 68 68 + { 69 69 + iotable_init(ks8695_io_desc, ARRAY_SIZE(ks8695_io_desc)); 70 70 + 71 71 + ks8695_processor_info(); 72 72 + ks8695_clock_info(); 73 73 + }

+191

arch/arm/mach-ks8695/devices.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-ks8695/devices.c 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License as published by 8 8 + * the Free Software Foundation. 9 9 + * 10 10 + * This program is distributed in the hope that it will be useful, 11 11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 13 + * GNU General Public License for more details. 14 14 + * 15 15 + * You should have received a copy of the GNU General Public License 16 16 + * along with this program; if not, write to the Free Software 17 17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 18 + */ 19 19 + 20 20 + #include <asm/mach/arch.h> 21 21 + #include <asm/mach/map.h> 22 22 + 23 23 + #include <linux/platform_device.h> 24 24 + 25 25 + #include <asm/arch/regs-wan.h> 26 26 + #include <asm/arch/regs-lan.h> 27 27 + #include <asm/arch/regs-hpna.h> 28 28 + 29 29 + 30 30 + /* -------------------------------------------------------------------- 31 31 + * Ethernet 32 32 + * -------------------------------------------------------------------- */ 33 33 + 34 34 + #if defined(CONFIG_ARM_KS8695_ETHER) || defined(CONFIG_ARM_KS8695_ETHER_MODULE) 35 35 + static u64 eth_dmamask = 0xffffffffUL; 36 36 + 37 37 + static struct resource ks8695_wan_resources[] = { 38 38 + [0] = { 39 39 + .start = KS8695_WAN_VA, 40 40 + .end = KS8695_WAN_VA + 0x00ff, 41 41 + .flags = IORESOURCE_MEM, 42 42 + }, 43 43 + [1] = { 44 44 + .name = "WAN RX", 45 45 + .start = KS8695_IRQ_WAN_RX_STATUS, 46 46 + .end = KS8695_IRQ_WAN_RX_STATUS, 47 47 + .flags = IORESOURCE_IRQ, 48 48 + }, 49 49 + [2] = { 50 50 + .name = "WAN TX", 51 51 + .start = KS8695_IRQ_WAN_TX_STATUS, 52 52 + .end = KS8695_IRQ_WAN_TX_STATUS, 53 53 + .flags = IORESOURCE_IRQ, 54 54 + }, 55 55 + [3] = { 56 56 + .name = "WAN Link", 57 57 + .start = KS8695_IRQ_WAN_LINK, 58 58 + .end = KS8695_IRQ_WAN_LINK, 59 59 + .flags = IORESOURCE_IRQ, 60 60 + }, 61 61 + }; 62 62 + 63 63 + static struct platform_device ks8695_wan_device = { 64 64 + .name = "ks8695_ether", 65 65 + .id = 0, 66 66 + .dev = { 67 67 + .dma_mask = &eth_dmamask, 68 68 + .coherent_dma_mask = 0xffffffff, 69 69 + }, 70 70 + .resource = ks8695_wan_resources, 71 71 + .num_resources = ARRAY_SIZE(ks8695_wan_resources), 72 72 + }; 73 73 + 74 74 + 75 75 + static struct resource ks8695_lan_resources[] = { 76 76 + [0] = { 77 77 + .start = KS8695_LAN_VA, 78 78 + .end = KS8695_LAN_VA + 0x00ff, 79 79 + .flags = IORESOURCE_MEM, 80 80 + }, 81 81 + [1] = { 82 82 + .name = "LAN RX", 83 83 + .start = KS8695_IRQ_LAN_RX_STATUS, 84 84 + .end = KS8695_IRQ_LAN_RX_STATUS, 85 85 + .flags = IORESOURCE_IRQ, 86 86 + }, 87 87 + [2] = { 88 88 + .name = "LAN TX", 89 89 + .start = KS8695_IRQ_LAN_TX_STATUS, 90 90 + .end = KS8695_IRQ_LAN_TX_STATUS, 91 91 + .flags = IORESOURCE_IRQ, 92 92 + }, 93 93 + }; 94 94 + 95 95 + static struct platform_device ks8695_lan_device = { 96 96 + .name = "ks8695_ether", 97 97 + .id = 1, 98 98 + .dev = { 99 99 + .dma_mask = &eth_dmamask, 100 100 + .coherent_dma_mask = 0xffffffff, 101 101 + }, 102 102 + .resource = ks8695_lan_resources, 103 103 + .num_resources = ARRAY_SIZE(ks8695_lan_resources), 104 104 + }; 105 105 + 106 106 + 107 107 + static struct resource ks8695_hpna_resources[] = { 108 108 + [0] = { 109 109 + .start = KS8695_HPNA_VA, 110 110 + .end = KS8695_HPNA_VA + 0x00ff, 111 111 + .flags = IORESOURCE_MEM, 112 112 + }, 113 113 + [1] = { 114 114 + .name = "HPNA RX", 115 115 + .start = KS8695_IRQ_HPNA_RX_STATUS, 116 116 + .end = KS8695_IRQ_HPNA_RX_STATUS, 117 117 + .flags = IORESOURCE_IRQ, 118 118 + }, 119 119 + [2] = { 120 120 + .name = "HPNA TX", 121 121 + .start = KS8695_IRQ_HPNA_TX_STATUS, 122 122 + .end = KS8695_IRQ_HPNA_TX_STATUS, 123 123 + .flags = IORESOURCE_IRQ, 124 124 + }, 125 125 + }; 126 126 + 127 127 + static struct platform_device ks8695_hpna_device = { 128 128 + .name = "ks8695_ether", 129 129 + .id = 2, 130 130 + .dev = { 131 131 + .dma_mask = &eth_dmamask, 132 132 + .coherent_dma_mask = 0xffffffff, 133 133 + }, 134 134 + .resource = ks8695_hpna_resources, 135 135 + .num_resources = ARRAY_SIZE(ks8695_hpna_resources), 136 136 + }; 137 137 + 138 138 + void __init ks8695_add_device_wan(void) 139 139 + { 140 140 + platform_device_register(&ks8695_wan_device); 141 141 + } 142 142 + 143 143 + void __init ks8695_add_device_lan(void) 144 144 + { 145 145 + platform_device_register(&ks8695_lan_device); 146 146 + } 147 147 + 148 148 + void __init ks8696_add_device_hpna(void) 149 149 + { 150 150 + platform_device_register(&ks8695_hpna_device); 151 151 + } 152 152 + #else 153 153 + void __init ks8695_add_device_wan(void) {} 154 154 + void __init ks8695_add_device_lan(void) {} 155 155 + void __init ks8696_add_device_hpna(void) {} 156 156 + #endif 157 157 + 158 158 + 159 159 + /* -------------------------------------------------------------------- 160 160 + * Watchdog 161 161 + * -------------------------------------------------------------------- */ 162 162 + 163 163 + #if defined(CONFIG_KS8695_WATCHDOG) || defined(CONFIG_KS8695_WATCHDOG_MODULE) 164 164 + static struct platform_device ks8695_wdt_device = { 165 165 + .name = "ks8695_wdt", 166 166 + .id = -1, 167 167 + .num_resources = 0, 168 168 + }; 169 169 + 170 170 + static void __init ks8695_add_device_watchdog(void) 171 171 + { 172 172 + platform_device_register(&ks8695_wdt_device); 173 173 + } 174 174 + #else 175 175 + static void __init ks8695_add_device_watchdog(void) {} 176 176 + #endif 177 177 + 178 178 + 179 179 + /* -------------------------------------------------------------------- */ 180 180 + 181 181 + /* 182 182 + * These devices are always present and don't need any board-specific 183 183 + * setup. 184 184 + */ 185 185 + static int __init ks8695_add_standard_devices(void) 186 186 + { 187 187 + ks8695_add_device_watchdog(); 188 188 + return 0; 189 189 + } 190 190 + 191 191 + arch_initcall(ks8695_add_standard_devices);

+15

arch/arm/mach-ks8695/generic.h

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-ks8695/generic.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * This program is free software; you can redistribute it and/or modify 8 8 + * it under the terms of the GNU General Public License as published by 9 9 + * the Free Software Foundation; either version 2 of the License, or 10 10 + * (at your option) any later version. 11 11 + */ 12 12 + 13 13 + extern __init void ks8695_map_io(void); 14 14 + extern __init void ks8695_init_irq(void); 15 15 + extern struct sys_timer ks8695_timer;

+175

arch/arm/mach-ks8695/irq.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-ks8695/irq.c 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * This program is free software; you can redistribute it and/or modify 8 8 + * it under the terms of the GNU General Public License as published by 9 9 + * the Free Software Foundation; either version 2 of the License, or 10 10 + * (at your option) any later version. 11 11 + * 12 12 + * This program is distributed in the hope that it will be useful, 13 13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 15 + * GNU General Public License for more details. 16 16 + * 17 17 + * You should have received a copy of the GNU General Public License 18 18 + * along with this program; if not, write to the Free Software 19 19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 20 + */ 21 21 + 22 22 + #include <linux/init.h> 23 23 + #include <linux/module.h> 24 24 + #include <linux/interrupt.h> 25 25 + #include <linux/ioport.h> 26 26 + #include <linux/ptrace.h> 27 27 + #include <linux/sysdev.h> 28 28 + 29 29 + #include <asm/hardware.h> 30 30 + #include <asm/irq.h> 31 31 + #include <asm/io.h> 32 32 + 33 33 + #include <asm/mach/irq.h> 34 34 + 35 35 + #include <asm/arch/regs-irq.h> 36 36 + #include <asm/arch/regs-gpio.h> 37 37 + 38 38 + static void ks8695_irq_mask(unsigned int irqno) 39 39 + { 40 40 + unsigned long inten; 41 41 + 42 42 + inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); 43 43 + inten &= ~(1 << irqno); 44 44 + 45 45 + __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); 46 46 + } 47 47 + 48 48 + static void ks8695_irq_unmask(unsigned int irqno) 49 49 + { 50 50 + unsigned long inten; 51 51 + 52 52 + inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); 53 53 + inten |= (1 << irqno); 54 54 + 55 55 + __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); 56 56 + } 57 57 + 58 58 + static void ks8695_irq_ack(unsigned int irqno) 59 59 + { 60 60 + __raw_writel((1 << irqno), KS8695_IRQ_VA + KS8695_INTST); 61 61 + } 62 62 + 63 63 + 64 64 + static struct irq_chip ks8695_irq_level_chip; 65 65 + static struct irq_chip ks8695_irq_edge_chip; 66 66 + 67 67 + 68 68 + static int ks8695_irq_set_type(unsigned int irqno, unsigned int type) 69 69 + { 70 70 + unsigned long ctrl, mode; 71 71 + unsigned short level_triggered = 0; 72 72 + 73 73 + ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); 74 74 + 75 75 + switch (type) { 76 76 + case IRQT_HIGH: 77 77 + mode = IOPC_TM_HIGH; 78 78 + level_triggered = 1; 79 79 + break; 80 80 + case IRQT_LOW: 81 81 + mode = IOPC_TM_LOW; 82 82 + level_triggered = 1; 83 83 + break; 84 84 + case IRQT_RISING: 85 85 + mode = IOPC_TM_RISING; 86 86 + break; 87 87 + case IRQT_FALLING: 88 88 + mode = IOPC_TM_FALLING; 89 89 + break; 90 90 + case IRQT_BOTHEDGE: 91 91 + mode = IOPC_TM_EDGE; 92 92 + break; 93 93 + default: 94 94 + return -EINVAL; 95 95 + } 96 96 + 97 97 + switch (irqno) { 98 98 + case KS8695_IRQ_EXTERN0: 99 99 + ctrl &= ~IOPC_IOEINT0TM; 100 100 + ctrl |= IOPC_IOEINT0_MODE(mode); 101 101 + break; 102 102 + case KS8695_IRQ_EXTERN1: 103 103 + ctrl &= ~IOPC_IOEINT1TM; 104 104 + ctrl |= IOPC_IOEINT1_MODE(mode); 105 105 + break; 106 106 + case KS8695_IRQ_EXTERN2: 107 107 + ctrl &= ~IOPC_IOEINT2TM; 108 108 + ctrl |= IOPC_IOEINT2_MODE(mode); 109 109 + break; 110 110 + case KS8695_IRQ_EXTERN3: 111 111 + ctrl &= ~IOPC_IOEINT3TM; 112 112 + ctrl |= IOPC_IOEINT3_MODE(mode); 113 113 + break; 114 114 + default: 115 115 + return -EINVAL; 116 116 + } 117 117 + 118 118 + if (level_triggered) { 119 119 + set_irq_chip(irqno, &ks8695_irq_level_chip); 120 120 + set_irq_handler(irqno, handle_level_irq); 121 121 + } 122 122 + else { 123 123 + set_irq_chip(irqno, &ks8695_irq_edge_chip); 124 124 + set_irq_handler(irqno, handle_edge_irq); 125 125 + } 126 126 + 127 127 + __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); 128 128 + return 0; 129 129 + } 130 130 + 131 131 + static struct irq_chip ks8695_irq_level_chip = { 132 132 + .ack = ks8695_irq_mask, 133 133 + .mask = ks8695_irq_mask, 134 134 + .unmask = ks8695_irq_unmask, 135 135 + .set_type = ks8695_irq_set_type, 136 136 + }; 137 137 + 138 138 + static struct irq_chip ks8695_irq_edge_chip = { 139 139 + .ack = ks8695_irq_ack, 140 140 + .mask = ks8695_irq_mask, 141 141 + .unmask = ks8695_irq_unmask, 142 142 + .set_type = ks8695_irq_set_type, 143 143 + }; 144 144 + 145 145 + void __init ks8695_init_irq(void) 146 146 + { 147 147 + unsigned int irq; 148 148 + 149 149 + /* Disable all interrupts initially */ 150 150 + __raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC); 151 151 + __raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN); 152 152 + 153 153 + for (irq = 0; irq < NR_IRQS; irq++) { 154 154 + switch (irq) { 155 155 + /* Level-triggered interrupts */ 156 156 + case KS8695_IRQ_BUS_ERROR: 157 157 + case KS8695_IRQ_UART_MODEM_STATUS: 158 158 + case KS8695_IRQ_UART_LINE_STATUS: 159 159 + case KS8695_IRQ_UART_RX: 160 160 + case KS8695_IRQ_COMM_TX: 161 161 + case KS8695_IRQ_COMM_RX: 162 162 + set_irq_chip(irq, &ks8695_irq_level_chip); 163 163 + set_irq_handler(irq, handle_level_irq); 164 164 + break; 165 165 + 166 166 + /* Edge-triggered interrupts */ 167 167 + default: 168 168 + ks8695_irq_ack(irq); /* clear pending bit */ 169 169 + set_irq_chip(irq, &ks8695_irq_edge_chip); 170 170 + set_irq_handler(irq, handle_edge_irq); 171 171 + } 172 172 + 173 173 + set_irq_flags(irq, IRQF_VALID); 174 174 + } 175 175 + }

+114

arch/arm/mach-ks8695/time.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-ks8695/time.c 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * This program is free software; you can redistribute it and/or modify 8 8 + * it under the terms of the GNU General Public License as published by 9 9 + * the Free Software Foundation; either version 2 of the License, or 10 10 + * (at your option) any later version. 11 11 + * 12 12 + * This program is distributed in the hope that it will be useful, 13 13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 15 + * GNU General Public License for more details. 16 16 + * 17 17 + * You should have received a copy of the GNU General Public License 18 18 + * along with this program; if not, write to the Free Software 19 19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 20 + */ 21 21 + 22 22 + #include <linux/init.h> 23 23 + #include <linux/interrupt.h> 24 24 + #include <linux/irq.h> 25 25 + #include <linux/kernel.h> 26 26 + #include <linux/sched.h> 27 27 + 28 28 + #include <asm/io.h> 29 29 + #include <asm/mach/time.h> 30 30 + 31 31 + #include <asm/arch/regs-timer.h> 32 32 + #include <asm/arch/regs-irq.h> 33 33 + 34 34 + #include "generic.h" 35 35 + 36 36 + /* 37 37 + * Returns number of ms since last clock interrupt. Note that interrupts 38 38 + * will have been disabled by do_gettimeoffset() 39 39 + */ 40 40 + static unsigned long ks8695_gettimeoffset (void) 41 41 + { 42 42 + unsigned long elapsed, tick2, intpending; 43 43 + 44 44 + /* 45 45 + * Get the current number of ticks. Note that there is a race 46 46 + * condition between us reading the timer and checking for an 47 47 + * interrupt. We solve this by ensuring that the counter has not 48 48 + * reloaded between our two reads. 49 49 + */ 50 50 + elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); 51 51 + do { 52 52 + tick2 = elapsed; 53 53 + intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1); 54 54 + elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); 55 55 + } while (elapsed > tick2); 56 56 + 57 57 + /* Convert to number of ticks expired (not remaining) */ 58 58 + elapsed = (CLOCK_TICK_RATE / HZ) - elapsed; 59 59 + 60 60 + /* Is interrupt pending? If so, then timer has been reloaded already. */ 61 61 + if (intpending) 62 62 + elapsed += (CLOCK_TICK_RATE / HZ); 63 63 + 64 64 + /* Convert ticks to usecs */ 65 65 + return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; 66 66 + } 67 67 + 68 68 + /* 69 69 + * IRQ handler for the timer. 70 70 + */ 71 71 + static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id) 72 72 + { 73 73 + write_seqlock(&xtime_lock); 74 74 + timer_tick(); 75 75 + write_sequnlock(&xtime_lock); 76 76 + 77 77 + return IRQ_HANDLED; 78 78 + } 79 79 + 80 80 + static struct irqaction ks8695_timer_irq = { 81 81 + .name = "ks8695_tick", 82 82 + .flags = IRQF_DISABLED | IRQF_TIMER, 83 83 + .handler = ks8695_timer_interrupt, 84 84 + }; 85 85 + 86 86 + static void ks8695_timer_setup(void) 87 87 + { 88 88 + unsigned long tmout = CLOCK_TICK_RATE / HZ; 89 89 + unsigned long tmcon; 90 90 + 91 91 + /* disable timer1 */ 92 92 + tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); 93 93 + __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); 94 94 + 95 95 + __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC); 96 96 + __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD); 97 97 + 98 98 + /* re-enable timer1 */ 99 99 + __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); 100 100 + } 101 101 + 102 102 + static void __init ks8695_timer_init (void) 103 103 + { 104 104 + ks8695_timer_setup(); 105 105 + 106 106 + /* Enable timer interrupts */ 107 107 + setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq); 108 108 + } 109 109 + 110 110 + struct sys_timer ks8695_timer = { 111 111 + .init = ks8695_timer_init, 112 112 + .offset = ks8695_gettimeoffset, 113 113 + .resume = ks8695_timer_setup, 114 114 + };

+1 -1

arch/arm/mach-omap1/board-h2.c

reviewed

··· 326 326 .ctrl_name = "internal", 327 327 }; 328 328 329 329 - static struct omap_board_config_kernel h2_config[] = { 329 329 + static struct omap_board_config_kernel h2_config[] __initdata = { 330 330 { OMAP_TAG_USB, &h2_usb_config }, 331 331 { OMAP_TAG_MMC, &h2_mmc_config }, 332 332 { OMAP_TAG_UART, &h2_uart_config },

+1 -10

arch/arm/mach-omap1/pm.c

reviewed

··· 1 1 - //kernel/linux-omap-fsample/arch/arm/mach-omap1/pm.c#3 - integrate change 4545 (text) 2 1 /* 3 2 * linux/arch/arm/mach-omap1/pm.c 4 3 * ··· 376 377 * Jump to assembly code. The processor will stay there 377 378 * until wake up. 378 379 */ 379 379 - omap_sram_suspend(arg0, arg1); 380 380 + omap_sram_suspend(arg0, arg1); 380 381 381 382 /* 382 383 * If we are here, processor is woken up! ··· 630 631 case PM_SUSPEND_STANDBY: 631 632 case PM_SUSPEND_MEM: 632 633 break; 633 633 - 634 634 - case PM_SUSPEND_DISK: 635 635 - return -ENOTSUPP; 636 636 - 637 634 default: 638 635 return -EINVAL; 639 636 } ··· 652 657 case PM_SUSPEND_MEM: 653 658 omap_pm_suspend(); 654 659 break; 655 655 - 656 656 - case PM_SUSPEND_DISK: 657 657 - return -ENOTSUPP; 658 658 - 659 660 default: 660 661 return -EINVAL; 661 662 }

+1 -1

arch/arm/mach-omap2/gpmc.c

reviewed

··· 54 54 55 55 static struct resource gpmc_mem_root; 56 56 static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 57 57 - static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED; 57 57 + static DEFINE_SPINLOCK(gpmc_mem_lock); 58 58 static unsigned gpmc_cs_map; 59 59 60 60 static void __iomem *gpmc_base =

+31 -2

arch/arm/mach-omap2/mux.c

reviewed

··· 43 43 /* 24xx I2C */ 44 44 MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1) 45 45 MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1) 46 46 - MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 0, 1) 46 46 + MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1) 47 47 MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1) 48 48 49 49 /* Menelaus interrupt */ ··· 52 52 /* 24xx clocks */ 53 53 MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) 54 54 55 55 - /* 24xx GPMC wait pin monitoring */ 55 55 + /* 24xx GPMC chipselects, wait pin monitoring */ 56 56 + MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) 57 57 + MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) 56 58 MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1) 57 59 MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1) 58 60 MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1) ··· 68 66 69 67 /* 24xx GPIO */ 70 68 MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) 69 69 + MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) 71 70 MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) 72 71 MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) 73 72 MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) ··· 78 75 MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) 79 76 MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) 80 77 MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) 78 78 + MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) 81 79 MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) 80 80 + MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) 82 81 83 82 /* 242x DBG GPIO */ 84 83 MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1) ··· 122 117 MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1) 123 118 MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1) 124 119 MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1) 120 120 + 121 121 + /* Full speed USB */ 122 122 + MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1) 123 123 + MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1) 124 124 + MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1) 125 125 + MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1) 126 126 + MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1) 127 127 + MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1) 128 128 + MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1) 129 129 + 130 130 + MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1) 131 131 + MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1) 132 132 + MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1) 133 133 + MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1) 134 134 + MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1) 135 135 + MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1) 136 136 + MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1) 137 137 + MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1) 138 138 + 139 139 + MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1) 140 140 + MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1) 141 141 + MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1) 142 142 + MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1) 143 143 + MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1) 125 144 126 145 /* Keypad GPIO*/ 127 146 MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)

+2 -2

arch/arm/mach-pnx4008/dma.c

reviewed

··· 47 47 int count; 48 48 } ll_pool; 49 49 50 50 - static spinlock_t ll_lock = SPIN_LOCK_UNLOCKED; 50 50 + static DEFINE_SPINLOCK(ll_lock); 51 51 52 52 struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma) 53 53 { ··· 135 135 } 136 136 } 137 137 138 138 - static spinlock_t dma_lock = SPIN_LOCK_UNLOCKED; 138 138 + static DEFINE_SPINLOCK(dma_lock); 139 139 140 140 static inline void pnx4008_dma_lock(void) 141 141 {

+49 -13

arch/arm/mach-pxa/trizeps4.c

reviewed

··· 24 24 #include <linux/delay.h> 25 25 #include <linux/serial_8250.h> 26 26 #include <linux/mtd/mtd.h> 27 27 + #include <linux/mtd/physmap.h> 27 28 #include <linux/mtd/partitions.h> 28 29 29 30 #include <asm/types.h> ··· 56 55 static struct mtd_partition trizeps4_partitions[] = { 57 56 { 58 57 .name = "Bootloader", 58 58 + .offset = 0x00000000, 59 59 .size = 0x00040000, 60 60 - .offset = 0, 61 60 .mask_flags = MTD_WRITEABLE /* force read-only */ 62 61 },{ 63 63 - .name = "Kernel", 64 64 - .size = 0x00400000, 65 65 - .offset = 0x00040000 62 62 + .name = "Backup", 63 63 + .offset = 0x00040000, 64 64 + .size = 0x00040000, 66 65 },{ 67 67 - .name = "Filesystem", 66 66 + .name = "Image", 67 67 + .offset = 0x00080000, 68 68 + .size = 0x01080000, 69 69 + },{ 70 70 + .name = "IPSM", 71 71 + .offset = 0x01100000, 72 72 + .size = 0x00e00000, 73 73 + },{ 74 74 + .name = "Registry", 75 75 + .offset = 0x01f00000, 68 76 .size = MTDPART_SIZ_FULL, 69 69 - .offset = 0x00440000 70 77 } 71 78 }; 72 79 73 73 - static struct flash_platform_data trizeps4_flash_data[] = { 80 80 + static struct physmap_flash_data trizeps4_flash_data[] = { 74 81 { 75 75 - .map_name = "cfi_probe", 82 82 + .width = 4, /* bankwidth in bytes */ 76 83 .parts = trizeps4_partitions, 77 84 .nr_parts = ARRAY_SIZE(trizeps4_partitions) 78 85 } ··· 88 79 89 80 static struct resource flash_resource = { 90 81 .start = PXA_CS0_PHYS, 91 91 - .end = PXA_CS0_PHYS + SZ_64M - 1, 82 82 + .end = PXA_CS0_PHYS + SZ_32M - 1, 92 83 .flags = IORESOURCE_MEM, 93 84 }; 94 85 95 86 static struct platform_device flash_device = { 96 96 - .name = "pxa2xx-flash", 87 87 + .name = "physmap-flash", 97 88 .id = 0, 98 89 .dev = { 99 99 - .platform_data = &trizeps4_flash_data, 90 90 + .platform_data = trizeps4_flash_data, 100 91 }, 101 92 .resource = &flash_resource, 102 93 .num_resources = 1, ··· 402 393 .pxafb_backlight_power = board_backlight_power, 403 394 }; 404 395 396 396 + static struct pxafb_mode_info toshiba_lcd_mode = { 397 397 + .pixclock = 39720, 398 398 + .xres = 640, 399 399 + .yres = 480, 400 400 + .bpp = 8, 401 401 + .hsync_len = 63, 402 402 + .left_margin = 12, 403 403 + .right_margin = 12, 404 404 + .vsync_len = 4, 405 405 + .upper_margin = 32, 406 406 + .lower_margin = 10, 407 407 + .sync = 0, 408 408 + .cmap_greyscale = 0, 409 409 + }; 410 410 + 411 411 + static struct pxafb_mach_info toshiba_lcd = { 412 412 + .modes = &toshiba_lcd_mode, 413 413 + .num_modes = 1, 414 414 + .cmap_inverse = 0, 415 415 + .cmap_static = 0, 416 416 + .lccr0 = LCCR0_Color | LCCR0_Act, 417 417 + .lccr3 = 0x03400002, 418 418 + .pxafb_backlight_power = board_backlight_power, 419 419 + }; 420 420 + 405 421 static void __init trizeps4_init(void) 406 422 { 407 423 platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices)); 408 424 409 409 - set_pxa_fb_info(&sharp_lcd); 425 425 + /* set_pxa_fb_info(&sharp_lcd); */ 426 426 + set_pxa_fb_info(&toshiba_lcd); 410 427 411 428 pxa_set_mci_info(&trizeps4_mci_platform_data); 412 429 pxa_set_ficp_info(&trizeps4_ficp_platform_data); ··· 471 436 /* whats that for ??? */ 472 437 pxa_gpio_mode(GPIO79_nCS_3_MD); 473 438 439 439 + #ifdef CONFIG_LEDS 474 440 pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */ 475 441 pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */ 476 476 - 442 442 + #endif 477 443 #ifdef CONFIG_MACH_TRIZEPS4_CONXS 478 444 #ifdef CONFIG_IDE_PXA_CF 479 445 /* if boot direct from compact flash dont disable power */

+1 -1

arch/arm/mach-s3c2410/Makefile

reviewed

··· 20 20 # Machine support 21 21 22 22 obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o 23 23 - obj-$(CONFIG_ARCH_H1940) += mach-h1940.o 23 23 + obj-$(CONFIG_ARCH_H1940) += mach-h1940.o h1940-bluetooth.o 24 24 obj-$(CONFIG_PM_H1940) += pm-h1940.o 25 25 obj-$(CONFIG_MACH_N30) += mach-n30.o 26 26 obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o

+142

arch/arm/mach-s3c2410/h1940-bluetooth.c

reviewed

··· 1 1 + /* 2 2 + * arch/arm/mach-s3c2410/h1940-bluetooth.c 3 3 + * Copyright (c) Arnaud Patard <arnaud.patard@rtp-net.org> 4 4 + * 5 5 + * This file is subject to the terms and conditions of the GNU General Public 6 6 + * License. See the file COPYING in the main directory of this archive for 7 7 + * more details. 8 8 + * 9 9 + * S3C2410 bluetooth "driver" 10 10 + * 11 11 + */ 12 12 + 13 13 + #include <linux/module.h> 14 14 + #include <linux/platform_device.h> 15 15 + #include <linux/delay.h> 16 16 + #include <linux/string.h> 17 17 + #include <linux/ctype.h> 18 18 + #include <linux/leds.h> 19 19 + #include <asm/arch/regs-gpio.h> 20 20 + #include <asm/hardware.h> 21 21 + #include <asm/arch/h1940-latch.h> 22 22 + 23 23 + #define DRV_NAME "h1940-bt" 24 24 + 25 25 + #ifdef CONFIG_LEDS_H1940 26 26 + DEFINE_LED_TRIGGER(bt_led_trigger); 27 27 + #endif 28 28 + 29 29 + static int state; 30 30 + 31 31 + /* Bluetooth control */ 32 32 + static void h1940bt_enable(int on) 33 33 + { 34 34 + if (on) { 35 35 + #ifdef CONFIG_LEDS_H1940 36 36 + /* flashing Blue */ 37 37 + led_trigger_event(bt_led_trigger, LED_HALF); 38 38 + #endif 39 39 + 40 40 + /* Power on the chip */ 41 41 + h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); 42 42 + /* Reset the chip */ 43 43 + mdelay(10); 44 44 + s3c2410_gpio_setpin(S3C2410_GPH1, 1); 45 45 + mdelay(10); 46 46 + s3c2410_gpio_setpin(S3C2410_GPH1, 0); 47 47 + 48 48 + state = 1; 49 49 + } 50 50 + else { 51 51 + #ifdef CONFIG_LEDS_H1940 52 52 + led_trigger_event(bt_led_trigger, 0); 53 53 + #endif 54 54 + 55 55 + s3c2410_gpio_setpin(S3C2410_GPH1, 1); 56 56 + mdelay(10); 57 57 + s3c2410_gpio_setpin(S3C2410_GPH1, 0); 58 58 + mdelay(10); 59 59 + h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); 60 60 + 61 61 + state = 0; 62 62 + } 63 63 + } 64 64 + 65 65 + static ssize_t h1940bt_show(struct device *dev, struct device_attribute *attr, char *buf) 66 66 + { 67 67 + return snprintf(buf, PAGE_SIZE, "%d\n", state); 68 68 + } 69 69 + 70 70 + static ssize_t h1940bt_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) 71 71 + { 72 72 + int new_state; 73 73 + char *endp; 74 74 + 75 75 + new_state = simple_strtoul(buf, &endp, 0); 76 76 + if (*endp && !isspace(*endp)) 77 77 + return -EINVAL; 78 78 + 79 79 + h1940bt_enable(new_state); 80 80 + 81 81 + return count; 82 82 + } 83 83 + static DEVICE_ATTR(enable, 0644, 84 84 + h1940bt_show, 85 85 + h1940bt_store); 86 86 + 87 87 + static int __init h1940bt_probe(struct platform_device *pdev) 88 88 + { 89 89 + /* Configures BT serial port GPIOs */ 90 90 + s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0); 91 91 + s3c2410_gpio_pullup(S3C2410_GPH0, 1); 92 92 + s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP); 93 93 + s3c2410_gpio_pullup(S3C2410_GPH1, 1); 94 94 + s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0); 95 95 + s3c2410_gpio_pullup(S3C2410_GPH2, 1); 96 96 + s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0); 97 97 + s3c2410_gpio_pullup(S3C2410_GPH3, 1); 98 98 + 99 99 + #ifdef CONFIG_LEDS_H1940 100 100 + led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); 101 101 + #endif 102 102 + 103 103 + /* disable BT by default */ 104 104 + h1940bt_enable(0); 105 105 + 106 106 + return device_create_file(&pdev->dev, &dev_attr_enable); 107 107 + } 108 108 + 109 109 + static int h1940bt_remove(struct platform_device *pdev) 110 110 + { 111 111 + #ifdef CONFIG_LEDS_H1940 112 112 + led_trigger_unregister_simple(bt_led_trigger); 113 113 + #endif 114 114 + return 0; 115 115 + } 116 116 + 117 117 + 118 118 + static struct platform_driver h1940bt_driver = { 119 119 + .driver = { 120 120 + .name = DRV_NAME, 121 121 + }, 122 122 + .probe = h1940bt_probe, 123 123 + .remove = h1940bt_remove, 124 124 + }; 125 125 + 126 126 + 127 127 + static int __init h1940bt_init(void) 128 128 + { 129 129 + return platform_driver_register(&h1940bt_driver); 130 130 + } 131 131 + 132 132 + static void __exit h1940bt_exit(void) 133 133 + { 134 134 + platform_driver_unregister(&h1940bt_driver); 135 135 + } 136 136 + 137 137 + module_init(h1940bt_init); 138 138 + module_exit(h1940bt_exit); 139 139 + 140 140 + MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); 141 141 + MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip"); 142 142 + MODULE_LICENSE("GPL");

+6

arch/arm/mach-s3c2410/mach-h1940.c

reviewed

··· 177 177 .id = -1, 178 178 }; 179 179 180 180 + static struct platform_device s3c_device_bluetooth = { 181 181 + .name = "h1940-bt", 182 182 + .id = -1, 183 183 + }; 184 184 + 180 185 static struct platform_device *h1940_devices[] __initdata = { 181 186 &s3c_device_usb, 182 187 &s3c_device_lcd, ··· 190 185 &s3c_device_iis, 191 186 &s3c_device_usbgadget, 192 187 &s3c_device_leds, 188 188 + &s3c_device_bluetooth, 193 189 }; 194 190 195 191 static void __init h1940_map_io(void)

+4

arch/arm/mach-s3c2443/clock.c

reviewed

··· 791 791 .name = "usb-bus-host", 792 792 .id = -1, 793 793 .parent = &clk_usb_bus_host, 794 794 + }, { .name = "ac97", 795 795 + .id = -1, 796 796 + .parent = &clk_p, 797 797 + .ctrlbit = S3C2443_PCLKCON_AC97, 794 798 } 795 799 }; 796 800

+5 -5

arch/arm/mm/Kconfig

reviewed

··· 131 131 # ARM922T 132 132 config CPU_ARM922T 133 133 bool "Support ARM922T processor" if ARCH_INTEGRATOR 134 134 - depends on ARCH_LH7A40X || ARCH_INTEGRATOR 135 135 - default y if ARCH_LH7A40X 134 134 + depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695 135 135 + default y if ARCH_LH7A40X || ARCH_KS8695 136 136 select CPU_32v4T 137 137 select CPU_ABRT_EV4T 138 138 select CPU_CACHE_V4WT ··· 143 143 help 144 144 The ARM922T is a version of the ARM920T, but with smaller 145 145 instruction and data caches. It is used in Altera's 146 146 - Excalibur XA device family. 146 146 + Excalibur XA device family and Micrel's KS8695 Centaur. 147 147 148 148 Say Y if you want support for the ARM922T processor. 149 149 Otherwise, say N. ··· 171 171 # ARM926T 172 172 config CPU_ARM926T 173 173 bool "Support ARM926T processor" 174 174 - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX 175 175 - default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX 174 174 + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI 175 175 + default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI 176 176 select CPU_32v5 177 177 select CPU_ABRT_EV5TJ 178 178 select CPU_CACHE_VIVT

+2 -2

arch/arm/plat-omap/dma.c

reviewed

··· 747 747 */ 748 748 dma_addr_t omap_get_dma_src_pos(int lch) 749 749 { 750 750 - dma_addr_t offset; 750 750 + dma_addr_t offset = 0; 751 751 752 752 if (cpu_class_is_omap1()) 753 753 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | ··· 769 769 */ 770 770 dma_addr_t omap_get_dma_dst_pos(int lch) 771 771 { 772 772 - dma_addr_t offset; 772 772 + dma_addr_t offset = 0; 773 773 774 774 if (cpu_class_is_omap1()) 775 775 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |

+15 -4

arch/arm/plat-omap/mux.c

reviewed

··· 83 83 reg |= OMAP24XX_PULL_ENA; 84 84 if(cfg->pu_pd_val) 85 85 reg |= OMAP24XX_PULL_UP; 86 86 - #ifdef CONFIG_OMAP_MUX_DEBUG 87 87 - printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n", 88 88 - cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg, 89 89 - omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg); 86 86 + #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) 87 87 + { 88 88 + u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); 89 89 + u8 debug = 0; 90 90 + 91 91 + #ifdef CONFIG_OMAP_MUX_DEBUG 92 92 + debug = cfg->debug; 93 93 + #endif 94 94 + warn = (orig != reg); 95 95 + if (debug || warn) 96 96 + printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", 97 97 + cfg->name, 98 98 + OMAP24XX_L4_BASE + cfg->mux_reg, 99 99 + orig, reg); 100 100 + } 90 101 #endif 91 102 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg); 92 103

+33 -1

arch/arm/tools/mach-types

reviewed

··· 12 12 # 13 13 # http://www.arm.linux.org.uk/developer/machines/?action=new 14 14 # 15 15 - # Last update: Mon Apr 16 21:01:04 2007 15 15 + # Last update: Fri May 11 19:53:41 2007 16 16 # 17 17 # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 18 18 # ··· 1335 1335 comtech_router MACH_COMTECH_ROUTER COMTECH_ROUTER 1327 1336 1336 sbc2410x MACH_SBC2410X SBC2410X 1328 1337 1337 at4x0bd MACH_AT4X0BD AT4X0BD 1329 1338 1338 + cbifr MACH_CBIFR CBIFR 1330 1339 1339 + arcom_quantum MACH_ARCOM_QUANTUM ARCOM_QUANTUM 1331 1340 1340 + matrix520 MACH_MATRIX520 MATRIX520 1332 1341 1341 + matrix510 MACH_MATRIX510 MATRIX510 1333 1342 1342 + matrix500 MACH_MATRIX500 MATRIX500 1334 1343 1343 + m501 MACH_M501 M501 1335 1344 1344 + aaeon1270 MACH_AAEON1270 AAEON1270 1336 1345 1345 + matrix500ev MACH_MATRIX500EV MATRIX500EV 1337 1346 1346 + pac500 MACH_PAC500 PAC500 1338 1347 1347 + pnx8181 MACH_PNX8181 PNX8181 1339 1348 1348 + colibri320 MACH_COLIBRI320 COLIBRI320 1340 1349 1349 + aztoolbb MACH_AZTOOLBB AZTOOLBB 1341 1350 1350 + aztoolg2 MACH_AZTOOLG2 AZTOOLG2 1342 1351 1351 + dvlhost MACH_DVLHOST DVLHOST 1343 1352 1352 + zir9200 MACH_ZIR9200 ZIR9200 1344 1353 1353 + zir9260 MACH_ZIR9260 ZIR9260 1345 1354 1354 + cocopah MACH_COCOPAH COCOPAH 1346 1355 1355 + nds MACH_NDS NDS 1347 1356 1356 + rosencrantz MACH_ROSENCRANTZ ROSENCRANTZ 1348 1357 1357 + fttx_odsc MACH_FTTX_ODSC FTTX_ODSC 1349 1358 1358 + classe_r6904 MACH_CLASSE_R6904 CLASSE_R6904 1350 1359 1359 + cam60 MACH_CAM60 CAM60 1351 1360 1360 + mxc30031ads MACH_MXC30031ADS MXC30031ADS 1352 1361 1361 + datacall MACH_DATACALL DATACALL 1353 1362 1362 + at91eb01 MACH_AT91EB01 AT91EB01 1354 1363 1363 + rty MACH_RTY RTY 1355 1364 1364 + dwl2100 MACH_DWL2100 DWL2100 1356 1365 1365 + vinsi MACH_VINSI VINSI 1357 1366 1366 + db88f5281 MACH_DB88F5281 DB88F5281 1358 1367 1367 + csb726 MACH_CSB726 CSB726 1359 1368 1368 + tik27 MACH_TIK27 TIK27 1360 1369 1369 + mx_uc7420 MACH_MX_UC7420 MX_UC7420 1361

+96 -88

drivers/ata/pata_icside.c

reviewed

··· 60 60 struct scatterlist sg[PATA_ICSIDE_MAX_SG]; 61 61 }; 62 62 63 63 + struct pata_icside_info { 64 64 + struct pata_icside_state *state; 65 65 + struct expansion_card *ec; 66 66 + void __iomem *base; 67 67 + void __iomem *irqaddr; 68 68 + unsigned int irqmask; 69 69 + const expansioncard_ops_t *irqops; 70 70 + unsigned int mwdma_mask; 71 71 + unsigned int nr_ports; 72 72 + const struct portinfo *port[2]; 73 73 + }; 74 74 + 63 75 #define ICS_TYPE_A3IN 0 64 76 #define ICS_TYPE_A3USER 1 65 77 #define ICS_TYPE_V6 3 ··· 281 269 return readb(irq_port) & 1 ? ATA_DMA_INTR : 0; 282 270 } 283 271 284 284 - static int icside_dma_init(struct ata_probe_ent *ae, struct expansion_card *ec) 272 272 + static int icside_dma_init(struct pata_icside_info *info) 285 273 { 286 286 - struct pata_icside_state *state = ae->private_data; 274 274 + struct pata_icside_state *state = info->state; 275 275 + struct expansion_card *ec = info->ec; 287 276 int i; 288 277 289 278 for (i = 0; i < ATA_MAX_DEVICES; i++) { ··· 294 281 295 282 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) { 296 283 state->dma = ec->dma; 297 297 - ae->mwdma_mask = 0x07; /* MW0..2 */ 284 284 + info->mwdma_mask = 0x07; /* MW0..2 */ 298 285 } 299 286 300 287 return 0; ··· 384 371 .check_status = ata_check_status, 385 372 .dev_select = ata_std_dev_select, 386 373 374 374 + .cable_detect = ata_cable_40wire, 375 375 + 387 376 .bmdma_setup = pata_icside_bmdma_setup, 388 377 .bmdma_start = pata_icside_bmdma_start, 389 378 ··· 400 385 .error_handler = ata_bmdma_error_handler, 401 386 .post_internal_cmd = pata_icside_bmdma_stop, 402 387 403 403 - .irq_handler = ata_interrupt, 404 388 .irq_clear = ata_dummy_noret, 405 389 .irq_on = ata_irq_on, 406 390 .irq_ack = pata_icside_irq_ack, ··· 410 396 .bmdma_status = pata_icside_bmdma_status, 411 397 }; 412 398 413 413 - static void 414 414 - pata_icside_add_port(struct ata_probe_ent *ae, void __iomem *base, 415 415 - const struct portinfo *info) 399 399 + static void __devinit 400 400 + pata_icside_setup_ioaddr(struct ata_ioports *ioaddr, void __iomem *base, 401 401 + const struct portinfo *info) 416 402 { 417 417 - struct ata_ioports *ioaddr = &ae->port[ae->n_ports++]; 418 403 void __iomem *cmd = base + info->dataoffset; 419 404 420 405 ioaddr->cmd_addr = cmd; ··· 432 419 ioaddr->altstatus_addr = ioaddr->ctl_addr; 433 420 } 434 421 435 435 - static int __init 436 436 - pata_icside_register_v5(struct ata_probe_ent *ae, struct expansion_card *ec) 422 422 + static int __devinit pata_icside_register_v5(struct pata_icside_info *info) 437 423 { 438 438 - struct pata_icside_state *state = ae->private_data; 424 424 + struct pata_icside_state *state = info->state; 439 425 void __iomem *base; 440 426 441 441 - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), 442 442 - ecard_resource_len(ec, ECARD_RES_MEMC)); 427 427 + base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0); 443 428 if (!base) 444 429 return -ENOMEM; 445 430 446 431 state->irq_port = base; 447 432 448 448 - ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; 449 449 - ec->irqmask = 1; 450 450 - ec->irq_data = state; 451 451 - ec->ops = &pata_icside_ops_arcin_v5; 452 452 - 453 453 - /* 454 454 - * Be on the safe side - disable interrupts 455 455 - */ 456 456 - ec->ops->irqdisable(ec, ec->irq); 457 457 - 458 458 - pata_icside_add_port(ae, base, &pata_icside_portinfo_v5); 433 433 + info->base = base; 434 434 + info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; 435 435 + info->irqmask = 1; 436 436 + info->irqops = &pata_icside_ops_arcin_v5; 437 437 + info->nr_ports = 1; 438 438 + info->port[0] = &pata_icside_portinfo_v5; 459 439 460 440 return 0; 461 441 } 462 442 463 463 - static int __init 464 464 - pata_icside_register_v6(struct ata_probe_ent *ae, struct expansion_card *ec) 443 443 + static int __devinit pata_icside_register_v6(struct pata_icside_info *info) 465 444 { 466 466 - struct pata_icside_state *state = ae->private_data; 445 445 + struct pata_icside_state *state = info->state; 446 446 + struct expansion_card *ec = info->ec; 467 447 void __iomem *ioc_base, *easi_base; 468 448 unsigned int sel = 0; 469 469 - int ret; 470 449 471 471 - ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), 472 472 - ecard_resource_len(ec, ECARD_RES_IOCFAST)); 473 473 - if (!ioc_base) { 474 474 - ret = -ENOMEM; 475 475 - goto out; 476 476 - } 450 450 + ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 451 451 + if (!ioc_base) 452 452 + return -ENOMEM; 477 453 478 454 easi_base = ioc_base; 479 455 480 456 if (ecard_resource_flags(ec, ECARD_RES_EASI)) { 481 481 - easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI), 482 482 - ecard_resource_len(ec, ECARD_RES_EASI)); 483 483 - if (!easi_base) { 484 484 - ret = -ENOMEM; 485 485 - goto unmap_slot; 486 486 - } 457 457 + easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); 458 458 + if (!easi_base) 459 459 + return -ENOMEM; 487 460 488 461 /* 489 462 * Enable access to the EASI region. ··· 479 480 480 481 writeb(sel, ioc_base); 481 482 482 482 - ec->irq_data = state; 483 483 - ec->ops = &pata_icside_ops_arcin_v6; 484 484 - 485 483 state->irq_port = easi_base; 486 484 state->ioc_base = ioc_base; 487 485 state->port[0].port_sel = sel; 488 486 state->port[1].port_sel = sel | 1; 489 489 - 490 490 - /* 491 491 - * Be on the safe side - disable interrupts 492 492 - */ 493 493 - ec->ops->irqdisable(ec, ec->irq); 494 494 - 495 495 - /* 496 496 - * Find and register the interfaces. 497 497 - */ 498 498 - pata_icside_add_port(ae, easi_base, &pata_icside_portinfo_v6_1); 499 499 - pata_icside_add_port(ae, easi_base, &pata_icside_portinfo_v6_2); 500 487 501 488 /* 502 489 * FIXME: work around libata's aversion to calling port_disable. ··· 491 506 */ 492 507 state->port[0].disabled = 1; 493 508 494 494 - return icside_dma_init(ae, ec); 509 509 + info->base = easi_base; 510 510 + info->irqops = &pata_icside_ops_arcin_v6; 511 511 + info->nr_ports = 2; 512 512 + info->port[0] = &pata_icside_portinfo_v6_1; 513 513 + info->port[1] = &pata_icside_portinfo_v6_2; 495 514 496 496 - unmap_slot: 497 497 - iounmap(ioc_base); 498 498 - out: 499 499 - return ret; 515 515 + return icside_dma_init(info); 516 516 + } 517 517 + 518 518 + static int __devinit pata_icside_add_ports(struct pata_icside_info *info) 519 519 + { 520 520 + struct expansion_card *ec = info->ec; 521 521 + struct ata_host *host; 522 522 + int i; 523 523 + 524 524 + if (info->irqaddr) { 525 525 + ec->irqaddr = info->irqaddr; 526 526 + ec->irqmask = info->irqmask; 527 527 + } 528 528 + if (info->irqops) 529 529 + ecard_setirq(ec, info->irqops, info->state); 530 530 + 531 531 + /* 532 532 + * Be on the safe side - disable interrupts 533 533 + */ 534 534 + ec->ops->irqdisable(ec, ec->irq); 535 535 + 536 536 + host = ata_host_alloc(&ec->dev, info->nr_ports); 537 537 + if (!host) 538 538 + return -ENOMEM; 539 539 + 540 540 + host->private_data = info->state; 541 541 + host->flags = ATA_HOST_SIMPLEX; 542 542 + 543 543 + for (i = 0; i < info->nr_ports; i++) { 544 544 + struct ata_port *ap = host->ports[i]; 545 545 + 546 546 + ap->pio_mask = 0x1f; 547 547 + ap->mwdma_mask = info->mwdma_mask; 548 548 + ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; 549 549 + ap->ops = &pata_icside_port_ops; 550 550 + 551 551 + pata_icside_setup_ioaddr(&ap->ioaddr, info->base, info->port[i]); 552 552 + } 553 553 + 554 554 + return ata_host_activate(host, ec->irq, ata_interrupt, 0, 555 555 + &pata_icside_sht); 500 556 } 501 557 502 558 static int __devinit 503 559 pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) 504 560 { 505 561 struct pata_icside_state *state; 506 506 - struct ata_probe_ent ae; 562 562 + struct pata_icside_info info; 507 563 void __iomem *idmem; 508 564 int ret; 509 565 ··· 552 526 if (ret) 553 527 goto out; 554 528 555 555 - state = kzalloc(sizeof(struct pata_icside_state), GFP_KERNEL); 529 529 + state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL); 556 530 if (!state) { 557 531 ret = -ENOMEM; 558 532 goto release; ··· 561 535 state->type = ICS_TYPE_NOTYPE; 562 536 state->dma = NO_DMA; 563 537 564 564 - idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), 565 565 - ecard_resource_len(ec, ECARD_RES_IOCFAST)); 538 538 + idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 566 539 if (idmem) { 567 540 unsigned int type; 568 541 ··· 569 544 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; 570 545 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; 571 546 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; 572 572 - iounmap(idmem); 547 547 + ecardm_iounmap(ec, idmem); 573 548 574 549 state->type = type; 575 550 } 576 551 577 577 - memset(&ae, 0, sizeof(ae)); 578 578 - INIT_LIST_HEAD(&ae.node); 579 579 - ae.dev = &ec->dev; 580 580 - ae.port_ops = &pata_icside_port_ops; 581 581 - ae.sht = &pata_icside_sht; 582 582 - ae.pio_mask = 0x1f; 583 583 - ae.irq = ec->irq; 584 584 - ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; 585 585 - ae._host_flags = ATA_HOST_SIMPLEX; 586 586 - ae.private_data = state; 552 552 + memset(&info, 0, sizeof(info)); 553 553 + info.state = state; 554 554 + info.ec = ec; 587 555 588 556 switch (state->type) { 589 557 case ICS_TYPE_A3IN: ··· 590 572 break; 591 573 592 574 case ICS_TYPE_V5: 593 593 - ret = pata_icside_register_v5(&ae, ec); 575 575 + ret = pata_icside_register_v5(&info); 594 576 break; 595 577 596 578 case ICS_TYPE_V6: 597 597 - ret = pata_icside_register_v6(&ae, ec); 579 579 + ret = pata_icside_register_v6(&info); 598 580 break; 599 581 600 582 default: ··· 604 586 } 605 587 606 588 if (ret == 0) 607 607 - ret = ata_device_add(&ae) == 0 ? -ENODEV : 0; 589 589 + ret = pata_icside_add_ports(&info); 608 590 609 591 if (ret == 0) 610 592 goto out; 611 593 612 612 - kfree(state); 613 594 release: 614 595 ecard_release_resources(ec); 615 596 out: ··· 626 609 * this register via that region. 627 610 */ 628 611 local_irq_save(flags); 629 629 - if (ec->ops) 630 630 - ec->ops->irqdisable(ec, ec->irq); 612 612 + ec->ops->irqdisable(ec, ec->irq); 631 613 local_irq_restore(flags); 632 614 633 615 /* ··· 654 638 * don't NULL out the drvdata - devres/libata wants it 655 639 * to free the ata_host structure. 656 640 */ 657 657 - ec->ops = NULL; 658 658 - ec->irq_data = NULL; 659 659 - 660 641 if (state->dma != NO_DMA) 661 642 free_dma(state->dma); 662 662 - if (state->ioc_base) 663 663 - iounmap(state->ioc_base); 664 664 - if (state->ioc_base != state->irq_port) 665 665 - iounmap(state->irq_port); 666 643 667 667 - kfree(state); 668 644 ecard_release_resources(ec); 669 645 } 670 646

+11 -30

drivers/ide/arm/icside.c

reviewed

··· 565 565 ide_hwif_t *hwif; 566 566 void __iomem *base; 567 567 568 568 - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), 569 569 - ecard_resource_len(ec, ECARD_RES_MEMC)); 568 568 + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); 570 569 if (!base) 571 570 return -ENOMEM; 572 571 ··· 573 574 574 575 ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; 575 576 ec->irqmask = 1; 576 576 - ec->irq_data = state; 577 577 - ec->ops = &icside_ops_arcin_v5; 577 577 + 578 578 + ecard_setirq(ec, &icside_ops_arcin_v5, state); 578 579 579 580 /* 580 581 * Be on the safe side - disable interrupts ··· 582 583 icside_irqdisable_arcin_v5(ec, 0); 583 584 584 585 hwif = icside_setup(base, &icside_cardinfo_v5, ec); 585 585 - if (!hwif) { 586 586 - iounmap(base); 586 586 + if (!hwif) 587 587 return -ENODEV; 588 588 - } 589 588 590 589 state->hwif[0] = hwif; 591 590 ··· 602 605 unsigned int sel = 0; 603 606 int ret; 604 607 605 605 - ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), 606 606 - ecard_resource_len(ec, ECARD_RES_IOCFAST)); 608 608 + ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 607 609 if (!ioc_base) { 608 610 ret = -ENOMEM; 609 611 goto out; ··· 611 615 easi_base = ioc_base; 612 616 613 617 if (ecard_resource_flags(ec, ECARD_RES_EASI)) { 614 614 - easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI), 615 615 - ecard_resource_len(ec, ECARD_RES_EASI)); 618 618 + easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); 616 619 if (!easi_base) { 617 620 ret = -ENOMEM; 618 618 - goto unmap_slot; 621 621 + goto out; 619 622 } 620 623 621 624 /* ··· 625 630 626 631 writeb(sel, ioc_base); 627 632 628 628 - ec->irq_data = state; 629 629 - ec->ops = &icside_ops_arcin_v6; 633 633 + ecard_setirq(ec, &icside_ops_arcin_v6, state); 630 634 631 635 state->irq_port = easi_base; 632 636 state->ioc_base = ioc_base; ··· 643 649 644 650 if (!hwif || !mate) { 645 651 ret = -ENODEV; 646 646 - goto unmap_port; 652 652 + goto out; 647 653 } 648 654 649 655 state->hwif[0] = hwif; ··· 680 686 681 687 return 0; 682 688 683 683 - unmap_port: 684 684 - if (easi_base != ioc_base) 685 685 - iounmap(easi_base); 686 686 - unmap_slot: 687 687 - iounmap(ioc_base); 688 689 out: 689 690 return ret; 690 691 } ··· 705 716 state->type = ICS_TYPE_NOTYPE; 706 717 state->dev = &ec->dev; 707 718 708 708 - idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), 709 709 - ecard_resource_len(ec, ECARD_RES_IOCFAST)); 719 719 + idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 710 720 if (idmem) { 711 721 unsigned int type; 712 722 ··· 713 725 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; 714 726 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; 715 727 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; 716 716 - iounmap(idmem); 728 728 + ecardm_iounmap(ec, idmem); 717 729 718 730 state->type = type; 719 731 } ··· 781 793 } 782 794 783 795 ecard_set_drvdata(ec, NULL); 784 784 - ec->ops = NULL; 785 785 - ec->irq_data = NULL; 786 786 - 787 787 - if (state->ioc_base) 788 788 - iounmap(state->ioc_base); 789 789 - if (state->ioc_base != state->irq_port) 790 790 - iounmap(state->irq_port); 791 796 792 797 kfree(state); 793 798 ecard_release_resources(ec);

+1 -4

drivers/ide/arm/rapide.c

reviewed

··· 63 63 if (ret) 64 64 goto out; 65 65 66 66 - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), 67 67 - ecard_resource_len(ec, ECARD_RES_MEMC)); 66 66 + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); 68 67 if (!base) { 69 68 ret = -ENOMEM; 70 69 goto release; ··· 80 81 goto out; 81 82 } 82 83 83 83 - iounmap(base); 84 84 release: 85 85 ecard_release_resources(ec); 86 86 out: ··· 94 96 95 97 /* there must be a better way */ 96 98 ide_unregister(hwif - ide_hwifs); 97 97 - iounmap(hwif->hwif_data); 98 99 ecard_release_resources(ec); 99 100 } 100 101

+1 -5

drivers/net/arm/ether1.c

reviewed

··· 1014 1014 SET_NETDEV_DEV(dev, &ec->dev); 1015 1015 1016 1016 dev->irq = ec->irq; 1017 1017 - priv(dev)->base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), 1018 1018 - ecard_resource_len(ec, ECARD_RES_IOCFAST)); 1017 1017 + priv(dev)->base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 1019 1018 if (!priv(dev)->base) { 1020 1019 ret = -ENOMEM; 1021 1020 goto free; ··· 1055 1056 return 0; 1056 1057 1057 1058 free: 1058 1058 - if (priv(dev)->base) 1059 1059 - iounmap(priv(dev)->base); 1060 1059 free_netdev(dev); 1061 1060 release: 1062 1061 ecard_release_resources(ec); ··· 1069 1072 ecard_set_drvdata(ec, NULL); 1070 1073 1071 1074 unregister_netdev(dev); 1072 1072 - iounmap(priv(dev)->base); 1073 1075 free_netdev(dev); 1074 1076 ecard_release_resources(ec); 1075 1077 }

+1 -5

drivers/net/arm/ether3.c

reviewed

··· 793 793 SET_MODULE_OWNER(dev); 794 794 SET_NETDEV_DEV(dev, &ec->dev); 795 795 796 796 - priv(dev)->base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), 797 797 - ecard_resource_len(ec, ECARD_RES_MEMC)); 796 796 + priv(dev)->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); 798 797 if (!priv(dev)->base) { 799 798 ret = -ENOMEM; 800 799 goto free; ··· 868 869 return 0; 869 870 870 871 free: 871 871 - if (priv(dev)->base) 872 872 - iounmap(priv(dev)->base); 873 872 free_netdev(dev); 874 873 release: 875 874 ecard_release_resources(ec); ··· 882 885 ecard_set_drvdata(ec, NULL); 883 886 884 887 unregister_netdev(dev); 885 885 - iounmap(priv(dev)->base); 886 888 free_netdev(dev); 887 889 ecard_release_resources(ec); 888 890 }

+3 -14

drivers/net/arm/etherh.c

reviewed

··· 686 686 eh->supported = data->supported; 687 687 eh->ctrl = 0; 688 688 eh->id = ec->cid.product; 689 689 - eh->memc = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), PAGE_SIZE); 689 689 + eh->memc = ecardm_iomap(ec, ECARD_RES_MEMC, 0, PAGE_SIZE); 690 690 if (!eh->memc) { 691 691 ret = -ENOMEM; 692 692 goto free; ··· 694 694 695 695 eh->ctrl_port = eh->memc; 696 696 if (data->ctrl_ioc) { 697 697 - eh->ioc_fast = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), PAGE_SIZE); 697 697 + eh->ioc_fast = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, PAGE_SIZE); 698 698 if (!eh->ioc_fast) { 699 699 ret = -ENOMEM; 700 700 goto free; ··· 710 710 * IRQ and control port handling - only for non-NIC slot cards. 711 711 */ 712 712 if (ec->slot_no != 8) { 713 713 - ec->ops = &etherh_ops; 714 714 - ec->irq_data = eh; 713 713 + ecard_setirq(ec, &etherh_ops, eh); 715 714 } else { 716 715 /* 717 716 * If we're in the NIC slot, make sure the IRQ is enabled ··· 758 759 return 0; 759 760 760 761 free: 761 761 - if (eh->ioc_fast) 762 762 - iounmap(eh->ioc_fast); 763 763 - if (eh->memc) 764 764 - iounmap(eh->memc); 765 762 free_netdev(dev); 766 763 release: 767 764 ecard_release_resources(ec); ··· 768 773 static void __devexit etherh_remove(struct expansion_card *ec) 769 774 { 770 775 struct net_device *dev = ecard_get_drvdata(ec); 771 771 - struct etherh_priv *eh = etherh_priv(dev); 772 776 773 777 ecard_set_drvdata(ec, NULL); 774 778 775 779 unregister_netdev(dev); 776 776 - ec->ops = NULL; 777 777 - 778 778 - if (eh->ioc_fast) 779 779 - iounmap(eh->ioc_fast); 780 780 - iounmap(eh->memc); 781 780 782 781 free_netdev(dev); 783 782

+2 -10

drivers/scsi/arm/arxescsi.c

reviewed

··· 281 281 { 282 282 struct Scsi_Host *host; 283 283 struct arxescsi_info *info; 284 284 - unsigned long resbase, reslen; 285 284 void __iomem *base; 286 285 int ret; 287 286 ··· 288 289 if (ret) 289 290 goto out; 290 291 291 291 - resbase = ecard_resource_start(ec, ECARD_RES_MEMC); 292 292 - reslen = ecard_resource_len(ec, ECARD_RES_MEMC); 293 293 - base = ioremap(resbase, reslen); 292 292 + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); 294 293 if (!base) { 295 294 ret = -ENOMEM; 296 295 goto out_region; ··· 297 300 host = scsi_host_alloc(&arxescsi_template, sizeof(struct arxescsi_info)); 298 301 if (!host) { 299 302 ret = -ENOMEM; 300 300 - goto out_unmap; 303 303 + goto out_region; 301 304 } 302 305 303 306 info = (struct arxescsi_info *)host->hostdata; ··· 334 337 fas216_release(host); 335 338 out_unregister: 336 339 scsi_host_put(host); 337 337 - out_unmap: 338 338 - iounmap(base); 339 340 out_region: 340 341 ecard_release_resources(ec); 341 342 out: ··· 343 348 static void __devexit arxescsi_remove(struct expansion_card *ec) 344 349 { 345 350 struct Scsi_Host *host = ecard_get_drvdata(ec); 346 346 - struct arxescsi_info *info = (struct arxescsi_info *)host->hostdata; 347 351 348 352 ecard_set_drvdata(ec, NULL); 349 353 fas216_remove(host); 350 350 - 351 351 - iounmap(info->base); 352 354 353 355 fas216_release(host); 354 356 scsi_host_put(host);

+4 -12

drivers/scsi/arm/cumana_2.c

reviewed

··· 401 401 { 402 402 struct Scsi_Host *host; 403 403 struct cumanascsi2_info *info; 404 404 - unsigned long resbase, reslen; 405 404 void __iomem *base; 406 405 int ret; 407 406 ··· 408 409 if (ret) 409 410 goto out; 410 411 411 411 - resbase = ecard_resource_start(ec, ECARD_RES_MEMC); 412 412 - reslen = ecard_resource_len(ec, ECARD_RES_MEMC); 413 413 - base = ioremap(resbase, reslen); 412 412 + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); 414 413 if (!base) { 415 414 ret = -ENOMEM; 416 415 goto out_region; ··· 418 421 sizeof(struct cumanascsi2_info)); 419 422 if (!host) { 420 423 ret = -ENOMEM; 421 421 - goto out_unmap; 424 424 + goto out_region; 422 425 } 423 426 424 427 ecard_set_drvdata(ec, host); ··· 447 450 448 451 ec->irqaddr = info->base + CUMANASCSI2_STATUS; 449 452 ec->irqmask = STATUS_INT; 450 450 - ec->irq_data = info; 451 451 - ec->ops = &cumanascsi_2_ops; 453 453 + 454 454 + ecard_setirq(ec, &cumanascsi_2_ops, info); 452 455 453 456 ret = fas216_init(host); 454 457 if (ret) ··· 487 490 out_free: 488 491 scsi_host_put(host); 489 492 490 490 - out_unmap: 491 491 - iounmap(base); 492 492 - 493 493 out_region: 494 494 ecard_release_resources(ec); 495 495 ··· 505 511 if (info->info.scsi.dma != NO_DMA) 506 512 free_dma(info->info.scsi.dma); 507 513 free_irq(ec->irq, info); 508 508 - 509 509 - iounmap(info->base); 510 514 511 515 fas216_release(host); 512 516 scsi_host_put(host);

+4 -12

drivers/scsi/arm/eesox.c

reviewed

··· 519 519 { 520 520 struct Scsi_Host *host; 521 521 struct eesoxscsi_info *info; 522 522 - unsigned long resbase, reslen; 523 522 void __iomem *base; 524 523 int ret; 525 524 ··· 526 527 if (ret) 527 528 goto out; 528 529 529 529 - resbase = ecard_resource_start(ec, ECARD_RES_IOCFAST); 530 530 - reslen = ecard_resource_len(ec, ECARD_RES_IOCFAST); 531 531 - base = ioremap(resbase, reslen); 530 530 + base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 532 531 if (!base) { 533 532 ret = -ENOMEM; 534 533 goto out_region; ··· 536 539 sizeof(struct eesoxscsi_info)); 537 540 if (!host) { 538 541 ret = -ENOMEM; 539 539 - goto out_unmap; 542 542 + goto out_region; 540 543 } 541 544 542 545 ecard_set_drvdata(ec, host); ··· 566 569 567 570 ec->irqaddr = base + EESOX_DMASTAT; 568 571 ec->irqmask = EESOX_STAT_INTR; 569 569 - ec->irq_data = info; 570 570 - ec->ops = &eesoxscsi_ops; 572 572 + 573 573 + ecard_setirq(ec, &eesoxscsi_ops, info); 571 574 572 575 device_create_file(&ec->dev, &dev_attr_bus_term); 573 576 ··· 609 612 device_remove_file(&ec->dev, &dev_attr_bus_term); 610 613 scsi_host_put(host); 611 614 612 612 - out_unmap: 613 613 - iounmap(base); 614 614 - 615 615 out_region: 616 616 ecard_release_resources(ec); 617 617 ··· 629 635 free_irq(ec->irq, info); 630 636 631 637 device_remove_file(&ec->dev, &dev_attr_bus_term); 632 632 - 633 633 - iounmap(info->base); 634 638 635 639 fas216_release(host); 636 640 scsi_host_put(host);

+4 -12

drivers/scsi/arm/powertec.c

reviewed

··· 313 313 { 314 314 struct Scsi_Host *host; 315 315 struct powertec_info *info; 316 316 - unsigned long resbase, reslen; 317 316 void __iomem *base; 318 317 int ret; 319 318 ··· 320 321 if (ret) 321 322 goto out; 322 323 323 323 - resbase = ecard_resource_start(ec, ECARD_RES_IOCFAST); 324 324 - reslen = ecard_resource_len(ec, ECARD_RES_IOCFAST); 325 325 - base = ioremap(resbase, reslen); 324 324 + base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 326 325 if (!base) { 327 326 ret = -ENOMEM; 328 327 goto out_region; ··· 330 333 sizeof (struct powertec_info)); 331 334 if (!host) { 332 335 ret = -ENOMEM; 333 333 - goto out_unmap; 336 336 + goto out_region; 334 337 } 335 338 336 339 ecard_set_drvdata(ec, host); ··· 358 361 359 362 ec->irqaddr = base + POWERTEC_INTR_STATUS; 360 363 ec->irqmask = POWERTEC_INTR_BIT; 361 361 - ec->irq_data = info; 362 362 - ec->ops = &powertecscsi_ops; 364 364 + 365 365 + ecard_setirq(ec, &powertecscsi_ops, info); 363 366 364 367 device_create_file(&ec->dev, &dev_attr_bus_term); 365 368 ··· 401 404 device_remove_file(&ec->dev, &dev_attr_bus_term); 402 405 scsi_host_put(host); 403 406 404 404 - out_unmap: 405 405 - iounmap(base); 406 406 - 407 407 out_region: 408 408 ecard_release_resources(ec); 409 409 ··· 421 427 if (info->info.scsi.dma != NO_DMA) 422 428 free_dma(info->info.scsi.dma); 423 429 free_irq(ec->irq, info); 424 424 - 425 425 - iounmap(info->base); 426 430 427 431 fas216_release(host); 428 432 scsi_host_put(host);

+1 -2

drivers/serial/8250_acorn.c

reviewed

··· 54 54 info->num_ports = type->num_ports; 55 55 56 56 bus_addr = ecard_resource_start(ec, type->type); 57 57 - info->vaddr = ioremap(bus_addr, ecard_resource_len(ec, type->type)); 57 57 + info->vaddr = ecardm_iomap(ec, type->type, 0, 0); 58 58 if (!info->vaddr) { 59 59 kfree(info); 60 60 return -ENOMEM; ··· 91 91 if (info->ports[i] > 0) 92 92 serial8250_unregister_port(info->ports[i]); 93 93 94 94 - iounmap(info->vaddr); 95 94 kfree(info); 96 95 } 97 96

+17

drivers/serial/Kconfig

reviewed

··· 359 359 360 360 Say Y if you have an external 8250/16C550 UART. If unsure, say N. 361 361 362 362 + config SERIAL_KS8695 363 363 + bool "Micrel KS8695 (Centaur) serial port support" 364 364 + depends on ARCH_KS8695 365 365 + select SERIAL_CORE 366 366 + help 367 367 + This selects the Micrel Centaur KS8695 UART. Say Y here. 368 368 + 369 369 + config SERIAL_KS8695_CONSOLE 370 370 + bool "Support for console on KS8695 (Centaur) serial port" 371 371 + depends on SERIAL_KS8695=y 372 372 + select SERIAL_CORE_CONSOLE 373 373 + help 374 374 + Say Y here if you wish to use a KS8695 (Centaur) UART as the 375 375 + system console (the system console is the device which 376 376 + receives all kernel messages and warnings and which allows 377 377 + logins in single user mode). 378 378 + 362 379 config SERIAL_CLPS711X 363 380 tristate "CLPS711X serial port support" 364 381 depends on ARM && ARCH_CLPS711X

+1

drivers/serial/Makefile

reviewed

··· 61 61 obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o 62 62 obj-$(CONFIG_SERIAL_NETX) += netx-serial.o 63 63 obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o 64 64 + obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o

+657

drivers/serial/serial_ks8695.c

reviewed

··· 1 1 + /* 2 2 + * drivers/serial/serial_ks8695.c 3 3 + * 4 4 + * Driver for KS8695 serial ports 5 5 + * 6 6 + * Based on drivers/serial/serial_amba.c, by Kam Lee. 7 7 + * 8 8 + * Copyright 2002-2005 Micrel Inc. 9 9 + * 10 10 + * This program is free software; you can redistribute it and/or modify 11 11 + * it under the terms of the GNU General Public License as published by 12 12 + * the Free Software Foundation; either version 2 of the License, or 13 13 + * (at your option) any later version. 14 14 + * 15 15 + */ 16 16 + #include <linux/module.h> 17 17 + #include <linux/tty.h> 18 18 + #include <linux/ioport.h> 19 19 + #include <linux/init.h> 20 20 + #include <linux/serial.h> 21 21 + #include <linux/console.h> 22 22 + #include <linux/sysrq.h> 23 23 + #include <linux/device.h> 24 24 + 25 25 + #include <asm/io.h> 26 26 + #include <asm/irq.h> 27 27 + #include <asm/mach/irq.h> 28 28 + 29 29 + #include <asm/arch/regs-uart.h> 30 30 + #include <asm/arch/regs-irq.h> 31 31 + 32 32 + #if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 33 33 + #define SUPPORT_SYSRQ 34 34 + #endif 35 35 + 36 36 + #include <linux/serial_core.h> 37 37 + 38 38 + 39 39 + #define SERIAL_KS8695_MAJOR 204 40 40 + #define SERIAL_KS8695_MINOR 16 41 41 + #define SERIAL_KS8695_DEVNAME "ttyAM" 42 42 + 43 43 + #define SERIAL_KS8695_NR 1 44 44 + 45 45 + /* 46 46 + * Access macros for the KS8695 UART 47 47 + */ 48 48 + #define UART_GET_CHAR(p) (__raw_readl((p)->membase + KS8695_URRB) & 0xFF) 49 49 + #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + KS8695_URTH) 50 50 + #define UART_GET_FCR(p) __raw_readl((p)->membase + KS8695_URFC) 51 51 + #define UART_PUT_FCR(p, c) __raw_writel((c), (p)->membase + KS8695_URFC) 52 52 + #define UART_GET_MSR(p) __raw_readl((p)->membase + KS8695_URMS) 53 53 + #define UART_GET_LSR(p) __raw_readl((p)->membase + KS8695_URLS) 54 54 + #define UART_GET_LCR(p) __raw_readl((p)->membase + KS8695_URLC) 55 55 + #define UART_PUT_LCR(p, c) __raw_writel((c), (p)->membase + KS8695_URLC) 56 56 + #define UART_GET_MCR(p) __raw_readl((p)->membase + KS8695_URMC) 57 57 + #define UART_PUT_MCR(p, c) __raw_writel((c), (p)->membase + KS8695_URMC) 58 58 + #define UART_GET_BRDR(p) __raw_readl((p)->membase + KS8695_URBD) 59 59 + #define UART_PUT_BRDR(p, c) __raw_writel((c), (p)->membase + KS8695_URBD) 60 60 + 61 61 + #define KS8695_CLR_TX_INT() __raw_writel(1 << KS8695_IRQ_UART_TX, KS8695_IRQ_VA + KS8695_INTST) 62 62 + 63 63 + #define UART_DUMMY_LSR_RX 0x100 64 64 + #define UART_PORT_SIZE (KS8695_USR - KS8695_URRB + 4) 65 65 + 66 66 + #define tx_enabled(port) ((port)->unused[0]) 67 67 + #define rx_enabled(port) ((port)->unused[1]) 68 68 + 69 69 + 70 70 + #ifdef SUPPORT_SYSRQ 71 71 + static struct console ks8695_console; 72 72 + #endif 73 73 + 74 74 + static void ks8695uart_stop_tx(struct uart_port *port) 75 75 + { 76 76 + if (tx_enabled(port)) { 77 77 + disable_irq(KS8695_IRQ_UART_TX); 78 78 + tx_enabled(port) = 0; 79 79 + } 80 80 + } 81 81 + 82 82 + static void ks8695uart_start_tx(struct uart_port *port) 83 83 + { 84 84 + if (!tx_enabled(port)) { 85 85 + enable_irq(KS8695_IRQ_UART_TX); 86 86 + tx_enabled(port) = 1; 87 87 + } 88 88 + } 89 89 + 90 90 + static void ks8695uart_stop_rx(struct uart_port *port) 91 91 + { 92 92 + if (rx_enabled(port)) { 93 93 + disable_irq(KS8695_IRQ_UART_RX); 94 94 + rx_enabled(port) = 0; 95 95 + } 96 96 + } 97 97 + 98 98 + static void ks8695uart_enable_ms(struct uart_port *port) 99 99 + { 100 100 + enable_irq(KS8695_IRQ_UART_MODEM_STATUS); 101 101 + } 102 102 + 103 103 + static void ks8695uart_disable_ms(struct uart_port *port) 104 104 + { 105 105 + disable_irq(KS8695_IRQ_UART_MODEM_STATUS); 106 106 + } 107 107 + 108 108 + static irqreturn_t ks8695uart_rx_chars(int irq, void *dev_id) 109 109 + { 110 110 + struct uart_port *port = dev_id; 111 111 + struct tty_struct *tty = port->info->tty; 112 112 + unsigned int status, ch, lsr, flg, max_count = 256; 113 113 + 114 114 + status = UART_GET_LSR(port); /* clears pending LSR interrupts */ 115 115 + while ((status & URLS_URDR) && max_count--) { 116 116 + ch = UART_GET_CHAR(port); 117 117 + flg = TTY_NORMAL; 118 118 + 119 119 + port->icount.rx++; 120 120 + 121 121 + /* 122 122 + * Note that the error handling code is 123 123 + * out of the main execution path 124 124 + */ 125 125 + lsr = UART_GET_LSR(port) | UART_DUMMY_LSR_RX; 126 126 + if (unlikely(lsr & (URLS_URBI | URLS_URPE | URLS_URFE | URLS_URROE))) { 127 127 + if (lsr & URLS_URBI) { 128 128 + lsr &= ~(URLS_URFE | URLS_URPE); 129 129 + port->icount.brk++; 130 130 + if (uart_handle_break(port)) 131 131 + goto ignore_char; 132 132 + } 133 133 + if (lsr & URLS_URPE) 134 134 + port->icount.parity++; 135 135 + if (lsr & URLS_URFE) 136 136 + port->icount.frame++; 137 137 + if (lsr & URLS_URROE) 138 138 + port->icount.overrun++; 139 139 + 140 140 + lsr &= port->read_status_mask; 141 141 + 142 142 + if (lsr & URLS_URBI) 143 143 + flg = TTY_BREAK; 144 144 + else if (lsr & URLS_URPE) 145 145 + flg = TTY_PARITY; 146 146 + else if (lsr & URLS_URFE) 147 147 + flg = TTY_FRAME; 148 148 + } 149 149 + 150 150 + if (uart_handle_sysrq_char(port, ch)) 151 151 + goto ignore_char; 152 152 + 153 153 + uart_insert_char(port, lsr, URLS_URROE, ch, flg); 154 154 + 155 155 + ignore_char: 156 156 + status = UART_GET_LSR(port); 157 157 + } 158 158 + tty_flip_buffer_push(tty); 159 159 + 160 160 + return IRQ_HANDLED; 161 161 + } 162 162 + 163 163 + 164 164 + static irqreturn_t ks8695uart_tx_chars(int irq, void *dev_id) 165 165 + { 166 166 + struct uart_port *port = dev_id; 167 167 + struct circ_buf *xmit = &port->info->xmit; 168 168 + unsigned int count; 169 169 + 170 170 + if (port->x_char) { 171 171 + KS8695_CLR_TX_INT(); 172 172 + UART_PUT_CHAR(port, port->x_char); 173 173 + port->icount.tx++; 174 174 + port->x_char = 0; 175 175 + return IRQ_HANDLED; 176 176 + } 177 177 + 178 178 + if (uart_tx_stopped(port) || uart_circ_empty(xmit)) { 179 179 + ks8695uart_stop_tx(port); 180 180 + return IRQ_HANDLED; 181 181 + } 182 182 + 183 183 + count = 16; /* fifo size */ 184 184 + while (!uart_circ_empty(xmit) && (count-- > 0)) { 185 185 + KS8695_CLR_TX_INT(); 186 186 + UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 187 187 + 188 188 + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 189 189 + port->icount.tx++; 190 190 + } 191 191 + 192 192 + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 193 193 + uart_write_wakeup(port); 194 194 + 195 195 + if (uart_circ_empty(xmit)) 196 196 + ks8695uart_stop_tx(port); 197 197 + 198 198 + return IRQ_HANDLED; 199 199 + } 200 200 + 201 201 + static irqreturn_t ks8695uart_modem_status(int irq, void *dev_id) 202 202 + { 203 203 + struct uart_port *port = dev_id; 204 204 + unsigned int status; 205 205 + 206 206 + /* 207 207 + * clear modem interrupt by reading MSR 208 208 + */ 209 209 + status = UART_GET_MSR(port); 210 210 + 211 211 + if (status & URMS_URDDCD) 212 212 + uart_handle_dcd_change(port, status & URMS_URDDCD); 213 213 + 214 214 + if (status & URMS_URDDST) 215 215 + port->icount.dsr++; 216 216 + 217 217 + if (status & URMS_URDCTS) 218 218 + uart_handle_cts_change(port, status & URMS_URDCTS); 219 219 + 220 220 + if (status & URMS_URTERI) 221 221 + port->icount.rng++; 222 222 + 223 223 + wake_up_interruptible(&port->info->delta_msr_wait); 224 224 + 225 225 + return IRQ_HANDLED; 226 226 + } 227 227 + 228 228 + static unsigned int ks8695uart_tx_empty(struct uart_port *port) 229 229 + { 230 230 + return (UART_GET_LSR(port) & URLS_URTE) ? TIOCSER_TEMT : 0; 231 231 + } 232 232 + 233 233 + static unsigned int ks8695uart_get_mctrl(struct uart_port *port) 234 234 + { 235 235 + unsigned int result = 0; 236 236 + unsigned int status; 237 237 + 238 238 + status = UART_GET_MSR(port); 239 239 + if (status & URMS_URDCD) 240 240 + result |= TIOCM_CAR; 241 241 + if (status & URMS_URDSR) 242 242 + result |= TIOCM_DSR; 243 243 + if (status & URMS_URCTS) 244 244 + result |= TIOCM_CTS; 245 245 + if (status & URMS_URRI) 246 246 + result |= TIOCM_RI; 247 247 + 248 248 + return result; 249 249 + } 250 250 + 251 251 + static void ks8695uart_set_mctrl(struct uart_port *port, u_int mctrl) 252 252 + { 253 253 + unsigned int mcr; 254 254 + 255 255 + mcr = UART_GET_MCR(port); 256 256 + if (mctrl & TIOCM_RTS) 257 257 + mcr |= URMC_URRTS; 258 258 + else 259 259 + mcr &= ~URMC_URRTS; 260 260 + 261 261 + if (mctrl & TIOCM_DTR) 262 262 + mcr |= URMC_URDTR; 263 263 + else 264 264 + mcr &= ~URMC_URDTR; 265 265 + 266 266 + UART_PUT_MCR(port, mcr); 267 267 + } 268 268 + 269 269 + static void ks8695uart_break_ctl(struct uart_port *port, int break_state) 270 270 + { 271 271 + unsigned int lcr; 272 272 + 273 273 + lcr = UART_GET_LCR(port); 274 274 + 275 275 + if (break_state == -1) 276 276 + lcr |= URLC_URSBC; 277 277 + else 278 278 + lcr &= ~URLC_URSBC; 279 279 + 280 280 + UART_PUT_LCR(port, lcr); 281 281 + } 282 282 + 283 283 + static int ks8695uart_startup(struct uart_port *port) 284 284 + { 285 285 + int retval; 286 286 + 287 287 + set_irq_flags(KS8695_IRQ_UART_TX, IRQF_VALID | IRQF_NOAUTOEN); 288 288 + tx_enabled(port) = 0; 289 289 + rx_enabled(port) = 1; 290 290 + 291 291 + /* 292 292 + * Allocate the IRQ 293 293 + */ 294 294 + retval = request_irq(KS8695_IRQ_UART_TX, ks8695uart_tx_chars, IRQF_DISABLED, "UART TX", port); 295 295 + if (retval) 296 296 + goto err_tx; 297 297 + 298 298 + retval = request_irq(KS8695_IRQ_UART_RX, ks8695uart_rx_chars, IRQF_DISABLED, "UART RX", port); 299 299 + if (retval) 300 300 + goto err_rx; 301 301 + 302 302 + retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port); 303 303 + if (retval) 304 304 + return err_ls; 305 305 + 306 306 + retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port); 307 307 + if (retval) 308 308 + return err_ms; 309 309 + 310 310 + return 0; 311 311 + 312 312 + err_ms: 313 313 + free_irq(KS8695_IRQ_UART_LINE_STATUS, port); 314 314 + err_ls: 315 315 + free_irq(KS8695_IRQ_UART_RX, port); 316 316 + err_rx: 317 317 + free_irq(KS8695_IRQ_UART_TX, port); 318 318 + err_tx: 319 319 + return retval; 320 320 + } 321 321 + 322 322 + static void ks8695uart_shutdown(struct uart_port *port) 323 323 + { 324 324 + /* 325 325 + * Free the interrupt 326 326 + */ 327 327 + free_irq(KS8695_IRQ_UART_RX, port); 328 328 + free_irq(KS8695_IRQ_UART_TX, port); 329 329 + free_irq(KS8695_IRQ_UART_MODEM_STATUS, port); 330 330 + free_irq(KS8695_IRQ_UART_LINE_STATUS, port); 331 331 + 332 332 + /* disable break condition and fifos */ 333 333 + UART_PUT_LCR(port, UART_GET_LCR(port) & ~URLC_URSBC); 334 334 + UART_PUT_FCR(port, UART_GET_FCR(port) & ~URFC_URFE); 335 335 + } 336 336 + 337 337 + static void ks8695uart_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) 338 338 + { 339 339 + unsigned int lcr, fcr = 0; 340 340 + unsigned long flags; 341 341 + unsigned int baud, quot; 342 342 + 343 343 + /* 344 344 + * Ask the core to calculate the divisor for us. 345 345 + */ 346 346 + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 347 347 + quot = uart_get_divisor(port, baud); 348 348 + 349 349 + switch (termios->c_cflag & CSIZE) { 350 350 + case CS5: 351 351 + lcr = URCL_5; 352 352 + break; 353 353 + case CS6: 354 354 + lcr = URCL_6; 355 355 + break; 356 356 + case CS7: 357 357 + lcr = URCL_7; 358 358 + break; 359 359 + default: 360 360 + lcr = URCL_8; 361 361 + break; 362 362 + } 363 363 + 364 364 + /* stop bits */ 365 365 + if (termios->c_cflag & CSTOPB) 366 366 + lcr |= URLC_URSB; 367 367 + 368 368 + /* parity */ 369 369 + if (termios->c_cflag & PARENB) { 370 370 + if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */ 371 371 + if (termios->c_cflag & PARODD) 372 372 + lcr |= URPE_MARK; 373 373 + else 374 374 + lcr |= URPE_SPACE; 375 375 + } 376 376 + else if (termios->c_cflag & PARODD) 377 377 + lcr |= URPE_ODD; 378 378 + else 379 379 + lcr |= URPE_EVEN; 380 380 + } 381 381 + 382 382 + if (port->fifosize > 1) 383 383 + fcr = URFC_URFRT_8 | URFC_URTFR | URFC_URRFR | URFC_URFE; 384 384 + 385 385 + spin_lock_irqsave(&port->lock, flags); 386 386 + 387 387 + /* 388 388 + * Update the per-port timeout. 389 389 + */ 390 390 + uart_update_timeout(port, termios->c_cflag, baud); 391 391 + 392 392 + port->read_status_mask = URLS_URROE; 393 393 + if (termios->c_iflag & INPCK) 394 394 + port->read_status_mask |= (URLS_URFE | URLS_URPE); 395 395 + if (termios->c_iflag & (BRKINT | PARMRK)) 396 396 + port->read_status_mask |= URLS_URBI; 397 397 + 398 398 + /* 399 399 + * Characters to ignore 400 400 + */ 401 401 + port->ignore_status_mask = 0; 402 402 + if (termios->c_iflag & IGNPAR) 403 403 + port->ignore_status_mask |= (URLS_URFE | URLS_URPE); 404 404 + if (termios->c_iflag & IGNBRK) { 405 405 + port->ignore_status_mask |= URLS_URBI; 406 406 + /* 407 407 + * If we're ignoring parity and break indicators, 408 408 + * ignore overruns too (for real raw support). 409 409 + */ 410 410 + if (termios->c_iflag & IGNPAR) 411 411 + port->ignore_status_mask |= URLS_URROE; 412 412 + } 413 413 + 414 414 + /* 415 415 + * Ignore all characters if CREAD is not set. 416 416 + */ 417 417 + if ((termios->c_cflag & CREAD) == 0) 418 418 + port->ignore_status_mask |= UART_DUMMY_LSR_RX; 419 419 + 420 420 + /* first, disable everything */ 421 421 + if (UART_ENABLE_MS(port, termios->c_cflag)) 422 422 + ks8695uart_enable_ms(port); 423 423 + else 424 424 + ks8695uart_disable_ms(port); 425 425 + 426 426 + /* Set baud rate */ 427 427 + UART_PUT_BRDR(port, quot); 428 428 + 429 429 + UART_PUT_LCR(port, lcr); 430 430 + UART_PUT_FCR(port, fcr); 431 431 + 432 432 + spin_unlock_irqrestore(&port->lock, flags); 433 433 + } 434 434 + 435 435 + static const char *ks8695uart_type(struct uart_port *port) 436 436 + { 437 437 + return port->type == PORT_KS8695 ? "KS8695" : NULL; 438 438 + } 439 439 + 440 440 + /* 441 441 + * Release the memory region(s) being used by 'port' 442 442 + */ 443 443 + static void ks8695uart_release_port(struct uart_port *port) 444 444 + { 445 445 + release_mem_region(port->mapbase, UART_PORT_SIZE); 446 446 + } 447 447 + 448 448 + /* 449 449 + * Request the memory region(s) being used by 'port' 450 450 + */ 451 451 + static int ks8695uart_request_port(struct uart_port *port) 452 452 + { 453 453 + return request_mem_region(port->mapbase, UART_PORT_SIZE, 454 454 + "serial_ks8695") != NULL ? 0 : -EBUSY; 455 455 + } 456 456 + 457 457 + /* 458 458 + * Configure/autoconfigure the port. 459 459 + */ 460 460 + static void ks8695uart_config_port(struct uart_port *port, int flags) 461 461 + { 462 462 + if (flags & UART_CONFIG_TYPE) { 463 463 + port->type = PORT_KS8695; 464 464 + ks8695uart_request_port(port); 465 465 + } 466 466 + } 467 467 + 468 468 + /* 469 469 + * verify the new serial_struct (for TIOCSSERIAL). 470 470 + */ 471 471 + static int ks8695uart_verify_port(struct uart_port *port, struct serial_struct *ser) 472 472 + { 473 473 + int ret = 0; 474 474 + 475 475 + if (ser->type != PORT_UNKNOWN && ser->type != PORT_KS8695) 476 476 + ret = -EINVAL; 477 477 + if (ser->irq != port->irq) 478 478 + ret = -EINVAL; 479 479 + if (ser->baud_base < 9600) 480 480 + ret = -EINVAL; 481 481 + return ret; 482 482 + } 483 483 + 484 484 + static struct uart_ops ks8695uart_pops = { 485 485 + .tx_empty = ks8695uart_tx_empty, 486 486 + .set_mctrl = ks8695uart_set_mctrl, 487 487 + .get_mctrl = ks8695uart_get_mctrl, 488 488 + .stop_tx = ks8695uart_stop_tx, 489 489 + .start_tx = ks8695uart_start_tx, 490 490 + .stop_rx = ks8695uart_stop_rx, 491 491 + .enable_ms = ks8695uart_enable_ms, 492 492 + .break_ctl = ks8695uart_break_ctl, 493 493 + .startup = ks8695uart_startup, 494 494 + .shutdown = ks8695uart_shutdown, 495 495 + .set_termios = ks8695uart_set_termios, 496 496 + .type = ks8695uart_type, 497 497 + .release_port = ks8695uart_release_port, 498 498 + .request_port = ks8695uart_request_port, 499 499 + .config_port = ks8695uart_config_port, 500 500 + .verify_port = ks8695uart_verify_port, 501 501 + }; 502 502 + 503 503 + static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = { 504 504 + { 505 505 + .membase = (void *) KS8695_UART_VA, 506 506 + .mapbase = KS8695_UART_VA, 507 507 + .iotype = SERIAL_IO_MEM, 508 508 + .irq = KS8695_IRQ_UART_TX, 509 509 + .uartclk = CLOCK_TICK_RATE * 16, 510 510 + .fifosize = 16, 511 511 + .ops = &ks8695uart_pops, 512 512 + .flags = ASYNC_BOOT_AUTOCONF, 513 513 + .line = 0, 514 514 + } 515 515 + }; 516 516 + 517 517 + #ifdef CONFIG_SERIAL_KS8695_CONSOLE 518 518 + static void ks8695_console_putchar(struct uart_port *port, int ch) 519 519 + { 520 520 + while (!(UART_GET_LSR(port) & URLS_URTHRE)) 521 521 + barrier(); 522 522 + 523 523 + UART_PUT_CHAR(port, ch); 524 524 + } 525 525 + 526 526 + static void ks8695_console_write(struct console *co, const char *s, u_int count) 527 527 + { 528 528 + struct uart_port *port = ks8695uart_ports + co->index; 529 529 + 530 530 + uart_console_write(port, s, count, ks8695_console_putchar); 531 531 + } 532 532 + 533 533 + static void __init ks8695_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) 534 534 + { 535 535 + unsigned int lcr; 536 536 + 537 537 + lcr = UART_GET_LCR(port); 538 538 + 539 539 + switch (lcr & URLC_PARITY) { 540 540 + case URPE_ODD: 541 541 + *parity = 'o'; 542 542 + break; 543 543 + case URPE_EVEN: 544 544 + *parity = 'e'; 545 545 + break; 546 546 + default: 547 547 + *parity = 'n'; 548 548 + } 549 549 + 550 550 + switch (lcr & URLC_URCL) { 551 551 + case URCL_5: 552 552 + *bits = 5; 553 553 + break; 554 554 + case URCL_6: 555 555 + *bits = 6; 556 556 + break; 557 557 + case URCL_7: 558 558 + *bits = 7; 559 559 + break; 560 560 + default: 561 561 + *bits = 8; 562 562 + } 563 563 + 564 564 + *baud = port->uartclk / (UART_GET_BRDR(port) & 0x0FFF); 565 565 + *baud /= 16; 566 566 + *baud &= 0xFFFFFFF0; 567 567 + } 568 568 + 569 569 + static int __init ks8695_console_setup(struct console *co, char *options) 570 570 + { 571 571 + struct uart_port *port; 572 572 + int baud = 115200; 573 573 + int bits = 8; 574 574 + int parity = 'n'; 575 575 + int flow = 'n'; 576 576 + 577 577 + /* 578 578 + * Check whether an invalid uart number has been specified, and 579 579 + * if so, search for the first available port that does have 580 580 + * console support. 581 581 + */ 582 582 + port = uart_get_console(ks8695uart_ports, SERIAL_KS8695_NR, co); 583 583 + 584 584 + if (options) 585 585 + uart_parse_options(options, &baud, &parity, &bits, &flow); 586 586 + else 587 587 + ks8695_console_get_options(port, &baud, &parity, &bits); 588 588 + 589 589 + return uart_set_options(port, co, baud, parity, bits, flow); 590 590 + } 591 591 + 592 592 + extern struct uart_driver ks8695_reg; 593 593 + 594 594 + static struct console ks8695_console = { 595 595 + .name = SERIAL_KS8695_DEVNAME, 596 596 + .write = ks8695_console_write, 597 597 + .device = uart_console_device, 598 598 + .setup = ks8695_console_setup, 599 599 + .flags = CON_PRINTBUFFER, 600 600 + .index = -1, 601 601 + .data = &ks8695_reg, 602 602 + }; 603 603 + 604 604 + static int __init ks8695_console_init(void) 605 605 + { 606 606 + register_console(&ks8695_console); 607 607 + return 0; 608 608 + } 609 609 + 610 610 + console_initcall(ks8695_console_init); 611 611 + 612 612 + #define KS8695_CONSOLE &ks8695_console 613 613 + #else 614 614 + #define KS8695_CONSOLE NULL 615 615 + #endif 616 616 + 617 617 + static struct uart_driver ks8695_reg = { 618 618 + .owner = THIS_MODULE, 619 619 + .driver_name = "serial_ks8695", 620 620 + .dev_name = SERIAL_KS8695_DEVNAME, 621 621 + .major = SERIAL_KS8695_MAJOR, 622 622 + .minor = SERIAL_KS8695_MINOR, 623 623 + .nr = SERIAL_KS8695_NR, 624 624 + .cons = KS8695_CONSOLE, 625 625 + }; 626 626 + 627 627 + static int __init ks8695uart_init(void) 628 628 + { 629 629 + int i, ret; 630 630 + 631 631 + printk(KERN_INFO "Serial: Micrel KS8695 UART driver\n"); 632 632 + 633 633 + ret = uart_register_driver(&ks8695_reg); 634 634 + if (ret) 635 635 + return ret; 636 636 + 637 637 + for (i = 0; i < SERIAL_KS8695_NR; i++) 638 638 + uart_add_one_port(&ks8695_reg, &ks8695uart_ports[0]); 639 639 + 640 640 + return 0; 641 641 + } 642 642 + 643 643 + static void __exit ks8695uart_exit(void) 644 644 + { 645 645 + int i; 646 646 + 647 647 + for (i = 0; i < SERIAL_KS8695_NR; i++) 648 648 + uart_remove_one_port(&ks8695_reg, &ks8695uart_ports[0]); 649 649 + uart_unregister_driver(&ks8695_reg); 650 650 + } 651 651 + 652 652 + module_init(ks8695uart_init); 653 653 + module_exit(ks8695uart_exit); 654 654 + 655 655 + MODULE_DESCRIPTION("KS8695 serial port driver"); 656 656 + MODULE_AUTHOR("Micrel Inc."); 657 657 + MODULE_LICENSE("GPL");

+1 -1

drivers/usb/gadget/Kconfig

reviewed

··· 210 210 211 211 config USB_GADGET_AT91 212 212 boolean "AT91 USB Device Port" 213 213 - depends on ARCH_AT91 213 213 + depends on ARCH_AT91 && !ARCH_AT91SAM9RL 214 214 select USB_GADGET_SELECTED 215 215 help 216 216 Many Atmel AT91 processors (such as the AT91RM2000) have a

+110

include/asm-arm/arch-at91/at91sam9rl.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-at91/at91sam9260.h 3 3 + * 4 4 + * Copyright (C) 2007 Atmel Corporation 5 5 + * 6 6 + * Common definitions. 7 7 + * Based on AT91SAM9RL datasheet revision A. (Preliminary) 8 8 + * 9 9 + * This file is subject to the terms and conditions of the GNU General Public 10 10 + * License. See the file COPYING in the main directory of this archive for 11 11 + * more details. 12 12 + */ 13 13 + 14 14 + #ifndef AT91SAM9RL_H 15 15 + #define AT91SAM9RL_H 16 16 + 17 17 + /* 18 18 + * Peripheral identifiers/interrupts. 19 19 + */ 20 20 + #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 21 21 + #define AT91_ID_SYS 1 /* System Controller */ 22 22 + #define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ 23 23 + #define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ 24 24 + #define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ 25 25 + #define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ 26 26 + #define AT91SAM9RL_ID_US0 6 /* USART 0 */ 27 27 + #define AT91SAM9RL_ID_US1 7 /* USART 1 */ 28 28 + #define AT91SAM9RL_ID_US2 8 /* USART 2 */ 29 29 + #define AT91SAM9RL_ID_US3 9 /* USART 3 */ 30 30 + #define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ 31 31 + #define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ 32 32 + #define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ 33 33 + #define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ 34 34 + #define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 35 35 + #define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 36 36 + #define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ 37 37 + #define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ 38 38 + #define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ 39 39 + #define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ 40 40 + #define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ 41 41 + #define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ 42 42 + #define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ 43 43 + #define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ 44 44 + #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ 45 45 + #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ 46 46 + 47 47 + 48 48 + /* 49 49 + * User Peripheral physical base addresses. 50 50 + */ 51 51 + #define AT91SAM9RL_BASE_TCB0 0xfffa0000 52 52 + #define AT91SAM9RL_BASE_TC0 0xfffa0000 53 53 + #define AT91SAM9RL_BASE_TC1 0xfffa0040 54 54 + #define AT91SAM9RL_BASE_TC2 0xfffa0080 55 55 + #define AT91SAM9RL_BASE_MCI 0xfffa4000 56 56 + #define AT91SAM9RL_BASE_TWI0 0xfffa8000 57 57 + #define AT91SAM9RL_BASE_TWI1 0xfffac000 58 58 + #define AT91SAM9RL_BASE_US0 0xfffb0000 59 59 + #define AT91SAM9RL_BASE_US1 0xfffb4000 60 60 + #define AT91SAM9RL_BASE_US2 0xfffb8000 61 61 + #define AT91SAM9RL_BASE_US3 0xfffbc000 62 62 + #define AT91SAM9RL_BASE_SSC0 0xfffc0000 63 63 + #define AT91SAM9RL_BASE_SSC1 0xfffc4000 64 64 + #define AT91SAM9RL_BASE_PWMC 0xfffc8000 65 65 + #define AT91SAM9RL_BASE_SPI 0xfffcc000 66 66 + #define AT91SAM9RL_BASE_TSC 0xfffd0000 67 67 + #define AT91SAM9RL_BASE_UDPHS 0xfffd4000 68 68 + #define AT91SAM9RL_BASE_AC97C 0xfffd8000 69 69 + #define AT91_BASE_SYS 0xffffc000 70 70 + 71 71 + 72 72 + /* 73 73 + * System Peripherals (offset from AT91_BASE_SYS) 74 74 + */ 75 75 + #define AT91_DMA (0xffffe600 - AT91_BASE_SYS) 76 76 + #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 77 77 + #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 78 78 + #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 79 79 + #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 80 80 + #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 81 81 + #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 82 82 + #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) 83 83 + #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) 84 84 + #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) 85 85 + #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) 86 86 + #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) 87 87 + #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 88 88 + #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 89 89 + #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 90 90 + #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) 91 91 + #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) 92 92 + #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 93 93 + #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 94 94 + #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 95 95 + #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) 96 96 + 97 97 + 98 98 + /* 99 99 + * Internal Memory. 100 100 + */ 101 101 + #define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 102 102 + #define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ 103 103 + 104 104 + #define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ 105 105 + #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ 106 106 + 107 107 + #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ 108 108 + #define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ 109 109 + 110 110 + #endif

+96

include/asm-arm/arch-at91/at91sam9rl_matrix.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-at91/at91sam9rl_matrix.h 3 3 + * 4 4 + * Copyright (C) 2007 Atmel Corporation 5 5 + * 6 6 + * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7 7 + * Based on AT91SAM9RL datasheet revision A. (Preliminary) 8 8 + * 9 9 + * This file is subject to the terms and conditions of the GNU General Public 10 10 + * License. See the file COPYING in the main directory of this archive for 11 11 + * more details. 12 12 + */ 13 13 + 14 14 + #ifndef AT91SAM9RL_MATRIX_H 15 15 + #define AT91SAM9RL_MATRIX_H 16 16 + 17 17 + #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18 18 + #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19 19 + #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20 20 + #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21 21 + #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22 22 + #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23 23 + #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 24 24 + #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 25 25 + #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 26 26 + #define AT91_MATRIX_ULBT_FOUR (2 << 0) 27 27 + #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 28 28 + #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 29 29 + 30 30 + #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 31 31 + #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 32 32 + #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 33 33 + #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 34 34 + #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 35 35 + #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 36 36 + #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 37 37 + #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 38 38 + #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 39 39 + #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 40 40 + #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 41 41 + #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 42 42 + #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ 43 43 + #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 44 44 + #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 45 45 + 46 46 + #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 47 47 + #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 48 48 + #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 49 49 + #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 50 50 + #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 51 51 + #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 52 52 + #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 53 53 + #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 54 54 + #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 55 55 + #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ 56 56 + #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 57 57 + #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 58 58 + 59 59 + #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 60 60 + #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 61 61 + #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 62 62 + #define AT91_MATRIX_RCB2 (1 << 2) 63 63 + #define AT91_MATRIX_RCB3 (1 << 3) 64 64 + #define AT91_MATRIX_RCB4 (1 << 4) 65 65 + #define AT91_MATRIX_RCB5 (1 << 5) 66 66 + 67 67 + #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ 68 68 + #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 69 69 + #define AT91_MATRIX_ITCM_0 (0 << 0) 70 70 + #define AT91_MATRIX_ITCM_16 (5 << 0) 71 71 + #define AT91_MATRIX_ITCM_32 (6 << 0) 72 72 + #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ 73 73 + #define AT91_MATRIX_DTCM_0 (0 << 4) 74 74 + #define AT91_MATRIX_DTCM_16 (5 << 4) 75 75 + #define AT91_MATRIX_DTCM_32 (6 << 4) 76 76 + 77 77 + #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ 78 78 + #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 79 79 + #define AT91_MATRIX_CS1A_SMC (0 << 1) 80 80 + #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 81 81 + #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ 82 82 + #define AT91_MATRIX_CS3A_SMC (0 << 3) 83 83 + #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 84 84 + #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ 85 85 + #define AT91_MATRIX_CS4A_SMC (0 << 4) 86 86 + #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) 87 87 + #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ 88 88 + #define AT91_MATRIX_CS5A_SMC (0 << 5) 89 89 + #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 90 90 + #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ 91 91 + #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ 92 92 + #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) 93 93 + #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) 94 94 + 95 95 + 96 96 + #endif

+9

include/asm-arm/arch-at91/cpu.h

reviewed

··· 26 26 #define ARCH_ID_AT91SAM9XE256 0x329a93a0 27 27 #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 28 28 29 29 + #define ARCH_ID_AT91SAM9RL64 0x019b03a0 30 30 + 29 31 static inline unsigned long at91_cpu_identify(void) 30 32 { 31 33 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); ··· 69 67 #else 70 68 #define cpu_is_at91sam9263() (0) 71 69 #endif 70 70 + 71 71 + #ifdef CONFIG_ARCH_AT91SAM9RL 72 72 + #define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) 73 73 + #else 74 74 + #define cpu_is_at91sam9rl() (0) 75 75 + #endif 76 76 + 72 77 73 78 /* 74 79 * Since this is ARM, we will never run on any AVR32 CPU. But these

+2 -17

include/asm-arm/arch-at91/hardware.h

reviewed

··· 24 24 #include <asm/arch/at91sam9261.h> 25 25 #elif defined(CONFIG_ARCH_AT91SAM9263) 26 26 #include <asm/arch/at91sam9263.h> 27 27 + #elif defined(CONFIG_ARCH_AT91SAM9RL) 28 28 + #include <asm/arch/at91sam9rl.h> 27 29 #else 28 30 #error "Unsupported AT91 processor" 29 31 #endif ··· 71 69 /* Clocks */ 72 70 #define AT91_SLOW_CLOCK 32768 /* slow clock */ 73 71 74 74 - #ifndef __ASSEMBLY__ 75 75 - #include <asm/io.h> 76 76 - 77 77 - static inline unsigned int at91_sys_read(unsigned int reg_offset) 78 78 - { 79 79 - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; 80 80 - 81 81 - return __raw_readl(addr + reg_offset); 82 82 - } 83 83 - 84 84 - static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) 85 85 - { 86 86 - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; 87 87 - 88 88 - __raw_writel(value, addr + reg_offset); 89 89 - } 90 90 - #endif 91 72 92 73 #endif

+18

include/asm-arm/arch-at91/io.h

reviewed

··· 29 29 #define __mem_pci(a) (a) 30 30 31 31 32 32 + #ifndef __ASSEMBLY__ 33 33 + 34 34 + static inline unsigned int at91_sys_read(unsigned int reg_offset) 35 35 + { 36 36 + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; 37 37 + 38 38 + return __raw_readl(addr + reg_offset); 39 39 + } 40 40 + 41 41 + static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) 42 42 + { 43 43 + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; 44 44 + 45 45 + __raw_writel(value, addr + reg_offset); 46 46 + } 47 47 + 48 48 + #endif 49 49 + 32 50 #endif

+1

include/asm-arm/arch-at91/irqs.h

reviewed

··· 21 21 #ifndef __ASM_ARCH_IRQS_H 22 22 #define __ASM_ARCH_IRQS_H 23 23 24 24 + #include <asm/io.h> 24 25 #include <asm/arch/at91_aic.h> 25 26 26 27 #define NR_AIC_IRQS 32

+5

include/asm-arm/arch-at91/timex.h

reviewed

··· 37 37 #define AT91SAM9_MASTER_CLOCK 99959500 38 38 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 39 39 40 40 + #elif defined(CONFIG_ARCH_AT91SAM9RL) 41 41 + 42 42 + #define AT91SAM9_MASTER_CLOCK 100000000 43 43 + #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 44 44 + 40 45 #endif 41 46 42 47 #endif

+1 -1

include/asm-arm/arch-at91/uncompress.h

reviewed

··· 21 21 #ifndef __ASM_ARCH_UNCOMPRESS_H 22 22 #define __ASM_ARCH_UNCOMPRESS_H 23 23 24 24 - #include <asm/hardware.h> 24 24 + #include <asm/io.h> 25 25 #include <asm/arch/at91_dbgu.h> 26 26 27 27 /*

+8

include/asm-arm/arch-cl7500/entry-macro.S

reviewed

··· 1 1 #include <asm/hardware.h> 2 2 #include <asm/hardware/entry-macro-iomd.S> 3 3 + 4 4 + .equ ioc_base_high, IOC_BASE & 0xff000000 5 5 + .equ ioc_base_low, IOC_BASE & 0x00ff0000 6 6 + 3 7 .macro get_irqnr_preamble, base, tmp 8 8 + mov \base, #ioc_base_high @ point at IOC 9 9 + .if ioc_base_low 10 10 + orr \base, \base, #ioc_base_low 11 11 + .endif 4 12 .endm 5 13 6 14 .macro arch_ret_to_user, tmp1, tmp2

+19

include/asm-arm/arch-davinci/common.h

reviewed

··· 1 1 + /* 2 2 + * Header for code common to all DaVinci machines. 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + 12 12 + #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H 13 13 + #define __ARCH_ARM_MACH_DAVINCI_COMMON_H 14 14 + 15 15 + struct sys_timer; 16 16 + 17 17 + extern struct sys_timer davinci_timer; 18 18 + 19 19 + #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */

+21

include/asm-arm/arch-davinci/debug-macro.S

reviewed

··· 1 1 + /* 2 2 + * Debugging macro for DaVinci 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + 12 12 + .macro addruart, rx 13 13 + mrc p15, 0, \rx, c1, c0 14 14 + tst \rx, #1 @ MMU enabled? 15 15 + moveq \rx, #0x01000000 @ physical base address 16 16 + movne \rx, #0xfe000000 @ virtual base 17 17 + orr \rx, \rx, #0x00c20000 @ UART 0 18 18 + .endm 19 19 + 20 20 + #define UART_SHIFT 2 21 21 + #include <asm/hardware/debug-8250.S>

+16

include/asm-arm/arch-davinci/dma.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci DMA definitions 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #ifndef __ASM_ARCH_DMA_H 12 12 + #define __ASM_ARCH_DMA_H 13 13 + 14 14 + #define MAX_DMA_ADDRESS 0xffffffff 15 15 + 16 16 + #endif /* __ASM_ARCH_DMA_H */

+32

include/asm-arm/arch-davinci/entry-macro.S

reviewed

··· 1 1 + /* 2 2 + * Low-level IRQ helper macros for TI DaVinci-based platforms 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #include <asm/arch/io.h> 12 12 + #include <asm/arch/irqs.h> 13 13 + 14 14 + .macro disable_fiq 15 15 + .endm 16 16 + 17 17 + .macro get_irqnr_preamble, base, tmp 18 18 + ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) 19 19 + .endm 20 20 + 21 21 + .macro arch_ret_to_user, tmp1, tmp2 22 22 + .endm 23 23 + 24 24 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 25 25 + ldr \tmp, [\base, #0x14] 26 26 + mov \tmp, \tmp, lsr #2 27 27 + sub \irqnr, \tmp, #1 28 28 + cmp \tmp, #0 29 29 + .endm 30 30 + 31 31 + .macro irq_prio_table 32 32 + .endm

+14

include/asm-arm/arch-davinci/hardware.h

reviewed

··· 1 1 + /* 2 2 + * Common hardware definitions 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #ifndef __ASM_ARCH_HARDWARE_H 12 12 + #define __ASM_ARCH_HARDWARE_H 13 13 + 14 14 + #endif /* __ASM_ARCH_HARDWARE_H */

+79

include/asm-arm/arch-davinci/io.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci IO address definitions 3 3 + * 4 4 + * Copied from include/asm/arm/arch-omap/io.h 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #ifndef __ASM_ARCH_IO_H 12 12 + #define __ASM_ARCH_IO_H 13 13 + 14 14 + #define IO_SPACE_LIMIT 0xffffffff 15 15 + 16 16 + /* 17 17 + * ---------------------------------------------------------------------------- 18 18 + * I/O mapping 19 19 + * ---------------------------------------------------------------------------- 20 20 + */ 21 21 + #define IO_PHYS 0x01c00000 22 22 + #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ 23 23 + #define IO_SIZE 0x00400000 24 24 + #define IO_VIRT (IO_PHYS + IO_OFFSET) 25 25 + #define io_p2v(pa) ((pa) + IO_OFFSET) 26 26 + #define io_v2p(va) ((va) - IO_OFFSET) 27 27 + #define IO_ADDRESS(x) io_p2v(x) 28 28 + 29 29 + /* 30 30 + * We don't actually have real ISA nor PCI buses, but there is so many 31 31 + * drivers out there that might just work if we fake them... 32 32 + */ 33 33 + #define PCIO_BASE 0 34 34 + #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) 35 35 + #define __mem_pci(a) (a) 36 36 + #define __mem_isa(a) (a) 37 37 + 38 38 + #ifndef __ASSEMBLER__ 39 39 + 40 40 + /* 41 41 + * Functions to access the DaVinci IO region 42 42 + * 43 43 + * NOTE: - Use davinci_read/write[bwl] for physical register addresses 44 44 + * - Use __raw_read/write[bwl]() for virtual register addresses 45 45 + * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses 46 46 + * - DO NOT use hardcoded virtual addresses to allow changing the 47 47 + * IO address space again if needed 48 48 + */ 49 49 + #define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) 50 50 + #define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) 51 51 + #define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) 52 52 + 53 53 + #define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) 54 54 + #define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 55 55 + #define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 56 56 + 57 57 + /* 16 bit uses LDRH/STRH, base +/- offset_8 */ 58 58 + typedef struct { volatile u16 offset[256]; } __regbase16; 59 59 + #define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ 60 60 + ->offset[((vaddr)&0xff)>>1] 61 61 + #define __REG16(paddr) __REGV16(io_p2v(paddr)) 62 62 + 63 63 + /* 8/32 bit uses LDR/STR, base +/- offset_12 */ 64 64 + typedef struct { volatile u8 offset[4096]; } __regbase8; 65 65 + #define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ 66 66 + ->offset[((vaddr)&4095)>>0] 67 67 + #define __REG8(paddr) __REGV8(io_p2v(paddr)) 68 68 + 69 69 + typedef struct { volatile u32 offset[4096]; } __regbase32; 70 70 + #define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ 71 71 + ->offset[((vaddr)&4095)>>2] 72 72 + 73 73 + #define __REG(paddr) __REGV32(io_p2v(paddr)) 74 74 + #else 75 75 + 76 76 + #define __REG(x) (*((volatile unsigned long *)io_p2v(x))) 77 77 + 78 78 + #endif /* __ASSEMBLER__ */ 79 79 + #endif /* __ASM_ARCH_IO_H */

+105

include/asm-arm/arch-davinci/irqs.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci interrupt controller definitions 3 3 + * 4 4 + * Copyright (C) 2006 Texas Instruments. 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify it 7 7 + * under the terms of the GNU General Public License as published by the 8 8 + * Free Software Foundation; either version 2 of the License, or (at your 9 9 + * option) any later version. 10 10 + * 11 11 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 12 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 13 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 14 14 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 15 15 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 16 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 17 17 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 18 18 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 19 19 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 20 20 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 21 + * 22 22 + * You should have received a copy of the GNU General Public License along 23 23 + * with this program; if not, write to the Free Software Foundation, Inc., 24 24 + * 675 Mass Ave, Cambridge, MA 02139, USA. 25 25 + * 26 26 + */ 27 27 + #ifndef __ASM_ARCH_IRQS_H 28 28 + #define __ASM_ARCH_IRQS_H 29 29 + 30 30 + /* Base address */ 31 31 + #define DAVINCI_ARM_INTC_BASE 0x01C48000 32 32 + 33 33 + /* Interrupt lines */ 34 34 + #define IRQ_VDINT0 0 35 35 + #define IRQ_VDINT1 1 36 36 + #define IRQ_VDINT2 2 37 37 + #define IRQ_HISTINT 3 38 38 + #define IRQ_H3AINT 4 39 39 + #define IRQ_PRVUINT 5 40 40 + #define IRQ_RSZINT 6 41 41 + #define IRQ_VFOCINT 7 42 42 + #define IRQ_VENCINT 8 43 43 + #define IRQ_ASQINT 9 44 44 + #define IRQ_IMXINT 10 45 45 + #define IRQ_VLCDINT 11 46 46 + #define IRQ_USBINT 12 47 47 + #define IRQ_EMACINT 13 48 48 + 49 49 + #define IRQ_CCINT0 16 50 50 + #define IRQ_CCERRINT 17 51 51 + #define IRQ_TCERRINT0 18 52 52 + #define IRQ_TCERRINT 19 53 53 + #define IRQ_PSCIN 20 54 54 + 55 55 + #define IRQ_IDE 22 56 56 + #define IRQ_HPIINT 23 57 57 + #define IRQ_MBXINT 24 58 58 + #define IRQ_MBRINT 25 59 59 + #define IRQ_MMCINT 26 60 60 + #define IRQ_SDIOINT 27 61 61 + #define IRQ_MSINT 28 62 62 + #define IRQ_DDRINT 29 63 63 + #define IRQ_AEMIFINT 30 64 64 + #define IRQ_VLQINT 31 65 65 + #define IRQ_TINT0_TINT12 32 66 66 + #define IRQ_TINT0_TINT34 33 67 67 + #define IRQ_TINT1_TINT12 34 68 68 + #define IRQ_TINT1_TINT34 35 69 69 + #define IRQ_PWMINT0 36 70 70 + #define IRQ_PWMINT1 37 71 71 + #define IRQ_PWMINT2 38 72 72 + #define IRQ_I2C 39 73 73 + #define IRQ_UARTINT0 40 74 74 + #define IRQ_UARTINT1 41 75 75 + #define IRQ_UARTINT2 42 76 76 + #define IRQ_SPINT0 43 77 77 + #define IRQ_SPINT1 44 78 78 + 79 79 + #define IRQ_DSP2ARM0 46 80 80 + #define IRQ_DSP2ARM1 47 81 81 + #define IRQ_GPIO0 48 82 82 + #define IRQ_GPIO1 49 83 83 + #define IRQ_GPIO2 50 84 84 + #define IRQ_GPIO3 51 85 85 + #define IRQ_GPIO4 52 86 86 + #define IRQ_GPIO5 53 87 87 + #define IRQ_GPIO6 54 88 88 + #define IRQ_GPIO7 55 89 89 + #define IRQ_GPIOBNK0 56 90 90 + #define IRQ_GPIOBNK1 57 91 91 + #define IRQ_GPIOBNK2 58 92 92 + #define IRQ_GPIOBNK3 59 93 93 + #define IRQ_GPIOBNK4 60 94 94 + #define IRQ_COMMTX 61 95 95 + #define IRQ_COMMRX 62 96 96 + #define IRQ_EMUINT 63 97 97 + 98 98 + #define DAVINCI_N_AINTC_IRQ 64 99 99 + #define DAVINCI_N_GPIO 71 100 100 + 101 101 + #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) 102 102 + 103 103 + #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 104 104 + 105 105 + #endif /* __ASM_ARCH_IRQS_H */

+64

include/asm-arm/arch-davinci/memory.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci memory space definitions 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #ifndef __ASM_ARCH_MEMORY_H 12 12 + #define __ASM_ARCH_MEMORY_H 13 13 + 14 14 + /************************************************************************** 15 15 + * Included Files 16 16 + **************************************************************************/ 17 17 + #include <asm/page.h> 18 18 + #include <asm/sizes.h> 19 19 + 20 20 + /************************************************************************** 21 21 + * Definitions 22 22 + **************************************************************************/ 23 23 + #define DAVINCI_DDR_BASE 0x80000000 24 24 + #define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ 25 25 + 26 26 + #define PHYS_OFFSET DAVINCI_DDR_BASE 27 27 + 28 28 + /* 29 29 + * Increase size of DMA-consistent memory region 30 30 + */ 31 31 + #define CONSISTENT_DMA_SIZE (14<<20) 32 32 + 33 33 + #ifndef __ASSEMBLY__ 34 34 + /* 35 35 + * Restrict DMA-able region to workaround silicon bug. The bug 36 36 + * restricts buffers available for DMA to video hardware to be 37 37 + * below 128M 38 38 + */ 39 39 + static inline void 40 40 + __arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) 41 41 + { 42 42 + unsigned int sz = (128<<20) >> PAGE_SHIFT; 43 43 + 44 44 + if (node != 0) 45 45 + sz = 0; 46 46 + 47 47 + size[1] = size[0] - sz; 48 48 + size[0] = sz; 49 49 + } 50 50 + 51 51 + #define arch_adjust_zones(node, zone_size, holes) \ 52 52 + if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) 53 53 + 54 54 + #define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) 55 55 + 56 56 + #endif 57 57 + 58 58 + /* 59 59 + * Bus address is physical address 60 60 + */ 61 61 + #define __virt_to_bus(x) __virt_to_phys(x) 62 62 + #define __bus_to_virt(x) __phys_to_virt(x) 63 63 + 64 64 + #endif /* __ASM_ARCH_MEMORY_H */

+76

include/asm-arm/arch-davinci/psc.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci Power & Sleep Controller (PSC) defines 3 3 + * 4 4 + * Copyright (C) 2006 Texas Instruments. 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify it 7 7 + * under the terms of the GNU General Public License as published by the 8 8 + * Free Software Foundation; either version 2 of the License, or (at your 9 9 + * option) any later version. 10 10 + * 11 11 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 12 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 13 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 14 14 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 15 15 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 16 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 17 17 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 18 18 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 19 19 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 20 20 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 21 + * 22 22 + * You should have received a copy of the GNU General Public License along 23 23 + * with this program; if not, write to the Free Software Foundation, Inc., 24 24 + * 675 Mass Ave, Cambridge, MA 02139, USA. 25 25 + * 26 26 + */ 27 27 + #ifndef __ASM_ARCH_PSC_H 28 28 + #define __ASM_ARCH_PSC_H 29 29 + 30 30 + /* Power and Sleep Controller (PSC) Domains */ 31 31 + #define DAVINCI_GPSC_ARMDOMAIN 0 32 32 + #define DAVINCI_GPSC_DSPDOMAIN 1 33 33 + 34 34 + #define DAVINCI_LPSC_VPSSMSTR 0 35 35 + #define DAVINCI_LPSC_VPSSSLV 1 36 36 + #define DAVINCI_LPSC_TPCC 2 37 37 + #define DAVINCI_LPSC_TPTC0 3 38 38 + #define DAVINCI_LPSC_TPTC1 4 39 39 + #define DAVINCI_LPSC_EMAC 5 40 40 + #define DAVINCI_LPSC_EMAC_WRAPPER 6 41 41 + #define DAVINCI_LPSC_MDIO 7 42 42 + #define DAVINCI_LPSC_IEEE1394 8 43 43 + #define DAVINCI_LPSC_USB 9 44 44 + #define DAVINCI_LPSC_ATA 10 45 45 + #define DAVINCI_LPSC_VLYNQ 11 46 46 + #define DAVINCI_LPSC_UHPI 12 47 47 + #define DAVINCI_LPSC_DDR_EMIF 13 48 48 + #define DAVINCI_LPSC_AEMIF 14 49 49 + #define DAVINCI_LPSC_MMC_SD 15 50 50 + #define DAVINCI_LPSC_MEMSTICK 16 51 51 + #define DAVINCI_LPSC_McBSP 17 52 52 + #define DAVINCI_LPSC_I2C 18 53 53 + #define DAVINCI_LPSC_UART0 19 54 54 + #define DAVINCI_LPSC_UART1 20 55 55 + #define DAVINCI_LPSC_UART2 21 56 56 + #define DAVINCI_LPSC_SPI 22 57 57 + #define DAVINCI_LPSC_PWM0 23 58 58 + #define DAVINCI_LPSC_PWM1 24 59 59 + #define DAVINCI_LPSC_PWM2 25 60 60 + #define DAVINCI_LPSC_GPIO 26 61 61 + #define DAVINCI_LPSC_TIMER0 27 62 62 + #define DAVINCI_LPSC_TIMER1 28 63 63 + #define DAVINCI_LPSC_TIMER2 29 64 64 + #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 65 65 + #define DAVINCI_LPSC_ARM 31 66 66 + #define DAVINCI_LPSC_SCR2 32 67 67 + #define DAVINCI_LPSC_SCR3 33 68 68 + #define DAVINCI_LPSC_SCR4 34 69 69 + #define DAVINCI_LPSC_CROSSBAR 35 70 70 + #define DAVINCI_LPSC_CFG27 36 71 71 + #define DAVINCI_LPSC_CFG3 37 72 72 + #define DAVINCI_LPSC_CFG5 38 73 73 + #define DAVINCI_LPSC_GEM 39 74 74 + #define DAVINCI_LPSC_IMCOP 40 75 75 + 76 76 + #endif /* __ASM_ARCH_PSC_H */

+20

include/asm-arm/arch-davinci/serial.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci serial device definitions 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #ifndef __ASM_ARCH_SERIAL_H 12 12 + #define __ASM_ARCH_SERIAL_H 13 13 + 14 14 + #include <asm/arch/io.h> 15 15 + 16 16 + #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 17 17 + #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 18 18 + #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 19 19 + 20 20 + #endif /* __ASM_ARCH_SERIAL_H */

+29

include/asm-arm/arch-davinci/system.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci system defines 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #ifndef __ASM_ARCH_SYSTEM_H 12 12 + #define __ASM_ARCH_SYSTEM_H 13 13 + 14 14 + #include <asm/io.h> 15 15 + #include <asm/hardware.h> 16 16 + 17 17 + extern void davinci_watchdog_reset(void); 18 18 + 19 19 + static void arch_idle(void) 20 20 + { 21 21 + cpu_do_idle(); 22 22 + } 23 23 + 24 24 + static void arch_reset(char mode) 25 25 + { 26 26 + davinci_watchdog_reset(); 27 27 + } 28 28 + 29 29 + #endif /* __ASM_ARCH_SYSTEM_H */

+17

include/asm-arm/arch-davinci/timex.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci timer defines 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #ifndef __ASM_ARCH_TIMEX_H 12 12 + #define __ASM_ARCH_TIMEX_H 13 13 + 14 14 + /* The source frequency for the timers is the 27MHz clock */ 15 15 + #define CLOCK_TICK_RATE 27000000 16 16 + 17 17 + #endif /* __ASM_ARCH_TIMEX_H__ */

+35

include/asm-arm/arch-davinci/uncompress.h

reviewed

··· 1 1 + /* 2 2 + * Serial port stubs for kernel decompress status messages 3 3 + * 4 4 + * Author: Anant Gole 5 5 + * (C) Copyright (C) 2006, Texas Instruments, Inc 6 6 + * 7 7 + * This file is licensed under the terms of the GNU General Public License 8 8 + * version 2. This program is licensed "as is" without any warranty of any 9 9 + * kind, whether express or implied. 10 10 + */ 11 11 + 12 12 + #include <linux/types.h> 13 13 + #include <linux/serial_reg.h> 14 14 + #include <asm/arch/serial.h> 15 15 + 16 16 + /* PORT_16C550A, in polled non-fifo mode */ 17 17 + 18 18 + static void putc(char c) 19 19 + { 20 20 + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; 21 21 + 22 22 + while (!(uart[UART_LSR] & UART_LSR_THRE)) 23 23 + barrier(); 24 24 + uart[UART_TX] = c; 25 25 + } 26 26 + 27 27 + static inline void flush(void) 28 28 + { 29 29 + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; 30 30 + while (!(uart[UART_LSR] & UART_LSR_THRE)) 31 31 + barrier(); 32 32 + } 33 33 + 34 34 + #define arch_decomp_setup() 35 35 + #define arch_decomp_wdog()

+15

include/asm-arm/arch-davinci/vmalloc.h

reviewed

··· 1 1 + /* 2 2 + * DaVinci vmalloc definitions 3 3 + * 4 4 + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 5 + * 6 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 7 + * the terms of the GNU General Public License version 2. This program 8 8 + * is licensed "as is" without any warranty of any kind, whether express 9 9 + * or implied. 10 10 + */ 11 11 + #include <asm/memory.h> 12 12 + #include <asm/arch/io.h> 13 13 + 14 14 + /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ 15 15 + #define VMALLOC_END (IO_VIRT - (2<<20))

+1 -1

include/asm-arm/arch-ebsa110/entry-macro.S

reviewed

··· 16 16 .endm 17 17 18 18 .macro get_irqnr_preamble, base, tmp 19 19 + mov \base, #IRQ_STAT 19 20 .endm 20 21 21 22 .macro arch_ret_to_user, tmp1, tmp2 22 23 .endm 23 24 24 25 .macro get_irqnr_and_base, irqnr, stat, base, tmp 25 25 - mov \base, #IRQ_STAT 26 26 ldrb \stat, [\base] @ get interrupts 27 27 mov \irqnr, #0 28 28 tst \stat, #15

+8 -8

include/asm-arm/arch-ebsa285/entry-macro.S

reviewed

··· 11 11 #include <asm/arch/irqs.h> 12 12 #include <asm/hardware/dec21285.h> 13 13 14 14 + .equ dc21285_high, ARMCSR_BASE & 0xff000000 15 15 + .equ dc21285_low, ARMCSR_BASE & 0x00ffffff 16 16 + 14 17 .macro disable_fiq 15 18 .endm 16 19 17 20 .macro get_irqnr_preamble, base, tmp 21 21 + mov \base, #dc21285_high 22 22 + .if dc21285_low 23 23 + orr \base, \base, #dc21285_low 24 24 + .endif 18 25 .endm 19 26 20 27 .macro arch_ret_to_user, tmp1, tmp2 21 28 .endm 22 29 23 23 - .equ dc21285_high, ARMCSR_BASE & 0xff000000 24 24 - .equ dc21285_low, ARMCSR_BASE & 0x00ffffff 25 25 - 26 30 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 27 27 - mov r4, #dc21285_high 28 28 - .if dc21285_low 29 29 - orr r4, r4, #dc21285_low 30 30 - .endif 31 31 - ldr \irqstat, [r4, #0x180] @ get interrupts 31 31 + ldr \irqstat, [\base, #0x180] @ get interrupts 32 32 33 33 mov \irqnr, #IRQ_SDRAMPARITY 34 34 tst \irqstat, #IRQ_MASK_SDRAMPARITY

+1 -1

include/asm-arm/arch-iop13xx/io.h

reviewed

··· 27 27 28 28 extern void __iomem * __iop13xx_io(unsigned long io_addr); 29 29 extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, 30 30 - unsigned long flags); 30 30 + unsigned int mtype); 31 31 extern void __iop13xx_iounmap(void __iomem *addr); 32 32 33 33 extern u32 iop13xx_atue_mem_base;

+29

include/asm-arm/arch-iop13xx/iop13xx.h

reviewed

··· 181 181 #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 182 182 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 183 183 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 184 184 + #define IOP13XX_MU_PMMR_OFFSET 0x00004000 184 185 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 185 186 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) 186 187 ··· 411 410 #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000) 412 411 #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28) 413 412 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) 413 413 + /*=======================================================================*/ 414 414 + 415 415 + /*============================MESSAGING UNIT=============================*/ 416 416 + #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ 417 417 + (ofs)) 418 418 + 419 419 + #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) 420 420 + #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) 421 421 + #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) 422 422 + #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) 423 423 + #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) 424 424 + #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) 425 425 + #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) 426 426 + #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) 427 427 + #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) 428 428 + #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) 429 429 + #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) 430 430 + #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) 431 431 + #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) 432 432 + #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) 433 433 + #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) 434 434 + #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) 435 435 + 436 436 + #define IOP13XX_MU_WINDOW_SIZE (8 * 1024) 437 437 + #define IOP13XX_MU_BASE_PHYS (0xff000000) 438 438 + #define IOP13XX_MU_BASE_PCI (0xff000000) 439 439 + #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) 440 440 + #define IOP13XX_MU_MIMR_CORE_SELECT (15) 414 441 /*=======================================================================*/ 415 442 416 443 /*==============================ADMA UNITS===============================*/

+7 -1

include/asm-arm/arch-iop13xx/irqs.h

reviewed

··· 168 168 #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ 169 169 #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ 170 170 #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ 171 171 - #define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ 171 171 + #define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ 172 172 #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ 173 173 #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ 174 174 #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ ··· 184 184 #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ 185 185 #define IRQ_IOP13XX_HPI (127) /* 31 */ 186 186 187 187 + #ifdef CONFIG_PCI_MSI 188 188 + #define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) 189 189 + #define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) 190 190 + #else 187 191 #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) 192 192 + #endif 193 193 + 188 194 #define NR_IRQS NR_IOP13XX_IRQS 189 195 190 196 #endif /* _IOP13XX_IRQ_H_ */

+11

include/asm-arm/arch-iop13xx/msi.h

reviewed

··· 1 1 + #ifndef _IOP13XX_MSI_H_ 2 2 + #define _IOP13XX_MSI_H_ 3 3 + #ifdef CONFIG_PCI_MSI 4 4 + void iop13xx_msi_init(void); 5 5 + #else 6 6 + static inline void iop13xx_msi_init(void) 7 7 + { 8 8 + return; 9 9 + } 10 10 + #endif 11 11 + #endif

+1 -1

include/asm-arm/arch-iop32x/io.h

reviewed

··· 14 14 #include <asm/hardware.h> 15 15 16 16 extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, 17 17 - unsigned long flags); 17 17 + unsigned int mtype); 18 18 extern void __iop3xx_iounmap(void __iomem *addr); 19 19 20 20 #define IO_SPACE_LIMIT 0xffffffff

+1 -1

include/asm-arm/arch-iop33x/io.h

reviewed

··· 14 14 #include <asm/hardware.h> 15 15 16 16 extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, 17 17 - unsigned long flags); 17 17 + unsigned int mtype); 18 18 extern void __iop3xx_iounmap(void __iomem *addr); 19 19 20 20 #define IO_SPACE_LIMIT 0xffffffff

+38

include/asm-arm/arch-ks8695/debug-macro.S

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/debug-macro.S 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - Debug macros 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License version 2 as 11 11 + * published by the Free Software Foundation. 12 12 + */ 13 13 + 14 14 + #include <asm/hardware.h> 15 15 + #include <asm/arch/regs-uart.h> 16 16 + 17 17 + .macro addruart, rx 18 18 + mrc p15, 0, \rx, c1, c0 19 19 + tst \rx, #1 @ MMU enabled? 20 20 + ldreq \rx, =KS8695_UART_PA @ physical base address 21 21 + ldrne \rx, =KS8695_UART_VA @ virtual base address 22 22 + .endm 23 23 + 24 24 + .macro senduart, rd, rx 25 25 + str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register 26 26 + .endm 27 27 + 28 28 + .macro busyuart, rd, rx 29 29 + 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register 30 30 + tst \rd, #URLS_URTE @ Holding & Shift registers empty? 31 31 + beq 1001b 32 32 + .endm 33 33 + 34 34 + .macro waituart, rd, rx 35 35 + 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register 36 36 + tst \rd, #URLS_URTHRE @ Holding Register empty? 37 37 + beq 1001b 38 38 + .endm

+32

include/asm-arm/arch-ks8695/devices.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/devices.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License version 2 as 8 8 + * published by the Free Software Foundation. 9 9 + */ 10 10 + 11 11 + #ifndef __ASM_ARCH_DEVICES_H 12 12 + #define __ASM_ARCH_DEVICES_H 13 13 + 14 14 + #include <linux/pci.h> 15 15 + 16 16 + /* Ethernet */ 17 17 + extern void __init ks8695_add_device_wan(void); 18 18 + extern void __init ks8695_add_device_lan(void); 19 19 + extern void __init ks8695_add_device_hpna(void); 20 20 + 21 21 + /* PCI */ 22 22 + #define KS8695_MODE_PCI 0 23 23 + #define KS8695_MODE_MINIPCI 1 24 24 + #define KS8695_MODE_CARDBUS 2 25 25 + 26 26 + struct ks8695_pci_cfg { 27 27 + short mode; 28 28 + int (*map_irq)(struct pci_dev *, u8, u8); 29 29 + }; 30 30 + extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); 31 31 + 32 32 + #endif

+17

include/asm-arm/arch-ks8695/dma.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/dma.h 3 3 + * 4 4 + * This program is free software; you can redistribute it and/or modify 5 5 + * it under the terms of the GNU General Public License as published by 6 6 + * the Free Software Foundation; either version 2 of the License, or 7 7 + * (at your option) any later version. 8 8 + * 9 9 + * This program is distributed in the hope that it will be useful, 10 10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 12 + * GNU General Public License for more details. 13 13 + * 14 14 + * You should have received a copy of the GNU General Public License 15 15 + * along with this program; if not, write to the Free Software 16 16 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 17 + */

+53

include/asm-arm/arch-ks8695/entry-macro.S

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/entry-macro.S 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * Low-level IRQ helper macros for KS8695 8 8 + * 9 9 + * This file is licensed under the terms of the GNU General Public 10 10 + * License version 2. This program is licensed "as is" without any 11 11 + * warranty of any kind, whether express or implied. 12 12 + */ 13 13 + 14 14 + #include <asm/hardware.h> 15 15 + #include <asm/arch/regs-irq.h> 16 16 + 17 17 + .macro disable_fiq 18 18 + .endm 19 19 + 20 20 + .macro get_irqnr_preamble, base, tmp 21 21 + ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller 22 22 + .endm 23 23 + 24 24 + .macro arch_ret_to_user, tmp1, tmp2 25 25 + .endm 26 26 + 27 27 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 28 28 + ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register 29 29 + 30 30 + teq \irqstat, #0 31 31 + beq 1001f 32 32 + 33 33 + mov \irqnr, #0 34 34 + 35 35 + tst \irqstat, #0xff 36 36 + moveq \irqstat, \irqstat, lsr #8 37 37 + addeq \irqnr, \irqnr, #8 38 38 + tsteq \irqstat, #0xff 39 39 + moveq \irqstat, \irqstat, lsr #8 40 40 + addeq \irqnr, \irqnr, #8 41 41 + tsteq \irqstat, #0xff 42 42 + moveq \irqstat, \irqstat, lsr #8 43 43 + addeq \irqnr, \irqnr, #8 44 44 + tst \irqstat, #0x0f 45 45 + moveq \irqstat, \irqstat, lsr #4 46 46 + addeq \irqnr, \irqnr, #4 47 47 + tst \irqstat, #0x03 48 48 + moveq \irqstat, \irqstat, lsr #2 49 49 + addeq \irqnr, \irqnr, #2 50 50 + tst \irqstat, #0x01 51 51 + addeqs \irqnr, \irqnr, #1 52 52 + 1001: 53 53 + .endm

+49

include/asm-arm/arch-ks8695/hardware.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/hardware.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - Memory Map definitions 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License version 2 as 11 11 + * published by the Free Software Foundation. 12 12 + */ 13 13 + 14 14 + #ifndef __ASM_ARCH_HARDWARE_H 15 15 + #define __ASM_ARCH_HARDWARE_H 16 16 + 17 17 + #include <asm/sizes.h> 18 18 + 19 19 + /* 20 20 + * Physical RAM address. 21 21 + */ 22 22 + #define KS8695_SDRAM_PA 0x00000000 23 23 + 24 24 + 25 25 + /* 26 26 + * We map an entire MiB with the System Configuration Registers in even 27 27 + * though only 64KiB is needed. This makes it easier for use with the 28 28 + * head debug code as the initial MMU setup only deals in L1 sections. 29 29 + */ 30 30 + #define KS8695_IO_PA 0x03F00000 31 31 + #define KS8695_IO_VA 0xF0000000 32 32 + #define KS8695_IO_SIZE SZ_1M 33 33 + 34 34 + #define KS8695_PCIMEM_PA 0x60000000 35 35 + #define KS8695_PCIMEM_SIZE SZ_512M 36 36 + 37 37 + #define KS8695_PCIIO_PA 0x80000000 38 38 + #define KS8695_PCIIO_SIZE SZ_64K 39 39 + 40 40 + 41 41 + /* 42 42 + * PCI support 43 43 + */ 44 44 + #define pcibios_assign_all_busses() 1 45 45 + 46 46 + #define PCIBIOS_MIN_IO 0 47 47 + #define PCIBIOS_MIN_MEM 0 48 48 + 49 49 + #endif

+19

include/asm-arm/arch-ks8695/io.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/io.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * This file is licensed under the terms of the GNU General Public 7 7 + * License version 2. This program is licensed "as is" without any 8 8 + * warranty of any kind, whether express or implied. 9 9 + */ 10 10 + 11 11 + #ifndef __ASM_ARCH_IO_H 12 12 + #define __ASM_ARCH_IO_H 13 13 + 14 14 + #define IO_SPACE_LIMIT 0xffffffff 15 15 + 16 16 + #define __io(a) ((void __iomem *)(a)) 17 17 + #define __mem_pci(a) (a) 18 18 + 19 19 + #endif

+54

include/asm-arm/arch-ks8695/irqs.h

reviewed

··· 1 1 + /* 2 2 + * linux/include/asm-arm/arch-ks8695/irqs.h 3 3 + * 4 4 + * Copyright (C) 2006 Simtec Electronics 5 5 + * Ben Dooks <ben@simtec.co.uk> 6 6 + * 7 7 + * This program is free software; you can redistribute it and/or modify 8 8 + * it under the terms of the GNU General Public License version 2 as 9 9 + * published by the Free Software Foundation. 10 10 + */ 11 11 + 12 12 + #ifndef __ASM_ARCH_IRQS_H 13 13 + #define __ASM_ARCH_IRQS_H 14 14 + 15 15 + 16 16 + #define NR_IRQS 32 17 17 + 18 18 + /* 19 19 + * IRQ definitions 20 20 + */ 21 21 + #define KS8695_IRQ_COMM_RX 0 22 22 + #define KS8695_IRQ_COMM_TX 1 23 23 + #define KS8695_IRQ_EXTERN0 2 24 24 + #define KS8695_IRQ_EXTERN1 3 25 25 + #define KS8695_IRQ_EXTERN2 4 26 26 + #define KS8695_IRQ_EXTERN3 5 27 27 + #define KS8695_IRQ_TIMER0 6 28 28 + #define KS8695_IRQ_TIMER1 7 29 29 + #define KS8695_IRQ_UART_TX 8 30 30 + #define KS8695_IRQ_UART_RX 9 31 31 + #define KS8695_IRQ_UART_LINE_STATUS 10 32 32 + #define KS8695_IRQ_UART_MODEM_STATUS 11 33 33 + #define KS8695_IRQ_LAN_RX_STOP 12 34 34 + #define KS8695_IRQ_LAN_TX_STOP 13 35 35 + #define KS8695_IRQ_LAN_RX_BUF 14 36 36 + #define KS8695_IRQ_LAN_TX_BUF 15 37 37 + #define KS8695_IRQ_LAN_RX_STATUS 16 38 38 + #define KS8695_IRQ_LAN_TX_STATUS 17 39 39 + #define KS8695_IRQ_HPNA_RX_STOP 18 40 40 + #define KS8695_IRQ_HPNA_TX_STOP 19 41 41 + #define KS8695_IRQ_HPNA_RX_BUF 20 42 42 + #define KS8695_IRQ_HPNA_TX_BUF 21 43 43 + #define KS8695_IRQ_HPNA_RX_STATUS 22 44 44 + #define KS8695_IRQ_HPNA_TX_STATUS 23 45 45 + #define KS8695_IRQ_BUS_ERROR 24 46 46 + #define KS8695_IRQ_WAN_RX_STOP 25 47 47 + #define KS8695_IRQ_WAN_TX_STOP 26 48 48 + #define KS8695_IRQ_WAN_RX_BUF 27 49 49 + #define KS8695_IRQ_WAN_TX_BUF 28 50 50 + #define KS8695_IRQ_WAN_RX_STATUS 29 51 51 + #define KS8695_IRQ_WAN_TX_STATUS 30 52 52 + #define KS8695_IRQ_WAN_LINK 31 53 53 + 54 54 + #endif

+49

include/asm-arm/arch-ks8695/memory.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/memory.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * KS8695 Memory definitions 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef __ASM_ARCH_MEMORY_H 14 14 + #define __ASM_ARCH_MEMORY_H 15 15 + 16 16 + #include <asm/hardware.h> 17 17 + 18 18 + /* 19 19 + * Physical SRAM offset. 20 20 + */ 21 21 + #define PHYS_OFFSET KS8695_SDRAM_PA 22 22 + 23 23 + #ifndef __ASSEMBLY__ 24 24 + 25 25 + #ifdef CONFIG_PCI 26 26 + 27 27 + /* PCI mappings */ 28 28 + #define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) 29 29 + #define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) 30 30 + 31 31 + /* Platform-bus mapping */ 32 32 + extern struct bus_type platform_bus_type; 33 33 + #define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) 34 34 + #define __arch_dma_to_virt(dev, x) ({ is_lbus_device(dev) ? \ 35 35 + __phys_to_virt(x) : __bus_to_virt(x); }) 36 36 + #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ 37 37 + (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) 38 38 + #define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) 39 39 + 40 40 + #else 41 41 + 42 42 + #define __virt_to_bus(x) __virt_to_phys(x) 43 43 + #define __bus_to_virt(x) __phys_to_virt(x) 44 44 + 45 45 + #endif 46 46 + 47 47 + #endif 48 48 + 49 49 + #endif

+53

include/asm-arm/arch-ks8695/regs-gpio.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-gpio.h 3 3 + * 4 4 + * Copyright (C) 2007 Andrew Victor 5 5 + * 6 6 + * KS8695 - GPIO control registers and bit definitions. 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef KS8695_GPIO_H 14 14 + #define KS8695_GPIO_H 15 15 + 16 16 + #define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) 17 17 + #define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) 18 18 + #define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) 19 19 + 20 20 + 21 21 + #define KS8695_IOPM (0x00) /* I/O Port Mode Register */ 22 22 + #define KS8695_IOPC (0x04) /* I/O Port Control Register */ 23 23 + #define KS8695_IOPD (0x08) /* I/O Port Data Register */ 24 24 + 25 25 + 26 26 + /* Port Mode Register */ 27 27 + #define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */ 28 28 + 29 29 + /* Port Control Register */ 30 30 + #define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ 31 31 + #define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ 32 32 + #define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ 33 33 + #define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ 34 34 + #define IOPC_IOEINT3_MODE(x) ((x) << 12) 35 35 + #define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ 36 36 + #define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ 37 37 + #define IOPC_IOEINT2_MODE(x) ((x) << 8) 38 38 + #define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ 39 39 + #define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ 40 40 + #define IOPC_IOEINT1_MODE(x) ((x) << 4) 41 41 + #define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ 42 42 + #define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ 43 43 + #define IOPC_IOEINT0_MODE(x) ((x) << 0) 44 44 + 45 45 + /* Trigger Modes */ 46 46 + #define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ 47 47 + #define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ 48 48 + #define IOPC_TM_RISING (2) /* Rising Edge Detection */ 49 49 + #define IOPC_TM_FALLING (4) /* Falling Edge Detection */ 50 50 + #define IOPC_TM_EDGE (6) /* Both Edge Detection */ 51 51 + 52 52 + 53 53 + #endif

+25

include/asm-arm/arch-ks8695/regs-hpna.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-wan.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * KS8695 - HPNA Registers and bit definitions. 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef KS8695_HPNA_H 14 14 + #define KS8695_HPNA_H 15 15 + 16 16 + #define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) 17 17 + #define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) 18 18 + #define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) 19 19 + 20 20 + 21 21 + /* 22 22 + * HPNA registers 23 23 + */ 24 24 + 25 25 + #endif

+41

include/asm-arm/arch-ks8695/regs-irq.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-irq.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - IRQ registers and bit definitions 8 8 + * 9 9 + * This file is licensed under the terms of the GNU General Public 10 10 + * License version 2. This program is licensed "as is" without any 11 11 + * warranty of any kind, whether express or implied. 12 12 + */ 13 13 + 14 14 + #ifndef KS8695_IRQ_H 15 15 + #define KS8695_IRQ_H 16 16 + 17 17 + #define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) 18 18 + #define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) 19 19 + #define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) 20 20 + 21 21 + 22 22 + /* 23 23 + * Interrupt Controller registers 24 24 + */ 25 25 + #define KS8695_INTMC (0x00) /* Mode Control Register */ 26 26 + #define KS8695_INTEN (0x04) /* Interrupt Enable Register */ 27 27 + #define KS8695_INTST (0x08) /* Interrupt Status Register */ 28 28 + #define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ 29 29 + #define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ 30 30 + #define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ 31 31 + #define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ 32 32 + #define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ 33 33 + #define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ 34 34 + #define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ 35 35 + #define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ 36 36 + #define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ 37 37 + #define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ 38 38 + #define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ 39 39 + 40 40 + 41 41 + #endif

+65

include/asm-arm/arch-ks8695/regs-lan.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-lan.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * KS8695 - LAN Registers and bit definitions. 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef KS8695_LAN_H 14 14 + #define KS8695_LAN_H 15 15 + 16 16 + #define KS8695_LAN_OFFSET (0xF0000 + 0x8000) 17 17 + #define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) 18 18 + #define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) 19 19 + 20 20 + 21 21 + /* 22 22 + * LAN registers 23 23 + */ 24 24 + #define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ 25 25 + #define KS8695_LMDRXC (0x04) /* DMA Receive Control */ 26 26 + #define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ 27 27 + #define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ 28 28 + #define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ 29 29 + #define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ 30 30 + #define KS8695_LMAL (0x18) /* MAC Station Address Low */ 31 31 + #define KS8695_LMAH (0x1c) /* MAC Station Address High */ 32 32 + #define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ 33 33 + #define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ 34 34 + 35 35 + 36 36 + /* DMA Transmit Control Register */ 37 37 + #define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ 38 38 + #define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ 39 39 + #define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ 40 40 + #define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ 41 41 + #define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ 42 42 + #define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ 43 43 + #define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ 44 44 + #define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ 45 45 + #define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ 46 46 + #define LMDTXC_LMTE (1 << 0) /* TX Enable */ 47 47 + 48 48 + /* DMA Receive Control Register */ 49 49 + #define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ 50 50 + #define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ 51 51 + #define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ 52 52 + #define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ 53 53 + #define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ 54 54 + #define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ 55 55 + #define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ 56 56 + #define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ 57 57 + #define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ 58 58 + #define LMDRXC_LMRA (1 << 2) /* Receive All */ 59 59 + #define LMDRXC_LMRE (1 << 1) /* RX Enable */ 60 60 + 61 61 + /* Additional Station Address High */ 62 62 + #define LMAAH_E (1 << 31) /* Address Enabled */ 63 63 + 64 64 + 65 65 + #endif

+89

include/asm-arm/arch-ks8695/regs-mem.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-mem.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * KS8695 - Memory Controller registers and bit definitions 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef KS8695_MEM_H 14 14 + #define KS8695_MEM_H 15 15 + 16 16 + #define KS8695_MEM_OFFSET (0xF0000 + 0x4000) 17 17 + #define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) 18 18 + #define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) 19 19 + 20 20 + 21 21 + /* 22 22 + * Memory Controller Registers 23 23 + */ 24 24 + #define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ 25 25 + #define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ 26 26 + #define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ 27 27 + #define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ 28 28 + #define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ 29 29 + #define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ 30 30 + #define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ 31 31 + #define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ 32 32 + #define KS8695_SDGCON (0x38) /* SDRAM General Control */ 33 33 + #define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ 34 34 + #define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ 35 35 + 36 36 + 37 37 + /* External I/O Access Control Registers */ 38 38 + #define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ 39 39 + #define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ 40 40 + #define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ 41 41 + #define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ 42 42 + #define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ 43 43 + #define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ 44 44 + 45 45 + /* ROM/SRAM/Flash Control Register */ 46 46 + #define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ 47 47 + #define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ 48 48 + #define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ 49 49 + #define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ 50 50 + #define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ 51 51 + #define PMC_NORMAL (0 << 0) 52 52 + #define PMC_4WORD (1 << 0) 53 53 + #define PMC_8WORD (2 << 0) 54 54 + #define PMC_16WORD (3 << 0) 55 55 + 56 56 + /* External I/O and ROM/SRAM/Flash General Register */ 57 57 + #define ERGCON_TMULT (3 << 28) /* Time Multiplier */ 58 58 + #define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ 59 59 + #define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ 60 60 + #define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ 61 61 + #define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ 62 62 + #define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ 63 63 + 64 64 + /* SDRAM Control Register */ 65 65 + #define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ 66 66 + #define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ 67 67 + #define SDCON_DBCAB (3 << 8) /* Column Address Bits */ 68 68 + #define SDCON_DBBNUM (1 << 3) /* Number of Banks */ 69 69 + #define SDCON_DBDBW (3 << 1) /* Data Bus Width */ 70 70 + 71 71 + /* SDRAM General Control Register */ 72 72 + #define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ 73 73 + #define SDGCON_SDCAS (3 << 0) /* CAS latency */ 74 74 + 75 75 + /* SDRAM Buffer Control Register */ 76 76 + #define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ 77 77 + #define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ 78 78 + #define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ 79 79 + #define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ 80 80 + #define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ 81 81 + #define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ 82 82 + #define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ 83 83 + #define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ 84 84 + 85 85 + /* SDRAM Refresh Timer Register */ 86 86 + #define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ 87 87 + 88 88 + 89 89 + #endif

+97

include/asm-arm/arch-ks8695/regs-misc.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-misc.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * KS8695 - Miscellaneous Registers 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef KS8695_MISC_H 14 14 + #define KS8695_MISC_H 15 15 + 16 16 + #define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) 17 17 + #define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) 18 18 + #define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) 19 19 + 20 20 + 21 21 + /* 22 22 + * Miscellaneous registers 23 23 + */ 24 24 + #define KS8695_DID (0x00) /* Device ID */ 25 25 + #define KS8695_RID (0x04) /* Revision ID */ 26 26 + #define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ 27 27 + #define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ 28 28 + #define KS8695_WPPM (0x10) /* WAN PHY Power Management */ 29 29 + #define KS8695_PPS (0x1c) /* PHY PowerSave */ 30 30 + 31 31 + /* Device ID Register */ 32 32 + #define DID_ID (0xffff << 0) /* Device ID */ 33 33 + 34 34 + /* Revision ID Register */ 35 35 + #define RID_SUBID (0xf << 4) /* Sub-Device ID */ 36 36 + #define RID_REVISION (0xf << 0) /* Revision ID */ 37 37 + 38 38 + /* HPNA Miscellaneous Control Register */ 39 39 + #define HMC_HSS (1 << 1) /* Speed */ 40 40 + #define HMC_HDS (1 << 0) /* Duplex */ 41 41 + 42 42 + /* WAN Miscellaneous Control Register */ 43 43 + #define WMC_WANC (1 << 30) /* Auto-negotiation complete */ 44 44 + #define WMC_WANR (1 << 29) /* Auto-negotiation restart */ 45 45 + #define WMC_WANAP (1 << 28) /* Advertise Pause */ 46 46 + #define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ 47 47 + #define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ 48 48 + #define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ 49 49 + #define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ 50 50 + #define WMC_WLS (1 << 23) /* Link status */ 51 51 + #define WMC_WDS (1 << 22) /* Duplex status */ 52 52 + #define WMC_WSS (1 << 21) /* Speed status */ 53 53 + #define WMC_WLPP (1 << 20) /* Link Partner Pause */ 54 54 + #define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ 55 55 + #define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ 56 56 + #define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ 57 57 + #define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ 58 58 + #define WMC_WAND (1 << 15) /* Auto-negotiation disable */ 59 59 + #define WMC_WANF100 (1 << 14) /* Force 100 */ 60 60 + #define WMC_WANFF (1 << 13) /* Force FDX */ 61 61 + #define WMC_WLED1S (7 << 4) /* LED1 Select */ 62 62 + #define WLED1S_SPEED (0 << 4) 63 63 + #define WLED1S_LINK (1 << 4) 64 64 + #define WLED1S_DUPLEX (2 << 4) 65 65 + #define WLED1S_COLLISION (3 << 4) 66 66 + #define WLED1S_ACTIVITY (4 << 4) 67 67 + #define WLED1S_FDX_COLLISION (5 << 4) 68 68 + #define WLED1S_LINK_ACTIVITY (6 << 4) 69 69 + #define WMC_WLED0S (7 << 0) /* LED0 Select */ 70 70 + #define WLED0S_SPEED (0 << 0) 71 71 + #define WLED0S_LINK (1 << 0) 72 72 + #define WLED0S_DUPLEX (2 << 0) 73 73 + #define WLED0S_COLLISION (3 << 0) 74 74 + #define WLED0S_ACTIVITY (4 << 0) 75 75 + #define WLED0S_FDX_COLLISION (5 << 0) 76 76 + #define WLED0S_LINK_ACTIVITY (6 << 0) 77 77 + 78 78 + /* WAN PHY Power Management Register */ 79 79 + #define WPPM_WLPBK (1 << 14) /* Local Loopback */ 80 80 + #define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ 81 81 + #define WPPM_WPI (1 << 12) /* PHY isolate */ 82 82 + #define WPPM_WFL (1 << 10) /* Force link */ 83 83 + #define WPPM_MDIXS (1 << 9) /* MDIX Status */ 84 84 + #define WPPM_FEF (1 << 8) /* Far End Fault */ 85 85 + #define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ 86 86 + #define WPPM_TXDIS (1 << 6) /* Disable transmitter */ 87 87 + #define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ 88 88 + #define WPPM_PD (1 << 4) /* Power Down */ 89 89 + #define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ 90 90 + #define WPPM_FMDX (1 << 2) /* Force MDIX */ 91 91 + #define WPPM_LPBK (1 << 1) /* MAX Loopback */ 92 92 + 93 93 + /* PHY Power Save Register */ 94 94 + #define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ 95 95 + 96 96 + 97 97 + #endif

+53

include/asm-arm/arch-ks8695/regs-pci.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-pci.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - PCI bridge registers and bit definitions. 8 8 + * 9 9 + * This file is licensed under the terms of the GNU General Public 10 10 + * License version 2. This program is licensed "as is" without any 11 11 + * warranty of any kind, whether express or implied. 12 12 + */ 13 13 + 14 14 + #define KS8695_PCI_OFFSET (0xF0000 + 0x2000) 15 15 + #define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) 16 16 + #define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) 17 17 + 18 18 + 19 19 + #define KS8695_CRCFID (0x000) /* Configuration: Identification */ 20 20 + #define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ 21 21 + #define KS8695_CRCFRV (0x008) /* Configuration: Revision */ 22 22 + #define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ 23 23 + #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ 24 24 + #define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ 25 25 + #define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ 26 26 + #define KS8695_PBCA (0x100) /* Bridge Configuration Address */ 27 27 + #define KS8695_PBCD (0x104) /* Bridge Configuration Data */ 28 28 + #define KS8695_PBM (0x200) /* Bridge Mode */ 29 29 + #define KS8695_PBCS (0x204) /* Bridge Control and Status */ 30 30 + #define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ 31 31 + #define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ 32 32 + #define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ 33 33 + #define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ 34 34 + #define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ 35 35 + #define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ 36 36 + #define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ 37 37 + #define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ 38 38 + 39 39 + 40 40 + /* Configuration: Identification */ 41 41 + 42 42 + /* Configuration: Command and Status */ 43 43 + 44 44 + /* Configuration: Revision */ 45 45 + 46 46 + 47 47 + 48 48 + #define CFRV_GUEST (1 << 23) 49 49 + 50 50 + #define PBCA_TYPE1 (1) 51 51 + #define PBCA_ENABLE (1 << 31) 52 52 + 53 53 +

+66

include/asm-arm/arch-ks8695/regs-switch.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-switch.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * KS8695 - Switch Registers and bit definitions. 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef KS8695_SWITCH_H 14 14 + #define KS8695_SWITCH_H 15 15 + 16 16 + #define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) 17 17 + #define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) 18 18 + #define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) 19 19 + 20 20 + 21 21 + /* 22 22 + * Switch registers 23 23 + */ 24 24 + #define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ 25 25 + #define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ 26 26 + #define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ 27 27 + 28 28 + #define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ 29 29 + 30 30 + #define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ 31 31 + #define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ 32 32 + #define KS8695_SEIAC (0x50) /* Indirect Access Control */ 33 33 + #define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ 34 34 + #define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ 35 35 + #define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ 36 36 + #define KS8695_SEAFC (0x60) /* Advance Feature Control */ 37 37 + #define KS8695_SEDSCPH (0x64) /* TOS Priority High */ 38 38 + #define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ 39 39 + #define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ 40 40 + #define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ 41 41 + #define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ 42 42 + #define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ 43 43 + 44 44 + 45 45 + /* Switch Engine Control 0 */ 46 46 + #define SEC0_LLED1S (7 << 25) /* LED1 Select */ 47 47 + #define LLED1S_SPEED (0 << 25) 48 48 + #define LLED1S_LINK (1 << 25) 49 49 + #define LLED1S_DUPLEX (2 << 25) 50 50 + #define LLED1S_COLLISION (3 << 25) 51 51 + #define LLED1S_ACTIVITY (4 << 25) 52 52 + #define LLED1S_FDX_COLLISION (5 << 25) 53 53 + #define LLED1S_LINK_ACTIVITY (6 << 25) 54 54 + #define SEC0_LLED0S (7 << 22) /* LED0 Select */ 55 55 + #define LLED0S_SPEED (0 << 22) 56 56 + #define LLED0S_LINK (1 << 22) 57 57 + #define LLED0S_DUPLEX (2 << 22) 58 58 + #define LLED0S_COLLISION (3 << 22) 59 59 + #define LLED0S_ACTIVITY (4 << 22) 60 60 + #define LLED0S_FDX_COLLISION (5 << 22) 61 61 + #define LLED0S_LINK_ACTIVITY (6 << 22) 62 62 + #define SEC0_ENABLE (1 << 0) /* Enable Switch */ 63 63 + 64 64 + 65 65 + 66 66 + #endif

+34

include/asm-arm/arch-ks8695/regs-sys.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-sys.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - System control registers and bit definitions 8 8 + * 9 9 + * This file is licensed under the terms of the GNU General Public 10 10 + * License version 2. This program is licensed "as is" without any 11 11 + * warranty of any kind, whether express or implied. 12 12 + */ 13 13 + 14 14 + #ifndef KS8695_SYS_H 15 15 + #define KS8695_SYS_H 16 16 + 17 17 + #define KS8695_SYS_OFFSET (0xF0000 + 0x0000) 18 18 + #define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) 19 19 + #define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) 20 20 + 21 21 + 22 22 + #define KS8695_SYSCFG (0x00) /* System Configuration Register */ 23 23 + #define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ 24 24 + 25 25 + 26 26 + /* System Configuration Register */ 27 27 + #define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ 28 28 + 29 29 + /* System Clock and Bus Control Register */ 30 30 + #define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ 31 31 + #define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ 32 32 + 33 33 + 34 34 + #endif

+40

include/asm-arm/arch-ks8695/regs-timer.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-timer.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - Timer registers and bit definitions. 8 8 + * 9 9 + * This file is licensed under the terms of the GNU General Public 10 10 + * License version 2. This program is licensed "as is" without any 11 11 + * warranty of any kind, whether express or implied. 12 12 + */ 13 13 + 14 14 + #ifndef KS8695_TIMER_H 15 15 + #define KS8695_TIMER_H 16 16 + 17 17 + #define KS8695_TMR_OFFSET (0xF0000 + 0xE400) 18 18 + #define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) 19 19 + #define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) 20 20 + 21 21 + 22 22 + /* 23 23 + * Timer registers 24 24 + */ 25 25 + #define KS8695_TMCON (0x00) /* Timer Control Register */ 26 26 + #define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ 27 27 + #define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ 28 28 + #define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ 29 29 + #define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ 30 30 + 31 31 + 32 32 + /* Timer Control Register */ 33 33 + #define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ 34 34 + #define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ 35 35 + 36 36 + /* Timer0 Timeout Counter Register */ 37 37 + #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ 38 38 + 39 39 + 40 40 + #endif

+92

include/asm-arm/arch-ks8695/regs-uart.h

reviewed

··· 1 1 + /* 2 2 + * linux/include/asm-arm/arch-ks8695/regs-uart.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - UART register and bit definitions. 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License version 2 as 11 11 + * published by the Free Software Foundation. 12 12 + */ 13 13 + 14 14 + #ifndef KS8695_UART_H 15 15 + #define KS8695_UART_H 16 16 + 17 17 + #define KS8695_UART_OFFSET (0xF0000 + 0xE000) 18 18 + #define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) 19 19 + #define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) 20 20 + 21 21 + 22 22 + /* 23 23 + * UART registers 24 24 + */ 25 25 + #define KS8695_URRB (0x00) /* Receive Buffer Register */ 26 26 + #define KS8695_URTH (0x04) /* Transmit Holding Register */ 27 27 + #define KS8695_URFC (0x08) /* FIFO Control Register */ 28 28 + #define KS8695_URLC (0x0C) /* Line Control Register */ 29 29 + #define KS8695_URMC (0x10) /* Modem Control Register */ 30 30 + #define KS8695_URLS (0x14) /* Line Status Register */ 31 31 + #define KS8695_URMS (0x18) /* Modem Status Register */ 32 32 + #define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ 33 33 + #define KS8695_USR (0x20) /* Status Register */ 34 34 + 35 35 + 36 36 + /* FIFO Control Register */ 37 37 + #define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ 38 38 + #define URFC_URFRT_1 (0 << 6) 39 39 + #define URFC_URFRT_4 (1 << 6) 40 40 + #define URFC_URFRT_8 (2 << 6) 41 41 + #define URFC_URFRT_14 (3 << 6) 42 42 + #define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ 43 43 + #define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ 44 44 + #define URFC_URFE (1 << 0) /* FIFO Enable */ 45 45 + 46 46 + /* Line Control Register */ 47 47 + #define URLC_URSBC (1 << 6) /* Set Break Condition */ 48 48 + #define URLC_PARITY (7 << 3) /* Parity */ 49 49 + #define URPE_NONE (0 << 3) 50 50 + #define URPE_ODD (1 << 3) 51 51 + #define URPE_EVEN (3 << 3) 52 52 + #define URPE_MARK (5 << 3) 53 53 + #define URPE_SPACE (7 << 3) 54 54 + #define URLC_URSB (1 << 2) /* Stop Bits */ 55 55 + #define URLC_URCL (3 << 0) /* Character Length */ 56 56 + #define URCL_5 (0 << 0) 57 57 + #define URCL_6 (1 << 0) 58 58 + #define URCL_7 (2 << 0) 59 59 + #define URCL_8 (3 << 0) 60 60 + 61 61 + /* Modem Control Register */ 62 62 + #define URMC_URLB (1 << 4) /* Loop-back mode */ 63 63 + #define URMC_UROUT2 (1 << 3) /* OUT2 signal */ 64 64 + #define URMC_UROUT1 (1 << 2) /* OUT1 signal */ 65 65 + #define URMC_URRTS (1 << 1) /* Request to Send */ 66 66 + #define URMC_URDTR (1 << 0) /* Data Terminal Ready */ 67 67 + 68 68 + /* Line Status Register */ 69 69 + #define URLS_URRFE (1 << 7) /* Receive FIFO Error */ 70 70 + #define URLS_URTE (1 << 6) /* Transmit Empty */ 71 71 + #define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ 72 72 + #define URLS_URBI (1 << 4) /* Break Interrupt */ 73 73 + #define URLS_URFE (1 << 3) /* Framing Error */ 74 74 + #define URLS_URPE (1 << 2) /* Parity Error */ 75 75 + #define URLS_URROE (1 << 1) /* Receive Overrun Error */ 76 76 + #define URLS_URDR (1 << 0) /* Receive Data Ready */ 77 77 + 78 78 + /* Modem Status Register */ 79 79 + #define URMS_URDCD (1 << 7) /* Data Carrier Detect */ 80 80 + #define URMS_URRI (1 << 6) /* Ring Indicator */ 81 81 + #define URMS_URDSR (1 << 5) /* Data Set Ready */ 82 82 + #define URMS_URCTS (1 << 4) /* Clear to Send */ 83 83 + #define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ 84 84 + #define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ 85 85 + #define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ 86 86 + #define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ 87 87 + 88 88 + /* Status Register */ 89 89 + #define USR_UTI (1 << 0) /* Timeout Indication */ 90 90 + 91 91 + 92 92 + #endif

+65

include/asm-arm/arch-ks8695/regs-wan.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/regs-wan.h 3 3 + * 4 4 + * Copyright (C) 2006 Andrew Victor 5 5 + * 6 6 + * KS8695 - WAN Registers and bit definitions. 7 7 + * 8 8 + * This file is licensed under the terms of the GNU General Public 9 9 + * License version 2. This program is licensed "as is" without any 10 10 + * warranty of any kind, whether express or implied. 11 11 + */ 12 12 + 13 13 + #ifndef KS8695_WAN_H 14 14 + #define KS8695_WAN_H 15 15 + 16 16 + #define KS8695_WAN_OFFSET (0xF0000 + 0x6000) 17 17 + #define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) 18 18 + #define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) 19 19 + 20 20 + 21 21 + /* 22 22 + * WAN registers 23 23 + */ 24 24 + #define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ 25 25 + #define KS8695_WMDRXC (0x04) /* DMA Receive Control */ 26 26 + #define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ 27 27 + #define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ 28 28 + #define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ 29 29 + #define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ 30 30 + #define KS8695_WMAL (0x18) /* MAC Station Address Low */ 31 31 + #define KS8695_WMAH (0x1c) /* MAC Station Address High */ 32 32 + #define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ 33 33 + #define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ 34 34 + 35 35 + 36 36 + /* DMA Transmit Control Register */ 37 37 + #define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ 38 38 + #define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ 39 39 + #define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ 40 40 + #define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ 41 41 + #define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ 42 42 + #define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ 43 43 + #define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ 44 44 + #define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ 45 45 + #define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ 46 46 + #define WMDTXC_WMTE (1 << 0) /* TX Enable */ 47 47 + 48 48 + /* DMA Receive Control Register */ 49 49 + #define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ 50 50 + #define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ 51 51 + #define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ 52 52 + #define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ 53 53 + #define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ 54 54 + #define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ 55 55 + #define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ 56 56 + #define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ 57 57 + #define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ 58 58 + #define WMDRXC_WMRA (1 << 2) /* Receive All */ 59 59 + #define WMDRXC_WMRE (1 << 0) /* RX Enable */ 60 60 + 61 61 + /* Additional Station Address High */ 62 62 + #define WMAAH_E (1 << 31) /* Address Enabled */ 63 63 + 64 64 + 65 65 + #endif

+48

include/asm-arm/arch-ks8695/system.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-s3c2410/system.h 3 3 + * 4 4 + * Copyright (C) 2006 Simtec Electronics 5 5 + * Ben Dooks <ben@simtec.co.uk> 6 6 + * 7 7 + * KS8695 - System function defines and includes 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License version 2 as 11 11 + * published by the Free Software Foundation. 12 12 + */ 13 13 + 14 14 + #ifndef __ASM_ARCH_SYSTEM_H 15 15 + #define __ASM_ARCH_SYSTEM_H 16 16 + 17 17 + #include <asm/io.h> 18 18 + #include <asm/arch/regs-timer.h> 19 19 + 20 20 + static void arch_idle(void) 21 21 + { 22 22 + /* 23 23 + * This should do all the clock switching 24 24 + * and wait for interrupt tricks, 25 25 + */ 26 26 + cpu_do_idle(); 27 27 + 28 28 + } 29 29 + 30 30 + static void arch_reset(char mode) 31 31 + { 32 32 + unsigned int reg; 33 33 + 34 34 + if (mode == 's') 35 35 + cpu_reset(0); 36 36 + 37 37 + /* disable timer0 */ 38 38 + reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); 39 39 + __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); 40 40 + 41 41 + /* enable watchdog mode */ 42 42 + __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); 43 43 + 44 44 + /* re-enable timer0 */ 45 45 + __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); 46 46 + } 47 47 + 48 48 + #endif

+20

include/asm-arm/arch-ks8695/timex.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/timex.h 3 3 + * 4 4 + * Copyright (C) 2006 Simtec Electronics 5 5 + * Ben Dooks <ben@simtec.co.uk> 6 6 + * 7 7 + * KS8695 - Time Parameters 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License version 2 as 11 11 + * published by the Free Software Foundation. 12 12 + */ 13 13 + 14 14 + #ifndef __ASM_ARCH_TIMEX_H 15 15 + #define __ASM_ARCH_TIMEX_H 16 16 + 17 17 + /* timers are derived from MCLK, which is 25MHz */ 18 18 + #define CLOCK_TICK_RATE 25000000 19 19 + 20 20 + #endif

+37

include/asm-arm/arch-ks8695/uncompress.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/uncompress.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 5 + * Copyright (C) 2006 Simtec Electronics 6 6 + * 7 7 + * KS8695 - Kernel uncompressor 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License version 2 as 11 11 + * published by the Free Software Foundation. 12 12 + */ 13 13 + 14 14 + #ifndef __ASM_ARCH_UNCOMPRESS_H 15 15 + #define __ASM_ARCH_UNCOMPRESS_H 16 16 + 17 17 + #include <asm/io.h> 18 18 + #include <asm/arch/regs-uart.h> 19 19 + 20 20 + static void putc(char c) 21 21 + { 22 22 + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) 23 23 + barrier(); 24 24 + 25 25 + __raw_writel(c, KS8695_UART_PA + KS8695_URTH); 26 26 + } 27 27 + 28 28 + static inline void flush(void) 29 29 + { 30 30 + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) 31 31 + barrier(); 32 32 + } 33 33 + 34 34 + #define arch_decomp_setup() 35 35 + #define arch_decomp_wdog() 36 36 + 37 37 + #endif

+19

include/asm-arm/arch-ks8695/vmalloc.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-ks8695/vmalloc.h 3 3 + * 4 4 + * Copyright (C) 2006 Ben Dooks 5 5 + * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk> 6 6 + * 7 7 + * KS8695 vmalloc definition 8 8 + * 9 9 + * This program is free software; you can redistribute it and/or modify 10 10 + * it under the terms of the GNU General Public License version 2 as 11 11 + * published by the Free Software Foundation. 12 12 + */ 13 13 + 14 14 + #ifndef __ASM_ARCH_VMALLOC_H 15 15 + #define __ASM_ARCH_VMALLOC_H 16 16 + 17 17 + #define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK) 18 18 + 19 19 + #endif

+30 -1

include/asm-arm/arch-omap/mux.h

reviewed

··· 421 421 /* 24xx clock */ 422 422 W14_24XX_SYS_CLKOUT, 423 423 424 424 - /* 24xx GPMC wait pin monitoring */ 424 424 + /* 24xx GPMC chipselects, wait pin monitoring */ 425 425 + E2_GPMC_NCS2, 426 426 + L2_GPMC_NCS7, 425 427 L3_GPMC_WAIT0, 426 428 N7_GPMC_WAIT1, 427 429 M1_GPMC_WAIT2, ··· 437 435 438 436 /* 24xx GPIO */ 439 437 M21_242X_GPIO11, 438 438 + P21_242X_GPIO12, 440 439 AA10_242X_GPIO13, 441 440 AA6_242X_GPIO14, 442 441 AA4_242X_GPIO15, ··· 447 444 Y20_24XX_GPIO60, 448 445 W4__24XX_GPIO74, 449 446 M15_24XX_GPIO92, 447 447 + J15_24XX_GPIO99, 450 448 V14_24XX_GPIO117, 449 449 + P14_24XX_GPIO125, 451 450 452 451 /* 242x DBG GPIO */ 453 452 V4_242X_GPIO49, ··· 490 485 E18_24XX_MMC_DAT_DIR3, 491 486 G18_24XX_MMC_CMD_DIR, 492 487 H15_24XX_MMC_CLKI, 488 488 + 489 489 + /* Full speed USB */ 490 490 + J20_24XX_USB0_PUEN, 491 491 + J19_24XX_USB0_VP, 492 492 + K20_24XX_USB0_VM, 493 493 + J18_24XX_USB0_RCV, 494 494 + K19_24XX_USB0_TXEN, 495 495 + J14_24XX_USB0_SE0, 496 496 + K18_24XX_USB0_DAT, 497 497 + 498 498 + N14_24XX_USB1_SE0, 499 499 + W12_24XX_USB1_SE0, 500 500 + P15_24XX_USB1_DAT, 501 501 + R13_24XX_USB1_DAT, 502 502 + W20_24XX_USB1_TXEN, 503 503 + P13_24XX_USB1_TXEN, 504 504 + V19_24XX_USB1_RCV, 505 505 + V12_24XX_USB1_RCV, 506 506 + 507 507 + AA10_24XX_USB2_SE0, 508 508 + Y11_24XX_USB2_DAT, 509 509 + AA12_24XX_USB2_TXEN, 510 510 + AA6_24XX_USB2_RCV, 511 511 + AA4_24XX_USB2_TLLSE0, 493 512 494 513 /* Keypad GPIO*/ 495 514 T19_24XX_KBR0,

+1 -1

include/asm-arm/arch-realview/entry-macro.S

reviewed

··· 14 14 .endm 15 15 16 16 .macro get_irqnr_preamble, base, tmp 17 17 + ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) 17 18 .endm 18 19 19 20 .macro arch_ret_to_user, tmp1, tmp2 ··· 41 40 42 41 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 43 42 44 44 - ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) 45 43 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ 46 44 47 45 ldr \tmp, =1021

+8

include/asm-arm/arch-rpc/entry-macro.S

reviewed

··· 1 1 #include <asm/hardware.h> 2 2 #include <asm/hardware/entry-macro-iomd.S> 3 3 + 4 4 + .equ ioc_base_high, IOC_BASE & 0xff000000 5 5 + .equ ioc_base_low, IOC_BASE & 0x00ff0000 6 6 + 3 7 .macro get_irqnr_preamble, base, tmp 8 8 + mov \base, #ioc_base_high @ point at IOC 9 9 + .if ioc_base_low 10 10 + orr \base, \base, #ioc_base_low 11 11 + .endif 4 12 .endm 5 13 6 14 .macro arch_ret_to_user, tmp1, tmp2

+1

include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h

reviewed

··· 129 129 #define S3C2443_PCLKCON_IIC (1<<4) 130 130 #define S3C2443_PCLKCON_SDI (1<<5) 131 131 #define S3C2443_PCLKCON_ADC (1<<7) 132 132 + #define S3C2443_PCLKCON_AC97 (1<<8) 132 133 #define S3C2443_PCLKCON_IIS (1<<9) 133 134 #define S3C2443_PCLKCON_PWMT (1<<10) 134 135 #define S3C2443_PCLKCON_WDT (1<<11)

+4 -4

include/asm-arm/arch-sa1100/entry-macro.S

reviewed

··· 12 12 .endm 13 13 14 14 .macro get_irqnr_preamble, base, tmp 15 15 + mov \base, #0xfa000000 @ ICIP = 0xfa050000 16 16 + add \base, \base, #0x00050000 15 17 .endm 16 18 17 19 .macro arch_ret_to_user, tmp1, tmp2 18 20 .endm 19 21 20 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 21 21 - mov r4, #0xfa000000 @ ICIP = 0xfa050000 22 22 - add r4, r4, #0x00050000 23 23 - ldr \irqstat, [r4] @ get irqs 24 24 - ldr \irqnr, [r4, #4] @ ICMR = 0xfa050004 23 23 + ldr \irqstat, [\base] @ get irqs 24 24 + ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 25 25 ands \irqstat, \irqstat, \irqnr 26 26 mov \irqnr, #0 27 27 beq 1001f

+1 -1

include/asm-arm/arch-versatile/entry-macro.S

reviewed

··· 14 14 .endm 15 15 16 16 .macro get_irqnr_preamble, base, tmp 17 17 + ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) 17 18 .endm 18 19 19 20 .macro arch_ret_to_user, tmp1, tmp2 20 21 .endm 21 22 22 23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 23 23 - ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) 24 24 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status 25 25 mov \irqnr, #0 26 26 teq \irqstat, #0

+7 -1

include/asm-arm/ecard.h

reviewed

··· 121 121 typedef struct expansion_card ecard_t; 122 122 typedef unsigned long *loader_t; 123 123 124 124 - typedef struct { /* Card handler routines */ 124 124 + typedef struct expansion_card_ops { /* Card handler routines */ 125 125 void (*irqenable)(ecard_t *ec, int irqnr); 126 126 void (*irqdisable)(ecard_t *ec, int irqnr); 127 127 int (*irqpending)(ecard_t *ec); ··· 179 179 u64 dma_mask; 180 180 }; 181 181 182 182 + void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data); 183 183 + 182 184 struct in_chunk_dir { 183 185 unsigned int start_offset; 184 186 union { ··· 225 223 */ 226 224 extern int ecard_request_resources(struct expansion_card *ec); 227 225 extern void ecard_release_resources(struct expansion_card *ec); 226 226 + 227 227 + void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, 228 228 + unsigned long offset, unsigned long maxsize); 229 229 + #define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) 228 230 229 231 extern struct bus_type ecard_bus_type; 230 232

+11 -17

include/asm-arm/hardware/entry-macro-iomd.S

reviewed

··· 11 11 /* IOC / IOMD based hardware */ 12 12 #include <asm/hardware/iomd.h> 13 13 14 14 - .equ ioc_base_high, IOC_BASE & 0xff000000 15 15 - .equ ioc_base_low, IOC_BASE & 0x00ff0000 16 14 .macro disable_fiq 17 15 mov r12, #ioc_base_high 18 16 .if ioc_base_low ··· 20 22 .endm 21 23 22 24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 23 23 - mov r4, #ioc_base_high @ point at IOC 24 24 - .if ioc_base_low 25 25 - orr r4, r4, #ioc_base_low 26 26 - .endif 27 27 - ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first 28 28 - ldr \base, =irq_prio_h 25 25 + ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first 26 26 + ldr \tmp, =irq_prio_h 29 27 teq \irqstat, #0 30 28 #ifdef IOMD_BASE 31 31 - ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma 32 32 - addeq \base, \base, #256 @ irq_prio_h table size 29 29 + ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma 30 30 + addeq \tmp, \tmp, #256 @ irq_prio_h table size 33 31 teqeq \irqstat, #0 34 32 bne 2406f 35 33 #endif 36 36 - ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority 37 37 - addeq \base, \base, #256 @ irq_prio_d table size 34 34 + ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority 35 35 + addeq \tmp, \tmp, #256 @ irq_prio_d table size 38 36 teqeq \irqstat, #0 39 37 #ifdef IOMD_IRQREQC 40 40 - ldreqb \irqstat, [r4, #IOMD_IRQREQC] 41 41 - addeq \base, \base, #256 @ irq_prio_l table size 38 38 + ldreqb \irqstat, [\base, #IOMD_IRQREQC] 39 39 + addeq \tmp, \tmp, #256 @ irq_prio_l table size 42 40 teqeq \irqstat, #0 43 41 #endif 44 42 #ifdef IOMD_IRQREQD 45 45 - ldreqb \irqstat, [r4, #IOMD_IRQREQD] 46 46 - addeq \base, \base, #256 @ irq_prio_lc table size 43 43 + ldreqb \irqstat, [\base, #IOMD_IRQREQD] 44 44 + addeq \tmp, \tmp, #256 @ irq_prio_lc table size 47 45 teqeq \irqstat, #0 48 46 #endif 49 49 - 2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number 47 47 + 2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number 50 48 .endm 51 49 52 50 /*

+4

include/asm-arm/sizes.h

reviewed

··· 24 24 #define __sizes_h 1 25 25 26 26 /* handy sizes */ 27 27 + #define SZ_16 0x00000010 28 28 + #define SZ_256 0x00000100 29 29 + #define SZ_512 0x00000200 30 30 + 27 31 #define SZ_1K 0x00000400 28 32 #define SZ_4K 0x00001000 29 33 #define SZ_8K 0x00002000

+1

include/asm-avr32/arch-at32ap/cpu.h

reviewed

··· 29 29 #define cpu_is_at91sam9260() (0) 30 30 #define cpu_is_at91sam9261() (0) 31 31 #define cpu_is_at91sam9263() (0) 32 32 + #define cpu_is_at91sam9rl() (0) 32 33 33 34 #endif /* __ASM_ARCH_CPU_H */

+4

include/linux/serial_core.h

reviewed

··· 139 139 /* Blackfin bf5xx */ 140 140 #define PORT_BFIN 75 141 141 142 142 + /* Micrel KS8695 */ 143 143 + #define PORT_KS8695 76 144 144 + 145 145 + 142 146 #ifdef __KERNEL__ 143 147 144 148 #include <linux/compiler.h>