Merge tag 'drm-fixes-2023-07-21' of git://anongit.freedesktop.org/drm/drm

+9

drivers/accel/habanalabs/common/habanalabs.h

··· 3980 3980 { 3981 3981 } 3982 3982 3983 + static inline int hl_debugfs_device_init(struct hl_device *hdev) 3984 + { 3985 + return 0; 3986 + } 3987 + 3988 + static inline void hl_debugfs_device_fini(struct hl_device *hdev) 3989 + { 3990 + } 3991 + 3983 3992 static inline void hl_debugfs_add_device(struct hl_device *hdev) 3984 3993 { 3985 3994 }

+25 -14

drivers/accel/qaic/qaic_control.c

··· 14 14 #include <linux/mm.h> 15 15 #include <linux/moduleparam.h> 16 16 #include <linux/mutex.h> 17 + #include <linux/overflow.h> 17 18 #include <linux/pci.h> 18 19 #include <linux/scatterlist.h> 19 20 #include <linux/types.h> ··· 367 366 if (in_trans->hdr.len % 8 != 0) 368 367 return -EINVAL; 369 368 370 - if (msg_hdr_len + in_trans->hdr.len > QAIC_MANAGE_EXT_MSG_LENGTH) 369 + if (size_add(msg_hdr_len, in_trans->hdr.len) > QAIC_MANAGE_EXT_MSG_LENGTH) 371 370 return -ENOSPC; 372 371 373 372 trans_wrapper = add_wrapper(wrappers, ··· 419 418 } 420 419 421 420 ret = get_user_pages_fast(xfer_start_addr, nr_pages, 0, page_list); 422 - if (ret < 0 || ret != nr_pages) { 423 - ret = -EFAULT; 421 + if (ret < 0) 424 422 goto free_page_list; 423 + if (ret != nr_pages) { 424 + nr_pages = ret; 425 + ret = -EFAULT; 426 + goto put_pages; 425 427 } 426 428 427 429 sgt = kmalloc(sizeof(*sgt), GFP_KERNEL); ··· 561 557 msg = &wrapper->msg; 562 558 msg_hdr_len = le32_to_cpu(msg->hdr.len); 563 559 564 - if (msg_hdr_len > (UINT_MAX - QAIC_MANAGE_EXT_MSG_LENGTH)) 565 - return -EINVAL; 566 - 567 560 /* There should be enough space to hold at least one ASP entry. */ 568 - if (msg_hdr_len + sizeof(*out_trans) + sizeof(struct wire_addr_size_pair) > 561 + if (size_add(msg_hdr_len, sizeof(*out_trans) + sizeof(struct wire_addr_size_pair)) > 569 562 QAIC_MANAGE_EXT_MSG_LENGTH) 570 563 return -ENOMEM; 571 564 ··· 635 634 msg = &wrapper->msg; 636 635 msg_hdr_len = le32_to_cpu(msg->hdr.len); 637 636 638 - if (msg_hdr_len + sizeof(*out_trans) > QAIC_MANAGE_MAX_MSG_LENGTH) 637 + if (size_add(msg_hdr_len, sizeof(*out_trans)) > QAIC_MANAGE_MAX_MSG_LENGTH) 639 638 return -ENOSPC; 640 639 641 640 if (!in_trans->queue_size) ··· 719 718 msg = &wrapper->msg; 720 719 msg_hdr_len = le32_to_cpu(msg->hdr.len); 721 720 722 - if (msg_hdr_len + in_trans->hdr.len > QAIC_MANAGE_MAX_MSG_LENGTH) 721 + if (size_add(msg_hdr_len, in_trans->hdr.len) > QAIC_MANAGE_MAX_MSG_LENGTH) 723 722 return -ENOSPC; 724 723 725 724 trans_wrapper = add_wrapper(wrappers, sizeof(*trans_wrapper)); ··· 749 748 int ret; 750 749 int i; 751 750 752 - if (!user_msg->count) { 751 + if (!user_msg->count || 752 + user_msg->len < sizeof(*trans_hdr)) { 753 753 ret = -EINVAL; 754 754 goto out; 755 755 } ··· 767 765 } 768 766 769 767 for (i = 0; i < user_msg->count; ++i) { 770 - if (user_len >= user_msg->len) { 768 + if (user_len > user_msg->len - sizeof(*trans_hdr)) { 771 769 ret = -EINVAL; 772 770 break; 773 771 } 774 772 trans_hdr = (struct qaic_manage_trans_hdr *)(user_msg->data + user_len); 775 - if (user_len + trans_hdr->len > user_msg->len) { 773 + if (trans_hdr->len < sizeof(trans_hdr) || 774 + size_add(user_len, trans_hdr->len) > user_msg->len) { 776 775 ret = -EINVAL; 777 776 break; 778 777 } ··· 956 953 int ret; 957 954 int i; 958 955 959 - if (msg_hdr_len > QAIC_MANAGE_MAX_MSG_LENGTH) 956 + if (msg_hdr_len < sizeof(*trans_hdr) || 957 + msg_hdr_len > QAIC_MANAGE_MAX_MSG_LENGTH) 960 958 return -EINVAL; 961 959 962 960 user_msg->len = 0; 963 961 user_msg->count = le32_to_cpu(msg->hdr.count); 964 962 965 963 for (i = 0; i < user_msg->count; ++i) { 964 + u32 hdr_len; 965 + 966 + if (msg_len > msg_hdr_len - sizeof(*trans_hdr)) 967 + return -EINVAL; 968 + 966 969 trans_hdr = (struct wire_trans_hdr *)(msg->data + msg_len); 967 - if (msg_len + le32_to_cpu(trans_hdr->len) > msg_hdr_len) 970 + hdr_len = le32_to_cpu(trans_hdr->len); 971 + if (hdr_len < sizeof(*trans_hdr) || 972 + size_add(msg_len, hdr_len) > msg_hdr_len) 968 973 return -EINVAL; 969 974 970 975 switch (le32_to_cpu(trans_hdr->type)) {

+9 -4

drivers/dma-buf/dma-resv.c

··· 571 571 dma_resv_for_each_fence_unlocked(&cursor, fence) { 572 572 573 573 if (dma_resv_iter_is_restarted(&cursor)) { 574 + struct dma_fence **new_fences; 574 575 unsigned int count; 575 576 576 577 while (*num_fences) ··· 580 579 count = cursor.num_fences + 1; 581 580 582 581 /* Eventually re-allocate the array */ 583 - *fences = krealloc_array(*fences, count, 584 - sizeof(void *), 585 - GFP_KERNEL); 586 - if (count && !*fences) { 582 + new_fences = krealloc_array(*fences, count, 583 + sizeof(void *), 584 + GFP_KERNEL); 585 + if (count && !new_fences) { 586 + kfree(*fences); 587 + *fences = NULL; 588 + *num_fences = 0; 587 589 dma_resv_iter_end(&cursor); 588 590 return -ENOMEM; 589 591 } 592 + *fences = new_fences; 590 593 } 591 594 592 595 (*fences)[(*num_fences)++] = dma_fence_get(fence);

+2 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

··· 1709 1709 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ? 1710 1710 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0; 1711 1711 } 1712 - xcp_id = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id; 1712 + xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? 1713 + 0 : fpriv->xcp_id; 1713 1714 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 1714 1715 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT; 1715 1716 alloc_flags = 0;

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

··· 1229 1229 pasid = 0; 1230 1230 } 1231 1231 1232 - r = amdgpu_vm_init(adev, &fpriv->vm); 1232 + r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1233 1233 if (r) 1234 1234 goto error_pasid; 1235 1235 1236 - r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1236 + r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1237 1237 if (r) 1238 - goto error_vm; 1238 + goto error_pasid; 1239 1239 1240 1240 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1241 1241 if (r)

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

··· 1382 1382 goto error_pasid; 1383 1383 } 1384 1384 1385 - r = amdgpu_vm_init(adev, vm); 1385 + r = amdgpu_vm_init(adev, vm, -1); 1386 1386 if (r) { 1387 1387 DRM_ERROR("failed to initialize vm\n"); 1388 1388 goto error_pasid;

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

··· 55 55 DRM_WARN("%s: vblank timer overrun\n", __func__); 56 56 57 57 ret = drm_crtc_handle_vblank(crtc); 58 + /* Don't queue timer again when vblank is disabled. */ 58 59 if (!ret) 59 - DRM_ERROR("amdgpu_vkms failure on handling vblank"); 60 + return HRTIMER_NORESTART; 60 61 61 62 return HRTIMER_RESTART; 62 63 } ··· 82 81 { 83 82 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 84 83 85 - hrtimer_cancel(&amdgpu_crtc->vblank_timer); 84 + hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer); 86 85 } 87 86 88 87 static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

··· 2121 2121 * 2122 2122 * @adev: amdgpu_device pointer 2123 2123 * @vm: requested vm 2124 + * @xcp_id: GPU partition selection id 2124 2125 * 2125 2126 * Init @vm fields. 2126 2127 * 2127 2128 * Returns: 2128 2129 * 0 for success, error for failure. 2129 2130 */ 2130 - int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) 2131 + int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) 2131 2132 { 2132 2133 struct amdgpu_bo *root_bo; 2133 2134 struct amdgpu_bo_vm *root; ··· 2178 2177 vm->evicting = false; 2179 2178 2180 2179 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level, 2181 - false, &root); 2180 + false, &root, xcp_id); 2182 2181 if (r) 2183 2182 goto error_free_delayed; 2184 2183 root_bo = &root->bo;

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

··· 392 392 u32 pasid); 393 393 394 394 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 395 - int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 395 + int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 396 396 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 397 397 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 398 398 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); ··· 475 475 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 476 476 struct amdgpu_bo_vm *vmbo, bool immediate); 477 477 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 478 - int level, bool immediate, struct amdgpu_bo_vm **vmbo); 478 + int level, bool immediate, struct amdgpu_bo_vm **vmbo, 479 + int32_t xcp_id); 479 480 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 480 481 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev, 481 482 struct amdgpu_vm *vm);

+7 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c

··· 498 498 * @level: the page table level 499 499 * @immediate: use a immediate update 500 500 * @vmbo: pointer to the buffer object pointer 501 + * @xcp_id: GPU partition id 501 502 */ 502 503 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 503 - int level, bool immediate, struct amdgpu_bo_vm **vmbo) 504 + int level, bool immediate, struct amdgpu_bo_vm **vmbo, 505 + int32_t xcp_id) 504 506 { 505 - struct amdgpu_fpriv *fpriv = container_of(vm, struct amdgpu_fpriv, vm); 506 507 struct amdgpu_bo_param bp; 507 508 struct amdgpu_bo *bo; 508 509 struct dma_resv *resv; ··· 536 535 537 536 bp.type = ttm_bo_type_kernel; 538 537 bp.no_wait_gpu = immediate; 539 - bp.xcp_id_plus1 = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id + 1; 538 + bp.xcp_id_plus1 = xcp_id + 1; 540 539 541 540 if (vm->root.bo) 542 541 bp.resv = vm->root.bo->tbo.base.resv; ··· 562 561 bp.type = ttm_bo_type_kernel; 563 562 bp.resv = bo->tbo.base.resv; 564 563 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 565 - bp.xcp_id_plus1 = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id + 1; 564 + bp.xcp_id_plus1 = xcp_id + 1; 566 565 567 566 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow); 568 567 ··· 607 606 return 0; 608 607 609 608 amdgpu_vm_eviction_unlock(vm); 610 - r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt); 609 + r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt, 610 + vm->root.bo->xcp_id); 611 611 amdgpu_vm_eviction_lock(vm); 612 612 if (r) 613 613 return r;

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

··· 363 363 if (!adev->xcp_mgr) 364 364 return 0; 365 365 366 - fpriv->xcp_id = ~0; 366 + fpriv->xcp_id = AMDGPU_XCP_NO_PARTITION; 367 367 for (i = 0; i < MAX_XCP; ++i) { 368 368 if (!adev->xcp_mgr->xcp[i].ddev) 369 369 break; ··· 381 381 } 382 382 } 383 383 384 - fpriv->vm.mem_id = fpriv->xcp_id == ~0 ? -1 : 384 + fpriv->vm.mem_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? -1 : 385 385 adev->xcp_mgr->xcp[fpriv->xcp_id].mem_id; 386 386 return 0; 387 387 }

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

··· 37 37 #define AMDGPU_XCP_FL_NONE 0 38 38 #define AMDGPU_XCP_FL_LOCKED (1 << 0) 39 39 40 + #define AMDGPU_XCP_NO_PARTITION (~0) 41 + 40 42 struct amdgpu_fpriv; 41 43 42 44 enum AMDGPU_XCP_IP_BLOCK {

+2 -2

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c

··· 68 68 enum AMDGPU_XCP_IP_BLOCK ip_blk; 69 69 uint32_t inst_mask; 70 70 71 - ring->xcp_id = ~0; 71 + ring->xcp_id = AMDGPU_XCP_NO_PARTITION; 72 72 if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE) 73 73 return; 74 74 ··· 177 177 u32 sel_xcp_id; 178 178 int i; 179 179 180 - if (fpriv->xcp_id == ~0) { 180 + if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) { 181 181 u32 least_ref_cnt = ~0; 182 182 183 183 fpriv->xcp_id = 0;

+1

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

··· 49 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 52 + MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 52 53 53 54 /* For large FW files the time to complete can be very long */ 54 55 #define USBC_PD_POLLING_LIMIT_S 240

+103 -153

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 424 424 425 425 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 426 426 427 - if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 428 - DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 429 - amdgpu_crtc->pflip_status, 430 - AMDGPU_FLIP_SUBMITTED, 431 - amdgpu_crtc->crtc_id, 432 - amdgpu_crtc); 427 + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 428 + DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 429 + amdgpu_crtc->pflip_status, 430 + AMDGPU_FLIP_SUBMITTED, 431 + amdgpu_crtc->crtc_id, 432 + amdgpu_crtc); 433 433 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 434 434 return; 435 435 } ··· 883 883 } 884 884 885 885 /* Prototypes of private functions */ 886 - static int dm_early_init(void* handle); 886 + static int dm_early_init(void *handle); 887 887 888 888 /* Allocate memory for FBC compressed data */ 889 889 static void amdgpu_dm_fbc_init(struct drm_connector *connector) ··· 1282 1282 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1283 1283 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1284 1284 1285 - pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 1285 + pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1286 1286 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1287 1287 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1288 1288 ··· 1347 1347 if (amdgpu_in_reset(adev)) 1348 1348 goto skip; 1349 1349 1350 + if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1351 + offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1352 + dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1353 + spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1354 + offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1355 + spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1356 + goto skip; 1357 + } 1358 + 1350 1359 mutex_lock(&adev->dm.dc_lock); 1351 1360 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1352 1361 dc_link_dp_handle_automated_test(dc_link); ··· 1374 1365 DP_TEST_RESPONSE, 1375 1366 &test_response.raw, 1376 1367 sizeof(test_response)); 1377 - } 1378 - else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1368 + } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1379 1369 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1380 1370 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1381 1371 /* offload_work->data is from handle_hpd_rx_irq-> ··· 1562 1554 mutex_init(&adev->dm.dc_lock); 1563 1555 mutex_init(&adev->dm.audio_lock); 1564 1556 1565 - if(amdgpu_dm_irq_init(adev)) { 1557 + if (amdgpu_dm_irq_init(adev)) { 1566 1558 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1567 1559 goto error; 1568 1560 } ··· 1704 1696 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1705 1697 adev->dm.dc->debug.disable_stutter = true; 1706 1698 1707 - if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 1699 + if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1708 1700 adev->dm.dc->debug.disable_dsc = true; 1709 - } 1710 1701 1711 1702 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1712 1703 adev->dm.dc->debug.disable_clock_gate = true; ··· 1949 1942 mutex_destroy(&adev->dm.audio_lock); 1950 1943 mutex_destroy(&adev->dm.dc_lock); 1951 1944 mutex_destroy(&adev->dm.dpia_aux_lock); 1952 - 1953 - return; 1954 1945 } 1955 1946 1956 1947 static int load_dmcu_fw(struct amdgpu_device *adev) ··· 1957 1952 int r; 1958 1953 const struct dmcu_firmware_header_v1_0 *hdr; 1959 1954 1960 - switch(adev->asic_type) { 1955 + switch (adev->asic_type) { 1961 1956 #if defined(CONFIG_DRM_AMD_DC_SI) 1962 1957 case CHIP_TAHITI: 1963 1958 case CHIP_PITCAIRN: ··· 2714 2709 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2715 2710 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2716 2711 struct dc_stream_update stream_update; 2717 - } * bundle; 2712 + } *bundle; 2718 2713 int k, m; 2719 2714 2720 2715 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); ··· 2744 2739 2745 2740 cleanup: 2746 2741 kfree(bundle); 2747 - 2748 - return; 2749 2742 } 2750 2743 2751 2744 static int dm_resume(void *handle) ··· 2957 2954 .set_powergating_state = dm_set_powergating_state, 2958 2955 }; 2959 2956 2960 - const struct amdgpu_ip_block_version dm_ip_block = 2961 - { 2957 + const struct amdgpu_ip_block_version dm_ip_block = { 2962 2958 .type = AMD_IP_BLOCK_TYPE_DCE, 2963 2959 .major = 1, 2964 2960 .minor = 0, ··· 3002 3000 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3003 3001 caps->aux_support = false; 3004 3002 3005 - if (caps->ext_caps->bits.oled == 1 /*|| 3006 - caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3007 - caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 3003 + if (caps->ext_caps->bits.oled == 1 3004 + /* 3005 + * || 3006 + * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3007 + * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3008 + */) 3008 3009 caps->aux_support = true; 3009 3010 3010 3011 if (amdgpu_backlight == 0) ··· 3241 3236 3242 3237 } 3243 3238 3244 - static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 3245 - { 3246 - u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 3247 - u8 dret; 3248 - bool new_irq_handled = false; 3249 - int dpcd_addr; 3250 - int dpcd_bytes_to_read; 3251 - 3252 - const int max_process_count = 30; 3253 - int process_count = 0; 3254 - 3255 - const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 3256 - 3257 - if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 3258 - dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 3259 - /* DPCD 0x200 - 0x201 for downstream IRQ */ 3260 - dpcd_addr = DP_SINK_COUNT; 3261 - } else { 3262 - dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 3263 - /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 3264 - dpcd_addr = DP_SINK_COUNT_ESI; 3265 - } 3266 - 3267 - dret = drm_dp_dpcd_read( 3268 - &aconnector->dm_dp_aux.aux, 3269 - dpcd_addr, 3270 - esi, 3271 - dpcd_bytes_to_read); 3272 - 3273 - while (dret == dpcd_bytes_to_read && 3274 - process_count < max_process_count) { 3275 - u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 3276 - u8 retry; 3277 - dret = 0; 3278 - 3279 - process_count++; 3280 - 3281 - DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3282 - /* handle HPD short pulse irq */ 3283 - if (aconnector->mst_mgr.mst_state) 3284 - drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, 3285 - esi, 3286 - ack, 3287 - &new_irq_handled); 3288 - 3289 - if (new_irq_handled) { 3290 - /* ACK at DPCD to notify down stream */ 3291 - for (retry = 0; retry < 3; retry++) { 3292 - ssize_t wret; 3293 - 3294 - wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, 3295 - dpcd_addr + 1, 3296 - ack[1]); 3297 - if (wret == 1) 3298 - break; 3299 - } 3300 - 3301 - if (retry == 3) { 3302 - DRM_ERROR("Failed to ack MST event.\n"); 3303 - return; 3304 - } 3305 - 3306 - drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); 3307 - /* check if there is new irq to be handled */ 3308 - dret = drm_dp_dpcd_read( 3309 - &aconnector->dm_dp_aux.aux, 3310 - dpcd_addr, 3311 - esi, 3312 - dpcd_bytes_to_read); 3313 - 3314 - new_irq_handled = false; 3315 - } else { 3316 - break; 3317 - } 3318 - } 3319 - 3320 - if (process_count == max_process_count) 3321 - DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 3322 - } 3323 - 3324 3239 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3325 3240 union hpd_irq_data hpd_irq_data) 3326 3241 { ··· 3302 3377 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3303 3378 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3304 3379 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3305 - dm_handle_mst_sideband_msg(aconnector); 3380 + bool skip = false; 3381 + 3382 + /* 3383 + * DOWN_REP_MSG_RDY is also handled by polling method 3384 + * mgr->cbs->poll_hpd_irq() 3385 + */ 3386 + spin_lock(&offload_wq->offload_lock); 3387 + skip = offload_wq->is_handling_mst_msg_rdy_event; 3388 + 3389 + if (!skip) 3390 + offload_wq->is_handling_mst_msg_rdy_event = true; 3391 + 3392 + spin_unlock(&offload_wq->offload_lock); 3393 + 3394 + if (!skip) 3395 + schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3396 + 3306 3397 goto out; 3307 3398 } 3308 3399 ··· 3409 3468 aconnector = to_amdgpu_dm_connector(connector); 3410 3469 dc_link = aconnector->dc_link; 3411 3470 3412 - if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 3471 + if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3413 3472 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3414 3473 int_params.irq_source = dc_link->irq_source_hpd; 3415 3474 ··· 3418 3477 (void *) aconnector); 3419 3478 } 3420 3479 3421 - if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 3480 + if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3422 3481 3423 3482 /* Also register for DP short pulse (hpd_rx). */ 3424 3483 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; ··· 3427 3486 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3428 3487 handle_hpd_rx_irq, 3429 3488 (void *) aconnector); 3430 - 3431 - if (adev->dm.hpd_rx_offload_wq) 3432 - adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector = 3433 - aconnector; 3434 3489 } 3490 + 3491 + if (adev->dm.hpd_rx_offload_wq) 3492 + adev->dm.hpd_rx_offload_wq[connector->index].aconnector = 3493 + aconnector; 3435 3494 } 3436 3495 } 3437 3496 ··· 3444 3503 struct dc_interrupt_params int_params = {0}; 3445 3504 int r; 3446 3505 int i; 3447 - unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3506 + unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3448 3507 3449 3508 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3450 3509 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; ··· 3458 3517 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3459 3518 * coming from DC hardware. 3460 3519 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3461 - * for acknowledging and handling. */ 3520 + * for acknowledging and handling. 3521 + */ 3462 3522 3463 3523 /* Use VBLANK interrupt */ 3464 3524 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3465 - r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 3525 + r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3466 3526 if (r) { 3467 3527 DRM_ERROR("Failed to add crtc irq id!\n"); 3468 3528 return r; ··· 3471 3529 3472 3530 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3473 3531 int_params.irq_source = 3474 - dc_interrupt_to_irq_source(dc, i+1 , 0); 3532 + dc_interrupt_to_irq_source(dc, i + 1, 0); 3475 3533 3476 3534 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3477 3535 ··· 3527 3585 struct dc_interrupt_params int_params = {0}; 3528 3586 int r; 3529 3587 int i; 3530 - unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3588 + unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3531 3589 3532 3590 if (adev->family >= AMDGPU_FAMILY_AI) 3533 3591 client_id = SOC15_IH_CLIENTID_DCE; ··· 3544 3602 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3545 3603 * coming from DC hardware. 3546 3604 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3547 - * for acknowledging and handling. */ 3605 + * for acknowledging and handling. 3606 + */ 3548 3607 3549 3608 /* Use VBLANK interrupt */ 3550 3609 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { ··· 3992 4049 } 3993 4050 3994 4051 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 3995 - unsigned *min, unsigned *max) 4052 + unsigned int *min, unsigned int *max) 3996 4053 { 3997 4054 if (!caps) 3998 4055 return 0; ··· 4012 4069 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4013 4070 uint32_t brightness) 4014 4071 { 4015 - unsigned min, max; 4072 + unsigned int min, max; 4016 4073 4017 4074 if (!get_brightness_range(caps, &min, &max)) 4018 4075 return brightness; ··· 4025 4082 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4026 4083 uint32_t brightness) 4027 4084 { 4028 - unsigned min, max; 4085 + unsigned int min, max; 4029 4086 4030 4087 if (!get_brightness_range(caps, &min, &max)) 4031 4088 return brightness; ··· 4505 4562 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4506 4563 { 4507 4564 drm_atomic_private_obj_fini(&dm->atomic_obj); 4508 - return; 4509 4565 } 4510 4566 4511 4567 /****************************************************************************** ··· 5336 5394 { 5337 5395 enum dc_color_depth depth = timing_out->display_color_depth; 5338 5396 int normalized_clk; 5397 + 5339 5398 do { 5340 5399 normalized_clk = timing_out->pix_clk_100hz / 10; 5341 5400 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ ··· 5552 5609 { 5553 5610 struct dc_sink_init_data sink_init_data = { 0 }; 5554 5611 struct dc_sink *sink = NULL; 5612 + 5555 5613 sink_init_data.link = aconnector->dc_link; 5556 5614 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5557 5615 ··· 5676 5732 return &aconnector->freesync_vid_base; 5677 5733 5678 5734 /* Find the preferred mode */ 5679 - list_for_each_entry (m, list_head, head) { 5735 + list_for_each_entry(m, list_head, head) { 5680 5736 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5681 5737 m_pref = m; 5682 5738 break; ··· 5700 5756 * For some monitors, preferred mode is not the mode with highest 5701 5757 * supported refresh rate. 5702 5758 */ 5703 - list_for_each_entry (m, list_head, head) { 5759 + list_for_each_entry(m, list_head, head) { 5704 5760 current_refresh = drm_mode_vrefresh(m); 5705 5761 5706 5762 if (m->hdisplay == m_pref->hdisplay && ··· 5972 6028 * This may not be an error, the use case is when we have no 5973 6029 * usermode calls to reset and set mode upon hotplug. In this 5974 6030 * case, we call set mode ourselves to restore the previous mode 5975 - * and the modelist may not be filled in in time. 6031 + * and the modelist may not be filled in time. 5976 6032 */ 5977 6033 DRM_DEBUG_DRIVER("No preferred mode found\n"); 5978 6034 } else { ··· 5995 6051 drm_mode_set_crtcinfo(&mode, 0); 5996 6052 5997 6053 /* 5998 - * If scaling is enabled and refresh rate didn't change 5999 - * we copy the vic and polarities of the old timings 6000 - */ 6054 + * If scaling is enabled and refresh rate didn't change 6055 + * we copy the vic and polarities of the old timings 6056 + */ 6001 6057 if (!scale || mode_refresh != preferred_refresh) 6002 6058 fill_stream_properties_from_drm_display_mode( 6003 6059 stream, &mode, &aconnector->base, con_state, NULL, ··· 6761 6817 6762 6818 if (!state->duplicated) { 6763 6819 int max_bpc = conn_state->max_requested_bpc; 6820 + 6764 6821 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6765 6822 aconnector->force_yuv420_output; 6766 6823 color_depth = convert_color_depth_from_display_info(connector, ··· 7080 7135 { 7081 7136 struct drm_display_mode *m; 7082 7137 7083 - list_for_each_entry (m, &aconnector->base.probed_modes, head) { 7138 + list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7084 7139 if (drm_mode_equal(m, mode)) 7085 7140 return true; 7086 7141 } ··· 7240 7295 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7241 7296 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7242 7297 mutex_init(&aconnector->hpd_lock); 7298 + mutex_init(&aconnector->handle_mst_msg_ready); 7243 7299 7244 7300 /* 7245 7301 * configure support HPD hot plug connector_>polled default value is 0 ··· 7400 7454 7401 7455 link->priv = aconnector; 7402 7456 7403 - DRM_DEBUG_DRIVER("%s()\n", __func__); 7404 7457 7405 7458 i2c = create_i2c(link->ddc, link->link_index, &res); 7406 7459 if (!i2c) { ··· 8070 8125 * Only allow immediate flips for fast updates that don't 8071 8126 * change memory domain, FB pitch, DCC state, rotation or 8072 8127 * mirroring. 8128 + * 8129 + * dm_crtc_helper_atomic_check() only accepts async flips with 8130 + * fast updates. 8073 8131 */ 8132 + if (crtc->state->async_flip && 8133 + acrtc_state->update_type != UPDATE_TYPE_FAST) 8134 + drm_warn_once(state->dev, 8135 + "[PLANE:%d:%s] async flip with non-fast update\n", 8136 + plane->base.id, plane->name); 8074 8137 bundle->flip_addrs[planes_count].flip_immediate = 8075 8138 crtc->state->async_flip && 8076 8139 acrtc_state->update_type == UPDATE_TYPE_FAST && ··· 8121 8168 * DRI3/Present extension with defined target_msc. 8122 8169 */ 8123 8170 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8124 - } 8125 - else { 8171 + } else { 8126 8172 /* For variable refresh rate mode only: 8127 8173 * Get vblank of last completed flip to avoid > 1 vrr 8128 8174 * flips per video frame by use of throttling, but allow ··· 8454 8502 dc_resource_state_copy_construct_current(dm->dc, dc_state); 8455 8503 } 8456 8504 8457 - for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 8458 - new_crtc_state, i) { 8505 + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 8506 + new_crtc_state, i) { 8459 8507 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8460 8508 8461 8509 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); ··· 8478 8526 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8479 8527 8480 8528 drm_dbg_state(state->dev, 8481 - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8482 - "planes_changed:%d, mode_changed:%d,active_changed:%d," 8483 - "connectors_changed:%d\n", 8529 + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 8484 8530 acrtc->crtc_id, 8485 8531 new_crtc_state->enable, 8486 8532 new_crtc_state->active, ··· 9054 9104 &commit->flip_done, 10*HZ); 9055 9105 9056 9106 if (ret == 0) 9057 - DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 9058 - "timed out\n", crtc->base.id, crtc->name); 9107 + DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 9108 + crtc->base.id, crtc->name); 9059 9109 9060 9110 drm_crtc_commit_put(commit); 9061 9111 } ··· 9140 9190 return false; 9141 9191 } 9142 9192 9143 - static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { 9193 + static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 9194 + { 9144 9195 u64 num, den, res; 9145 9196 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9146 9197 ··· 9263 9312 goto skip_modeset; 9264 9313 9265 9314 drm_dbg_state(state->dev, 9266 - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 9267 - "planes_changed:%d, mode_changed:%d,active_changed:%d," 9268 - "connectors_changed:%d\n", 9315 + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9269 9316 acrtc->crtc_id, 9270 9317 new_crtc_state->enable, 9271 9318 new_crtc_state->active, ··· 9292 9343 old_crtc_state)) { 9293 9344 new_crtc_state->mode_changed = false; 9294 9345 DRM_DEBUG_DRIVER( 9295 - "Mode change not required for front porch change, " 9296 - "setting mode_changed to %d", 9346 + "Mode change not required for front porch change, setting mode_changed to %d", 9297 9347 new_crtc_state->mode_changed); 9298 9348 9299 9349 set_freesync_fixed_config(dm_new_crtc_state); ··· 9304 9356 struct drm_display_mode *high_mode; 9305 9357 9306 9358 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9307 - if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { 9359 + if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 9308 9360 set_freesync_fixed_config(dm_new_crtc_state); 9309 - } 9310 9361 } 9311 9362 9312 9363 ret = dm_atomic_get_state(state, &dm_state); ··· 9473 9526 */ 9474 9527 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9475 9528 struct amdgpu_framebuffer *old_afb, *new_afb; 9529 + 9476 9530 if (other->type == DRM_PLANE_TYPE_CURSOR) 9477 9531 continue; 9478 9532 ··· 9572 9624 } 9573 9625 9574 9626 /* Core DRM takes care of checking FB modifiers, so we only need to 9575 - * check tiling flags when the FB doesn't have a modifier. */ 9627 + * check tiling flags when the FB doesn't have a modifier. 9628 + */ 9576 9629 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9577 9630 if (adev->family < AMDGPU_FAMILY_AI) { 9578 9631 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9579 - AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9632 + AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9580 9633 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9581 9634 } else { 9582 9635 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; ··· 9799 9850 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9800 9851 * cursor per pipe but it's going to inherit the scaling and 9801 9852 * positioning from the underlying pipe. Check the cursor plane's 9802 - * blending properties match the underlying planes'. */ 9853 + * blending properties match the underlying planes'. 9854 + */ 9803 9855 9804 9856 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); 9805 - if (!new_cursor_state || !new_cursor_state->fb) { 9857 + if (!new_cursor_state || !new_cursor_state->fb) 9806 9858 return 0; 9807 - } 9808 9859 9809 9860 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); 9810 9861 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; ··· 9849 9900 struct drm_connector_state *conn_state, *old_conn_state; 9850 9901 struct amdgpu_dm_connector *aconnector = NULL; 9851 9902 int i; 9903 + 9852 9904 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 9853 9905 if (!conn_state->crtc) 9854 9906 conn_state = old_conn_state; ··· 10284 10334 } 10285 10335 10286 10336 /* Store the overall update type for use later in atomic check. */ 10287 - for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 10337 + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10288 10338 struct dm_crtc_state *dm_new_crtc_state = 10289 10339 to_dm_crtc_state(new_crtc_state); 10290 10340 ··· 10306 10356 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 10307 10357 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 10308 10358 else 10309 - DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 10359 + DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); 10310 10360 10311 10361 trace_amdgpu_dm_atomic_check_finish(state, ret); 10312 10362

+7

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

··· 195 195 */ 196 196 bool is_handling_link_loss; 197 197 /** 198 + * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 199 + * ready event when we're already handling mst message ready event 200 + */ 201 + bool is_handling_mst_msg_rdy_event; 202 + /** 198 203 * @aconnector: The aconnector that this work queue is attached to 199 204 */ 200 205 struct amdgpu_dm_connector *aconnector; ··· 643 638 struct drm_dp_mst_port *mst_output_port; 644 639 struct amdgpu_dm_connector *mst_root; 645 640 struct drm_dp_aux *dsc_aux; 641 + struct mutex handle_mst_msg_ready; 642 + 646 643 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 647 644 struct amdgpu_i2c_adapter *i2c; 648 645

+12

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

··· 398 398 return -EINVAL; 399 399 } 400 400 401 + /* 402 + * Only allow async flips for fast updates that don't change the FB 403 + * pitch, the DCC state, rotation, etc. 404 + */ 405 + if (crtc_state->async_flip && 406 + dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 407 + drm_dbg_atomic(crtc->dev, 408 + "[CRTC:%d:%s] async flips are only supported for fast updates\n", 409 + crtc->base.id, crtc->name); 410 + return -EINVAL; 411 + } 412 + 401 413 /* In some use cases, like reset, no stream is attached */ 402 414 if (!dm_crtc_state->stream) 403 415 return 0;

+110

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

··· 619 619 return connector; 620 620 } 621 621 622 + void dm_handle_mst_sideband_msg_ready_event( 623 + struct drm_dp_mst_topology_mgr *mgr, 624 + enum mst_msg_ready_type msg_rdy_type) 625 + { 626 + uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 627 + uint8_t dret; 628 + bool new_irq_handled = false; 629 + int dpcd_addr; 630 + uint8_t dpcd_bytes_to_read; 631 + const uint8_t max_process_count = 30; 632 + uint8_t process_count = 0; 633 + u8 retry; 634 + struct amdgpu_dm_connector *aconnector = 635 + container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 636 + 637 + 638 + const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 639 + 640 + if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 641 + dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 642 + /* DPCD 0x200 - 0x201 for downstream IRQ */ 643 + dpcd_addr = DP_SINK_COUNT; 644 + } else { 645 + dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 646 + /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 647 + dpcd_addr = DP_SINK_COUNT_ESI; 648 + } 649 + 650 + mutex_lock(&aconnector->handle_mst_msg_ready); 651 + 652 + while (process_count < max_process_count) { 653 + u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 654 + 655 + process_count++; 656 + 657 + dret = drm_dp_dpcd_read( 658 + &aconnector->dm_dp_aux.aux, 659 + dpcd_addr, 660 + esi, 661 + dpcd_bytes_to_read); 662 + 663 + if (dret != dpcd_bytes_to_read) { 664 + DRM_DEBUG_KMS("DPCD read and acked number is not as expected!"); 665 + break; 666 + } 667 + 668 + DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 669 + 670 + switch (msg_rdy_type) { 671 + case DOWN_REP_MSG_RDY_EVENT: 672 + /* Only handle DOWN_REP_MSG_RDY case*/ 673 + esi[1] &= DP_DOWN_REP_MSG_RDY; 674 + break; 675 + case UP_REQ_MSG_RDY_EVENT: 676 + /* Only handle UP_REQ_MSG_RDY case*/ 677 + esi[1] &= DP_UP_REQ_MSG_RDY; 678 + break; 679 + default: 680 + /* Handle both cases*/ 681 + esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY); 682 + break; 683 + } 684 + 685 + if (!esi[1]) 686 + break; 687 + 688 + /* handle MST irq */ 689 + if (aconnector->mst_mgr.mst_state) 690 + drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, 691 + esi, 692 + ack, 693 + &new_irq_handled); 694 + 695 + if (new_irq_handled) { 696 + /* ACK at DPCD to notify down stream */ 697 + for (retry = 0; retry < 3; retry++) { 698 + ssize_t wret; 699 + 700 + wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, 701 + dpcd_addr + 1, 702 + ack[1]); 703 + if (wret == 1) 704 + break; 705 + } 706 + 707 + if (retry == 3) { 708 + DRM_ERROR("Failed to ack MST event.\n"); 709 + return; 710 + } 711 + 712 + drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); 713 + 714 + new_irq_handled = false; 715 + } else { 716 + break; 717 + } 718 + } 719 + 720 + mutex_unlock(&aconnector->handle_mst_msg_ready); 721 + 722 + if (process_count == max_process_count) 723 + DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 724 + } 725 + 726 + static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) 727 + { 728 + dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); 729 + } 730 + 622 731 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 623 732 .add_connector = dm_dp_add_mst_connector, 733 + .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, 624 734 }; 625 735 626 736 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,

+11

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h

··· 49 49 #define PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B 1031 50 50 #define PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B 1000 51 51 52 + enum mst_msg_ready_type { 53 + NONE_MSG_RDY_EVENT = 0, 54 + DOWN_REP_MSG_RDY_EVENT = 1, 55 + UP_REQ_MSG_RDY_EVENT = 2, 56 + DOWN_OR_UP_MSG_RDY_EVENT = 3 57 + }; 58 + 52 59 struct amdgpu_display_manager; 53 60 struct amdgpu_dm_connector; 54 61 ··· 67 60 68 61 void 69 62 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev); 63 + 64 + void dm_handle_mst_sideband_msg_ready_event( 65 + struct drm_dp_mst_topology_mgr *mgr, 66 + enum mst_msg_ready_type msg_rdy_type); 70 67 71 68 struct dsc_mst_fairness_vars { 72 69 int pbn;

+5

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

··· 87 87 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 88 88 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 89 89 tmds_present = true; 90 + 91 + /* Checking stream / link detection ensuring that PHY is active*/ 92 + if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) 93 + display_count++; 94 + 90 95 } 91 96 92 97 for (i = 0; i < dc->link_count; i++) {

+2 -1

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

··· 3278 3278 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { 3279 3279 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); 3280 3280 3281 - if (pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) 3281 + if (pipe_ctx->stream_res.tg && 3282 + pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) 3282 3283 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); 3283 3284 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; 3284 3285 hubp->funcs->set_blank(hubp, true);

+2 -2

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c

··· 215 215 optc1->opp_count = 1; 216 216 } 217 217 218 - static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 218 + void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 219 219 struct dc_crtc_timing *timing) 220 220 { 221 221 struct optc *optc1 = DCN10TG_FROM_TG(optc); ··· 293 293 OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode); 294 294 } 295 295 296 - static void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc) 296 + void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc) 297 297 { 298 298 struct optc *optc1 = DCN10TG_FROM_TG(optc); 299 299

+3

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h

··· 351 351 352 352 void optc3_set_odm_bypass(struct timing_generator *optc, 353 353 const struct dc_crtc_timing *dc_crtc_timing); 354 + void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 355 + struct dc_crtc_timing *timing); 356 + void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc); 354 357 void optc3_tg_init(struct timing_generator *optc); 355 358 void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); 356 359 #endif /* __DC_OPTC_DCN30_H__ */

+2 -1

drivers/gpu/drm/amd/display/dc/dcn301/Makefile

··· 11 11 # Makefile for dcn30. 12 12 13 13 DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \ 14 - dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o 14 + dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o \ 15 + dcn301_optc.o 15 16 16 17 AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301)) 17 18

+185

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c

··· 1 + /* 2 + * Copyright 2020 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * Authors: AMD 23 + * 24 + */ 25 + 26 + #include "reg_helper.h" 27 + #include "dcn301_optc.h" 28 + #include "dc.h" 29 + #include "dcn_calc_math.h" 30 + #include "dc_dmub_srv.h" 31 + 32 + #include "dml/dcn30/dcn30_fpu.h" 33 + #include "dc_trace.h" 34 + 35 + #define REG(reg)\ 36 + optc1->tg_regs->reg 37 + 38 + #define CTX \ 39 + optc1->base.ctx 40 + 41 + #undef FN 42 + #define FN(reg_name, field_name) \ 43 + optc1->tg_shift->field_name, optc1->tg_mask->field_name 44 + 45 + 46 + /** 47 + * optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 48 + * 49 + * @optc: timing_generator instance. 50 + * @params: parameters used for Dynamic Refresh Rate. 51 + */ 52 + void optc301_set_drr( 53 + struct timing_generator *optc, 54 + const struct drr_params *params) 55 + { 56 + struct optc *optc1 = DCN10TG_FROM_TG(optc); 57 + 58 + if (params != NULL && 59 + params->vertical_total_max > 0 && 60 + params->vertical_total_min > 0) { 61 + 62 + if (params->vertical_total_mid != 0) { 63 + 64 + REG_SET(OTG_V_TOTAL_MID, 0, 65 + OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 66 + 67 + REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 68 + OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 69 + OTG_VTOTAL_MID_FRAME_NUM, 70 + (uint8_t)params->vertical_total_mid_frame_num); 71 + 72 + } 73 + 74 + optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 75 + 76 + REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 77 + OTG_V_TOTAL_MIN_SEL, 1, 78 + OTG_V_TOTAL_MAX_SEL, 1, 79 + OTG_FORCE_LOCK_ON_EVENT, 0, 80 + OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 81 + OTG_SET_V_TOTAL_MIN_MASK, 0); 82 + // Setup manual flow control for EOF via TRIG_A 83 + optc->funcs->setup_manual_trigger(optc); 84 + 85 + } else { 86 + REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 87 + OTG_SET_V_TOTAL_MIN_MASK, 0, 88 + OTG_V_TOTAL_MIN_SEL, 0, 89 + OTG_V_TOTAL_MAX_SEL, 0, 90 + OTG_FORCE_LOCK_ON_EVENT, 0); 91 + 92 + optc->funcs->set_vtotal_min_max(optc, 0, 0); 93 + } 94 + } 95 + 96 + 97 + void optc301_setup_manual_trigger(struct timing_generator *optc) 98 + { 99 + struct optc *optc1 = DCN10TG_FROM_TG(optc); 100 + 101 + REG_SET_8(OTG_TRIGA_CNTL, 0, 102 + OTG_TRIGA_SOURCE_SELECT, 21, 103 + OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 104 + OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 105 + OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 106 + OTG_TRIGA_POLARITY_SELECT, 0, 107 + OTG_TRIGA_FREQUENCY_SELECT, 0, 108 + OTG_TRIGA_DELAY, 0, 109 + OTG_TRIGA_CLEAR, 1); 110 + } 111 + 112 + static struct timing_generator_funcs dcn30_tg_funcs = { 113 + .validate_timing = optc1_validate_timing, 114 + .program_timing = optc1_program_timing, 115 + .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 116 + .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 117 + .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 118 + .program_global_sync = optc1_program_global_sync, 119 + .enable_crtc = optc2_enable_crtc, 120 + .disable_crtc = optc1_disable_crtc, 121 + /* used by enable_timing_synchronization. Not need for FPGA */ 122 + .is_counter_moving = optc1_is_counter_moving, 123 + .get_position = optc1_get_position, 124 + .get_frame_count = optc1_get_vblank_counter, 125 + .get_scanoutpos = optc1_get_crtc_scanoutpos, 126 + .get_otg_active_size = optc1_get_otg_active_size, 127 + .set_early_control = optc1_set_early_control, 128 + /* used by enable_timing_synchronization. Not need for FPGA */ 129 + .wait_for_state = optc1_wait_for_state, 130 + .set_blank_color = optc3_program_blank_color, 131 + .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 132 + .triplebuffer_lock = optc3_triplebuffer_lock, 133 + .triplebuffer_unlock = optc2_triplebuffer_unlock, 134 + .enable_reset_trigger = optc1_enable_reset_trigger, 135 + .enable_crtc_reset = optc1_enable_crtc_reset, 136 + .disable_reset_trigger = optc1_disable_reset_trigger, 137 + .lock = optc3_lock, 138 + .unlock = optc1_unlock, 139 + .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 140 + .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 141 + .enable_optc_clock = optc1_enable_optc_clock, 142 + .set_drr = optc301_set_drr, 143 + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 144 + .set_vtotal_min_max = optc3_set_vtotal_min_max, 145 + .set_static_screen_control = optc1_set_static_screen_control, 146 + .program_stereo = optc1_program_stereo, 147 + .is_stereo_left_eye = optc1_is_stereo_left_eye, 148 + .tg_init = optc3_tg_init, 149 + .is_tg_enabled = optc1_is_tg_enabled, 150 + .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 151 + .clear_optc_underflow = optc1_clear_optc_underflow, 152 + .setup_global_swap_lock = NULL, 153 + .get_crc = optc1_get_crc, 154 + .configure_crc = optc2_configure_crc, 155 + .set_dsc_config = optc3_set_dsc_config, 156 + .get_dsc_status = optc2_get_dsc_status, 157 + .set_dwb_source = NULL, 158 + .set_odm_bypass = optc3_set_odm_bypass, 159 + .set_odm_combine = optc3_set_odm_combine, 160 + .get_optc_source = optc2_get_optc_source, 161 + .set_out_mux = optc3_set_out_mux, 162 + .set_drr_trigger_window = optc3_set_drr_trigger_window, 163 + .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 164 + .set_gsl = optc2_set_gsl, 165 + .set_gsl_source_select = optc2_set_gsl_source_select, 166 + .set_vtg_params = optc1_set_vtg_params, 167 + .program_manual_trigger = optc2_program_manual_trigger, 168 + .setup_manual_trigger = optc301_setup_manual_trigger, 169 + .get_hw_timing = optc1_get_hw_timing, 170 + .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, 171 + }; 172 + 173 + void dcn301_timing_generator_init(struct optc *optc1) 174 + { 175 + optc1->base.funcs = &dcn30_tg_funcs; 176 + 177 + optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 178 + optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 179 + 180 + optc1->min_h_blank = 32; 181 + optc1->min_v_blank = 3; 182 + optc1->min_v_blank_interlace = 5; 183 + optc1->min_h_sync_width = 4; 184 + optc1->min_v_sync_width = 1; 185 + }

+36

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h

··· 1 + /* 2 + * Copyright 2020 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * Authors: AMD 23 + * 24 + */ 25 + 26 + #ifndef __DC_OPTC_DCN301_H__ 27 + #define __DC_OPTC_DCN301_H__ 28 + 29 + #include "dcn20/dcn20_optc.h" 30 + #include "dcn30/dcn30_optc.h" 31 + 32 + void dcn301_timing_generator_init(struct optc *optc1); 33 + void optc301_setup_manual_trigger(struct timing_generator *optc); 34 + void optc301_set_drr(struct timing_generator *optc, const struct drr_params *params); 35 + 36 + #endif /* __DC_OPTC_DCN301_H__ */

+2 -2

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

··· 42 42 #include "dcn30/dcn30_hubp.h" 43 43 #include "irq/dcn30/irq_service_dcn30.h" 44 44 #include "dcn30/dcn30_dpp.h" 45 - #include "dcn30/dcn30_optc.h" 45 + #include "dcn301/dcn301_optc.h" 46 46 #include "dcn20/dcn20_hwseq.h" 47 47 #include "dcn30/dcn30_hwseq.h" 48 48 #include "dce110/dce110_hw_sequencer.h" ··· 855 855 tgn10->tg_shift = &optc_shift; 856 856 tgn10->tg_mask = &optc_mask; 857 857 858 - dcn30_timing_generator_init(tgn10); 858 + dcn301_timing_generator_init(tgn10); 859 859 860 860 return &tgn10->base; 861 861 }

+1 -1

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

··· 65 65 .timing_trace = false, 66 66 .clock_trace = true, 67 67 .disable_pplib_clock_request = true, 68 - .pipe_split_policy = MPC_SPLIT_DYNAMIC, 68 + .pipe_split_policy = MPC_SPLIT_AVOID, 69 69 .force_single_disp_pipe_split = false, 70 70 .disable_dcc = DCC_ENABLE, 71 71 .vsr_support = true,

+5 -1

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

··· 295 295 pipe = &res_ctx->pipe_ctx[i]; 296 296 timing = &pipe->stream->timing; 297 297 298 - pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 298 + if (pipe->stream->adjust.v_total_min != 0) 299 + pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 300 + else 301 + pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; 302 + 299 303 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 300 304 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS); 301 305 pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width);

+2 -12

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

··· 1798 1798 return result; 1799 1799 } 1800 1800 1801 - static bool intel_core_rkl_chk(void) 1802 - { 1803 - #if IS_ENABLED(CONFIG_X86_64) 1804 - struct cpuinfo_x86 *c = &cpu_data(0); 1805 - 1806 - return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE); 1807 - #else 1808 - return false; 1809 - #endif 1810 - } 1811 - 1812 1801 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 1813 1802 { 1814 1803 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); ··· 1824 1835 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 1825 1836 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 1826 1837 data->pcie_dpm_key_disabled = 1827 - intel_core_rkl_chk() || !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1838 + !amdgpu_device_pcie_dynamic_switching_supported() || 1839 + !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1828 1840 /* need to set voltage control types before EVV patching */ 1829 1841 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE; 1830 1842 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;

+6 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

··· 1927 1927 *size = 4; 1928 1928 break; 1929 1929 case AMDGPU_PP_SENSOR_GFX_MCLK: 1930 - ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1930 + ret = sienna_cichlid_get_smu_metrics_data(smu, 1931 + METRICS_CURR_UCLK, 1932 + (uint32_t *)data); 1931 1933 *(uint32_t *)data *= 100; 1932 1934 *size = 4; 1933 1935 break; 1934 1936 case AMDGPU_PP_SENSOR_GFX_SCLK: 1935 - ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1937 + ret = sienna_cichlid_get_smu_metrics_data(smu, 1938 + METRICS_AVERAGE_GFXCLK, 1939 + (uint32_t *)data); 1936 1940 *(uint32_t *)data *= 100; 1937 1941 *size = 4; 1938 1942 break;

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

··· 949 949 break; 950 950 case AMDGPU_PP_SENSOR_GFX_MCLK: 951 951 ret = smu_v13_0_7_get_smu_metrics_data(smu, 952 - METRICS_AVERAGE_UCLK, 952 + METRICS_CURR_UCLK, 953 953 (uint32_t *)data); 954 954 *(uint32_t *)data *= 100; 955 955 *size = 4;

+6

drivers/gpu/drm/drm_client_modeset.c

··· 311 311 can_clone = true; 312 312 dmt_mode = drm_mode_find_dmt(dev, 1024, 768, 60, false); 313 313 314 + if (!dmt_mode) 315 + goto fail; 316 + 314 317 for (i = 0; i < connector_count; i++) { 315 318 if (!enabled[i]) 316 319 continue; ··· 329 326 if (!modes[i]) 330 327 can_clone = false; 331 328 } 329 + kfree(dmt_mode); 332 330 333 331 if (can_clone) { 334 332 DRM_DEBUG_KMS("can clone using 1024x768\n"); 335 333 return true; 336 334 } 335 + fail: 337 336 DRM_INFO("kms: can't enable cloning when we probably wanted to.\n"); 338 337 return false; 339 338 } ··· 867 862 break; 868 863 } 869 864 865 + kfree(modeset->mode); 870 866 modeset->mode = drm_mode_duplicate(dev, mode); 871 867 drm_connector_get(connector); 872 868 modeset->connectors[modeset->num_connectors++] = connector;

+5

drivers/gpu/drm/i915/Makefile

··· 23 23 subdir-ccflags-y += $(call cc-disable-warning, frame-address) 24 24 subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror 25 25 26 + # Fine grained warnings disable 27 + CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init) 28 + CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init) 29 + CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init) 30 + 26 31 subdir-ccflags-y += -I$(srctree)/$(src) 27 32 28 33 # Please keep these build lists sorted!

-5

drivers/gpu/drm/i915/display/intel_display_device.c

··· 16 16 #include "intel_display_reg_defs.h" 17 17 #include "intel_fbc.h" 18 18 19 - __diag_push(); 20 - __diag_ignore_all("-Woverride-init", "Allow overriding inherited members"); 21 - 22 19 static const struct intel_display_device_info no_display = {}; 23 20 24 21 #define PIPE_A_OFFSET 0x70000 ··· 661 664 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 662 665 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 663 666 }; 664 - 665 - __diag_pop(); 666 667 667 668 #undef INTEL_VGA_DEVICE 668 669 #undef INTEL_QUANTA_VGA_DEVICE

-5

drivers/gpu/drm/i915/display/intel_fbdev.c

··· 135 135 return i915_gem_fb_mmap(obj, vma); 136 136 } 137 137 138 - __diag_push(); 139 - __diag_ignore_all("-Woverride-init", "Allow overriding the default ops"); 140 - 141 138 static const struct fb_ops intelfb_ops = { 142 139 .owner = THIS_MODULE, 143 140 __FB_DEFAULT_DEFERRED_OPS_RDWR(intel_fbdev), ··· 145 148 __FB_DEFAULT_DEFERRED_OPS_DRAW(intel_fbdev), 146 149 .fb_mmap = intel_fbdev_mmap, 147 150 }; 148 - 149 - __diag_pop(); 150 151 151 152 static int intelfb_alloc(struct drm_fb_helper *helper, 152 153 struct drm_fb_helper_surface_size *sizes)

-5

drivers/gpu/drm/i915/i915_pci.c

··· 38 38 #include "i915_reg.h" 39 39 #include "intel_pci_config.h" 40 40 41 - __diag_push(); 42 - __diag_ignore_all("-Woverride-init", "Allow overriding inherited members"); 43 - 44 41 #define PLATFORM(x) .platform = (x) 45 42 #define GEN(x) \ 46 43 .__runtime.graphics.ip.ver = (x), \ ··· 842 845 }; 843 846 844 847 #undef PLATFORM 845 - 846 - __diag_pop(); 847 848 848 849 /* 849 850 * Make sure any device matches here are from most specific to most

+1

drivers/gpu/drm/i915/i915_perf.c

··· 4431 4431 static const struct i915_range xehp_oa_b_counters[] = { 4432 4432 { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */ 4433 4433 { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */ 4434 + {} 4434 4435 }; 4435 4436 4436 4437 static const struct i915_range gen7_oa_mux_regs[] = {

+4

drivers/gpu/drm/nouveau/dispnv50/disp.c

··· 1877 1877 nvif_outp_dtor(&nv_encoder->outp); 1878 1878 1879 1879 drm_encoder_cleanup(encoder); 1880 + 1881 + mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1880 1882 kfree(encoder); 1881 1883 } 1882 1884 ··· 1922 1920 nv_encoder->dcb = dcbe; 1923 1921 nv_encoder->i2c = ddc; 1924 1922 nv_encoder->aux = aux; 1923 + 1924 + mutex_init(&nv_encoder->dp.hpd_irq_lock); 1925 1925 1926 1926 encoder = to_drm_encoder(nv_encoder); 1927 1927 encoder->possible_crtcs = dcbe->heads;

+2 -2

drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h

··· 16 16 const struct nvkm_i2c_bus_func *func; 17 17 struct nvkm_i2c_pad *pad; 18 18 #define NVKM_I2C_BUS_CCB(n) /* 'n' is ccb index */ (n) 19 - #define NVKM_I2C_BUS_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x100) 19 + #define NVKM_I2C_BUS_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x10) 20 20 #define NVKM_I2C_BUS_PRI /* ccb primary comm. port */ -1 21 21 #define NVKM_I2C_BUS_SEC /* ccb secondary comm. port */ -2 22 22 int id; ··· 38 38 const struct nvkm_i2c_aux_func *func; 39 39 struct nvkm_i2c_pad *pad; 40 40 #define NVKM_I2C_AUX_CCB(n) /* 'n' is ccb index */ (n) 41 - #define NVKM_I2C_AUX_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x100) 41 + #define NVKM_I2C_AUX_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x10) 42 42 int id; 43 43 44 44 struct mutex mutex;

+18 -9

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

··· 81 81 return -ENOSYS; 82 82 83 83 list_for_each_entry(outp, &conn->disp->outps, head) { 84 - if (outp->info.connector == conn->index && outp->dp.aux) { 85 - if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_I2C_PLUG; 86 - if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_I2C_UNPLUG; 87 - if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ ) bits |= NVKM_I2C_IRQ; 84 + if (outp->info.connector == conn->index) 85 + break; 86 + } 88 87 89 - return nvkm_uevent_add(uevent, &device->i2c->event, outp->dp.aux->id, bits, 90 - nvkm_uconn_uevent_aux); 91 - } 88 + if (&outp->head == &conn->disp->outps) 89 + return -EINVAL; 90 + 91 + if (outp->dp.aux && !outp->info.location) { 92 + if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_I2C_PLUG; 93 + if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_I2C_UNPLUG; 94 + if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ ) bits |= NVKM_I2C_IRQ; 95 + 96 + return nvkm_uevent_add(uevent, &device->i2c->event, outp->dp.aux->id, bits, 97 + nvkm_uconn_uevent_aux); 92 98 } 93 99 94 100 if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_GPIO_HI; 95 101 if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_GPIO_LO; 96 - if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ) 97 - return -EINVAL; 102 + if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ) { 103 + /* TODO: support DP IRQ on ANX9805 and remove this hack. */ 104 + if (!outp->info.location) 105 + return -EINVAL; 106 + } 98 107 99 108 return nvkm_uevent_add(uevent, &device->gpio->event, conn->info.hpd, bits, 100 109 nvkm_uconn_uevent_gpio);

+9 -2

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c

··· 260 260 { 261 261 struct nvkm_bios *bios = device->bios; 262 262 struct nvkm_i2c *i2c; 263 + struct nvkm_i2c_aux *aux; 263 264 struct dcb_i2c_entry ccbE; 264 265 struct dcb_output dcbE; 265 266 u8 ver, hdr; 266 - int ret, i; 267 + int ret, i, ids; 267 268 268 269 if (!(i2c = *pi2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) 269 270 return -ENOMEM; ··· 407 406 } 408 407 } 409 408 410 - return nvkm_event_init(&nvkm_i2c_intr_func, &i2c->subdev, 4, i, &i2c->event); 409 + ids = 0; 410 + list_for_each_entry(aux, &i2c->aux, head) 411 + ids = max(ids, aux->id + 1); 412 + if (!ids) 413 + return 0; 414 + 415 + return nvkm_event_init(&nvkm_i2c_intr_func, &i2c->subdev, 4, ids, &i2c->event); 411 416 }

Configure Feed

Configure Feed