clk: qcom: smd: Add missing RPM clocks for msm8992/4

XO and MSS_CFG were omitted when first adding the clocks for these SoCs.
Add them, and while at it, move the XO clock to the top of the definition
list, as ideally everyone should start using it sooner or later..

Fixes: b4297844995f ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226214126.21209-2-konrad.dybcio@somainline.org

authored by

Konrad Dybcio and committed by

Bjorn Andersson 4 years ago f804360b 5b2fa289

+12 -2

2 changed files

expand all

drivers

clk

qcom

clk-smd-rpm.c

include

linux

soc

qcom

smd-rpm.h

+11 -2

drivers/clk/qcom/clk-smd-rpm.c

··· 413 413 .recalc_rate = clk_smd_rpm_recalc_rate, 414 414 }; 415 415 416 + DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); 416 417 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 417 418 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 418 419 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); ··· 605 604 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 606 605 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); 607 606 607 + DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk, 608 + QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); 608 609 static struct clk_smd_rpm *msm8992_clks[] = { 610 + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 611 + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 609 612 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, 610 613 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, 611 614 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, ··· 642 637 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, 643 638 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, 644 639 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, 640 + [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, 641 + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk, 645 642 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 646 643 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 647 644 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, ··· 668 661 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); 669 662 670 663 static struct clk_smd_rpm *msm8994_clks[] = { 664 + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 665 + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 671 666 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, 672 667 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, 673 668 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, ··· 702 693 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, 703 694 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, 704 695 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, 696 + [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, 697 + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk, 705 698 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 706 699 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 707 700 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, ··· 868 857 .num_clks = ARRAY_SIZE(msm8998_clks), 869 858 }; 870 859 871 - DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 872 - 19200000); 873 860 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); 874 861 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000); 875 862

include/linux/soc/qcom/smd-rpm.h

··· 40 40 #define QCOM_SMD_RPM_AGGR_CLK 0x72676761 41 41 #define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768 42 42 #define QCOM_SMD_RPM_PKA_CLK 0x616b70 43 + #define QCOM_SMD_RPM_MCFG_CLK 0x6766636d 43 44 44 45 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, 45 46 int state,

Configure Feed

Configure Feed