tjh.dev / kernel
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drm/amdgpu: Move vcn ras block init to ras sw_init

Initialize vcn ras block only when vcn ip block
supports ras features. Driver queries ras capabilities
after early_init, ras block init needs to be moved to
sw_int.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Stanley Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher f81c31d9 5640e06e

+28 -15
+19 -10
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
··· 1162 1162 return 0; 1163 1163 } 1164 1164 1165 - void amdgpu_vcn_set_ras_funcs(struct amdgpu_device *adev) 1165 + int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1166 1166 { 1167 + int err; 1168 + struct amdgpu_vcn_ras *ras; 1169 + 1167 1170 if (!adev->vcn.ras) 1168 - return; 1171 + return 0; 1169 1172 1170 - amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block); 1173 + ras = adev->vcn.ras; 1174 + err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1175 + if (err) { 1176 + dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1177 + return err; 1178 + } 1171 1179 1172 - strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn"); 1173 - adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1174 - adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1175 - adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm; 1180 + strcpy(ras->ras_block.ras_comm.name, "vcn"); 1181 + ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1182 + ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1183 + adev->vcn.ras_if = &ras->ras_block.ras_comm; 1176 1184 1177 - /* If don't define special ras_late_init function, use default ras_late_init */ 1178 - if (!adev->vcn.ras->ras_block.ras_late_init) 1179 - adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; 1185 + if (!ras->ras_block.ras_late_init) 1186 + ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; 1187 + 1188 + return 0; 1180 1189 }
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
··· 400 400 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 401 401 struct amdgpu_irq_src *source, 402 402 struct amdgpu_iv_entry *entry); 403 - void amdgpu_vcn_set_ras_funcs(struct amdgpu_device *adev); 403 + int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev); 404 404 405 405 #endif
+4 -2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
··· 225 225 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 226 226 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; 227 227 228 + r = amdgpu_vcn_ras_sw_init(adev); 229 + if (r) 230 + return r; 231 + 228 232 return 0; 229 233 } 230 234 ··· 2035 2031 default: 2036 2032 break; 2037 2033 } 2038 - 2039 - amdgpu_vcn_set_ras_funcs(adev); 2040 2034 }
+4 -2
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
··· 181 181 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 182 182 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 183 183 184 + r = amdgpu_vcn_ras_sw_init(adev); 185 + if (r) 186 + return r; 187 + 184 188 return 0; 185 189 } 186 190 ··· 2127 2123 default: 2128 2124 break; 2129 2125 } 2130 - 2131 - amdgpu_vcn_set_ras_funcs(adev); 2132 2126 }