+1

drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c

reviewed

··· 503 503 unsigned int integer_bits, 504 504 unsigned int fractional_bits) 505 505 { 506 506 + (void)integer_bits; 506 507 struct fixed31_32 fixpt_value = dc_fixpt_from_int(int_value); 507 508 508 509 fixpt_value.value |= (long long)frac_value << (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);

+1

drivers/gpu/drm/amd/display/dc/basics/vector.c

reviewed

··· 56 56 void *initial_value, 57 57 uint32_t struct_size) 58 58 { 59 59 + (void)ctx; 59 60 uint32_t i; 60 61 61 62 vector->container = NULL;

+1

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

reviewed

··· 2696 2696 struct slot_layout_info *slot_layout_info, 2697 2697 unsigned int record_offset) 2698 2698 { 2699 2699 + (void)i; 2699 2700 unsigned int j; 2700 2701 struct bios_parser *bp; 2701 2702 ATOM_BRACKET_LAYOUT_RECORD *record;

+9

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

reviewed

··· 205 205 struct graphics_object_id object_id, uint32_t index, 206 206 struct graphics_object_id *src_object_id) 207 207 { 208 208 + (void)index; 208 209 struct bios_parser *bp = BP_FROM_DCB(dcb); 209 210 unsigned int i; 210 211 enum bp_result bp_result = BP_RESULT_BADINPUT; ··· 766 765 uint32_t device_tag_index, 767 766 struct connector_device_tag_info *info) 768 767 { 768 768 + (void)device_tag_index; 769 769 struct bios_parser *bp = BP_FROM_DCB(dcb); 770 770 struct atom_display_object_path_v2 *object; 771 771 ··· 811 809 uint32_t index, 812 810 struct spread_spectrum_info *ss_info) 813 811 { 812 812 + (void)index; 814 813 enum bp_result result = BP_RESULT_OK; 815 814 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 816 815 struct atom_smu_info_v3_3 *smu_info = NULL; ··· 900 897 uint32_t index, 901 898 struct spread_spectrum_info *ss_info) 902 899 { 900 900 + (void)index; 903 901 enum bp_result result = BP_RESULT_OK; 904 902 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 905 903 struct atom_smu_info_v3_1 *smu_info = NULL; ··· 981 977 uint32_t index, 982 978 struct spread_spectrum_info *ss_info) 983 979 { 980 980 + (void)index; 984 981 enum bp_result result = BP_RESULT_OK; 985 982 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 986 983 ··· 1609 1604 struct dc_bios *dcb, 1610 1605 enum as_signal_type signal) 1611 1606 { 1607 1607 + (void)dcb; 1608 1608 + (void)signal; 1612 1609 /* TODO: DAL2 atomfirmware implementation does not need this. 1613 1610 * why DAL3 need this? 1614 1611 */ ··· 3543 3536 struct dc_bios *dcb, 3544 3537 void *dst) 3545 3538 { 3539 3539 + (void)dcb; 3540 3540 + (void)dst; 3546 3541 // TODO: There is data bytes alignment issue, disable it for now. 3547 3542 return 0; 3548 3543 }

+2

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

reviewed

··· 783 783 struct bios_parser *bp, 784 784 struct bp_external_encoder_control *cntl) 785 785 { 786 786 + (void)bp; 787 787 + (void)cntl; 786 788 /* TODO */ 787 789 return BP_RESULT_OK; 788 790 }

+1

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

reviewed

··· 94 94 95 95 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 96 96 { 97 97 + (void)id; 97 98 /* On any ASIC after DCE80, we manually program the DIG_FE 98 99 * selection (see connect_dig_be_to_fe function of the link 99 100 * encoder), so translation should always return 0 (no FE).

+1

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

reviewed

··· 93 93 94 94 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 95 95 { 96 96 + (void)id; 96 97 /* On any ASIC after DCE80, we manually program the DIG_FE 97 98 * selection (see connect_dig_be_to_fe function of the link 98 99 * encoder), so translation should always return 0 (no FE).

+1

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

reviewed

··· 91 91 92 92 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 93 93 { 94 94 + (void)id; 94 95 /* On any ASIC after DCE80, we manually program the DIG_FE 95 96 * selection (see connect_dig_be_to_fe function of the link 96 97 * encoder), so translation should always return 0 (no FE).

+1

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

reviewed

··· 78 78 struct dc *dc, 79 79 struct dc_state *context) 80 80 { 81 81 + (void)dc; 81 82 int i, total_plane_count; 82 83 83 84 total_plane_count = 0;

+1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

reviewed

··· 521 521 struct pp_smu_funcs *pp_smu, 522 522 struct dccg *dccg) 523 523 { 524 524 + (void)pp_smu; 524 525 struct clk_state_registers_and_bypass s = { 0 }; 525 526 526 527 clk_mgr->base.ctx = ctx;

+3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

reviewed

··· 329 329 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 330 330 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 331 331 { 332 332 + (void)regs_and_bypass; 333 333 + (void)clk_mgr_base; 334 334 + (void)log_info; 332 335 return; 333 336 } 334 337

+3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

reviewed

··· 395 395 static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 396 396 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 397 397 { 398 398 + (void)regs_and_bypass; 399 399 + (void)clk_mgr_base; 400 400 + (void)log_info; 398 401 return; 399 402 } 400 403

+3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

reviewed

··· 247 247 static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 248 248 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 249 249 { 250 250 + (void)regs_and_bypass; 251 251 + (void)clk_mgr_base; 252 252 + (void)log_info; 250 253 return; 251 254 } 252 255

+3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

reviewed

··· 255 255 static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 256 256 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 257 257 { 258 258 + (void)regs_and_bypass; 259 259 + (void)clk_mgr_base; 260 260 + (void)log_info; 258 261 return; 259 262 } 260 263

+2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

reviewed

··· 872 872 static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 873 873 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 874 874 { 875 875 + (void)log_info; 875 876 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 876 877 uint32_t dprefclk_did = 0; 877 878 uint32_t dcfclk_did = 0; ··· 1146 1145 struct pp_smu_funcs *pp_smu, 1147 1146 struct dccg *dccg) 1148 1147 { 1148 1148 + (void)pp_smu; 1149 1149 struct clk_log_info log_info = {0}; 1150 1150 1151 1151 clk_mgr->base.ctx = ctx;

+3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

reviewed

··· 333 333 static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 334 334 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 335 335 { 336 336 + (void)log_info; 336 337 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 337 338 uint32_t dprefclk_did = 0; 338 339 uint32_t dcfclk_did = 0; ··· 526 525 struct dc_state *context, 527 526 int ref_dtbclk_khz) 528 527 { 528 528 + (void)ref_dtbclk_khz; 529 529 int i; 530 530 struct dccg *dccg = clk_mgr->dccg; 531 531 struct pipe_ctx *otg_master; ··· 616 614 struct clk_mgr_internal *clk_mgr, 617 615 struct dc_state *context) 618 616 { 617 617 + (void)context; 619 618 uint32_t new_disp_divider = 0; 620 619 uint32_t new_dispclk_wdivider = 0; 621 620 uint32_t dentist_dispclk_wdivider_readback = 0;

+5

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

reviewed

··· 158 158 struct dc_state *context, 159 159 int ref_dtbclk_khz) 160 160 { 161 161 + (void)clk_mgr; 162 162 + (void)context; 163 163 + (void)ref_dtbclk_khz; 161 164 /* DCN42 does not implement set_dtbclk_dto function, so this is a no-op */ 162 165 } 163 166 ··· 838 835 839 836 void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base) 840 837 { 838 838 + (void)clk_mgr_base; 841 839 842 840 } 843 841 ··· 941 937 942 938 int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) 943 939 { 940 940 + (void)clk_mgr_base; 944 941 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 945 942 uint32_t dispclk_wdivider; 946 943 int disp_divider;

+12

drivers/gpu/drm/amd/display/dc/core/dc.c

reviewed

··· 1134 1134 struct dc_stream_state *stream, 1135 1135 struct dc_state *context) 1136 1136 { 1137 1137 + (void)dc; 1138 1138 + (void)context; 1137 1139 int i; 1138 1140 1139 1141 for (i = 0; i < stream->num_wb_info; i++) ··· 1147 1145 struct dc_stream_state *stream, 1148 1146 bool lock) 1149 1147 { 1148 1148 + (void)dc; 1149 1149 + (void)context; 1150 1150 int i; 1151 1151 1152 1152 /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */ ··· 3011 3007 */ 3012 3008 static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_update *updates, int surface_count) 3013 3009 { 3010 3010 + (void)dc; 3014 3011 bool has_flip_immediate_plane = false; 3015 3012 int i; 3016 3013 ··· 3290 3285 struct dc_stream_state *stream, 3291 3286 struct dc_stream_update *update) 3292 3287 { 3288 3288 + (void)context; 3293 3289 struct dc_context *dc_ctx = dc->ctx; 3294 3290 3295 3291 if (update == NULL || stream == NULL) ··· 3895 3889 3896 3890 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream) 3897 3891 { 3892 3892 + (void)dc; 3898 3893 if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 3899 3894 || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) 3900 3895 && stream->ctx->dce_version >= DCN_VERSION_3_1) ··· 4696 4689 int surface_count, 4697 4690 bool *is_plane_addition) 4698 4691 { 4692 4692 + (void)srf_updates; 4699 4693 4700 4694 struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream); 4701 4695 bool force_minimal_pipe_splitting = false; ··· 5551 5543 struct dc_stream_update *stream_update, 5552 5544 struct dc_state *state) 5553 5545 { 5546 5546 + (void)state; 5554 5547 bool ret = false; 5555 5548 5556 5549 dc_exit_ips_for_hw_access(dc); ··· 5861 5852 5862 5853 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz) 5863 5854 { 5855 5855 + (void)apply; 5864 5856 struct dc_state *context = dc->current_state; 5865 5857 struct hubp *hubp; 5866 5858 struct pipe_ctx *pipe; ··· 6536 6526 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 6537 6527 bool powerOn) 6538 6528 { 6529 6529 + (void)dc; 6539 6530 if (edp_link->connector_signal != SIGNAL_TYPE_EDP) 6540 6531 return; 6541 6532 ··· 6663 6652 void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, 6664 6653 struct power_features *out_data) 6665 6654 { 6655 6655 + (void)primary_otg_inst; 6666 6656 out_data->uclk_p_state = dc->current_state->clk_mgr->clks.p_state_change_support; 6667 6657 out_data->fams = dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; 6668 6658 }

+1

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

reviewed

··· 249 249 enum dc_color_space colorspace, 250 250 struct tg_color *black_color) 251 251 { 252 252 + (void)dc; 252 253 switch (colorspace) { 253 254 case COLOR_SPACE_YCBCR601: 254 255 case COLOR_SPACE_YCBCR709:

+7

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

reviewed

··· 1748 1748 const struct dc *dc, 1749 1749 struct dc_state *context) 1750 1750 { 1751 1751 + (void)dc; 1751 1752 int i; 1752 1753 1753 1754 for (i = 0; i < MAX_PIPES; i++) { ··· 1826 1825 struct resource_context *new_res_ctx, 1827 1826 const struct pipe_ctx *cur_otg_master) 1828 1827 { 1828 1828 + (void)cur_res_ctx; 1829 1829 const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe; 1830 1830 struct pipe_ctx *new_pipe; 1831 1831 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; ··· 1848 1846 struct resource_context *new_res_ctx, 1849 1847 const struct pipe_ctx *cur_opp_head) 1850 1848 { 1849 1849 + (void)cur_res_ctx; 1851 1850 const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe; 1852 1851 struct pipe_ctx *new_pipe; 1853 1852 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; ··· 2944 2941 const struct resource_pool *pool, 2945 2942 struct dc_stream_state *stream) 2946 2943 { 2944 2944 + (void)pool; 2947 2945 struct dc *dc = stream->ctx->dc; 2948 2946 2949 2947 return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); ··· 3027 3023 struct dc_plane_state *plane_state, 3028 3024 struct dc_state *context) 3029 3025 { 3026 3026 + (void)context; 3030 3027 struct pipe_ctx *opp_head_pipe = otg_master_pipe; 3031 3028 3032 3029 while (opp_head_pipe) { ··· 3620 3615 const struct resource_pool *pool, 3621 3616 struct dc_stream_state *stream) 3622 3617 { 3618 3618 + (void)stream; 3623 3619 int i; 3624 3620 3625 3621 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { ··· 3640 3634 enum engine_id id, 3641 3635 enum dce_version dc_version) 3642 3636 { 3637 3637 + (void)dc_version; 3643 3638 int i, available_audio_count; 3644 3639 3645 3640 if (id == ENGINE_ID_UNKNOWN)

+2

drivers/gpu/drm/amd/display/dc/core/dc_state.c

reviewed

··· 409 409 struct dc_state *state, 410 410 struct dc_stream_state *stream) 411 411 { 412 412 + (void)dc; 412 413 enum dc_status res; 413 414 414 415 DC_LOGGER_INIT(dc->ctx->logger); ··· 785 784 struct dc_state *state, 786 785 struct dc_plane_state *main_plane) 787 786 { 787 787 + (void)main_plane; 788 788 struct dc_plane_state *phantom_plane = dc_create_plane_state(dc); 789 789 790 790 DC_LOGGER_INIT(dc->ctx->logger);

+1

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

reviewed

··· 57 57 58 58 void dc_plane_destruct(struct dc_plane_state *plane_state) 59 59 { 60 60 + (void)plane_state; 60 61 // no more pointers to free within dc_plane_state 61 62 } 62 63

+1

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

reviewed

··· 1085 1085 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 1086 1086 const struct hubp *hubp, const struct dpp *dpp) 1087 1087 { 1088 1088 + (void)p_idx; 1088 1089 /* Hubp */ 1089 1090 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 1090 1091 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;

+1

drivers/gpu/drm/amd/display/dc/dc_helper.c

reviewed

··· 108 108 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 109 109 va_list ap) 110 110 { 111 111 + (void)addr; 111 112 uint32_t shift, mask, field_value; 112 113 int i = 1; 113 114

+2

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

reviewed

··· 165 165 int otg_inst, 166 166 int dp_hpo_inst) 167 167 { 168 168 + (void)dp_hpo_inst; 168 169 if (src == REFCLK) 169 170 dccg31_disable_dpstreamclk(dccg, otg_inst); 170 171 else ··· 645 644 unsigned int xtalin_freq_inKhz, 646 645 unsigned int *dccg_ref_freq_inKhz) 647 646 { 647 647 + (void)dccg; 648 648 /* 649 649 * Assume refclk is sourced from xtalin 650 650 * expect 24MHz

+1

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

reviewed

··· 265 265 unsigned int xtalin_freq_inKhz, 266 266 unsigned int *dccg_ref_freq_inKhz) 267 267 { 268 268 + (void)dccg; 268 269 /* 269 270 * Assume refclk is sourced from xtalin 270 271 * expect 100MHz

+2

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

reviewed

··· 558 558 static int 559 559 dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst) 560 560 { 561 561 + (void)symclk_32_se_inst; 561 562 uint32_t en; 562 563 uint32_t src_sel; 563 564 ··· 2374 2373 uint32_t stream_enc_inst, 2375 2374 uint32_t link_enc_inst) 2376 2375 { 2376 2376 + (void)link_enc_inst; 2377 2377 dccg35_disable_symclk_fe_new(dccg, stream_enc_inst); 2378 2378 2379 2379 /* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock once PHY is turned off */

+4

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

reviewed

··· 161 161 enum pixel_rate_div tmds_div, 162 162 enum pixel_rate_div unused) 163 163 { 164 164 + (void)unused; 164 165 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 165 166 uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA; 166 167 uint32_t dp_dto_int; ··· 354 353 unsigned int xtalin_freq_inKhz, 355 354 unsigned int *dccg_ref_freq_inKhz) 356 355 { 356 356 + (void)dccg; 357 357 /* 358 358 * Assume refclk is sourced from xtalin 359 359 * expect 100MHz ··· 723 721 724 722 void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h) 725 723 { 724 724 + (void)num_slices_h; 726 725 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 727 726 728 727 switch (inst) { ··· 841 838 842 839 void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) 843 840 { 841 841 + (void)link_enc_inst; 844 842 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 845 843 846 844 switch (stream_enc_inst) {

+1

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

reviewed

··· 186 186 enum pixel_rate_div tmds_div, 187 187 enum pixel_rate_div unused) 188 188 { 189 189 + (void)unused; 189 190 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 190 191 uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA; 191 192 uint32_t dp_dto_int;

+1

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

reviewed

··· 57 57 58 58 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst) 59 59 { 60 60 + (void)panel_inst; 60 61 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 61 62 uint32_t rampingBoundary = 0xFFFF; 62 63

+3

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

reviewed

··· 350 350 uint32_t av_stream_map_lane_count, 351 351 uint32_t audio_sdp_overhead) 352 352 { 353 353 + (void)channel_count; 353 354 /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ 354 355 struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100); 355 356 struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( ··· 1028 1027 uint32_t actual_pixel_clock_100Hz, 1029 1028 struct azalia_clock_info *azalia_clock_info) 1030 1029 { 1030 1030 + (void)crtc_pixel_clock_100hz; 1031 1031 /* audio_dto_phase= 24 * 10,000; 1032 1032 * 24MHz in [100Hz] units */ 1033 1033 azalia_clock_info->audio_dto_phase = ··· 1045 1043 const struct audio_pll_info *pll_info, 1046 1044 struct azalia_clock_info *azalia_clock_info) 1047 1045 { 1046 1046 + (void)requested_pixel_clock_100Hz; 1048 1047 /* Reported dpDtoSourceClockInkhz value for 1049 1048 * DCE8 already adjusted for SS, do not need any 1050 1049 * adjustment here anymore

+4

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

reviewed

··· 539 539 struct pll_settings *pll_settings, 540 540 struct pixel_clk_params *pix_clk_params) 541 541 { 542 542 + (void)clk_src; 542 543 uint32_t actual_pixel_clock_100hz; 543 544 544 545 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz; ··· 848 847 enum dp_link_encoding encoding, 849 848 struct pll_settings *pll_settings) 850 849 { 850 850 + (void)encoding; 851 851 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 852 852 struct bp_pixel_clock_parameters bp_pc_params = {0}; 853 853 ··· 923 921 enum dp_link_encoding encoding, 924 922 struct pll_settings *pll_settings) 925 923 { 924 924 + (void)encoding; 926 925 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 927 926 struct bp_pixel_clock_parameters bp_pc_params = {0}; 928 927 ··· 1073 1070 enum dp_link_encoding encoding, 1074 1071 struct pll_settings *pll_settings) 1075 1072 { 1073 1073 + (void)encoding; 1076 1074 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1077 1075 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1078 1076 const struct pixel_rate_range_table_entry *e =

+1

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

reviewed

··· 71 71 72 72 static bool dce_dmcu_init(struct dmcu *dmcu) 73 73 { 74 74 + (void)dmcu; 74 75 // Do nothing 75 76 return true; 76 77 }

+1

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

reviewed

··· 31 31 size_t slave_address 32 32 ) 33 33 { 34 34 + (void)pool; 34 35 struct dc *dc = ddc->ctx->dc; 35 36 struct dc_bios *dcb = dc->ctx->dc_bios; 36 37 struct graphics_object_id id = {0};

+2

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

reviewed

··· 69 69 struct dce_i2c_hw *dce_i2c_hw, 70 70 uint8_t *returned_bytes) 71 71 { 72 72 + (void)returned_bytes; 72 73 uint32_t i2c_sw_status = 0; 73 74 uint32_t value = 74 75 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); ··· 632 631 struct i2c_command *cmd, 633 632 struct dce_i2c_hw *dce_i2c_hw) 634 633 { 634 634 + (void)ddc; 635 635 uint8_t index_of_payload = 0; 636 636 bool result; 637 637

+3

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

reviewed

··· 67 67 struct resource_pool *pool, 68 68 struct dce_i2c_sw *dce_i2c_sw) 69 69 { 70 70 + (void)pool; 70 71 dal_ddc_close(dce_i2c_sw->ddc); 71 72 dce_i2c_sw->ddc = NULL; 72 73 } ··· 77 76 struct ddc *ddc, 78 77 uint16_t clock_delay_div_4) 79 78 { 79 79 + (void)ctx; 80 80 uint32_t scl_retry = 0; 81 81 uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4; 82 82 ··· 471 469 struct i2c_command *cmd, 472 470 struct dce_i2c_sw *dce_i2c_sw) 473 471 { 472 472 + (void)ddc; 474 473 uint8_t index_of_payload = 0; 475 474 bool result; 476 475

+1

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

reviewed

··· 43 43 const struct dc_cursor_position *position, 44 44 const struct dc_cursor_mi_param *param) 45 45 { 46 46 + (void)param; 46 47 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 47 48 48 49 /* lock cursor registers */

+1

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

reviewed

··· 847 847 const struct dce110_link_encoder *enc110, 848 848 const struct dc_crtc_timing *crtc_timing) 849 849 { 850 850 + (void)enc110; 850 851 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 851 852 return false; 852 853

+4

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

reviewed

··· 317 317 struct dce_watermarks urgent, 318 318 uint32_t total_dest_line_time_ns) 319 319 { 320 320 + (void)stutter_enter; 320 321 struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); 321 322 uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; 322 323 ··· 371 370 struct dce_watermarks urgent, 372 371 uint32_t total_dest_line_time_ns) 373 372 { 373 373 + (void)stutter_entry; 374 374 struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); 375 375 uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; 376 376 ··· 658 656 struct dc_plane_dcc_param *dcc, 659 657 bool horizontal_mirror) 660 658 { 659 659 + (void)dcc; 660 660 + (void)horizontal_mirror; 661 661 struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); 662 662 REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1); 663 663

+1

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

reviewed

··· 600 600 enum dc_color_depth color_dpth, 601 601 enum signal_type signal) 602 602 { 603 603 + (void)color_sp; 603 604 struct dce110_opp *opp110 = TO_DCE110_OPP(opp); 604 605 605 606 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,

+4

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

reviewed

··· 271 271 bool use_vsc_sdp_for_colorimetry, 272 272 uint32_t enable_sdp_splitting) 273 273 { 274 274 + (void)use_vsc_sdp_for_colorimetry; 275 275 + (void)enable_sdp_splitting; 274 276 uint32_t h_active_start; 275 277 uint32_t v_active_start; 276 278 uint32_t misc0 = 0; ··· 903 901 struct dc_link *link, 904 902 struct stream_encoder *enc) 905 903 { 904 904 + (void)link; 906 905 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 907 906 uint32_t reg1 = 0; 908 907 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; ··· 954 951 struct stream_encoder *enc, 955 952 const struct encoder_unblank_param *param) 956 953 { 954 954 + (void)link; 957 955 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 958 956 959 957 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {

+2

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

reviewed

··· 282 282 const struct scaler_data *data, 283 283 struct scl_ratios_inits *inits) 284 284 { 285 285 + (void)xfm_dce; 285 286 struct fixed31_32 h_init; 286 287 struct fixed31_32 v_init; 287 288 ··· 1241 1240 const struct out_csc_color_matrix *tbl_entry, 1242 1241 enum grph_color_adjust_option options) 1243 1242 { 1243 1243 + (void)options; 1244 1244 { 1245 1245 REG_SET_2(OUTPUT_CSC_C11_C12, 0, 1246 1246 OUTPUT_CSC_C11, tbl_entry->regval[0],

+1

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

reviewed

··· 173 173 unsigned int controller_id, 174 174 unsigned int panel_inst) 175 175 { 176 176 + (void)controller_id; 176 177 bool ret = false; 177 178 unsigned int feature_support; 178 179

+1

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

reviewed

··· 188 188 189 189 bool dmub_abm_set_pause(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int stream_inst) 190 190 { 191 191 + (void)stream_inst; 191 192 union dmub_rb_cmd cmd; 192 193 struct dc_context *dc = abm->ctx; 193 194 uint8_t panel_mask = 0x01 << panel_inst;

+1

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

reviewed

··· 216 216 uint8_t panel_inst, 217 217 uint16_t frame_skip_number) 218 218 { 219 219 + (void)panel_inst; 219 220 union dmub_rb_cmd cmd; 220 221 struct dc_context *dc = dmub->ctx; 221 222 struct dmub_rb_cmd_replay_set_coasting_vtotal *pCmd = NULL;

+10

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

reviewed

··· 40 40 struct dce_mem_input *mem_input110, 41 41 bool immediate) 42 42 { 43 43 + (void)immediate; 43 44 uint32_t value = 0; 44 45 45 46 value = dm_read_reg( ··· 166 165 const struct dc_tiling_info *info, 167 166 const enum surface_pixel_format pixel_format) 168 167 { 168 168 + (void)pixel_format; 169 169 uint32_t value = 0; 170 170 171 171 set_reg_field_value(value, info->gfx8.num_banks, ··· 644 642 struct dc_plane_dcc_param *dcc, 645 643 bool horizotal_mirror) 646 644 { 645 645 + (void)dcc; 646 646 + (void)horizotal_mirror; 647 647 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input); 648 648 649 649 enable(mem_input110); ··· 931 927 struct dce_watermarks urgent, 932 928 uint32_t total_dest_line_time_ns) 933 929 { 930 930 + (void)stutter_enter; 934 931 program_urgency_watermark_l( 935 932 mem_input->ctx, 936 933 urgent, ··· 975 970 uint32_t pix_clk_khz,/* for current stream */ 976 971 uint32_t total_stream_num) 977 972 { 973 973 + (void)h_total; 974 974 + (void)v_total; 975 975 + (void)total_stream_num; 978 976 uint32_t addr; 979 977 uint32_t value; 980 978 uint32_t pix_dur; ··· 1017 1009 struct mem_input *mi, 1018 1010 uint32_t total_stream_num) 1019 1011 { 1012 1012 + (void)mi; 1013 1013 + (void)total_stream_num; 1020 1014 } 1021 1015 1022 1016 static const struct mem_input_funcs dce110_mem_input_v_funcs = {

+1

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

reviewed

··· 110 110 const struct out_csc_color_matrix *tbl_entry, 111 111 enum grph_color_adjust_option options) 112 112 { 113 113 + (void)options; 113 114 struct dc_context *ctx = xfm_dce->base.ctx; 114 115 uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); 115 116 bool use_set_a = (get_reg_field_value(cntl_value,

+2

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

reviewed

··· 551 551 struct transform *xfm, 552 552 enum opp_regamma mode) 553 553 { 554 554 + (void)xfm; 555 555 + (void)mode; 554 556 // TODO: need to implement the function 555 557 }

+9

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

reviewed

··· 66 66 struct timing_generator *tg, 67 67 struct dc_crtc_timing *timing) 68 68 { 69 69 + (void)tg; 69 70 if (timing->flags.INTERLACE == 1) { 70 71 if (timing->v_front_porch < 2) 71 72 timing->v_front_porch = 2; ··· 1116 1115 const struct dc_crtc_timing *timing, 1117 1116 enum signal_type signal) 1118 1117 { 1118 1118 + (void)signal; 1119 1119 uint32_t h_blank; 1120 1120 uint32_t h_back_porch, hsync_offset, h_sync_start; 1121 1121 ··· 1492 1490 struct timing_generator *tg, 1493 1491 int source_tg_inst) 1494 1492 { 1493 1493 + (void)source_tg_inst; 1495 1494 uint32_t value; 1496 1495 uint32_t rising_edge = 0; 1497 1496 uint32_t falling_edge = 0; ··· 1962 1959 const enum signal_type signal, 1963 1960 bool use_vbios) 1964 1961 { 1962 1962 + (void)vready_offset; 1963 1963 + (void)vstartup_start; 1964 1964 + (void)vupdate_offset; 1965 1965 + (void)vupdate_width; 1966 1966 + (void)pstate_keepout; 1967 1967 + (void)signal; 1965 1968 if (use_vbios) 1966 1969 dce110_timing_generator_program_timing_generator(tg, timing); 1967 1970 else

+9

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

reviewed

··· 442 442 const enum signal_type signal, 443 443 bool use_vbios) 444 444 { 445 445 + (void)vready_offset; 446 446 + (void)vstartup_start; 447 447 + (void)vupdate_offset; 448 448 + (void)vupdate_width; 449 449 + (void)pstate_keepout; 450 450 + (void)signal; 445 451 if (use_vbios) 446 452 dce110_timing_generator_program_timing_generator(tg, timing); 447 453 else ··· 627 621 struct timing_generator *tg, 628 622 const struct dcp_gsl_params *gsl_params) 629 623 { 624 624 + (void)gsl_params; 630 625 DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n"); 631 626 return; 632 627 } ··· 636 629 struct timing_generator *tg, 637 630 int source_tg_inst) 638 631 { 632 632 + (void)source_tg_inst; 639 633 DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n"); 640 634 return; 641 635 } ··· 658 650 static void dce110_timing_generator_v_disable_vga( 659 651 struct timing_generator *tg) 660 652 { 653 653 + (void)tg; 661 654 return; 662 655 } 663 656

+6

drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c

reviewed

··· 371 371 struct rect *luma_viewport, 372 372 struct rect *chroma_viewport) 373 373 { 374 374 + (void)xfm_dce; 375 375 + (void)luma_viewport; 376 376 + (void)chroma_viewport; 374 377 inits->h_int_scale_ratio_luma = 375 378 dc_fixpt_u2d19(data->ratios.horz) << 5; 376 379 inits->v_int_scale_ratio_luma = ··· 622 619 struct transform *xfm, 623 620 const struct xfm_grph_csc_adjustment *adjust) 624 621 { 622 622 + (void)xfm; 623 623 + (void)adjust; 625 624 /* DO NOTHING*/ 626 625 } 627 626 ··· 632 627 enum lb_pixel_depth depth, 633 628 const struct bit_depth_reduction_params *bit_depth_params) 634 629 { 630 630 + (void)bit_depth_params; 635 631 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 636 632 int pixel_depth = 0; 637 633 int expan_mode = 0;

+1

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

reviewed

··· 284 284 struct dce112_compressor *cp110, 285 285 uint32_t pixels) 286 286 { 287 287 + (void)cp110; 287 288 return 256 * ((pixels + 255) / 256); 288 289 } 289 290

+7

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

reviewed

··· 304 304 struct timing_generator *tg, 305 305 int source) 306 306 { 307 307 + (void)source; 307 308 enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO; 308 309 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); 309 310 uint32_t rising_edge = 0; ··· 702 701 const enum signal_type signal, 703 702 bool use_vbios) 704 703 { 704 704 + (void)vready_offset; 705 705 + (void)vstartup_start; 706 706 + (void)vupdate_offset; 707 707 + (void)vupdate_width; 708 708 + (void)pstate_keepout; 709 709 + (void)signal; 705 710 if (use_vbios) 706 711 dce110_timing_generator_program_timing_generator(tg, timing); 707 712 else

+6

drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c

reviewed

··· 115 115 const enum signal_type signal, 116 116 bool use_vbios) 117 117 { 118 118 + (void)vready_offset; 119 119 + (void)vstartup_start; 120 120 + (void)vupdate_offset; 121 121 + (void)vupdate_width; 122 122 + (void)pstate_keepout; 123 123 + (void)signal; 118 124 if (!use_vbios) 119 125 program_pix_dur(tg, timing->pix_clk_100hz); 120 126

+2

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

reviewed

··· 44 44 45 45 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) 46 46 { 47 47 + (void)dwbc; 47 48 if (caps) { 48 49 caps->adapter_id = 0; /* we only support 1 adapter currently */ 49 50 caps->hw_version = DCN_VERSION_1_0; ··· 64 63 65 64 static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params) 66 65 { 66 66 + (void)params; 67 67 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); 68 68 69 69 /* disable first. */

+1

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

reviewed

··· 77 77 unsigned int az_inst, 78 78 struct audio_info *audio_info) 79 79 { 80 80 + (void)az_inst; 80 81 struct dcn31_apg *apg31 = DCN31_APG_FROM_APG(apg); 81 82 82 83 ASSERT(audio_info);

+2

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

reviewed

··· 249 249 bool use_vsc_sdp_for_colorimetry, 250 250 uint32_t enable_sdp_splitting) 251 251 { 252 252 + (void)enable_sdp_splitting; 252 253 uint32_t h_active_start; 253 254 uint32_t v_active_start; 254 255 uint32_t misc0 = 0; ··· 784 783 const uint8_t *custom_sdp_message, 785 784 unsigned int sdp_message_size) 786 785 { 786 786 + (void)sdp_message_size; 787 787 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 788 788 uint32_t value = 0; 789 789

+2

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

reviewed

··· 394 394 uint32_t dsc_bytes_per_pixel, 395 395 uint32_t dsc_slice_width) 396 396 { 397 397 + (void)dsc_bytes_per_pixel; 398 398 + (void)dsc_slice_width; 397 399 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 398 400 399 401 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

+2

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

reviewed

··· 356 356 uint32_t dsc_bytes_per_pixel, 357 357 uint32_t dsc_slice_width) 358 358 { 359 359 + (void)dsc_bytes_per_pixel; 360 360 + (void)dsc_slice_width; 359 361 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 360 362 361 363 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

+1

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

reviewed

··· 369 369 uint32_t stream_enc_inst, 370 370 uint32_t link_enc_inst) 371 371 { 372 372 + (void)stream_enc_inst; 372 373 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 373 374 374 375 ASSERT(stream_enc_inst < 5 && link_enc_inst < 5);

+3

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

reviewed

··· 57 57 struct stream_encoder *enc, 58 58 bool odm_combine) 59 59 { 60 60 + (void)enc; 61 61 + (void)odm_combine; 60 62 } 61 63 62 64 /* setup stream encoder in dvi mode */ ··· 712 710 uint32_t stream_enc_inst, 713 711 uint32_t link_enc_inst) 714 712 { 713 713 + (void)stream_enc_inst; 715 714 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 716 715 717 716 REG_UPDATE(STREAM_MAPPER_CONTROL,

+53 -12

drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c

reviewed

··· 30 30 31 31 static bool virtual_link_encoder_validate_output_with_stream( 32 32 struct link_encoder *enc, 33 33 - const struct dc_stream_state *stream) { return true; } 33 33 + const struct dc_stream_state *stream) { 34 34 + (void)enc; 35 35 + (void)stream; 36 36 + return true; 37 37 + } 34 38 35 35 - static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} 39 39 + static void virtual_link_encoder_hw_init(struct link_encoder *enc) 40 40 + { 41 41 + (void)enc; 42 42 + } 36 43 37 44 static void virtual_link_encoder_setup( 38 38 - struct link_encoder *enc, 39 39 - enum signal_type signal) {} 45 45 + struct link_encoder *enc, enum signal_type signal) { 46 46 + (void)enc; 47 47 + (void)signal; 48 48 + } 40 49 41 50 static void virtual_link_encoder_enable_tmds_output( 42 51 struct link_encoder *enc, 43 52 enum clock_source_id clock_source, 44 53 enum dc_color_depth color_depth, 45 54 enum signal_type signal, 46 46 - uint32_t pixel_clock) {} 55 55 + uint32_t pixel_clock) { 56 56 + (void)enc; 57 57 + (void)clock_source; 58 58 + (void)color_depth; 59 59 + (void)signal; 60 60 + (void)pixel_clock; 61 61 + } 47 62 48 63 static void virtual_link_encoder_enable_dp_output( 49 64 struct link_encoder *enc, 50 65 const struct dc_link_settings *link_settings, 51 51 - enum clock_source_id clock_source) {} 66 66 + enum clock_source_id clock_source) { 67 67 + (void)enc; 68 68 + (void)link_settings; 69 69 + (void)clock_source; 70 70 + } 52 71 53 72 static void virtual_link_encoder_enable_dp_mst_output( 54 73 struct link_encoder *enc, 55 74 const struct dc_link_settings *link_settings, 56 56 - enum clock_source_id clock_source) {} 75 75 + enum clock_source_id clock_source) { 76 76 + (void)enc; 77 77 + (void)link_settings; 78 78 + (void)clock_source; 79 79 + } 57 80 58 81 static void virtual_link_encoder_disable_output( 59 82 struct link_encoder *link_enc, 60 60 - enum signal_type signal) {} 83 83 + enum signal_type signal) { 84 84 + (void)link_enc; 85 85 + (void)signal; 86 86 + } 61 87 62 88 static void virtual_link_encoder_dp_set_lane_settings( 63 89 struct link_encoder *enc, 64 90 const struct dc_link_settings *link_settings, 65 65 - const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {} 91 91 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) { 92 92 + (void)enc; 93 93 + (void)link_settings; 94 94 + (void)lane_settings; 95 95 + } 66 96 67 97 static void virtual_link_encoder_dp_set_phy_pattern( 68 98 struct link_encoder *enc, 69 69 - const struct encoder_set_dp_phy_pattern_param *param) {} 99 99 + const struct encoder_set_dp_phy_pattern_param *param) { 100 100 + (void)enc; 101 101 + (void)param; 102 102 + } 70 103 71 104 static void virtual_link_encoder_update_mst_stream_allocation_table( 72 105 struct link_encoder *enc, 73 73 - const struct link_mst_stream_allocation_table *table) {} 106 106 + const struct link_mst_stream_allocation_table *table) { 107 107 + (void)enc; 108 108 + (void)table; 109 109 + } 74 110 75 111 static void virtual_link_encoder_connect_dig_be_to_fe( 76 112 struct link_encoder *enc, 77 113 enum engine_id engine, 78 78 - bool connect) {} 114 114 + bool connect) { 115 115 + (void)enc; 116 116 + (void)engine; 117 117 + (void)connect; 118 118 + } 79 119 80 120 static void virtual_link_encoder_destroy(struct link_encoder **enc) 81 121 { ··· 126 86 static void virtual_link_encoder_get_max_link_cap(struct link_encoder *enc, 127 87 struct dc_link_settings *link_settings) 128 88 { 89 89 + (void)enc; 129 90 /* Set Default link settings */ 130 91 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, 131 92 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};

+79 -32

drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c

reviewed

··· 31 31 struct dc_crtc_timing *crtc_timing, 32 32 enum dc_color_space output_color_space, 33 33 bool use_vsc_sdp_for_colorimetry, 34 34 - uint32_t enable_sdp_splitting) {} 34 34 + uint32_t enable_sdp_splitting) { 35 35 + (void)enc; 36 36 + (void)crtc_timing; 37 37 + (void)output_color_space; 38 38 + (void)use_vsc_sdp_for_colorimetry; 39 39 + (void)enable_sdp_splitting; 40 40 + } 35 41 36 42 static void virtual_stream_encoder_hdmi_set_stream_attribute( 37 43 struct stream_encoder *enc, 38 44 struct dc_crtc_timing *crtc_timing, 39 45 int actual_pix_clk_khz, 40 40 - bool enable_audio) {} 46 46 + bool enable_audio) { 47 47 + (void)enc; 48 48 + (void)crtc_timing; 49 49 + (void)actual_pix_clk_khz; 50 50 + (void)enable_audio; 51 51 + } 41 52 42 53 static void virtual_stream_encoder_dvi_set_stream_attribute( 43 54 struct stream_encoder *enc, 44 55 struct dc_crtc_timing *crtc_timing, 45 45 - bool is_dual_link) {} 56 56 + bool is_dual_link) { 57 57 + (void)enc; 58 58 + (void)crtc_timing; 59 59 + (void)is_dual_link; 60 60 + } 46 61 47 62 static void virtual_stream_encoder_set_throttled_vcp_size( 48 63 struct stream_encoder *enc, 49 49 - struct fixed31_32 avg_time_slots_per_mtp) 50 50 - {} 64 64 + struct fixed31_32 avg_time_slots_per_mtp) { 65 65 + (void)enc; 66 66 + (void)avg_time_slots_per_mtp; 67 67 + } 51 68 52 69 static void virtual_stream_encoder_update_hdmi_info_packets( 53 70 struct stream_encoder *enc, 54 54 - const struct encoder_info_frame *info_frame) {} 71 71 + const struct encoder_info_frame *info_frame) { 72 72 + (void)enc; 73 73 + (void)info_frame; 74 74 + } 55 75 56 76 static void virtual_stream_encoder_stop_hdmi_info_packets( 57 57 - struct stream_encoder *enc) {} 77 77 + struct stream_encoder *enc) { 78 78 + (void)enc; 79 79 + } 58 80 59 81 static void virtual_stream_encoder_set_avmute( 60 60 - struct stream_encoder *enc, 61 61 - bool enable) {} 82 82 + struct stream_encoder *enc, bool enable) { 83 83 + (void)enc; 84 84 + (void)enable; 85 85 + } 62 86 static void virtual_stream_encoder_update_dp_info_packets( 63 87 struct stream_encoder *enc, 64 64 - const struct encoder_info_frame *info_frame) {} 88 88 + const struct encoder_info_frame *info_frame) { 89 89 + (void)enc; 90 90 + (void)info_frame; 91 91 + } 65 92 66 93 static void virtual_stream_encoder_stop_dp_info_packets( 67 67 - struct stream_encoder *enc) {} 94 94 + struct stream_encoder *enc) { 95 95 + (void)enc; 96 96 + } 68 97 69 98 static void virtual_stream_encoder_dp_blank( 70 99 struct dc_link *link, 71 71 - struct stream_encoder *enc) {} 100 100 + struct stream_encoder *enc) { 101 101 + (void)link; 102 102 + (void)enc; 103 103 + } 72 104 73 105 static void virtual_stream_encoder_dp_unblank( 74 106 struct dc_link *link, 75 107 struct stream_encoder *enc, 76 76 - const struct encoder_unblank_param *param) {} 108 108 + const struct encoder_unblank_param *param) { 109 109 + (void)enc; 110 110 + (void)link; 111 111 + (void)param; 112 112 + } 77 113 78 114 static void virtual_audio_mute_control( 79 79 - struct stream_encoder *enc, 80 80 - bool mute) {} 115 115 + struct stream_encoder *enc, bool mute) { 116 116 + (void)enc; 117 117 + (void)mute; 118 118 + } 81 119 82 120 static void virtual_stream_encoder_reset_hdmi_stream_attribute( 83 83 - struct stream_encoder *enc) 84 84 - {} 121 121 + struct stream_encoder *enc) 122 122 + { 123 123 + (void)enc; 124 124 + } 85 125 86 126 static void virtual_enc_dp_set_odm_combine( 87 87 - struct stream_encoder *enc, 88 88 - bool odm_combine) 89 89 - {} 127 127 + struct stream_encoder *enc, bool odm_combine) { 128 128 + (void)enc; 129 129 + (void)odm_combine; 130 130 + } 90 131 91 132 static void virtual_dig_connect_to_otg( 92 92 - struct stream_encoder *enc, 93 93 - int tg_inst) 94 94 - {} 133 133 + struct stream_encoder *enc, int tg_inst) { 134 134 + (void)enc; 135 135 + (void)tg_inst; 136 136 + } 95 137 96 138 static void virtual_setup_stereo_sync( 97 97 - struct stream_encoder *enc, 98 98 - int tg_inst, 99 99 - bool enable) 100 100 - {} 139 139 + struct stream_encoder *enc, 140 140 + int tg_inst, bool enable) { 141 141 + (void)enc; 142 142 + (void)tg_inst; 143 143 + (void)enable; 144 144 + } 101 145 102 146 static void virtual_stream_encoder_set_dsc_pps_info_packet( 103 103 - struct stream_encoder *enc, 104 104 - bool enable, 105 105 - uint8_t *dsc_packed_pps, 106 106 - bool immediate_update) 107 107 - {} 147 147 + struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, 148 148 + bool immediate_update) 149 149 + { 150 150 + (void)enc; 151 151 + (void)enable; 152 152 + (void)dsc_packed_pps; 153 153 + (void)immediate_update; 154 154 + } 108 155 109 156 static const struct stream_encoder_funcs virtual_str_enc_funcs = { 110 157 .dp_set_odm_combine =

+1

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

reviewed

··· 525 525 struct pipe_ctx *primary_pipe, 526 526 struct pipe_ctx *secondary_pipe) 527 527 { 528 528 + (void)res_ctx; 528 529 int pipe_idx = secondary_pipe->pipe_idx; 529 530 530 531 if (!primary_pipe->plane_state)

+1

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

reviewed

··· 1316 1316 display_e2e_pipe_params_st *pipes, 1317 1317 enum dc_validate_mode validate_mode) 1318 1318 { 1319 1319 + (void)validate_mode; 1319 1320 int pipe_cnt, i; 1320 1321 bool synchronized_vblank = true; 1321 1322 struct resource_context *res_ctx = &context->res_ctx;

+4

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

reviewed

··· 501 501 double *VUpdateWidthPix, 502 502 double *VReadyOffsetPix) 503 503 { 504 504 + (void)mode_lib; 505 505 + 504 506 bool MyError = false; 505 507 unsigned int DPPCycles, DISPCLKCycles; 506 508 double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime; ··· 880 878 unsigned int *dpte_row_height, 881 879 unsigned int *meta_row_height) 882 880 { 881 881 + (void)ViewportWidth; 883 882 unsigned int MetaRequestHeight; 884 883 unsigned int MetaRequestWidth; 885 884 unsigned int MetaSurfWidth; ··· 2956 2953 double *TInitXFill, 2957 2954 double *TslvChk) 2958 2955 { 2956 2956 + (void)mode_lib; 2959 2957 double TSlvSetup, AvgfillRate, result; 2960 2958 2961 2959 *SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;

+5

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

reviewed

··· 495 495 double *DSTYAfterScaler 496 496 ) 497 497 { 498 498 + (void)ReturnBW; 498 499 unsigned int DPPCycles, DISPCLKCycles; 499 500 double DataFabricLineDeliveryTimeLuma; 500 501 double DataFabricLineDeliveryTimeChroma; ··· 593 592 double *VUpdateWidthPix, 594 593 double *VReadyOffsetPix) 595 594 { 595 595 + (void)mode_lib; 596 596 + 596 597 bool MyError = false; 597 598 double TotalRepeaterDelayTime; 598 599 double Tdm, LineTime, Tsetup; ··· 941 938 unsigned int *dpte_row_height, 942 939 unsigned int *meta_row_height) 943 940 { 941 941 + (void)ViewportWidth; 944 942 unsigned int MetaRequestHeight; 945 943 unsigned int MetaRequestWidth; 946 944 unsigned int MetaSurfWidth; ··· 3030 3026 double *TInitXFill, 3031 3027 double *TslvChk) 3032 3028 { 3029 3029 + (void)mode_lib; 3033 3030 double TSlvSetup, AvgfillRate, result; 3034 3031 3035 3032 *SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;

+5

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

reviewed

··· 126 126 unsigned int delivery_width, 127 127 unsigned int req_per_swath_ub) 128 128 { 129 129 + (void)mode_lib; 129 130 double refcyc_per_delivery = 0.0; 130 131 131 132 if (vratio <= 1.0) { ··· 1539 1538 const bool ignore_viewport_pos, 1540 1539 const bool immediate_flip_support) 1541 1540 { 1541 1541 + (void)vm_en; 1542 1542 + (void)ignore_viewport_pos; 1543 1543 + (void)immediate_flip_support; 1542 1544 display_rq_params_st rq_param = {0}; 1543 1545 display_dlg_sys_params_st dlg_sys_param = {0}; 1544 1546 ··· 1592 1588 unsigned int cur_width, 1593 1589 enum cursor_bpp cur_bpp) 1594 1590 { 1591 1591 + (void)mode_lib; 1595 1592 unsigned int cur_src_width = cur_width; 1596 1593 unsigned int cur_req_size = 0; 1597 1594 unsigned int cur_req_width = 0;

+5

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

reviewed

··· 126 126 unsigned int delivery_width, 127 127 unsigned int req_per_swath_ub) 128 128 { 129 129 + (void)mode_lib; 129 130 double refcyc_per_delivery = 0.0; 130 131 131 132 if (vratio <= 1.0) { ··· 1540 1539 const bool ignore_viewport_pos, 1541 1540 const bool immediate_flip_support) 1542 1541 { 1542 1542 + (void)vm_en; 1543 1543 + (void)ignore_viewport_pos; 1544 1544 + (void)immediate_flip_support; 1543 1545 display_rq_params_st rq_param = {0}; 1544 1546 display_dlg_sys_params_st dlg_sys_param = {0}; 1545 1547 ··· 1593 1589 unsigned int cur_width, 1594 1590 enum cursor_bpp cur_bpp) 1595 1591 { 1592 1592 + (void)mode_lib; 1596 1593 unsigned int cur_src_width = cur_width; 1597 1594 unsigned int cur_req_size = 0; 1598 1595 unsigned int cur_req_width = 0;

+19

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

reviewed

··· 695 695 double *VUpdateWidthPix, 696 696 double *VReadyOffsetPix) 697 697 { 698 698 + (void)mode_lib; 699 699 + (void)XFCEnabled; 700 700 + 698 701 bool MyError = false; 699 702 unsigned int DPPCycles, DISPCLKCycles; 700 703 double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime; ··· 1293 1290 unsigned int *DPDE0BytesFrame, 1294 1291 unsigned int *MetaPTEBytesFrame) 1295 1292 { 1293 1293 + (void)SourcePixelFormat; 1294 1294 + (void)ViewportWidth; 1296 1295 unsigned int MPDEBytesFrame; 1297 1296 unsigned int DCCMetaSurfaceBytes; 1298 1297 unsigned int MacroTileSizeBytes; ··· 3045 3040 double *TInitXFill, 3046 3041 double *TslvChk) 3047 3042 { 3043 3043 + (void)mode_lib; 3048 3044 double TSlvSetup, AvgfillRate, result; 3049 3045 3050 3046 *SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime; ··· 3193 3187 double *final_flip_bw, 3194 3188 bool *ImmediateFlipSupportedForPipe) 3195 3189 { 3190 3190 + (void)mode_lib; 3196 3191 double min_row_time = 0.0; 3197 3192 unsigned int HostVMDynamicLevels; 3198 3193 double TimeForFetchingMetaPTEImmediateFlip; ··· 5301 5294 double *StutterEnterPlusExitWatermark, 5302 5295 double *MinActiveDRAMClockChangeLatencySupported) 5303 5296 { 5297 5297 + (void)DPPCLK; 5298 5298 + (void)SwathWidthSingleDPPY; 5299 5299 + (void)DCFCLK; 5300 5300 + (void)UrgentOutOfOrderReturn; 5301 5301 + (void)ReturnBW; 5302 5302 + (void)GPUVMEnable; 5303 5303 + (void)dpte_group_bytes; 5304 5304 + (void)MetaChunkSize; 5305 5305 + 5304 5306 double EffectiveLBLatencyHidingY; 5305 5307 double EffectiveLBLatencyHidingC; 5306 5308 double DPPOutputBufferLinesY; ··· 5901 5885 double TimePerVMRequestVBlank[], 5902 5886 double TimePerVMRequestFlip[]) 5903 5887 { 5888 5888 + (void)VRatioPrefetchY; 5889 5889 + (void)VRatioPrefetchC; 5890 5890 + 5904 5891 unsigned int meta_chunk_width; 5905 5892 unsigned int min_meta_chunk_width; 5906 5893 unsigned int meta_chunk_per_row_int;

+5

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

reviewed

··· 102 102 unsigned int delivery_width, 103 103 unsigned int req_per_swath_ub) 104 104 { 105 105 + (void)mode_lib; 105 106 double refcyc_per_delivery = 0.0; 106 107 107 108 if (vratio <= 1.0) { ··· 1648 1647 const bool ignore_viewport_pos, 1649 1648 const bool immediate_flip_support) 1650 1649 { 1650 1650 + (void)vm_en; 1651 1651 + (void)ignore_viewport_pos; 1652 1652 + (void)immediate_flip_support; 1651 1653 display_rq_params_st rq_param = {0}; 1652 1654 display_dlg_sys_params_st dlg_sys_param = {0}; 1653 1655 ··· 1706 1702 unsigned int cur_width, 1707 1703 enum cursor_bpp cur_bpp) 1708 1704 { 1705 1705 + (void)mode_lib; 1709 1706 unsigned int cur_src_width = cur_width; 1710 1707 unsigned int cur_req_size = 0; 1711 1708 unsigned int cur_req_width = 0;

+2

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

reviewed

··· 571 571 unsigned int *dcfclk_mhz, 572 572 unsigned int *dram_speed_mts) 573 573 { 574 574 + (void)bw_params; 574 575 unsigned int i; 575 576 576 577 dc_assert_fp_enabled(); ··· 721 720 722 721 void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip) 723 722 { 723 723 + (void)dcn3_0_ip; 724 724 dc_assert_fp_enabled(); 725 725 726 726 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

+23

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

reviewed

··· 778 778 double *RequiredPrefetchPixDataBWChroma, 779 779 bool *NotEnoughTimeForDynamicMetadata) 780 780 { 781 781 + (void)SwathWidthY; 782 782 + (void)SwathWidthC; 781 783 struct vba_vars_st *v = &mode_lib->vba; 782 784 double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater; 783 785 bool MyError = false; ··· 1235 1233 unsigned int *IndependentBlockLuma, 1236 1234 unsigned int *IndependentBlockChroma) 1237 1235 { 1236 1236 + (void)SurfaceWidthChroma; 1237 1237 + (void)SurfaceHeightChroma; 1238 1238 + (void)BytePerPixelDETY; 1239 1239 + (void)BytePerPixelDETC; 1238 1240 int yuv420 = 0; 1239 1241 int horz_div_l = 0; 1240 1242 int horz_div_c = 0; ··· 1601 1595 unsigned int *DPDE0BytesFrame, 1602 1596 unsigned int *MetaPTEBytesFrame) 1603 1597 { 1598 1598 + (void)SourcePixelFormat; 1604 1599 unsigned int MPDEBytesFrame = 0; 1605 1600 unsigned int DCCMetaSurfaceBytes = 0; 1606 1601 unsigned int MacroTileSizeBytes = 0; ··· 3075 3068 unsigned int HTotal, 3076 3069 unsigned int WritebackLineBufferSize) 3077 3070 { 3071 3071 + (void)WritebackPixelFormat; 3072 3072 + (void)WritebackVRatio; 3078 3073 double DISPCLK_H = 0, DISPCLK_V = 0, DISPCLK_HB = 0; 3079 3074 3080 3075 DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; ··· 3095 3086 long WritebackSourceHeight, 3096 3087 unsigned int HTotal) 3097 3088 { 3089 3089 + (void)WritebackPixelFormat; 3090 3090 + (void)WritebackHRatio; 3098 3091 double CalculateWriteBackDelay = 0; 3099 3092 double Line_length = 0; 3100 3093 double Output_lines_last_notclamped = 0; ··· 3210 3199 double *final_flip_bw, 3211 3200 bool *ImmediateFlipSupportedForPipe) 3212 3201 { 3202 3202 + (void)mode_lib; 3203 3203 + (void)HostVMMinPageSize; 3213 3204 double min_row_time = 0.0; 3214 3205 unsigned int HostVMDynamicLevelsTrips = 0; 3215 3206 double TimeForFetchingMetaPTEImmediateFlip = 0; ··· 4981 4968 double BytePerPixelDETC[], 4982 4969 enum clock_change_support *DRAMClockChangeSupport) 4983 4970 { 4971 4971 + (void)DCFCLK; 4972 4972 + (void)ReturnBW; 4973 4973 + (void)DPPCLK; 4974 4974 + (void)DETBufferSizeC; 4984 4975 struct vba_vars_st *v = &mode_lib->vba; 4985 4976 double EffectiveLBLatencyHidingY = 0; 4986 4977 double EffectiveLBLatencyHidingC = 0; ··· 5229 5212 double *UrgentBurstFactorChroma, 5230 5213 bool *NotEnoughUrgentLatencyHiding) 5231 5214 { 5215 5215 + (void)DETBufferSizeInKByte; 5216 5216 + (void)VRatioC; 5232 5217 double LinesInDETLuma = 0; 5233 5218 double LinesInDETChroma = 0; 5234 5219 unsigned int LinesInCursorBuffer = 0; ··· 5594 5575 double TimePerVMRequestVBlank[], 5595 5576 double TimePerVMRequestFlip[]) 5596 5577 { 5578 5578 + (void)dpte_row_width_luma_ub; 5579 5579 + (void)dpte_row_width_chroma_ub; 5597 5580 int num_group_per_lower_vm_stage = 0; 5598 5581 int num_req_per_lower_vm_stage = 0; 5599 5582 unsigned int k; ··· 5878 5857 bool ViewportSizeSupportPerPlane[], 5879 5858 bool *ViewportSizeSupport) 5880 5859 { 5860 5860 + (void)HRatioChroma; 5881 5861 int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 }; 5882 5862 int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 }; 5883 5863 int MinimumSwathHeightY = 0; ··· 6061 6039 unsigned int swath_width_luma_ub[], 6062 6040 unsigned int swath_width_chroma_ub[]) 6063 6041 { 6042 6042 + (void)BytePerPixY; 6064 6043 unsigned int k, j; 6065 6044 long surface_width_ub_l; 6066 6045 long surface_height_ub_l;

+5

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

reviewed

··· 50 50 unsigned int delivery_width, 51 51 unsigned int req_per_swath_ub) 52 52 { 53 53 + (void)mode_lib; 53 54 double refcyc_per_delivery = 0.0; 54 55 55 56 if (vratio <= 1.0) { ··· 805 804 unsigned int cur_width, 806 805 enum cursor_bpp cur_bpp) 807 806 { 807 807 + (void)mode_lib; 808 808 unsigned int cur_src_width = cur_width; 809 809 unsigned int cur_req_size = 0; 810 810 unsigned int cur_req_width = 0; ··· 898 896 const bool ignore_viewport_pos, 899 897 const bool immediate_flip_support) 900 898 { 899 899 + (void)vm_en; 900 900 + (void)ignore_viewport_pos; 901 901 + (void)immediate_flip_support; 901 902 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 902 903 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 903 904 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;

+24

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

reviewed

··· 873 873 double *VUpdateWidthPix, 874 874 double *VReadyOffsetPix) 875 875 { 876 876 + (void)mode_lib; 877 877 + (void)HostVMMinPageSize; 878 878 + (void)SwathWidthY; 879 879 + (void)SwathWidthC; 880 880 + 876 881 bool MyError = false; 877 882 unsigned int DPPCycles, DISPCLKCycles; 878 883 double DSTTotalPixelsAfterScaler; ··· 1496 1491 unsigned int *IndependentBlockLuma, 1497 1492 unsigned int *IndependentBlockChroma) 1498 1493 { 1494 1494 + (void)SurfaceWidthChroma; 1495 1495 + (void)SurfaceHeightChroma; 1496 1496 + (void)BytePerPixelDETY; 1497 1497 + (void)BytePerPixelDETC; 1499 1498 int yuv420; 1500 1499 int horz_div_l; 1501 1500 int horz_div_c; ··· 1832 1823 int *DPDE0BytesFrame, 1833 1824 int *MetaPTEBytesFrame) 1834 1825 { 1826 1826 + (void)SourcePixelFormat; 1835 1827 struct vba_vars_st *v = &mode_lib->vba; 1836 1828 unsigned int MPDEBytesFrame; 1837 1829 unsigned int DCCMetaSurfaceBytes; ··· 3375 3365 unsigned int HTotal, 3376 3366 unsigned int WritebackLineBufferSize) 3377 3367 { 3368 3368 + (void)WritebackPixelFormat; 3369 3369 + (void)WritebackVRatio; 3378 3370 double DISPCLK_H, DISPCLK_V, DISPCLK_HB; 3379 3371 3380 3372 DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; ··· 3395 3383 int WritebackSourceHeight, 3396 3384 unsigned int HTotal) 3397 3385 { 3386 3386 + (void)WritebackPixelFormat; 3387 3387 + (void)WritebackHRatio; 3398 3388 double CalculateWriteBackDelay; 3399 3389 double Line_length; 3400 3390 double Output_lines_last_notclamped; ··· 5580 5566 double *Z8StutterExitWatermark, 5581 5567 double *Z8StutterEnterPlusExitWatermark) 5582 5568 { 5569 5569 + (void)DCFCLK; 5570 5570 + (void)ReturnBW; 5571 5571 + (void)DETBufferSizeC; 5583 5572 struct vba_vars_st *v = &mode_lib->vba; 5584 5573 double EffectiveLBLatencyHidingY; 5585 5574 double EffectiveLBLatencyHidingC; ··· 5848 5831 double *UrgentBurstFactorChroma, 5849 5832 bool *NotEnoughUrgentLatencyHiding) 5850 5833 { 5834 5834 + (void)VRatioC; 5851 5835 double LinesInDETLuma; 5852 5836 double LinesInDETChroma; 5853 5837 unsigned int LinesInCursorBuffer; ··· 6231 6213 double TimePerVMRequestVBlank[], 6232 6214 double TimePerVMRequestFlip[]) 6233 6215 { 6216 6216 + (void)dpte_row_width_luma_ub; 6217 6217 + (void)dpte_row_width_chroma_ub; 6234 6218 int num_group_per_lower_vm_stage; 6235 6219 int num_req_per_lower_vm_stage; 6236 6220 int k; ··· 6370 6350 int *Z8NumberOfStutterBurstsPerFrame, 6371 6351 double *StutterPeriod) 6372 6352 { 6353 6353 + (void)ConfigReturnBufferSizeInKByte; 6354 6354 + 6373 6355 struct vba_vars_st *v = &mode_lib->vba; 6374 6356 6375 6357 double DETBufferingTimeY; ··· 6671 6649 bool ViewportSizeSupportPerPlane[], 6672 6650 bool *ViewportSizeSupport) 6673 6651 { 6652 6652 + (void)HRatioChroma; 6674 6653 int MaximumSwathHeightY[DC__NUM_DPP__MAX]; 6675 6654 int MaximumSwathHeightC[DC__NUM_DPP__MAX]; 6676 6655 int MinimumSwathHeightY; ··· 6846 6823 int swath_width_luma_ub[], 6847 6824 int swath_width_chroma_ub[]) 6848 6825 { 6826 6826 + (void)BytePerPixY; 6849 6827 enum odm_combine_mode MainPlaneODMCombine; 6850 6828 int j, k; 6851 6829

+8

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

reviewed

··· 51 51 unsigned int delivery_width, 52 52 unsigned int req_per_swath_ub) 53 53 { 54 54 + (void)mode_lib; 54 55 double refcyc_per_delivery = 0.0; 55 56 56 57 if (vratio <= 1.0) { ··· 786 785 unsigned int cur_width, 787 786 enum cursor_bpp cur_bpp) 788 787 { 788 788 + (void)mode_lib; 789 789 unsigned int cur_src_width = cur_width; 790 790 unsigned int cur_req_size = 0; 791 791 unsigned int cur_req_width = 0; ··· 861 859 const bool ignore_viewport_pos, 862 860 const bool immediate_flip_support) 863 861 { 862 862 + (void)cstate_en; 863 863 + (void)pstate_en; 864 864 + (void)vm_en; 865 865 + (void)ignore_viewport_pos; 866 866 + (void)immediate_flip_support; 867 867 + (void)dlg_sys_param; 864 868 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 865 869 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 866 870 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;

+24

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

reviewed

··· 891 891 double *VUpdateWidthPix, 892 892 double *VReadyOffsetPix) 893 893 { 894 894 + (void)mode_lib; 895 895 + (void)HostVMMinPageSize; 896 896 + (void)SwathWidthY; 897 897 + (void)SwathWidthC; 898 898 + 894 899 bool MyError = false; 895 900 unsigned int DPPCycles, DISPCLKCycles; 896 901 double DSTTotalPixelsAfterScaler; ··· 1513 1508 unsigned int *IndependentBlockLuma, 1514 1509 unsigned int *IndependentBlockChroma) 1515 1510 { 1511 1511 + (void)SurfaceWidthChroma; 1512 1512 + (void)SurfaceHeightChroma; 1513 1513 + (void)BytePerPixelDETY; 1514 1514 + (void)BytePerPixelDETC; 1516 1515 int yuv420; 1517 1516 int horz_div_l; 1518 1517 int horz_div_c; ··· 1849 1840 int *DPDE0BytesFrame, 1850 1841 int *MetaPTEBytesFrame) 1851 1842 { 1843 1843 + (void)SourcePixelFormat; 1852 1844 struct vba_vars_st *v = &mode_lib->vba; 1853 1845 unsigned int MPDEBytesFrame; 1854 1846 unsigned int DCCMetaSurfaceBytes; ··· 3481 3471 unsigned int HTotal, 3482 3472 unsigned int WritebackLineBufferSize) 3483 3473 { 3474 3474 + (void)WritebackPixelFormat; 3475 3475 + (void)WritebackVRatio; 3484 3476 double DISPCLK_H, DISPCLK_V, DISPCLK_HB; 3485 3477 3486 3478 DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; ··· 3501 3489 int WritebackSourceHeight, 3502 3490 unsigned int HTotal) 3503 3491 { 3492 3492 + (void)WritebackPixelFormat; 3493 3493 + (void)WritebackHRatio; 3504 3494 double CalculateWriteBackDelay; 3505 3495 double Line_length; 3506 3496 double Output_lines_last_notclamped; ··· 5674 5660 double *Z8StutterExitWatermark, 5675 5661 double *Z8StutterEnterPlusExitWatermark) 5676 5662 { 5663 5663 + (void)DCFCLK; 5664 5664 + (void)ReturnBW; 5665 5665 + (void)DETBufferSizeC; 5677 5666 struct vba_vars_st *v = &mode_lib->vba; 5678 5667 double EffectiveLBLatencyHidingY; 5679 5668 double EffectiveLBLatencyHidingC; ··· 5942 5925 double *UrgentBurstFactorChroma, 5943 5926 bool *NotEnoughUrgentLatencyHiding) 5944 5927 { 5928 5928 + (void)VRatioC; 5945 5929 double LinesInDETLuma; 5946 5930 double LinesInDETChroma; 5947 5931 unsigned int LinesInCursorBuffer; ··· 6326 6308 double TimePerVMRequestVBlank[], 6327 6309 double TimePerVMRequestFlip[]) 6328 6310 { 6311 6311 + (void)dpte_row_width_luma_ub; 6312 6312 + (void)dpte_row_width_chroma_ub; 6329 6313 int num_group_per_lower_vm_stage; 6330 6314 int num_req_per_lower_vm_stage; 6331 6315 int k; ··· 6465 6445 int *Z8NumberOfStutterBurstsPerFrame, 6466 6446 double *StutterPeriod) 6467 6447 { 6448 6448 + (void)ConfigReturnBufferSizeInKByte; 6449 6449 + 6468 6450 struct vba_vars_st *v = &mode_lib->vba; 6469 6451 6470 6452 double DETBufferingTimeY; ··· 6765 6743 bool ViewportSizeSupportPerPlane[], 6766 6744 bool *ViewportSizeSupport) 6767 6745 { 6746 6746 + (void)HRatioChroma; 6768 6747 int MaximumSwathHeightY[DC__NUM_DPP__MAX]; 6769 6748 int MaximumSwathHeightC[DC__NUM_DPP__MAX]; 6770 6749 int MinimumSwathHeightY; ··· 6937 6914 int swath_width_luma_ub[], 6938 6915 int swath_width_chroma_ub[]) 6939 6916 { 6917 6917 + (void)BytePerPixY; 6940 6918 enum odm_combine_mode MainPlaneODMCombine; 6941 6919 int j, k; 6942 6920

+8

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

reviewed

··· 139 139 unsigned int delivery_width, 140 140 unsigned int req_per_swath_ub) 141 141 { 142 142 + (void)mode_lib; 142 143 double refcyc_per_delivery = 0.0; 143 144 144 145 if (vratio <= 1.0) { ··· 873 872 unsigned int cur_width, 874 873 enum cursor_bpp cur_bpp) 875 874 { 875 875 + (void)mode_lib; 876 876 unsigned int cur_src_width = cur_width; 877 877 unsigned int cur_req_size = 0; 878 878 unsigned int cur_req_width = 0; ··· 946 944 const bool ignore_viewport_pos, 947 945 const bool immediate_flip_support) 948 946 { 947 947 + (void)cstate_en; 948 948 + (void)pstate_en; 949 949 + (void)vm_en; 950 950 + (void)ignore_viewport_pos; 951 951 + (void)immediate_flip_support; 952 952 + (void)dlg_sys_param; 949 953 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 950 954 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 951 955 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;

+2

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

reviewed

··· 3488 3488 */ 3489 3489 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context) 3490 3490 { 3491 3491 + (void)dc; 3491 3492 double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4 3492 3493 int i; 3493 3494 ··· 3594 3593 3595 3594 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb) 3596 3595 { 3596 3596 + (void)soc_bb; 3597 3597 dc_assert_fp_enabled(); 3598 3598 dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0; 3599 3599 }

+23

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

reviewed

··· 457 457 bool ViewportSizeSupportPerSurface[], 458 458 bool *ViewportSizeSupport) 459 459 { 460 460 + (void)HRatioChroma; 460 461 unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; 461 462 unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; 462 463 unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX] = { 0 }; ··· 717 716 unsigned int swath_width_luma_ub[], // per-pipe 718 717 unsigned int swath_width_chroma_ub[]) // per-pipe 719 718 { 719 719 + (void)BytePerPixY; 720 720 unsigned int k, j; 721 721 enum odm_combine_mode MainSurfaceODMMode; 722 722 ··· 2306 2304 unsigned int *DPDE0BytesFrame, 2307 2305 unsigned int *MetaPTEBytesFrame) 2308 2306 { 2307 2307 + (void)SourcePixelFormat; 2309 2308 unsigned int MPDEBytesFrame; 2310 2309 unsigned int DCCMetaSurfaceBytes; 2311 2310 unsigned int ExtraDPDEBytesFrame; ··· 2748 2745 double *UrgentBurstFactorChroma, 2749 2746 bool *NotEnoughUrgentLatencyHiding) 2750 2747 { 2748 2748 + (void)VRatioC; 2751 2749 double LinesInDETLuma; 2752 2750 double LinesInDETChroma; 2753 2751 unsigned int LinesInCursorBuffer; ··· 2904 2900 unsigned int WritebackSourceHeight, 2905 2901 unsigned int HTotal) 2906 2902 { 2903 2903 + (void)WritebackPixelFormat; 2904 2904 + (void)WritebackHRatio; 2907 2905 double CalculateWriteBackDelay; 2908 2906 double Line_length; 2909 2907 double Output_lines_last_notclamped; ··· 2983 2977 /* Output */ 2984 2978 double DCFCLKState[][2]) 2985 2979 { 2980 2980 + (void)MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; 2981 2981 + (void)ReadBandwidthLuma; 2982 2982 + (void)ReadBandwidthChroma; 2986 2983 unsigned int i, j, k; 2987 2984 unsigned int dummy1; 2988 2985 double dummy2, dummy3; ··· 3456 3447 double *VUpdateWidthPix, 3457 3448 double *VReadyOffsetPix) 3458 3449 { 3450 3450 + (void)SwathWidthY; 3451 3451 + (void)SwathWidthC; 3459 3452 double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater; 3460 3453 bool MyError = false; 3461 3454 unsigned int DPPCycles, DISPCLKCycles; ··· 4156 4145 double *final_flip_bw, 4157 4146 bool *ImmediateFlipSupportedForPipe) 4158 4147 { 4148 4148 + (void)HostVMMinPageSize; 4159 4149 double min_row_time = 0.0; 4160 4150 unsigned int HostVMDynamicLevelsTrips; 4161 4151 double TimeForFetchingMetaPTEImmediateFlip; ··· 4299 4287 bool *USRRetrainingSupport, 4300 4288 double ActiveDRAMClockChangeLatencyMargin[]) 4301 4289 { 4290 4290 + (void)DCFCLK; 4291 4291 + (void)ReturnBW; 4302 4292 unsigned int i, j, k; 4303 4293 unsigned int SurfaceWithMinActiveFCLKChangeMargin = 0; 4304 4294 unsigned int DRAMClockChangeSupportNumber = 0; ··· 4669 4655 unsigned int WritebackLineBufferSize, 4670 4656 double DISPCLKDPPCLKVCOSpeed) 4671 4657 { 4658 4658 + (void)WritebackPixelFormat; 4659 4659 + (void)WritebackVRatio; 4672 4660 double DISPCLK_H, DISPCLK_V, DISPCLK_HB; 4673 4661 4674 4662 DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; ··· 5182 5166 double TimePerVMRequestVBlank[], 5183 5167 double TimePerVMRequestFlip[]) 5184 5168 { 5169 5169 + (void)dpte_row_width_luma_ub; 5170 5170 + (void)dpte_row_width_chroma_ub; 5185 5171 unsigned int k; 5186 5172 unsigned int num_group_per_lower_vm_stage; 5187 5173 unsigned int num_req_per_lower_vm_stage; ··· 5339 5321 unsigned int *IndependentBlockLuma, 5340 5322 unsigned int *IndependentBlockChroma) 5341 5323 { 5324 5324 + (void)SurfaceWidthChroma; 5325 5325 + (void)SurfaceHeightChroma; 5326 5326 + (void)TilingFormat; 5327 5327 + (void)BytePerPixelDETY; 5328 5328 + (void)BytePerPixelDETC; 5342 5329 typedef enum { 5343 5330 REQ_256Bytes, 5344 5331 REQ_128BytesNonContiguous,

+1

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

reviewed

··· 202 202 203 203 void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr) 204 204 { 205 205 + (void)clk_mgr; 205 206 //TODO 206 207 } 207 208

+1

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c

reviewed

··· 162 162 display_e2e_pipe_params_st *pipes, 163 163 int pipe_cnt) 164 164 { 165 165 + (void)mode_lib; 165 166 display_pipe_source_params_st *pipe_src; 166 167 display_pipe_dest_params_st *pipe_dest; 167 168 scaler_ratio_depth_st *scale_ratio_depth;

+14

drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c

reviewed

··· 49 49 50 50 void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing) 51 51 { 52 52 + (void)mode_lib; 53 53 + (void)rq_sizing; 52 54 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 53 55 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n"); 54 56 dml_print("DML_RQ_DLG_CALC: chunk_bytes = %0d\n", rq_sizing->chunk_bytes); ··· 66 64 67 65 void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param) 68 66 { 67 67 + (void)mode_lib; 68 68 + (void)rq_dlg_param; 69 69 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 70 70 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n"); 71 71 dml_print( ··· 111 107 112 108 void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param) 113 109 { 110 110 + (void)mode_lib; 111 111 + (void)rq_misc_param; 114 112 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 115 113 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n"); 116 114 dml_print( ··· 130 124 131 125 void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param) 132 126 { 127 127 + (void)dlg_sys_param; 128 128 + (void)mode_lib; 133 129 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 134 130 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n"); 135 131 dml_print("DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f\n", dlg_sys_param->t_mclk_wm_us); ··· 152 144 153 145 void print__data_rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs) 154 146 { 147 147 + (void)mode_lib; 148 148 + (void)rq_regs; 155 149 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 156 150 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n"); 157 151 dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs->chunk_size); ··· 189 179 190 180 void print__dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs) 191 181 { 182 182 + (void)dlg_regs; 183 183 + (void)mode_lib; 192 184 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 193 185 dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n"); 194 186 dml_print( ··· 328 316 329 317 void print__ttu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_st *ttu_regs) 330 318 { 319 319 + (void)mode_lib; 320 320 + (void)ttu_regs; 331 321 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 332 322 dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n"); 333 323 dml_print(

+3

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

reviewed

··· 104 104 unsigned int delivery_width, 105 105 unsigned int req_per_swath_ub) 106 106 { 107 107 + (void)mode_lib; 107 108 double refcyc_per_delivery = 0.0; 108 109 109 110 if (vratio <= 1.0) { ··· 134 133 double vinit, 135 134 double l_sw) 136 135 { 136 136 + (void)mode_lib; 137 137 double prefill = dml_floor(vinit, 1); 138 138 double vratio_pre = 1.0; 139 139 ··· 176 174 unsigned int swath_height, 177 175 double vinit) 178 176 { 177 177 + (void)mode_lib; 179 178 double prefill = dml_floor(vinit, 1); 180 179 unsigned int max_partial_sw_int; 181 180

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

reviewed

··· 288 288 enum dc_color_space input_color_space, 289 289 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 290 290 { 291 291 + (void)alpha_2bit_lut; 291 292 uint32_t pixel_format; 292 293 uint32_t alpha_en; 293 294 enum pixel_format_description fmt ;

+9 -2

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

reviewed

··· 92 92 void dpp2_dummy_program_input_lut( 93 93 struct dpp *dpp_base, 94 94 const struct dc_gamma *gamma) 95 95 - {} 95 95 + { 96 96 + (void)dpp_base; 97 97 + (void)gamma; 98 98 + } 96 99 97 100 static void dpp2_cnv_setup ( 98 101 struct dpp *dpp_base, ··· 372 369 struct dpp *dpp, 373 370 const struct pwl_params *params, 374 371 enum opp_regamma mode) 375 375 - {} 372 372 + { 373 373 + (void)dpp; 374 374 + (void)params; 375 375 + (void)mode; 376 376 + } 376 377 377 378 static struct dpp_funcs dcn20_dpp_funcs = { 378 379 .dpp_read_state = dpp20_read_state,

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

reviewed

··· 1016 1016 bool is_color_channel_12bits, 1017 1017 bool is_lut_size17x17x17) 1018 1018 { 1019 1019 + (void)is_color_channel_12bits; 1019 1020 uint32_t lut_mode; 1020 1021 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 1021 1022

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

reviewed

··· 1307 1307 bool is_color_channel_12bits, 1308 1308 bool is_lut_size17x17x17) 1309 1309 { 1310 1310 + (void)is_color_channel_12bits; 1310 1311 uint32_t lut_mode; 1311 1312 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1312 1313

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

reviewed

··· 80 80 uint32_t num, 81 81 bool is_ram_a) 82 82 { 83 83 + (void)is_ram_a; 83 84 uint32_t i; 84 85 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 85 86 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;

+5

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

reviewed

··· 132 132 uint32_t width, 133 133 uint32_t height) 134 134 { 135 135 + (void)param; 136 136 + (void)width; 137 137 + (void)height; 135 138 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 136 139 uint32_t cur_en = pos->enable ? 1 : 0; 137 140 ··· 240 237 enum dc_color_space color_space, 241 238 struct dc_csc_transform cursor_csc_color_matrix) 242 239 { 240 240 + (void)color_space; 241 241 + (void)cursor_csc_color_matrix; 243 242 //Since we don't have cursor matrix information, force bypass mode by passing in unknown color space 244 243 dpp401_program_cursor_csc(dpp_base, COLOR_SPACE_UNKNOWN, NULL); 245 244 }

+1

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

reviewed

··· 45 45 46 46 static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) 47 47 { 48 48 + (void)dwbc; 48 49 if (caps) { 49 50 caps->adapter_id = 0; /* we only support 1 adapter currently */ 50 51 caps->hw_version = DCN_VERSION_3_0;

+1

drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c

reviewed

··· 45 45 enum gpio_id *id, 46 46 uint32_t *en) 47 47 { 48 48 + (void)mask; 48 49 switch (offset) { 49 50 /* HPD */ 50 51 case REG(HPD0_DC_HPD_INT_STATUS):

+1

drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c

reviewed

··· 60 60 enum dce_version dce_version, 61 61 enum dce_environment dce_environment) 62 62 { 63 63 + (void)dce_environment; 63 64 switch (dce_version) { 64 65 #if defined(CONFIG_DRM_AMD_DC_SI) 65 66 case DCE_VERSION_6_0:

+1

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

reviewed

··· 199 199 void dal_hw_gpio_destruct( 200 200 struct hw_gpio *pin) 201 201 { 202 202 + (void)pin; 202 203 ASSERT(!pin->base.opened); 203 204 }

+1

drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c

reviewed

··· 64 64 enum dce_version dce_version, 65 65 enum dce_environment dce_environment) 66 66 { 67 67 + (void)dce_environment; 67 68 switch (dce_version) { 68 69 #if defined(CONFIG_DRM_AMD_DC_SI) 69 70 case DCE_VERSION_6_0:

+1

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

reviewed

··· 943 943 unsigned int dccg_ref_freq_inKhz, 944 944 unsigned int *dchub_ref_freq_inKhz) 945 945 { 946 946 + (void)dccg_ref_freq_inKhz; 946 947 struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 947 948 uint32_t ref_div = 0; 948 949 uint32_t ref_en = 0;

+1

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

reviewed

··· 259 259 unsigned int dccg_ref_freq_inKhz, 260 260 unsigned int *dchub_ref_freq_inKhz) 261 261 { 262 262 + (void)dccg_ref_freq_inKhz; 262 263 struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 263 264 uint32_t ref_div = 0; 264 265 uint32_t ref_en = 0;

+4

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

reviewed

··· 70 70 unsigned int refclk_mhz, 71 71 bool safe_to_lower) 72 72 { 73 73 + (void)refclk_mhz; 73 74 struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 74 75 bool wm_pending = false; 75 76 ··· 189 188 unsigned int refclk_mhz, 190 189 bool safe_to_lower) 191 190 { 191 191 + (void)refclk_mhz; 192 192 struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 193 193 bool wm_pending = false; 194 194 ··· 289 287 unsigned int refclk_mhz, 290 288 bool safe_to_lower) 291 289 { 290 290 + (void)refclk_mhz; 292 291 struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 293 292 bool wm_pending = false; 294 293 ··· 417 414 unsigned int refclk_mhz, 418 415 bool safe_to_lower) 419 416 { 417 417 + (void)refclk_mhz; 420 418 struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 421 419 bool wm_pending = false; 422 420

+2

drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c

reviewed

··· 488 488 489 489 static void hubbub42_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel) 490 490 { 491 491 + (void)memory_channel_count; 492 492 + (void)words_per_channel; 491 493 struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 492 494 uint32_t request_limit = 96; //MAX(12 * memory_channel_count, 96); 493 495

+2

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

reviewed

··· 143 143 const struct dc_tiling_info *info, 144 144 const enum surface_pixel_format pixel_format) 145 145 { 146 146 + (void)pixel_format; 146 147 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 147 148 148 149 REG_UPDATE_6(DCSURF_ADDR_CONFIG, ··· 564 563 bool horizontal_mirror, 565 564 unsigned int compat_level) 566 565 { 566 566 + (void)compat_level; 567 567 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 568 568 hubp1_program_tiling(hubp, tiling_info, format); 569 569 hubp1_program_size(hubp, format, plane_size, dcc);

+2

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

reviewed

··· 313 313 const struct dc_tiling_info *info, 314 314 const enum surface_pixel_format pixel_format) 315 315 { 316 316 + (void)pixel_format; 316 317 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 317 318 NUM_PIPES, log_2(info->gfx9.num_pipes), 318 319 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, ··· 558 557 bool horizontal_mirror, 559 558 unsigned int compat_level) 560 559 { 560 560 + (void)compat_level; 561 561 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 562 562 563 563 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

+2

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

reviewed

··· 321 321 const struct dc_tiling_info *info, 322 322 const enum surface_pixel_format pixel_format) 323 323 { 324 324 + (void)pixel_format; 324 325 REG_UPDATE_4(DCSURF_ADDR_CONFIG, 325 326 NUM_PIPES, log_2(info->gfx9.num_pipes), 326 327 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, ··· 419 418 bool horizontal_mirror, 420 419 unsigned int compat_level) 421 420 { 421 421 + (void)compat_level; 422 422 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 423 423 424 424 hubp3_dcc_control_sienna_cichlid(hubp, dcc);

+1

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

reviewed

··· 179 179 bool horizontal_mirror, 180 180 unsigned int compat_level) 181 181 { 182 182 + (void)compat_level; 182 183 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 183 184 184 185 hubp3_dcc_control_sienna_cichlid(hubp, dcc);

+3

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

reviewed

··· 657 657 const struct dc_tiling_info *info, 658 658 const enum surface_pixel_format pixel_format) 659 659 { 660 660 + (void)pixel_format; 660 661 /* DCSURF_ADDR_CONFIG still shows up in reg spec, but does not need to be programmed for DCN4x 661 662 * All 4 fields NUM_PIPES, PIPE_INTERLEAVE, MAX_COMPRESSED_FRAGS and NUM_PKRS are irrelevant. 662 663 * ··· 672 671 const struct plane_size *plane_size, 673 672 struct dc_plane_dcc_param *dcc) 674 673 { 674 674 + (void)dcc; 675 675 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 676 676 uint32_t pitch, pitch_c; 677 677 bool use_pitch_c = false; ··· 711 709 bool horizontal_mirror, 712 710 unsigned int compat_level) 713 711 { 712 712 + (void)compat_level; 714 713 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 715 714 716 715 hubp401_dcc_control(hubp, dcc);

+1

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

reviewed

··· 301 301 bool horizontal_mirror, 302 302 unsigned int compat_level) 303 303 { 304 304 + (void)compat_level; 304 305 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 305 306 306 307 hubp3_dcc_control_sienna_cichlid(hubp, dcc);

+22

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

reviewed

··· 201 201 struct dc_context *ctx, 202 202 bool clock_gating) 203 203 { 204 204 + (void)ctx; 205 205 + (void)clock_gating; 204 206 /*TODO*/ 205 207 } 206 208 ··· 286 284 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 287 285 const struct dc_plane_state *plane_state) 288 286 { 287 287 + (void)dc; 289 288 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 290 289 const struct dc_transfer_func *tf = NULL; 291 290 struct ipp_prescale_params prescale_params = { 0 }; ··· 610 607 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 611 608 const struct dc_stream_state *stream) 612 609 { 610 610 + (void)dc; 613 611 struct transform *xfm = pipe_ctx->plane_res.xfm; 614 612 615 613 xfm->funcs->opp_power_on_regamma_lut(xfm, true); ··· 1543 1539 struct dc_state *context, 1544 1540 struct dc *dc) 1545 1541 { 1542 1542 + (void)context; 1546 1543 struct dc_stream_state *stream = pipe_ctx->stream; 1547 1544 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1548 1545 pipe_ctx[pipe_ctx->pipe_idx]; ··· 2733 2728 static void update_plane_addr(const struct dc *dc, 2734 2729 struct pipe_ctx *pipe_ctx) 2735 2730 { 2731 2731 + (void)dc; 2736 2732 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2737 2733 2738 2734 if (plane_state == NULL) ··· 2820 2814 int group_size, 2821 2815 struct pipe_ctx *grouped_pipes[]) 2822 2816 { 2817 2817 + (void)state; 2818 2818 + (void)group_index; 2823 2819 struct dcp_gsl_params gsl_params = { 0 }; 2824 2820 int i; 2825 2821 DC_LOGGER_INIT(dc->ctx); ··· 2897 2889 2898 2890 static void dce110_init_pipes(struct dc *dc, struct dc_state *context) 2899 2891 { 2892 2892 + (void)context; 2893 2893 + (void)dc; 2900 2894 // Do nothing 2901 2895 } 2902 2896 ··· 3164 3154 struct dc *dc, 3165 3155 struct dc_state *context) 3166 3156 { 3157 3157 + (void)dc; 3158 3158 + (void)context; 3167 3159 } 3168 3160 3169 3161 static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) 3170 3162 { 3163 3163 + (void)state; 3171 3164 struct dce_hwseq *hws = dc->hwseq; 3172 3165 int fe_idx = pipe_ctx->plane_res.mi ? 3173 3166 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; ··· 3191 3178 struct resource_pool *res_pool, 3192 3179 struct pipe_ctx *pipe_ctx) 3193 3180 { 3181 3181 + (void)dc; 3182 3182 + (void)res_pool; 3183 3183 + (void)pipe_ctx; 3194 3184 /* do nothing*/ 3195 3185 } 3196 3186 ··· 3203 3187 uint16_t *matrix, 3204 3188 int opp_id) 3205 3189 { 3190 3190 + (void)dc; 3191 3191 + (void)colorspace; 3192 3192 + (void)matrix; 3193 3193 + (void)opp_id; 3206 3194 int i; 3207 3195 struct out_csc_color_matrix tbl_entry; 3208 3196 ··· 3351 3331 enum clock_source_id clock_source, 3352 3332 uint32_t pixel_clock) 3353 3333 { 3334 3334 + (void)link_res; 3354 3335 link->link_enc->funcs->enable_lvds_output( 3355 3336 link->link_enc, 3356 3337 clock_source, ··· 3366 3345 enum dc_color_depth color_depth, 3367 3346 uint32_t pixel_clock) 3368 3347 { 3348 3348 + (void)link_res; 3369 3349 link->link_enc->funcs->enable_tmds_output( 3370 3350 link->link_enc, 3371 3351 clock_source,

+4

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

reviewed

··· 154 154 struct dc_bios *dcb, 155 155 enum pipe_gating_control power_gating) 156 156 { 157 157 + (void)dc; 158 158 + (void)controller_id; 159 159 + (void)dcb; 160 160 + (void)power_gating; 157 161 /* disable for bringup */ 158 162 #if 0 159 163 enum bp_result bp_result = BP_RESULT_OK;

+21

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

reviewed

··· 86 86 struct dc_log_buffer_ctx *log_ctx, 87 87 uint32_t ref_cycle) 88 88 { 89 89 + (void)log_ctx; 89 90 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; 90 91 static const unsigned int frac = 1000; 91 92 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz; ··· 253 252 static void log_mpc_crc(struct dc *dc, 254 253 struct dc_log_buffer_ctx *log_ctx) 255 254 { 255 255 + (void)log_ctx; 256 256 struct dc_context *dc_ctx = dc->ctx; 257 257 struct dce_hwseq *hws = dc->hwseq; 258 258 ··· 452 450 static void dcn10_log_color_state(struct dc *dc, 453 451 struct dc_log_buffer_ctx *log_ctx) 454 452 { 453 453 + (void)log_ctx; 455 454 struct dc_context *dc_ctx = dc->ctx; 456 455 struct resource_pool *pool = dc->res_pool; 457 456 bool is_gamut_remap_available = false; ··· 816 813 817 814 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx) 818 815 { 816 816 + (void)dc; 819 817 struct hubp *hubp = pipe_ctx->plane_res.hubp; 820 818 struct timing_generator *tg = pipe_ctx->stream_res.tg; 821 819 ··· 1185 1181 struct dc_state *context, 1186 1182 struct dc *dc) 1187 1183 { 1184 1184 + (void)context; 1188 1185 struct dc_stream_state *stream = pipe_ctx->stream; 1189 1186 enum dc_color_space color_space; 1190 1187 struct tg_color black_color = {0}; ··· 1289 1284 struct pipe_ctx *pipe_ctx, 1290 1285 struct dc_state *context) 1291 1286 { 1287 1287 + (void)context; 1292 1288 int i; 1293 1289 struct dc_link *link; 1294 1290 DC_LOGGER_INIT(dc->ctx); ··· 1557 1551 1558 1552 void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) 1559 1553 { 1554 1554 + (void)state; 1560 1555 struct dce_hwseq *hws = dc->hwseq; 1561 1556 DC_LOGGER_INIT(dc->ctx); 1562 1557 ··· 2011 2004 2012 2005 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2013 2006 { 2007 2007 + (void)dc; 2014 2008 bool addr_patched = false; 2015 2009 PHYSICAL_ADDRESS_LOC addr; 2016 2010 struct dc_plane_state *plane_state = pipe_ctx->plane_state; ··· 2038 2030 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 2039 2031 const struct dc_plane_state *plane_state) 2040 2032 { 2033 2033 + (void)dc; 2041 2034 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 2042 2035 const struct dc_transfer_func *tf = NULL; 2043 2036 bool result = true; ··· 2481 2472 int group_size, 2482 2473 struct pipe_ctx *grouped_pipes[]) 2483 2474 { 2475 2475 + (void)group_index; 2484 2476 struct output_pixel_processor *opp; 2485 2477 struct timing_generator *tg; 2486 2478 int i, width = 0, height = 0, master; ··· 2547 2537 int group_size, 2548 2538 struct pipe_ctx *grouped_pipes[]) 2549 2539 { 2540 2540 + (void)group_index; 2550 2541 struct output_pixel_processor *opp; 2551 2542 struct timing_generator *tg; 2552 2543 int i, width = 0, height = 0; ··· 2652 2641 struct vm_system_aperture_param *apt, 2653 2642 struct dce_hwseq *hws) 2654 2643 { 2644 2644 + (void)hubp1; 2655 2645 PHYSICAL_ADDRESS_LOC physical_page_number; 2656 2646 uint32_t logical_addr_low; 2657 2647 uint32_t logical_addr_high; ··· 2678 2666 struct vm_context0_param *vm0, 2679 2667 struct dce_hwseq *hws) 2680 2668 { 2669 2669 + (void)hubp1; 2681 2670 PHYSICAL_ADDRESS_LOC fb_base; 2682 2671 PHYSICAL_ADDRESS_LOC fb_offset; 2683 2672 uint32_t fb_base_value; ··· 2737 2724 struct pipe_ctx *pipe_ctx, 2738 2725 struct dc_state *context) 2739 2726 { 2727 2727 + (void)context; 2740 2728 struct dce_hwseq *hws = dc->hwseq; 2741 2729 2742 2730 if (dc->debug.sanity_checks) { ··· 2835 2821 uint16_t *matrix, 2836 2822 int opp_id) 2837 2823 { 2824 2824 + (void)dc; 2825 2825 + (void)opp_id; 2838 2826 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 2839 2827 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) { 2840 2828 ··· 3602 3586 struct dc_bios *dcb, 3603 3587 enum pipe_gating_control power_gating) 3604 3588 { 3589 3589 + (void)dc; 3590 3590 + (void)controller_id; 3591 3591 + (void)dcb; 3592 3592 + (void)power_gating; 3605 3593 return true; 3606 3594 } 3607 3595 ··· 4072 4052 uint32_t clk_khz, 4073 4053 uint32_t stepping) 4074 4054 { 4055 4055 + (void)stepping; 4075 4056 struct dc_state *context = dc->current_state; 4076 4057 struct dc_clock_config clock_cfg = {0}; 4077 4058 struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;

+9

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

reviewed

··· 75 75 void dcn20_log_color_state(struct dc *dc, 76 76 struct dc_log_buffer_ctx *log_ctx) 77 77 { 78 78 + (void)log_ctx; 78 79 struct dc_context *dc_ctx = dc->ctx; 79 80 struct resource_pool *pool = dc->res_pool; 80 81 bool is_gamut_remap_available = false; ··· 380 379 struct pipe_ctx *pipe_ctx, 381 380 bool enable_triple_buffer) 382 381 { 382 382 + (void)dc; 383 383 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 384 384 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 385 385 pipe_ctx->plane_res.hubp, ··· 1177 1175 1178 1176 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1179 1177 { 1178 1178 + (void)context; 1179 1179 + (void)dc; 1180 1180 struct pipe_ctx *odm_pipe; 1181 1181 int opp_cnt = 1; 1182 1182 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; ··· 1301 1297 void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1302 1298 struct dc_state *context) 1303 1299 { 1300 1300 + (void)context; 1304 1301 //if (dc->debug.sanity_checks) { 1305 1302 // dcn10_verify_allow_pstate_change_high(dc); 1306 1303 //} ··· 2657 2652 struct dc_virtual_addr_space_config *va_config, 2658 2653 int vmid) 2659 2654 { 2655 2655 + (void)hws; 2660 2656 struct dcn_hubbub_virt_addr_config config; 2661 2657 2662 2658 if (vmid == 0) { ··· 2676 2670 2677 2671 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2678 2672 { 2673 2673 + (void)hws; 2679 2674 struct dcn_hubbub_phys_addr_config config; 2680 2675 2681 2676 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; ··· 2806 2799 struct pipe_ctx *pipe_ctx, 2807 2800 struct dc_state *context) 2808 2801 { 2802 2802 + (void)context; 2809 2803 struct dc_link *link = pipe_ctx->stream->link; 2810 2804 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2811 2805 struct dccg *dccg = dc->res_pool->dccg; ··· 3253 3245 const struct tg_color *solid_color, 3254 3246 int width, int height, int offset) 3255 3247 { 3248 3248 + (void)dc; 3256 3249 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 3257 3250 color_space, color_depth, solid_color, width, height, offset); 3258 3251 }

+3

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

reviewed

··· 75 75 void dcn30_log_color_state(struct dc *dc, 76 76 struct dc_log_buffer_ctx *log_ctx) 77 77 { 78 78 + (void)log_ctx; 78 79 struct dc_context *dc_ctx = dc->ctx; 79 80 struct resource_pool *pool = dc->res_pool; 80 81 bool is_gamut_remap_available = false; ··· 1184 1183 const struct tg_color *solid_color, 1185 1184 int width, int height, int offset) 1186 1185 { 1186 1186 + (void)dc; 1187 1187 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 1188 1188 color_space, color_depth, solid_color, width, height, offset); 1189 1189 } ··· 1239 1237 struct timing_generator *tg, 1240 1238 struct dc_underflow_debug_data *out_data) 1241 1239 { 1240 1240 + (void)tg; 1242 1241 struct hubbub *hubbub = dc->res_pool->hubbub; 1243 1242 1244 1243 if (hubbub) {

+11

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

reviewed

··· 45 45 46 46 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) 47 47 { 48 48 + (void)dpp_inst; 49 49 + (void)hws; 50 50 + (void)power_on; 48 51 /*DCN303 removes PG registers*/ 49 52 } 50 53 51 54 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 52 55 { 56 56 + (void)hubp_inst; 57 57 + (void)hws; 58 58 + (void)power_on; 53 59 /*DCN303 removes PG registers*/ 54 60 } 55 61 56 62 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) 57 63 { 64 64 + (void)dsc_inst; 65 65 + (void)hws; 66 66 + (void)power_on; 58 67 /*DCN303 removes PG registers*/ 59 68 } 60 69 61 70 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) 62 71 { 72 72 + (void)enable; 73 73 + (void)hws; 63 74 /*DCN303 removes PG registers*/ 64 75 }

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

reviewed

··· 484 484 485 485 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 486 486 { 487 487 + (void)hws; 487 488 struct dcn_hubbub_phys_addr_config config = {0}; 488 489 489 490 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; ··· 512 511 struct pipe_ctx *pipe_ctx, 513 512 struct dc_state *context) 514 513 { 514 514 + (void)context; 515 515 struct dc_link *link; 516 516 517 517 if (pipe_ctx->stream_res.stream_enc == NULL) {

+1

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

reviewed

··· 172 172 173 173 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 174 174 { 175 175 + (void)context; 175 176 struct pipe_ctx *odm_pipe; 176 177 int opp_cnt = 0; 177 178 int opp_inst[MAX_PIPES] = {0};

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

reviewed

··· 570 570 struct pipe_ctx *pipe_ctx, 571 571 const struct dc_stream_state *stream) 572 572 { 573 573 + (void)dc; 573 574 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 574 575 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 575 576 const struct pwl_params *params = NULL; ··· 1144 1143 1145 1144 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1146 1145 { 1146 1146 + (void)context; 1147 1147 struct pipe_ctx *odm_pipe; 1148 1148 int opp_cnt = 0; 1149 1149 int opp_inst[MAX_PIPES] = {0};

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

reviewed

··· 428 428 429 429 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 430 430 { 431 431 + (void)context; 431 432 struct pipe_ctx *odm_pipe; 432 433 int opp_cnt = 0; 433 434 int opp_inst[MAX_PIPES] = {0}; ··· 817 816 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 818 817 struct dc_state *context) 819 818 { 819 819 + (void)context; 820 820 struct dpp *dpp = pipe_ctx->plane_res.dpp; 821 821 822 822 /* enable DCFCLK current DCHUB */

+6

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

reviewed

··· 557 557 struct pipe_ctx *pipe_ctx, 558 558 const struct dc_stream_state *stream) 559 559 { 560 560 + (void)dc; 560 561 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 561 562 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 562 563 const struct pwl_params *params = NULL; ··· 619 618 struct drr_params *params, 620 619 unsigned int *event_triggers) 621 620 { 621 621 + (void)dc; 622 622 struct dc_stream_state *stream = pipe_ctx->stream; 623 623 int i; 624 624 ··· 1397 1395 struct dc_state *context, 1398 1396 bool lock) 1399 1397 { 1398 1398 + (void)context; 1400 1399 /* use always for now */ 1401 1400 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 1402 1401 ··· 1872 1869 struct pipe_ctx *pipe_ctx, 1873 1870 struct dc_state *context) 1874 1871 { 1872 1872 + (void)context; 1875 1873 struct dc_link *link = pipe_ctx->stream->link; 1876 1874 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1877 1875 ··· 3248 3244 struct dc_state *context, 3249 3245 struct block_sequence_state *seq_state) 3250 3246 { 3247 3247 + (void)context; 3251 3248 struct dwbc *dwb; 3252 3249 struct mcif_wb *mcif_wb; 3253 3250 ··· 3454 3449 struct dc_state *context, 3455 3450 struct block_sequence_state *seq_state) 3456 3451 { 3452 3452 + (void)context; 3457 3453 struct dce_hwseq *hws = dc->hwseq; 3458 3454 uint32_t org_ip_request_cntl = 0; 3459 3455

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

reviewed

··· 386 386 struct pipe_ctx *pipe_ctx, 387 387 const struct dc_plane_state *plane_state) 388 388 { 389 389 + (void)dc; 389 390 struct dpp *dpp = pipe_ctx->plane_res.dpp; 390 391 391 392 if (dpp && dpp->funcs->dpp_cm_hist_control) ··· 1001 1000 } 1002 1001 void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) 1003 1002 { 1003 1003 + (void)dc; 1004 1004 struct crtc_stereo_flags flags = { 0 }; 1005 1005 struct dc_stream_state *stream = pipe_ctx->stream; 1006 1006

+2

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

reviewed

··· 183 183 const struct irq_source_info *info, 184 184 bool enable) 185 185 { 186 186 + (void)enable; 186 187 DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n", 187 188 __func__, info->src_id, info->ext_id); 188 189 ··· 329 328 uint32_t src_id, 330 329 uint32_t ext_id) 331 330 { 331 331 + (void)irq_service; 332 332 switch (src_id) { 333 333 case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0: 334 334 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

reviewed

··· 42 42 uint32_t src_id, 43 43 uint32_t ext_id) 44 44 { 45 45 + (void)irq_service; 46 46 + (void)src_id; 47 47 + (void)ext_id; 45 48 switch (src_id) { 46 49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 47 50 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

reviewed

··· 43 43 uint32_t src_id, 44 44 uint32_t ext_id) 45 45 { 46 46 + (void)irq_service; 47 47 + (void)src_id; 48 48 + (void)ext_id; 46 49 switch (src_id) { 47 50 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 48 51 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

reviewed

··· 42 42 uint32_t src_id, 43 43 uint32_t ext_id) 44 44 { 45 45 + (void)irq_service; 46 46 + (void)src_id; 47 47 + (void)ext_id; 45 48 switch (src_id) { 46 49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 47 50 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

reviewed

··· 50 50 uint32_t src_id, 51 51 uint32_t ext_id) 52 52 { 53 53 + (void)irq_service; 54 54 + (void)src_id; 55 55 + (void)ext_id; 53 56 switch (src_id) { 54 57 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 55 58 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

reviewed

··· 37 37 38 38 static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id) 39 39 { 40 40 + (void)ext_id; 41 41 + (void)irq_service; 42 42 + (void)src_id; 40 43 switch (src_id) { 41 44 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 42 45 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

reviewed

··· 38 38 uint32_t src_id, 39 39 uint32_t ext_id) 40 40 { 41 41 + (void)irq_service; 42 42 + (void)src_id; 43 43 + (void)ext_id; 41 44 switch (src_id) { 42 45 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 43 46 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

reviewed

··· 40 40 uint32_t src_id, 41 41 uint32_t ext_id) 42 42 { 43 43 + (void)irq_service; 44 44 + (void)src_id; 45 45 + (void)ext_id; 43 46 switch (src_id) { 44 47 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 45 48 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

reviewed

··· 42 42 uint32_t src_id, 43 43 uint32_t ext_id) 44 44 { 45 45 + (void)irq_service; 46 46 + (void)src_id; 47 47 + (void)ext_id; 45 48 switch (src_id) { 46 49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 47 50 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

reviewed

··· 47 47 uint32_t src_id, 48 48 uint32_t ext_id) 49 49 { 50 50 + (void)irq_service; 51 51 + (void)src_id; 52 52 + (void)ext_id; 50 53 switch (src_id) { 51 54 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 52 55 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

reviewed

··· 41 41 uint32_t src_id, 42 42 uint32_t ext_id) 43 43 { 44 44 + (void)irq_service; 45 45 + (void)src_id; 46 46 + (void)ext_id; 44 47 switch (src_id) { 45 48 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 46 49 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

reviewed

··· 39 39 uint32_t src_id, 40 40 uint32_t ext_id) 41 41 { 42 42 + (void)irq_service; 43 43 + (void)src_id; 44 44 + (void)ext_id; 42 45 switch (src_id) { 43 46 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 44 47 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

reviewed

··· 18 18 uint32_t src_id, 19 19 uint32_t ext_id) 20 20 { 21 21 + (void)irq_service; 22 22 + (void)src_id; 23 23 + (void)ext_id; 21 24 switch (src_id) { 22 25 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 23 26 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

reviewed

··· 17 17 uint32_t src_id, 18 18 uint32_t ext_id) 19 19 { 20 20 + (void)irq_service; 21 21 + (void)src_id; 22 22 + (void)ext_id; 20 23 switch (src_id) { 21 24 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 22 25 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

reviewed

··· 20 20 uint32_t src_id, 21 21 uint32_t ext_id) 22 22 { 23 23 + (void)irq_service; 24 24 + (void)src_id; 25 25 + (void)ext_id; 23 26 switch (src_id) { 24 27 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 25 28 return DC_IRQ_SOURCE_VBLANK1;

+3

drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c

reviewed

··· 19 19 uint32_t src_id, 20 20 uint32_t ext_id) 21 21 { 22 22 + (void)irq_service; 23 23 + (void)src_id; 24 24 + (void)ext_id; 22 25 switch (src_id) { 23 26 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 24 27 return DC_IRQ_SOURCE_VBLANK1;

+2

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

reviewed

··· 66 66 struct dc_link_settings *link_setting, 67 67 bool skip_video_pattern) 68 68 { 69 69 + (void)skip_video_pattern; 69 70 struct pipe_ctx *pipes[MAX_PIPES]; 70 71 struct dc_state *state = link->dc->current_state; 71 72 struct dc_stream_update stream_update = { 0 }; ··· 484 483 enum dp_test_pattern test_pattern, 485 484 enum dp_test_pattern_color_space test_pattern_color_space) 486 485 { 486 486 + (void)test_pattern_color_space; 487 487 enum controller_dp_test_pattern controller_test_pattern; 488 488 enum dc_color_depth color_depth = pipe_ctx-> 489 489 stream->timing.display_color_depth;

+4

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

reviewed

··· 81 81 const struct dc_link_settings *link_settings, 82 82 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 83 83 { 84 84 + (void)link; 85 85 + (void)link_res; 86 86 + (void)link_settings; 87 87 + (void)lane_settings; 84 88 } 85 89 86 90 static void enable_dpia_link_output(struct dc_link *link,

+6

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

reviewed

··· 110 110 enum clock_source_id clock_source, 111 111 const struct dc_link_settings *link_settings) 112 112 { 113 113 + (void)signal; 114 114 + (void)clock_source; 113 115 if (!link_res->hpo_dp_link_enc) { 114 116 DC_LOG_ERROR("%s: invalid hpo_dp_link_enc\n", __func__); 115 117 return; ··· 162 160 const struct dc_link_settings *link_settings, 163 161 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 164 162 { 163 163 + (void)link; 165 164 link_res->hpo_dp_link_enc->funcs->set_ffe( 166 165 link_res->hpo_dp_link_enc, 167 166 link_settings, ··· 173 170 const struct link_resource *link_res, 174 171 const struct link_mst_stream_allocation_table *table) 175 172 { 173 173 + (void)link; 176 174 link_res->hpo_dp_link_enc->funcs->update_stream_allocation_table( 177 175 link_res->hpo_dp_link_enc, 178 176 table); ··· 182 178 void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx, 183 179 struct audio_output *audio_output, uint32_t audio_inst) 184 180 { 181 181 + (void)audio_output; 185 182 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( 186 183 pipe_ctx->stream_res.hpo_dp_stream_enc, 187 184 audio_inst, ··· 223 218 bool can_use_hpo_dp_link_hwss(const struct dc_link *link, 224 219 const struct link_resource *link_res) 225 220 { 221 221 + (void)link; 226 222 return link_res->hpo_dp_link_enc != NULL; 227 223 } 228 224

+1

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

reviewed

··· 74 74 static void dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern(struct dc_link *link, 75 75 struct encoder_set_dp_phy_pattern_param *tp_params) 76 76 { 77 77 + (void)tp_params; 77 78 uint8_t clk_src = 0xC4; 78 79 uint8_t pattern = 0x4F; /* SQ128 */ 79 80

+6

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

reviewed

··· 27 27 28 28 void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx) 29 29 { 30 30 + (void)pipe_ctx; 30 31 } 31 32 32 33 void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx) 33 34 { 35 35 + (void)pipe_ctx; 34 36 } 35 37 36 38 void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx) 37 39 { 40 40 + (void)pipe_ctx; 38 41 } 39 42 40 43 static void virtual_disable_link_output(struct dc_link *link, 41 44 const struct link_resource *link_res, 42 45 enum signal_type signal) 43 46 { 47 47 + (void)link; 48 48 + (void)link_res; 49 49 + (void)signal; 44 50 } 45 51 46 52 static const struct link_hwss virtual_link_hwss = {

+1

drivers/gpu/drm/amd/display/dc/link/link_detection.c

reviewed

··· 823 823 static bool should_verify_link_capability_destructively(struct dc_link *link, 824 824 enum dc_detect_reason reason) 825 825 { 826 826 + (void)reason; 826 827 bool destrictive = false; 827 828 struct dc_link_settings max_link_cap; 828 829 bool is_link_enc_unavailable = false;

+1

drivers/gpu/drm/amd/display/dc/link/link_validation.c

reviewed

··· 391 391 */ 392 392 enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx) 393 393 { 394 394 + (void)dc; 394 395 struct dc_validation_dpia_set dpia_link_sets[MAX_DPIA_NUM] = { 0 }; 395 396 uint8_t link_count = 0; 396 397 enum dc_status result = DC_OK;

+2

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

reviewed

··· 554 554 struct dc_link *link, 555 555 const struct link_training_settings *link_training_setting) 556 556 { 557 557 + (void)link_training_setting; 557 558 enum link_training_result status = LINK_TRAINING_SUCCESS; 558 559 union lane_status lane_status; 559 560 union lane_align_status_updated dpcd_lane_status_updated; ··· 1388 1387 enum dc_dp_training_pattern pattern, 1389 1388 uint32_t offset) 1390 1389 { 1390 1390 + (void)offset; 1391 1391 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 1392 1392 1393 1393 switch (pattern) {

+1

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

reviewed

··· 158 158 const struct link_resource *link_res, 159 159 struct link_training_settings *lt_settings) 160 160 { 161 161 + (void)link_res; 161 162 /* Assumption: assume hardware has transmitted eq pattern */ 162 163 enum dc_status status = DC_OK; 163 164 enum link_training_result result = LINK_TRAINING_SUCCESS;

+6

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

reviewed

··· 172 172 struct dc_link *link, 173 173 struct link_training_settings *lt_settings) 174 174 { 175 175 + (void)link; 175 176 union dpia_set_config_data data; 176 177 177 178 data.raw = 0; ··· 291 290 struct link_training_settings *lt_settings, 292 291 uint32_t hop) 293 292 { 293 293 + (void)link_res; 294 294 enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0; 295 295 uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */ 296 296 enum dc_status status = DC_ERROR_UNEXPECTED; ··· 459 457 const struct link_resource *link_res, 460 458 struct link_training_settings *lt_settings) 461 459 { 460 460 + (void)link_res; 462 461 enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0; 463 462 enum dc_status status; 464 463 uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */ ··· 588 585 struct link_training_settings *lt_settings, 589 586 uint32_t hop) 590 587 { 588 588 + (void)link_res; 591 589 enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ; 592 590 uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */ 593 591 uint32_t retries_eq = 0; ··· 734 730 const struct link_resource *link_res, 735 731 struct link_training_settings *lt_settings) 736 732 { 733 733 + (void)link_res; 737 734 enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ; 738 735 uint32_t retries_eq = 0; 739 736 enum dc_status status; ··· 996 991 const struct dc_link_settings *link_setting, 997 992 bool skip_video_pattern) 998 993 { 994 994 + (void)skip_video_pattern; 999 995 enum link_training_result result; 1000 996 struct link_training_settings lt_settings = {0}; 1001 997 uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */

+1

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

reviewed

··· 180 180 uint8_t * const reduced_data, 181 181 const uint32_t reduced_size) 182 182 { 183 183 + (void)extended_size; 183 184 const uint32_t offset = reduced_address - extended_address; 184 185 185 186 /*

+4

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

reviewed

··· 117 117 bool rate_2x_mode, 118 118 struct mpc_dwb_flow_control *flow_control) 119 119 { 120 120 + (void)enable; 121 121 + (void)rate_2x_mode; 122 122 + (void)flow_control; 120 123 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 121 124 122 125 /* Always disable mpc out rate and flow control. ··· 911 908 bool is_lut_size17x17x17, 912 909 uint32_t rmu_idx) 913 910 { 911 911 + (void)is_color_channel_12bits; 914 912 uint32_t lut_mode; 915 913 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 916 914

+1

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

reviewed

··· 884 884 bool is_lut_size17x17x17, 885 885 uint32_t mpcc_id) 886 886 { 887 887 + (void)is_color_channel_12bits; 887 888 uint32_t lut_mode; 888 889 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 889 890

+1

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

reviewed

··· 250 250 enum dc_color_depth color_dpth, 251 251 enum signal_type signal) 252 252 { 253 253 + (void)color_sp; 253 254 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 254 255 255 256 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,

+4

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

reviewed

··· 164 164 const enum signal_type signal, 165 165 bool use_vbios) 166 166 { 167 167 + (void)use_vbios; 167 168 struct dc_crtc_timing patched_crtc_timing; 168 169 uint32_t asic_blank_end; 169 170 uint32_t asic_blank_start; ··· 856 855 struct timing_generator *optc, 857 856 uint32_t early_cntl) 858 857 { 858 858 + (void)optc; 859 859 + (void)early_cntl; 859 860 /* asic design change, do not need this control 860 861 * empty for share caller logic 861 862 */ ··· 1252 1249 static void optc1_enable_stereo(struct timing_generator *optc, 1253 1250 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1254 1251 { 1252 1252 + (void)timing; 1255 1253 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1256 1254 1257 1255 if (flags) {

+2

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

reviewed

··· 181 181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 182 182 int segment_width, int last_segment_width) 183 183 { 184 184 + (void)last_segment_width; 184 185 struct optc *optc1 = DCN10TG_FROM_TG(optc); 185 186 uint32_t memory_mask; 186 187 ··· 262 261 uint8_t master_clock_divider, 263 262 uint8_t slave_clock_divider) 264 263 { 264 264 + (void)slave_clock_divider; 265 265 /* accessing slave OTG registers */ 266 266 struct optc *optc1 = DCN10TG_FROM_TG(optc_slave); 267 267

+1

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

reviewed

··· 218 218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 219 219 int segment_width, int last_segment_width) 220 220 { 221 221 + (void)last_segment_width; 221 222 struct optc *optc1 = DCN10TG_FROM_TG(optc); 222 223 uint32_t memory_mask = 0; 223 224

+1

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

reviewed

··· 43 43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 44 44 int segment_width, int last_segment_width) 45 45 { 46 46 + (void)last_segment_width; 46 47 struct optc *optc1 = DCN10TG_FROM_TG(optc); 47 48 uint32_t memory_mask = 0; 48 49 int mem_count_per_opp = (segment_width + 2559) / 2560;

+1

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

reviewed

··· 50 50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 51 51 int segment_width, int last_segment_width) 52 52 { 53 53 + (void)last_segment_width; 53 54 struct optc *optc1 = DCN10TG_FROM_TG(optc); 54 55 uint32_t memory_mask = 0; 55 56 int h_active = segment_width * opp_cnt;

+1

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

reviewed

··· 45 45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 46 46 int segment_width, int last_segment_width) 47 47 { 48 48 + (void)last_segment_width; 48 49 struct optc *optc1 = DCN10TG_FROM_TG(optc); 49 50 uint32_t memory_mask = 0; 50 51 int h_active = segment_width * opp_cnt;

+1

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

reviewed

··· 58 58 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 59 59 int segment_width, int last_segment_width) 60 60 { 61 61 + (void)last_segment_width; 61 62 struct optc *optc1 = DCN10TG_FROM_TG(optc); 62 63 uint32_t memory_mask = 0; 63 64 int h_active = segment_width * opp_cnt;

+5

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

reviewed

··· 632 632 struct dc_context *ctx, 633 633 const struct encoder_init_data *enc_init_data) 634 634 { 635 635 + (void)ctx; 635 636 struct dce110_link_encoder *enc110 = 636 637 kzalloc_obj(struct dce110_link_encoder); 637 638 int link_regs_id; ··· 850 849 struct dc_state *context, 851 850 struct dc_stream_state *stream) 852 851 { 852 852 + (void)dc; 853 853 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 854 854 855 855 if (!pipe_ctx) ··· 868 866 struct dc_state *context, 869 867 enum dc_validate_mode validate_mode) 870 868 { 869 869 + (void)validate_mode; 871 870 int i; 872 871 bool at_least_one_pipe = false; 873 872 struct dc_stream_state *stream = NULL; ··· 929 926 struct dc *dc, 930 927 struct dc_state *context) 931 928 { 929 929 + (void)dc; 932 930 if (!dce100_validate_surface_sets(context)) 933 931 return DC_FAIL_SURFACE_VALIDATE; 934 932 ··· 965 961 966 962 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 967 963 { 964 964 + (void)caps; 968 965 969 966 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 970 967 return DC_OK;

+6

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

reviewed

··· 667 667 struct dc_context *ctx, 668 668 const struct encoder_init_data *enc_init_data) 669 669 { 670 670 + (void)ctx; 670 671 struct dce110_link_encoder *enc110 = 671 672 kzalloc_obj(struct dce110_link_encoder); 672 673 int link_regs_id; ··· 972 971 struct dc_state *context, 973 972 enum dc_validate_mode validate_mode) 974 973 { 974 974 + (void)validate_mode; 975 975 bool result = false; 976 976 977 977 DC_LOG_BANDWIDTH_CALCS( ··· 1045 1043 static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 1046 1044 struct dc_caps *caps) 1047 1045 { 1046 1046 + (void)caps; 1048 1047 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 1049 1048 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 1050 1049 return DC_FAIL_SURFACE_VALIDATE; ··· 1102 1099 struct dc *dc, 1103 1100 struct dc_state *context) 1104 1101 { 1102 1102 + (void)dc; 1105 1103 if (!dce110_validate_surface_sets(context)) 1106 1104 return DC_FAIL_SURFACE_VALIDATE; 1107 1105 ··· 1134 1130 const struct resource_pool *pool, 1135 1131 const struct pipe_ctx *opp_head_pipe) 1136 1132 { 1133 1133 + (void)cur_ctx; 1137 1134 struct dc_stream_state *stream = opp_head_pipe->stream; 1138 1135 struct dc *dc = stream->ctx->dc; 1139 1136 struct dce_hwseq *hws = dc->hwseq; ··· 1359 1354 struct dce110_resource_pool *pool, 1360 1355 struct hw_asic_id asic_id) 1361 1356 { 1357 1357 + (void)asic_id; 1362 1358 unsigned int i; 1363 1359 struct dc_context *ctx = dc->ctx; 1364 1360 struct dc_bios *bp;

+5

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

reviewed

··· 628 628 struct dc_context *ctx, 629 629 const struct encoder_init_data *enc_init_data) 630 630 { 631 631 + (void)ctx; 631 632 struct dce110_link_encoder *enc110 = 632 633 kzalloc_obj(struct dce110_link_encoder); 633 634 int link_regs_id; ··· 853 852 const struct resource_pool *pool, 854 853 const struct dc_stream_state *const stream) 855 854 { 855 855 + (void)res_ctx; 856 856 switch (stream->link->link_enc->transmitter) { 857 857 case TRANSMITTER_UNIPHY_A: 858 858 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; ··· 877 875 struct dc_state *context, 878 876 struct dc_stream_state *stream) 879 877 { 878 878 + (void)dc; 880 879 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 881 880 882 881 if (!pipe_ctx) ··· 895 892 struct dc_state *context, 896 893 enum dc_validate_mode validate_mode) 897 894 { 895 895 + (void)validate_mode; 898 896 bool result = false; 899 897 900 898 DC_LOG_BANDWIDTH_CALCS( ··· 1041 1037 struct dc *dc, 1042 1038 struct dc_state *context) 1043 1039 { 1040 1040 + (void)dc; 1044 1041 if (!dce112_validate_surface_sets(context)) 1045 1042 return DC_FAIL_SURFACE_VALIDATE; 1046 1043

+1

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

reviewed

··· 712 712 struct dc_context *ctx, 713 713 const struct encoder_init_data *enc_init_data) 714 714 { 715 715 + (void)ctx; 715 716 struct dce110_link_encoder *enc110 = 716 717 kzalloc_obj(struct dce110_link_encoder); 717 718 int link_regs_id;

+1

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

reviewed

··· 734 734 struct dc_context *ctx, 735 735 const struct encoder_init_data *enc_init_data) 736 736 { 737 737 + (void)ctx; 737 738 struct dce110_link_encoder *enc110 = 738 739 kzalloc_obj(struct dce110_link_encoder); 739 740 int link_regs_id;

+3

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

reviewed

··· 736 736 struct dc_context *ctx, 737 737 const struct encoder_init_data *enc_init_data) 738 738 { 739 739 + (void)ctx; 739 740 struct dcn10_link_encoder *enc10 = 740 741 kzalloc_obj(struct dcn10_link_encoder); 741 742 int link_regs_id; ··· 1050 1049 struct dc_state *context, 1051 1050 struct dc_stream_state *stream) 1052 1051 { 1052 1052 + (void)dc; 1053 1053 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 1054 1054 1055 1055 if (!pipe_ctx) ··· 1085 1083 const struct resource_pool *pool, 1086 1084 const struct pipe_ctx *opp_head_pipe) 1087 1085 { 1086 1086 + (void)cur_ctx; 1088 1087 struct resource_context *res_ctx = &new_ctx->res_ctx; 1089 1088 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream); 1090 1089 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

+6

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

reviewed

··· 916 916 struct dc_context *ctx, 917 917 const struct encoder_init_data *enc_init_data) 918 918 { 919 919 + (void)ctx; 919 920 struct dcn20_link_encoder *enc20 = 920 921 kzalloc_obj(struct dcn20_link_encoder); 921 922 int link_regs_id; ··· 1311 1310 1312 1311 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1313 1312 { 1313 1313 + (void)dc; 1314 1314 enum dc_status status = DC_OK; 1315 1315 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 1316 1316 ··· 1539 1537 struct pipe_ctx *primary_pipe, 1540 1538 struct pipe_ctx *secondary_pipe) 1541 1539 { 1540 1540 + (void)res_ctx; 1542 1541 int pipe_idx = secondary_pipe->pipe_idx; 1543 1542 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1544 1543 ··· 1685 1682 const struct resource_pool *pool, 1686 1683 const struct pipe_ctx *primary_pipe) 1687 1684 { 1685 1685 + (void)pool; 1688 1686 struct pipe_ctx *secondary_pipe = NULL; 1689 1687 1690 1688 if (dc && primary_pipe) { ··· 2165 2161 const struct resource_pool *pool, 2166 2162 const struct pipe_ctx *opp_head) 2167 2163 { 2164 2164 + (void)cur_ctx; 2168 2165 struct resource_context *res_ctx = &new_ctx->res_ctx; 2169 2166 struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream); 2170 2167 struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master); ··· 2348 2343 2349 2344 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 2350 2345 { 2346 2346 + (void)hw_internal_rev; 2351 2347 return DML_PROJECT_NAVI10v2; 2352 2348 } 2353 2349

+1

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

reviewed

··· 1299 1299 struct dc_context *ctx, 1300 1300 const struct encoder_init_data *enc_init_data) 1301 1301 { 1302 1302 + (void)ctx; 1302 1303 struct dcn21_link_encoder *enc21 = 1303 1304 kzalloc_obj(struct dcn21_link_encoder); 1304 1305 int link_regs_id;

+1

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

reviewed

··· 924 924 struct dc_context *ctx, 925 925 const struct encoder_init_data *enc_init_data) 926 926 { 927 927 + (void)ctx; 927 928 struct dcn20_link_encoder *enc20 = 928 929 kzalloc_obj(struct dcn20_link_encoder); 929 930

+1

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

reviewed

··· 880 880 struct dc_context *ctx, 881 881 const struct encoder_init_data *enc_init_data) 882 882 { 883 883 + (void)ctx; 883 884 struct dcn20_link_encoder *enc20 = 884 885 kzalloc_obj(struct dcn20_link_encoder); 885 886

+1

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

reviewed

··· 894 894 struct dc_context *ctx, 895 895 const struct encoder_init_data *enc_init_data) 896 896 { 897 897 + (void)ctx; 897 898 struct dcn20_link_encoder *enc20 = kzalloc_obj(struct dcn20_link_encoder); 898 899 899 900 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

+1

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

reviewed

··· 839 839 struct dc_context *ctx, 840 840 const struct encoder_init_data *enc_init_data) 841 841 { 842 842 + (void)ctx; 842 843 struct dcn20_link_encoder *enc20 = kzalloc_obj(struct dcn20_link_encoder); 843 844 844 845 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

+2

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

reviewed

··· 1090 1090 struct dc_context *ctx, 1091 1091 const struct encoder_init_data *enc_init_data) 1092 1092 { 1093 1093 + (void)ctx; 1093 1094 struct dcn20_link_encoder *enc20 = 1094 1095 kzalloc_obj(struct dcn20_link_encoder); 1095 1096 ··· 2244 2243 struct pipe_ctx *pipes, 2245 2244 struct audio_output *audio_output) 2246 2245 { 2246 2246 + (void)link_setting; 2247 2247 struct dc_state *state = link->dc->current_state; 2248 2248 int i; 2249 2249

+1

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

reviewed

··· 1148 1148 struct dc_context *ctx, 1149 1149 const struct encoder_init_data *enc_init_data) 1150 1150 { 1151 1151 + (void)ctx; 1151 1152 struct dcn20_link_encoder *enc20 = 1152 1153 kzalloc_obj(struct dcn20_link_encoder); 1153 1154

+1

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

reviewed

··· 1089 1089 struct dc_context *ctx, 1090 1090 const struct encoder_init_data *enc_init_data) 1091 1091 { 1092 1092 + (void)ctx; 1092 1093 struct dcn20_link_encoder *enc20 = 1093 1094 kzalloc_obj(struct dcn20_link_encoder); 1094 1095

+1

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

reviewed

··· 1082 1082 struct dc_context *ctx, 1083 1083 const struct encoder_init_data *enc_init_data) 1084 1084 { 1085 1085 + (void)ctx; 1085 1086 struct dcn20_link_encoder *enc20 = 1086 1087 kzalloc_obj(struct dcn20_link_encoder); 1087 1088

+1

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

reviewed

··· 41 41 struct pipe_ctx *pipe_ctx, 42 42 bool ignore_cursor_buf) 43 43 { 44 44 + (void)dc; 44 45 struct hubp *hubp = pipe_ctx->plane_res.hubp; 45 46 uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 46 47 uint32_t cursor_mall_size_bytes = 0;

+3

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

reviewed

··· 1698 1698 1699 1699 static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 1700 1700 { 1701 1701 + (void)bw_params; 1701 1702 dc_assert_fp_enabled(); 1702 1703 1703 1704 if (dc->current_state && dc->current_state->bw_ctx.dml2) ··· 1775 1774 struct dc_state *state, 1776 1775 const struct dc_stream_state *stream) 1777 1776 { 1777 1777 + (void)state; 1778 1778 + (void)stream; 1778 1779 return dc->caps.max_cursor_size; 1779 1780 } 1780 1781 static struct resource_funcs dcn42_res_pool_funcs = {

+1

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

reviewed

··· 159 159 160 160 static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) 161 161 { 162 162 + (void)config; 162 163 /* Individual modification can be overwritten even if it was obtained by a previous function. 163 164 * Modifications are acquired in order of priority (lowest to highest). 164 165 */