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linux
arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY
Only one PCIe controller has been described so far, but the SC7280 has
two controllers/phys. Describe the second one as well.
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250811-sc7280-pcie0-v1-1-6093e5b208f9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Bjorn Andersson
and committed by
Bjorn Andersson
f8328b75
ce4d0784
+134
+134
arch/arm64/boot/dts/qcom/sc7280.dtsi
+134
arch/arm64/boot/dts/qcom/sc7280.dtsi
···
2200
2200
qcom,smem-state-names = "wlan-smp2p-out";
2201
2201
};
2202
2202
2203
+
pcie0: pcie@1c00000 {
2204
+
compatible = "qcom,pcie-sc7280";
2205
+
reg = <0 0x01c00000 0 0x3000>,
2206
+
<0 0x60000000 0 0xf1d>,
2207
+
<0 0x60000f20 0 0xa8>,
2208
+
<0 0x60001000 0 0x1000>,
2209
+
<0 0x60100000 0 0x100000>,
2210
+
<0 0x01c03000 0 0x1000>;
2211
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2212
+
device_type = "pci";
2213
+
linux,pci-domain = <0>;
2214
+
bus-range = <0x00 0xff>;
2215
+
num-lanes = <1>;
2216
+
2217
+
#address-cells = <3>;
2218
+
#size-cells = <2>;
2219
+
2220
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2221
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2222
+
2223
+
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2224
+
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2225
+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2226
+
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2227
+
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2228
+
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2229
+
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2230
+
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2231
+
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2232
+
interrupt-names = "msi0",
2233
+
"msi1",
2234
+
"msi2",
2235
+
"msi3",
2236
+
"msi4",
2237
+
"msi5",
2238
+
"msi6",
2239
+
"msi7",
2240
+
"global";
2241
+
#interrupt-cells = <1>;
2242
+
interrupt-map-mask = <0 0 0 0x7>;
2243
+
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2244
+
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
2245
+
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
2246
+
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
2247
+
2248
+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2249
+
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
2250
+
<&pcie0_phy>,
2251
+
<&rpmhcc RPMH_CXO_CLK>,
2252
+
<&gcc GCC_PCIE_0_AUX_CLK>,
2253
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2254
+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2255
+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2256
+
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2257
+
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2258
+
<&gcc GCC_DDRSS_PCIE_SF_CLK>,
2259
+
<&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
2260
+
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
2261
+
clock-names = "pipe",
2262
+
"pipe_mux",
2263
+
"phy_pipe",
2264
+
"ref",
2265
+
"aux",
2266
+
"cfg",
2267
+
"bus_master",
2268
+
"bus_slave",
2269
+
"slave_q2a",
2270
+
"tbu",
2271
+
"ddrss_sf_tbu",
2272
+
"aggre0",
2273
+
"aggre1";
2274
+
2275
+
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2276
+
<0x100 &apps_smmu 0x1c01 0x1>;
2277
+
2278
+
resets = <&gcc GCC_PCIE_0_BCR>;
2279
+
reset-names = "pci";
2280
+
2281
+
power-domains = <&gcc GCC_PCIE_0_GDSC>;
2282
+
2283
+
phys = <&pcie0_phy>;
2284
+
phy-names = "pciephy";
2285
+
2286
+
pinctrl-names = "default";
2287
+
pinctrl-0 = <&pcie0_clkreq_n>;
2288
+
dma-coherent;
2289
+
2290
+
status = "disabled";
2291
+
2292
+
pcie0_port: pcie@0 {
2293
+
device_type = "pci";
2294
+
reg = <0x0 0x0 0x0 0x0 0x0>;
2295
+
bus-range = <0x01 0xff>;
2296
+
2297
+
#address-cells = <3>;
2298
+
#size-cells = <2>;
2299
+
ranges;
2300
+
};
2301
+
};
2302
+
2303
+
pcie0_phy: phy@1c06000 {
2304
+
compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2305
+
reg = <0 0x01c06000 0 0x1000>;
2306
+
2307
+
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2308
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2309
+
<&gcc GCC_PCIE_CLKREF_EN>,
2310
+
<&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
2311
+
<&gcc GCC_PCIE_0_PIPE_CLK>;
2312
+
clock-names = "aux",
2313
+
"cfg_ahb",
2314
+
"ref",
2315
+
"refgen",
2316
+
"pipe";
2317
+
2318
+
clock-output-names = "pcie_0_pipe_clk";
2319
+
#clock-cells = <0>;
2320
+
2321
+
#phy-cells = <0>;
2322
+
2323
+
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2324
+
reset-names = "phy";
2325
+
2326
+
assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
2327
+
assigned-clock-rates = <100000000>;
2328
+
2329
+
status = "disabled";
2330
+
};
2331
+
2203
2332
pcie1: pcie@1c08000 {
2204
2333
compatible = "qcom,pcie-sc7280";
2205
2334
reg = <0 0x01c08000 0 0x3000>,
···
5406
5277
mi2s1_ws: mi2s1-ws-state {
5407
5278
pins = "gpio108";
5408
5279
function = "mi2s1_ws";
5280
+
};
5281
+
5282
+
pcie0_clkreq_n: pcie0-clkreq-n-state {
5283
+
pins = "gpio88";
5284
+
function = "pcie0_clkreqn";
5409
5285
};
5410
5286
5411
5287
pcie1_clkreq_n: pcie1-clkreq-n-state {