Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into master
Pull clk fixes from Stephen Boyd:
"A couple build fixes for issues exposed this merge window and a fix
for the eMMC clk on AST2600 SoCs that fixes the rate that is
calculated by the clk framework"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: Specify IOMEM dependency for HSDK pll driver
clk: AST2600: Add mux for EMMC clock
clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
+43
-8
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
+41
-8
drivers/clk/clk-ast2600.c
+41
-8
drivers/clk/clk-ast2600.c
···
131
131
{ 0 }
132
132
};
133
133
134
+
static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
135
+
{ 0x0, 2 },
136
+
{ 0x1, 4 },
137
+
{ 0x2, 6 },
138
+
{ 0x3, 8 },
139
+
{ 0x4, 10 },
140
+
{ 0x5, 12 },
141
+
{ 0x6, 14 },
142
+
{ 0x7, 16 },
143
+
{ 0 }
144
+
};
145
+
134
146
static const struct clk_div_table ast2600_mac_div_table[] = {
135
147
{ 0x0, 4 },
136
148
{ 0x1, 4 },
···
402
390
return hw;
403
391
}
404
392
393
+
static const char *const emmc_extclk_parent_names[] = {
394
+
"emmc_extclk_hpll_in",
395
+
"mpll",
396
+
};
397
+
405
398
static const char * const vclk_parent_names[] = {
406
399
"dpll",
407
400
"d1pll",
···
476
459
return PTR_ERR(hw);
477
460
aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
478
461
479
-
/* EMMC ext clock divider */
480
-
hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
481
-
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
482
-
&aspeed_g6_clk_lock);
462
+
/* EMMC ext clock */
463
+
hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
464
+
0, 1, 2);
483
465
if (IS_ERR(hw))
484
466
return PTR_ERR(hw);
485
-
hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
486
-
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
487
-
ast2600_div_table,
488
-
&aspeed_g6_clk_lock);
467
+
468
+
hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
469
+
emmc_extclk_parent_names,
470
+
ARRAY_SIZE(emmc_extclk_parent_names), 0,
471
+
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
472
+
0, &aspeed_g6_clk_lock);
473
+
if (IS_ERR(hw))
474
+
return PTR_ERR(hw);
475
+
476
+
hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
477
+
0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
478
+
15, 0, &aspeed_g6_clk_lock);
479
+
if (IS_ERR(hw))
480
+
return PTR_ERR(hw);
481
+
482
+
hw = clk_hw_register_divider_table(dev, "emmc_extclk",
483
+
"emmc_extclk_gate", 0,
484
+
scu_g6_base +
485
+
ASPEED_G6_CLK_SELECTION1, 12,
486
+
3, 0, ast2600_emmc_extclk_div_table,
487
+
&aspeed_g6_clk_lock);
489
488
if (IS_ERR(hw))
490
489
return PTR_ERR(hw);
491
490
aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;