Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.15-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- platform updates for setting up clock correctly
- fixes to accomodate newer gcc (__builtin_trap, removed inline asm
modifier)
- other fixes
* tag 'arc-4.15-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: handle gcc generated __builtin_trap for older compiler
ARC: handle gcc generated __builtin_trap()
ARC: uaccess: dont use "l" gcc inline asm constraint modifier
ARC: [plat-axs103] refactor the quad core DT quirk code
ARC: [plat-axs103]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk] Switch DisplayLink driver from fbdev to DRM
arc: do not use __print_symbol()
ARC: Fix detection of dual-issue enabled
+57
-58
+8
arch/arc/boot/dts/axc003.dtsi
+8
arch/arc/boot/dts/axc003.dtsi
···
35
35
reg = <0x80 0x10>, <0x100 0x10>;
36
36
#clock-cells = <0>;
37
37
clocks = <&input_clk>;
38
+
39
+
/*
40
+
* Set initial core pll output frequency to 90MHz.
41
+
* It will be applied at the core pll driver probing
42
+
* on early boot.
43
+
*/
44
+
assigned-clocks = <&core_clk>;
45
+
assigned-clock-rates = <90000000>;
38
46
};
39
47
40
48
core_intc: archs-intc@cpu {
+8
arch/arc/boot/dts/axc003_idu.dtsi
+8
arch/arc/boot/dts/axc003_idu.dtsi
···
35
35
reg = <0x80 0x10>, <0x100 0x10>;
36
36
#clock-cells = <0>;
37
37
clocks = <&input_clk>;
38
+
39
+
/*
40
+
* Set initial core pll output frequency to 100MHz.
41
+
* It will be applied at the core pll driver probing
42
+
* on early boot.
43
+
*/
44
+
assigned-clocks = <&core_clk>;
45
+
assigned-clock-rates = <100000000>;
38
46
};
39
47
40
48
core_intc: archs-intc@cpu {
+8
arch/arc/boot/dts/hsdk.dts
+8
arch/arc/boot/dts/hsdk.dts
···
114
114
reg = <0x00 0x10>, <0x14B8 0x4>;
115
115
#clock-cells = <0>;
116
116
clocks = <&input_clk>;
117
+
118
+
/*
119
+
* Set initial core pll output frequency to 1GHz.
120
+
* It will be applied at the core pll driver probing
121
+
* on early boot.
122
+
*/
123
+
assigned-clocks = <&core_clk>;
124
+
assigned-clock-rates = <1000000000>;
117
125
};
118
126
119
127
serial: serial@5000 {
+3
-2
arch/arc/configs/hsdk_defconfig
+3
-2
arch/arc/configs/hsdk_defconfig
···
49
49
CONFIG_SERIAL_OF_PLATFORM=y
50
50
# CONFIG_HW_RANDOM is not set
51
51
# CONFIG_HWMON is not set
52
+
CONFIG_DRM=y
53
+
# CONFIG_DRM_FBDEV_EMULATION is not set
54
+
CONFIG_DRM_UDL=y
52
55
CONFIG_FB=y
53
-
CONFIG_FB_UDL=y
54
56
CONFIG_FRAMEBUFFER_CONSOLE=y
55
-
CONFIG_USB=y
56
57
CONFIG_USB_EHCI_HCD=y
57
58
CONFIG_USB_EHCI_HCD_PLATFORM=y
58
59
CONFIG_USB_OHCI_HCD=y
+3
-2
arch/arc/include/asm/uaccess.h
+3
-2
arch/arc/include/asm/uaccess.h
···
668
668
return 0;
669
669
670
670
__asm__ __volatile__(
671
+
" mov lp_count, %5 \n"
671
672
" lp 3f \n"
672
673
"1: ldb.ab %3, [%2, 1] \n"
673
674
" breq.d %3, 0, 3f \n"
···
685
684
" .word 1b, 4b \n"
686
685
" .previous \n"
687
686
: "+r"(res), "+r"(dst), "+r"(src), "=r"(val)
688
-
: "g"(-EFAULT), "l"(count)
689
-
: "memory");
687
+
: "g"(-EFAULT), "r"(count)
688
+
: "lp_count", "lp_start", "lp_end", "memory");
690
689
691
690
return res;
692
691
}
+1
-1
arch/arc/kernel/setup.c
+1
-1
arch/arc/kernel/setup.c
+1
-1
arch/arc/kernel/stacktrace.c
+1
-1
arch/arc/kernel/stacktrace.c
+14
arch/arc/kernel/traps.c
+14
arch/arc/kernel/traps.c
···
83
83
DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", __weak do_memory_error, BUS_ADRERR)
84
84
DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
85
85
DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
86
+
DO_ERROR_INFO(SIGSEGV, "gcc generated __builtin_trap", do_trap5_error, 0)
86
87
87
88
/*
88
89
* Entry Point for Misaligned Data access Exception, for emulating in software
···
116
115
* Thus TRAP_S <n> can be used for specific purpose
117
116
* -1 used for software breakpointing (gdb)
118
117
* -2 used by kprobes
118
+
* -5 __builtin_trap() generated by gcc (2018.03 onwards) for toggle such as
119
+
* -fno-isolate-erroneous-paths-dereference
119
120
*/
120
121
void do_non_swi_trap(unsigned long address, struct pt_regs *regs)
121
122
{
···
137
134
kgdb_trap(regs);
138
135
break;
139
136
137
+
case 5:
138
+
do_trap5_error(address, regs);
139
+
break;
140
140
default:
141
141
break;
142
142
}
···
160
154
return;
161
155
162
156
insterror_is_error(address, regs);
157
+
}
158
+
159
+
/*
160
+
* abort() call generated by older gcc for __builtin_trap()
161
+
*/
162
+
void abort(void)
163
+
{
164
+
__asm__ __volatile__("trap_s 5\n");
163
165
}
+3
arch/arc/kernel/troubleshoot.c
+3
arch/arc/kernel/troubleshoot.c
+8
-10
arch/arc/plat-axs10x/axs10x.c
+8
-10
arch/arc/plat-axs10x/axs10x.c
···
317
317
* Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
318
318
* of fudging the freq in DT
319
319
*/
320
+
#define AXS103_QUAD_CORE_CPU_FREQ_HZ 50000000
321
+
320
322
unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
321
323
if (num_cores > 2) {
322
-
u32 freq = 50, orig;
323
-
/*
324
-
* TODO: use cpu node "cpu-freq" param instead of platform-specific
325
-
* "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
326
-
*/
324
+
u32 freq;
327
325
int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
328
326
const struct fdt_property *prop;
329
327
330
328
prop = fdt_get_property(initial_boot_params, off,
331
-
"clock-frequency", NULL);
332
-
orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000;
329
+
"assigned-clock-rates", NULL);
330
+
freq = be32_to_cpu(*(u32 *)(prop->data));
333
331
334
332
/* Patching .dtb in-place with new core clock value */
335
-
if (freq != orig ) {
336
-
freq = cpu_to_be32(freq * 1000000);
333
+
if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) {
334
+
freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ);
337
335
fdt_setprop_inplace(initial_boot_params, off,
338
-
"clock-frequency", &freq, sizeof(freq));
336
+
"assigned-clock-rates", &freq, sizeof(freq));
339
337
}
340
338
}
341
339
#endif
-42
arch/arc/plat-hsdk/platform.c
-42
arch/arc/plat-hsdk/platform.c
···
38
38
#define CREG_PAE (CREG_BASE + 0x180)
39
39
#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
40
40
41
-
#define CREG_CORE_IF_CLK_DIV (CREG_BASE + 0x4B8)
42
-
#define CREG_CORE_IF_CLK_DIV_2 0x1
43
-
#define CGU_BASE ARC_PERIPHERAL_BASE
44
-
#define CGU_PLL_STATUS (ARC_PERIPHERAL_BASE + 0x4)
45
-
#define CGU_PLL_CTRL (ARC_PERIPHERAL_BASE + 0x0)
46
-
#define CGU_PLL_STATUS_LOCK BIT(0)
47
-
#define CGU_PLL_STATUS_ERR BIT(1)
48
-
#define CGU_PLL_CTRL_1GHZ 0x3A10
49
-
#define HSDK_PLL_LOCK_TIMEOUT 500
50
-
51
-
#define HSDK_PLL_LOCKED() \
52
-
!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
53
-
54
-
#define HSDK_PLL_ERR() \
55
-
!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
56
-
57
-
static void __init hsdk_set_cpu_freq_1ghz(void)
58
-
{
59
-
u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
60
-
61
-
/*
62
-
* As we set cpu clock which exceeds 500MHz, the divider for the interface
63
-
* clock must be programmed to div-by-2.
64
-
*/
65
-
iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
66
-
67
-
/* Set cpu clock to 1GHz */
68
-
iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
69
-
70
-
while (!HSDK_PLL_LOCKED() && timeout--)
71
-
cpu_relax();
72
-
73
-
if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
74
-
pr_err("Failed to setup CPU frequency to 1GHz!");
75
-
}
76
-
77
41
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
78
42
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
79
43
#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
···
62
98
* minimum possible div-by-2.
63
99
*/
64
100
iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
65
-
66
-
/*
67
-
* Setup CPU frequency to 1GHz.
68
-
* TODO: remove it after smart hsdk pll driver will be introduced.
69
-
*/
70
-
hsdk_set_cpu_freq_1ghz();
71
101
}
72
102
73
103
static const char *hsdk_compat[] __initconst = {