Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: mediatek: xsphy: support type switch by pericfg
Patch from Sam Shih <sam.shih@mediatek.com> found in MediaTek SDK
released under GPL.
Get syscon and use it to set the PHY type.
Extend support to PCIe and SGMII mode in addition to USB2 and USB3.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250422132438.15735-7-linux@fw-web.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Daniel Golle
and committed by
Vinod Koul
f85eb659
b484b25a
+84
-1
+84
-1
drivers/phy/mediatek/phy-mtk-xsphy.c
+84
-1
drivers/phy/mediatek/phy-mtk-xsphy.c
···
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "phy-mtk-io.h"
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···
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#define XSP_SR_COEF_DIVISOR 1000
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#define XSP_FM_DET_CYCLE_CNT 1024
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/* PHY switch between pcie/usb3/sgmii */
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#define USB_PHY_SWITCH_CTRL 0x0
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#define RG_PHY_SW_TYPE GENMASK(3, 0)
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#define RG_PHY_SW_PCIE 0x0
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#define RG_PHY_SW_USB3 0x1
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#define RG_PHY_SW_SGMII 0x2
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struct xsphy_instance {
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struct phy *phy;
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void __iomem *port_base;
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struct clk *ref_clk; /* reference clock of anolog phy */
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u32 index;
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u32 type;
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struct regmap *type_sw;
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u32 type_sw_reg;
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u32 type_sw_index;
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/* only for HQA test */
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int efuse_intr;
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int efuse_tx_imp;
···
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inst->efuse_intr, inst->efuse_tx_imp,
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inst->efuse_rx_imp);
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break;
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case PHY_TYPE_PCIE:
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case PHY_TYPE_SGMII:
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/* nothing to do */
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break;
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default:
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dev_err(xsphy->dev, "incompatible phy type\n");
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return;
···
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RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
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}
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/* type switch for usb3/pcie/sgmii */
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static int phy_type_syscon_get(struct xsphy_instance *instance,
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struct device_node *dn)
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{
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struct of_phandle_args args;
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int ret;
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/* type switch function is optional */
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if (!of_property_present(dn, "mediatek,syscon-type"))
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return 0;
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ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
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2, 0, &args);
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if (ret)
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return ret;
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instance->type_sw_reg = args.args[0];
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instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
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instance->type_sw = syscon_node_to_regmap(args.np);
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of_node_put(args.np);
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dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
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instance->type_sw_reg, instance->type_sw_index);
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return PTR_ERR_OR_ZERO(instance->type_sw);
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}
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static int phy_type_set(struct xsphy_instance *instance)
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{
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int type;
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u32 offset;
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if (!instance->type_sw)
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return 0;
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switch (instance->type) {
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case PHY_TYPE_USB3:
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type = RG_PHY_SW_USB3;
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break;
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case PHY_TYPE_PCIE:
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type = RG_PHY_SW_PCIE;
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break;
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case PHY_TYPE_SGMII:
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type = RG_PHY_SW_SGMII;
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break;
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case PHY_TYPE_USB2:
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default:
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return 0;
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}
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offset = instance->type_sw_index * BITS_PER_BYTE;
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regmap_update_bits(instance->type_sw, instance->type_sw_reg,
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RG_PHY_SW_TYPE << offset, type << offset);
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return 0;
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}
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static int mtk_phy_init(struct phy *phy)
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{
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struct xsphy_instance *inst = phy_get_drvdata(phy);
···
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break;
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case PHY_TYPE_USB3:
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u3_phy_props_set(xsphy, inst);
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break;
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case PHY_TYPE_PCIE:
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case PHY_TYPE_SGMII:
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/* nothing to do, only used to set type */
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break;
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default:
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dev_err(xsphy->dev, "incompatible phy type\n");
···
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inst->type = args->args[0];
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if (!(inst->type == PHY_TYPE_USB2 ||
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inst->type == PHY_TYPE_USB3)) {
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inst->type == PHY_TYPE_USB3 ||
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inst->type == PHY_TYPE_PCIE ||
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inst->type == PHY_TYPE_SGMII)) {
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dev_err(dev, "unsupported phy type: %d\n", inst->type);
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return ERR_PTR(-EINVAL);
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}
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phy_parse_property(xsphy, inst);
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phy_type_set(inst);
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return inst->phy;
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}
···
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dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
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return PTR_ERR(inst->ref_clk);
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}
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retval = phy_type_syscon_get(inst, child_np);
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if (retval)
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return retval;
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}
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provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);