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Merge tag 'spi-fix-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi fixes from Mark Brown:
"A few fairly small fixes for v6.13, the most substatial one being
disabling STIG mode for Cadence QSPI controllers on Altera SoCFPGA
platforms since it doesn't work"

* tag 'spi-fix-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA.
spi: rockchip: Fix PM runtime count on no-op cs
spi: aspeed: Fix an error handling path in aspeed_spi_[read|write]_user()

+28 -6
+6 -4
drivers/spi/spi-aspeed-smc.c
··· 239 239 240 240 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode); 241 241 if (ret < 0) 242 - return ret; 242 + goto stop_user; 243 243 244 244 if (op->dummy.buswidth && op->dummy.nbytes) { 245 245 for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++) ··· 249 249 aspeed_spi_set_io_mode(chip, io_mode); 250 250 251 251 aspeed_spi_read_from_ahb(buf, chip->ahb_base, len); 252 + stop_user: 252 253 aspeed_spi_stop_user(chip); 253 - return 0; 254 + return ret; 254 255 } 255 256 256 257 static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip, ··· 262 261 aspeed_spi_start_user(chip); 263 262 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode); 264 263 if (ret < 0) 265 - return ret; 264 + goto stop_user; 266 265 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes); 266 + stop_user: 267 267 aspeed_spi_stop_user(chip); 268 - return 0; 268 + return ret; 269 269 } 270 270 271 271 /* support for 1-1-1, 1-1-2 or 1-1-4 */
+8 -2
drivers/spi/spi-cadence-quadspi.c
··· 43 43 #define CQSPI_SLOW_SRAM BIT(4) 44 44 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) 45 45 #define CQSPI_RD_NO_IRQ BIT(6) 46 + #define CQSPI_DISABLE_STIG_MODE BIT(7) 46 47 47 48 /* Capabilities */ 48 49 #define CQSPI_SUPPORTS_OCTAL BIT(0) ··· 104 103 bool apb_ahb_hazard; 105 104 106 105 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ 106 + bool disable_stig_mode; 107 107 108 108 const struct cqspi_driver_platdata *ddata; 109 109 }; ··· 1418 1416 * reads, prefer STIG mode for such small reads. 1419 1417 */ 1420 1418 if (!op->addr.nbytes || 1421 - op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) 1419 + (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && 1420 + !cqspi->disable_stig_mode)) 1422 1421 return cqspi_command_read(f_pdata, op); 1423 1422 1424 1423 return cqspi_read(f_pdata, op); ··· 1883 1880 if (ret) 1884 1881 goto probe_reset_failed; 1885 1882 } 1883 + if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) 1884 + cqspi->disable_stig_mode = true; 1886 1885 1887 1886 if (of_device_is_compatible(pdev->dev.of_node, 1888 1887 "xlnx,versal-ospi-1.0")) { ··· 2048 2043 static const struct cqspi_driver_platdata socfpga_qspi = { 2049 2044 .quirks = CQSPI_DISABLE_DAC_MODE 2050 2045 | CQSPI_NO_SUPPORT_WR_COMPLETION 2051 - | CQSPI_SLOW_SRAM, 2046 + | CQSPI_SLOW_SRAM 2047 + | CQSPI_DISABLE_STIG_MODE, 2052 2048 }; 2053 2049 2054 2050 static const struct cqspi_driver_platdata versal_ospi = {
+14
drivers/spi/spi-rockchip.c
··· 241 241 struct spi_controller *ctlr = spi->controller; 242 242 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 243 243 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable; 244 + bool cs_actual; 245 + 246 + /* 247 + * SPI subsystem tries to avoid no-op calls that would break the PM 248 + * refcount below. It can't however for the first time it is used. 249 + * To detect this case we read it here and bail out early for no-ops. 250 + */ 251 + if (spi_get_csgpiod(spi, 0)) 252 + cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 1); 253 + else 254 + cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 255 + BIT(spi_get_chipselect(spi, 0))); 256 + if (unlikely(cs_actual == cs_asserted)) 257 + return; 244 258 245 259 if (cs_asserted) { 246 260 /* Keep things powered as long as CS is asserted */