Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2024-11-16' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Final week of fixes, lots of small amdgpu fixes, some i915 and xe
fixes, the nouveau changes fix a recent regression and some laptop
panel black screens, then a couple of other misc ones.
It's probably a little busier than I'd like, but each fix seems fine.
amdgpu:
- PSR fix
- Panel replay fixes
- DML fix
- vblank power fix
- Fix video caps
- SMU 14.0 fix
- GPUVM fix
- MES 12 fix
- APU carve out fix
- DC vbios fix
- NBIO fix
i915:
- Don't load GSC on ARL-H and ARL-U if too old FW
- Avoid potential OOPS in enabling/disabling TV output
xe:
- Fix unlock on exec ioctl error path
- Fix hibernation on LNL due to ggtt getting lost
- Fix missing runtime PM in OA release
bridge:
- tc358768: Fix DSI command tx
nouveau:
- Fix GSP AUX error handling
- dp: Handle retires for AUX CH transfers with GSP
- fw: Sync DMA after setup
panthor:
- Fix partial BO mappings to GPU
rockchip:
- vop: Avoid null-ptr deref in plane-state check
vmwgfx:
- Avoid null-ptr deref in surface creation"
* tag 'drm-fixes-2024-11-16' of https://gitlab.freedesktop.org/drm/kernel: (27 commits)
drm/bridge: tc358768: Fix DSI command tx
drm/vmwgfx: avoid null_ptr_deref in vmw_framebuffer_surface_create_handle
nouveau/dp: handle retries for AUX CH transfers with GSP.
nouveau: handle EBUSY and EAGAIN for GSP aux errors.
nouveau: fw: sync dma after setup is called.
drm/xe/oa: Fix "Missing outer runtime PM protection" warning
drm/xe: handle flat ccs during hibernation on igpu
drm/xe: improve hibernation on igpu
drm/xe: Restore system memory GGTT mappings
drm/xe: Ensure all locks released in exec IOCTL
drm/panthor: Fix handling of partial GPU mapping of BOs
drm/amd: Fix initialization mistake for NBIO 7.7.0
Revert "drm/amd/display: parse umc_info or vram_info based on ASIC"
drm/amd/display: Fix failure to read vram info due to static BP_RESULT
drm/amdgpu: enable GTT fallback handling for dGPUs only
drm/i915: Grab intel_display from the encoder to avoid potential oopsies
drm/i915/gsc: ARL-H and ARL-U need a newer GSC FW.
drm/amdgpu/mes12: correct kiq unmap latency
drm/amdgpu: fix check in gmc_v9_0_get_vm_pte()
drm/amd/pm: print pp_dpm_mclk in ascending order on SMU v14.0.0
...
+305
-197
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
···
161
161
* When GTT is just an alternative to VRAM make sure that we
162
162
* only use it as fallback and still try to fill up VRAM first.
163
163
*/
164
-
if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)
164
+
if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
165
+
!(adev->flags & AMD_IS_APU))
165
166
places[c].flags |= TTM_PL_FLAG_FALLBACK;
166
167
c++;
167
168
}
+8
-5
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+8
-5
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
···
1124
1124
uint64_t *flags)
1125
1125
{
1126
1126
struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1127
-
bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;
1128
-
bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT);
1127
+
bool is_vram = bo->tbo.resource &&
1128
+
bo->tbo.resource->mem_type == TTM_PL_VRAM;
1129
+
bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
1130
+
AMDGPU_GEM_CREATE_EXT_COHERENT);
1129
1131
bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
1130
1132
bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1131
1133
struct amdgpu_vm *vm = mapping->bo_va->base.vm;
1132
1134
unsigned int mtype_local, mtype;
1133
1135
bool snoop = false;
1134
1136
bool is_local;
1137
+
1138
+
dma_resv_assert_held(bo->tbo.base.resv);
1135
1139
1136
1140
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1137
1141
case IP_VERSION(9, 4, 1):
···
1255
1251
*flags &= ~AMDGPU_PTE_VALID;
1256
1252
}
1257
1253
1258
-
if (bo && bo->tbo.resource)
1259
-
gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo,
1260
-
mapping, flags);
1254
+
if ((*flags & AMDGPU_PTE_VALID) && bo)
1255
+
gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags);
1261
1256
}
1262
1257
1263
1258
static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
+1
-1
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
···
550
550
mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
551
551
mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
552
552
mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
553
-
mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
553
+
mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
554
554
555
555
return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
556
556
&mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
+6
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+6
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
···
247
247
if (def != data)
248
248
WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
249
249
250
+
switch (adev->ip_versions[NBIO_HWIP][0]) {
251
+
case IP_VERSION(7, 7, 0):
252
+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);
253
+
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data);
254
+
break;
255
+
}
250
256
}
251
257
252
258
static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+6
-6
drivers/gpu/drm/amd/amdgpu/nv.c
+6
-6
drivers/gpu/drm/amd/amdgpu/nv.c
···
67
67
68
68
/* Navi */
69
69
static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {
70
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
71
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
70
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
71
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
72
72
};
73
73
74
74
static const struct amdgpu_video_codecs nv_video_codecs_encode = {
···
94
94
95
95
/* Sienna Cichlid */
96
96
static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
97
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
98
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
97
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
98
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
99
99
};
100
100
101
101
static const struct amdgpu_video_codecs sc_video_codecs_encode = {
···
136
136
137
137
/* SRIOV Sienna Cichlid, not const since data is controlled by host */
138
138
static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {
139
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
140
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
139
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
140
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
141
141
};
142
142
143
143
static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {
+2
-2
drivers/gpu/drm/amd/amdgpu/soc15.c
+2
-2
drivers/gpu/drm/amd/amdgpu/soc15.c
···
90
90
/* Vega, Raven, Arcturus */
91
91
static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92
92
{
93
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
94
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
93
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
94
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
95
95
};
96
96
97
97
static const struct amdgpu_video_codecs vega_video_codecs_encode =
+6
-6
drivers/gpu/drm/amd/amdgpu/soc21.c
+6
-6
drivers/gpu/drm/amd/amdgpu/soc21.c
···
49
49
50
50
/* SOC21 */
51
51
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
52
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
52
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
53
53
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
54
54
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
55
55
};
56
56
57
57
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
58
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
58
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
59
59
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
60
60
};
61
61
···
96
96
97
97
/* SRIOV SOC21, not const since data is controlled by host */
98
98
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
100
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
99
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
100
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
101
101
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102
102
};
103
103
104
104
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
106
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
105
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
106
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
107
107
};
108
108
109
109
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
+1
-1
drivers/gpu/drm/amd/amdgpu/soc24.c
+1
-1
drivers/gpu/drm/amd/amdgpu/soc24.c
···
48
48
static const struct amd_ip_funcs soc24_common_ip_funcs;
49
49
50
50
static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_encode_array_vcn0[] = {
51
-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
51
+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
52
52
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
53
53
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
54
54
};
+4
-4
drivers/gpu/drm/amd/amdgpu/vi.c
+4
-4
drivers/gpu/drm/amd/amdgpu/vi.c
···
136
136
{
137
137
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
138
138
.max_width = 4096,
139
-
.max_height = 2304,
140
-
.max_pixels_per_frame = 4096 * 2304,
139
+
.max_height = 4096,
140
+
.max_pixels_per_frame = 4096 * 4096,
141
141
.max_level = 0,
142
142
},
143
143
{
144
144
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
145
145
.max_width = 4096,
146
-
.max_height = 2304,
147
-
.max_pixels_per_frame = 4096 * 2304,
146
+
.max_height = 4096,
147
+
.max_pixels_per_frame = 4096 * 4096,
148
148
.max_level = 0,
149
149
},
150
150
};
+60
-57
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+60
-57
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
6762
6762
if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
6763
6763
tf = TRANSFER_FUNC_GAMMA_22;
6764
6764
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6765
-
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6765
+
aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6766
6766
6767
6767
}
6768
6768
finish:
···
8875
8875
}
8876
8876
}
8877
8877
8878
+
static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
8879
+
const struct dm_crtc_state *acrtc_state,
8880
+
const u64 current_ts)
8881
+
{
8882
+
struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
8883
+
struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
8884
+
struct amdgpu_dm_connector *aconn =
8885
+
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8886
+
8887
+
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
8888
+
if (pr->config.replay_supported && !pr->replay_feature_enabled)
8889
+
amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
8890
+
else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8891
+
!psr->psr_feature_enabled)
8892
+
if (!aconn->disallow_edp_enter_psr)
8893
+
amdgpu_dm_link_setup_psr(acrtc_state->stream);
8894
+
}
8895
+
8896
+
/* Decrement skip count when SR is enabled and we're doing fast updates. */
8897
+
if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8898
+
(psr->psr_feature_enabled || pr->config.replay_supported)) {
8899
+
if (aconn->sr_skip_count > 0)
8900
+
aconn->sr_skip_count--;
8901
+
8902
+
/* Allow SR when skip count is 0. */
8903
+
acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
8904
+
8905
+
/*
8906
+
* If sink supports PSR SU/Panel Replay, there is no need to rely on
8907
+
* a vblank event disable request to enable PSR/RP. PSR SU/RP
8908
+
* can be enabled immediately once OS demonstrates an
8909
+
* adequate number of fast atomic commits to notify KMD
8910
+
* of update events. See `vblank_control_worker()`.
8911
+
*/
8912
+
if (acrtc_attach->dm_irq_params.allow_sr_entry &&
8913
+
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8914
+
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8915
+
#endif
8916
+
(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
8917
+
if (pr->replay_feature_enabled && !pr->replay_allow_active)
8918
+
amdgpu_dm_replay_enable(acrtc_state->stream, true);
8919
+
if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
8920
+
!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
8921
+
amdgpu_dm_psr_enable(acrtc_state->stream);
8922
+
}
8923
+
} else {
8924
+
acrtc_attach->dm_irq_params.allow_sr_entry = false;
8925
+
}
8926
+
}
8927
+
8878
8928
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8879
8929
struct drm_device *dev,
8880
8930
struct amdgpu_display_manager *dm,
···
9078
9028
* during the PSR-SU was disabled.
9079
9029
*/
9080
9030
if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
9081
-
acrtc_attach->dm_irq_params.allow_psr_entry &&
9031
+
acrtc_attach->dm_irq_params.allow_sr_entry &&
9082
9032
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
9083
9033
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
9084
9034
#endif
···
9253
9203
bundle->stream_update.abm_level = &acrtc_state->abm_level;
9254
9204
9255
9205
mutex_lock(&dm->dc_lock);
9256
-
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
9257
-
acrtc_state->stream->link->psr_settings.psr_allow_active)
9258
-
amdgpu_dm_psr_disable(acrtc_state->stream);
9206
+
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
9207
+
if (acrtc_state->stream->link->replay_settings.replay_allow_active)
9208
+
amdgpu_dm_replay_disable(acrtc_state->stream);
9209
+
if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9210
+
amdgpu_dm_psr_disable(acrtc_state->stream);
9211
+
}
9259
9212
mutex_unlock(&dm->dc_lock);
9260
9213
9261
9214
/*
···
9299
9246
dm_update_pflip_irq_state(drm_to_adev(dev),
9300
9247
acrtc_attach);
9301
9248
9302
-
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
9303
-
if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
9304
-
!acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
9305
-
struct amdgpu_dm_connector *aconn =
9306
-
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
9307
-
amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
9308
-
} else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
9309
-
!acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
9310
-
9311
-
struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
9312
-
acrtc_state->stream->dm_stream_context;
9313
-
9314
-
if (!aconn->disallow_edp_enter_psr)
9315
-
amdgpu_dm_link_setup_psr(acrtc_state->stream);
9316
-
}
9317
-
}
9318
-
9319
-
/* Decrement skip count when PSR is enabled and we're doing fast updates. */
9320
-
if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
9321
-
acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
9322
-
struct amdgpu_dm_connector *aconn =
9323
-
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
9324
-
9325
-
if (aconn->psr_skip_count > 0)
9326
-
aconn->psr_skip_count--;
9327
-
9328
-
/* Allow PSR when skip count is 0. */
9329
-
acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
9330
-
9331
-
/*
9332
-
* If sink supports PSR SU, there is no need to rely on
9333
-
* a vblank event disable request to enable PSR. PSR SU
9334
-
* can be enabled immediately once OS demonstrates an
9335
-
* adequate number of fast atomic commits to notify KMD
9336
-
* of update events. See `vblank_control_worker()`.
9337
-
*/
9338
-
if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
9339
-
acrtc_attach->dm_irq_params.allow_psr_entry &&
9340
-
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
9341
-
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
9342
-
#endif
9343
-
!acrtc_state->stream->link->psr_settings.psr_allow_active &&
9344
-
!aconn->disallow_edp_enter_psr &&
9345
-
(timestamp_ns -
9346
-
acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
9347
-
500000000)
9348
-
amdgpu_dm_psr_enable(acrtc_state->stream);
9349
-
} else {
9350
-
acrtc_attach->dm_irq_params.allow_psr_entry = false;
9351
-
}
9352
-
9249
+
amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
9353
9250
mutex_unlock(&dm->dc_lock);
9354
9251
}
9355
9252
···
12083
12080
break;
12084
12081
}
12085
12082
12086
-
while (j < EDID_LENGTH) {
12083
+
while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
12087
12084
struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
12088
12085
unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
12089
12086
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+2
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+2
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
···
266
266
* where the SU region is the full hactive*vactive region. See
267
267
* fill_dc_dirty_rects().
268
268
*/
269
-
if (vblank_work->stream && vblank_work->stream->link) {
269
+
if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) {
270
270
amdgpu_dm_crtc_set_panel_sr_feature(
271
271
vblank_work, vblank_work->enable,
272
-
vblank_work->acrtc->dm_irq_params.allow_psr_entry ||
273
-
vblank_work->stream->link->replay_settings.replay_feature_enabled);
272
+
vblank_work->acrtc->dm_irq_params.allow_sr_entry);
274
273
}
275
274
276
275
if (dm->active_vblank_irq_count == 0) {
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
+2
-4
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+2
-4
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
···
3122
3122
struct dc_vram_info *info)
3123
3123
{
3124
3124
struct bios_parser *bp = BP_FROM_DCB(dcb);
3125
-
static enum bp_result result = BP_RESULT_BADBIOSTABLE;
3125
+
enum bp_result result = BP_RESULT_BADBIOSTABLE;
3126
3126
struct atom_common_table_header *header;
3127
3127
struct atom_data_revision revision;
3128
3128
3129
3129
// vram info moved to umc_info for DCN4x
3130
-
if (dcb->ctx->dce_version >= DCN_VERSION_4_01 &&
3131
-
dcb->ctx->dce_version < DCN_VERSION_MAX &&
3132
-
info && DATA_TABLES(umc_info)) {
3130
+
if (info && DATA_TABLES(umc_info)) {
3133
3131
header = GET_IMAGE(struct atom_common_table_header,
3134
3132
DATA_TABLES(umc_info));
3135
3133
+3
drivers/gpu/drm/amd/display/dc/core/dc_state.c
+3
drivers/gpu/drm/amd/display/dc/core/dc_state.c
···
265
265
dc_state_copy_internal(new_state, src_state);
266
266
267
267
#ifdef CONFIG_DRM_AMD_DC_FP
268
+
new_state->bw_ctx.dml2 = NULL;
269
+
new_state->bw_ctx.dml2_dc_power_source = NULL;
270
+
268
271
if (src_state->bw_ctx.dml2 &&
269
272
!dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) {
270
273
dc_state_release(new_state);
+9
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+9
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
···
8
8
#include "dml2_pmo_dcn4_fams2.h"
9
9
10
10
static const double MIN_VACTIVE_MARGIN_PCT = 0.25; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding
11
+
static const double MIN_BLANK_STUTTER_FACTOR = 3.0;
11
12
12
13
static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = {
13
14
// VActive Preferred
···
2140
2139
struct dml2_pmo_instance *pmo = in_out->instance;
2141
2140
bool stutter_period_meets_z8_eco = true;
2142
2141
bool z8_stutter_optimization_too_expensive = false;
2142
+
bool stutter_optimization_too_expensive = false;
2143
2143
double line_time_us, vblank_nom_time_us;
2144
2144
2145
2145
unsigned int i;
···
2162
2160
line_time_us = (double)in_out->base_display_config->display_config.stream_descriptors[i].timing.h_total / (in_out->base_display_config->display_config.stream_descriptors[i].timing.pixel_clock_khz * 1000) * 1000000;
2163
2161
vblank_nom_time_us = line_time_us * in_out->base_display_config->display_config.stream_descriptors[i].timing.vblank_nom;
2164
2162
2165
-
if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us) {
2163
+
if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) {
2166
2164
z8_stutter_optimization_too_expensive = true;
2165
+
break;
2166
+
}
2167
+
2168
+
if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) {
2169
+
stutter_optimization_too_expensive = true;
2167
2170
break;
2168
2171
}
2169
2172
}
···
2186
2179
pmo->scratch.pmo_dcn4.z8_vblank_optimizable = false;
2187
2180
}
2188
2181
2189
-
if (pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0) {
2182
+
if (!stutter_optimization_too_expensive && pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0) {
2190
2183
pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us;
2191
2184
pmo->scratch.pmo_dcn4.num_stutter_candidates++;
2192
2185
}
+3
-2
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+3
-2
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
···
1132
1132
static int smu_v14_0_0_print_clk_levels(struct smu_context *smu,
1133
1133
enum smu_clk_type clk_type, char *buf)
1134
1134
{
1135
-
int i, size = 0, ret = 0;
1135
+
int i, idx, ret = 0, size = 0;
1136
1136
uint32_t cur_value = 0, value = 0, count = 0;
1137
1137
uint32_t min, max;
1138
1138
···
1168
1168
break;
1169
1169
1170
1170
for (i = 0; i < count; i++) {
1171
-
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, i, &value);
1171
+
idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
1172
+
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
1172
1173
if (ret)
1173
1174
break;
1174
1175
+19
-2
drivers/gpu/drm/bridge/tc358768.c
+19
-2
drivers/gpu/drm/bridge/tc358768.c
···
125
125
#define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
126
126
#define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
127
127
128
+
/* TC358768_DSICMD_TX (0x0600) register */
129
+
#define TC358768_DSI_CMDTX_DC_START BIT(0)
130
+
128
131
static const char * const tc358768_supplies[] = {
129
132
"vddc", "vddmipi", "vddio"
130
133
};
···
230
227
tmp |= val & mask;
231
228
if (tmp != orig)
232
229
tc358768_write(priv, reg, tmp);
230
+
}
231
+
232
+
static void tc358768_dsicmd_tx(struct tc358768_priv *priv)
233
+
{
234
+
u32 val;
235
+
236
+
/* start transfer */
237
+
tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START);
238
+
if (priv->error)
239
+
return;
240
+
241
+
/* wait transfer completion */
242
+
priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val,
243
+
(val & TC358768_DSI_CMDTX_DC_START) == 0,
244
+
100, 100000);
233
245
}
234
246
235
247
static int tc358768_sw_reset(struct tc358768_priv *priv)
···
534
516
}
535
517
}
536
518
537
-
/* start transfer */
538
-
tc358768_write(priv, TC358768_DSICMD_TX, 1);
519
+
tc358768_dsicmd_tx(priv);
539
520
540
521
ret = tc358768_clear_error(priv);
541
522
if (ret)
+2
-2
drivers/gpu/drm/i915/display/intel_tv.c
+2
-2
drivers/gpu/drm/i915/display/intel_tv.c
···
928
928
const struct intel_crtc_state *pipe_config,
929
929
const struct drm_connector_state *conn_state)
930
930
{
931
-
struct intel_display *display = to_intel_display(state);
931
+
struct intel_display *display = to_intel_display(encoder);
932
932
933
933
/* Prevents vblank waits from timing out in intel_tv_detect_type() */
934
934
intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
···
942
942
const struct intel_crtc_state *old_crtc_state,
943
943
const struct drm_connector_state *old_conn_state)
944
944
{
945
-
struct intel_display *display = to_intel_display(state);
945
+
struct intel_display *display = to_intel_display(encoder);
946
946
947
947
intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0);
948
948
}
+32
-18
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+32
-18
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
···
80
80
const struct intel_gsc_cpd_header_v2 *cpd_header = NULL;
81
81
const struct intel_gsc_cpd_entry *cpd_entry = NULL;
82
82
const struct intel_gsc_manifest_header *manifest;
83
+
struct intel_uc_fw_ver min_ver = { 0 };
83
84
size_t min_size = sizeof(*layout);
84
85
int i;
85
86
···
213
212
}
214
213
}
215
214
216
-
if (IS_ARROWLAKE(gt->i915)) {
215
+
/*
216
+
* ARL SKUs require newer firmwares, but the blob is actually common
217
+
* across all MTL and ARL SKUs, so we need to do an explicit version check
218
+
* here rather than using a separate table entry. If a too old version
219
+
* is found, then just don't use GSC rather than aborting the driver load.
220
+
* Note that the major number in the GSC FW version is used to indicate
221
+
* the platform, so we expect it to always be 102 for MTL/ARL binaries.
222
+
*/
223
+
if (IS_ARROWLAKE_S(gt->i915))
224
+
min_ver = (struct intel_uc_fw_ver){ 102, 0, 10, 1878 };
225
+
else if (IS_ARROWLAKE_H(gt->i915) || IS_ARROWLAKE_U(gt->i915))
226
+
min_ver = (struct intel_uc_fw_ver){ 102, 1, 15, 1926 };
227
+
228
+
if (IS_METEORLAKE(gt->i915) && gsc->release.major != 102) {
229
+
gt_info(gt, "Invalid GSC firmware for MTL/ARL, got %d.%d.%d.%d but need 102.x.x.x",
230
+
gsc->release.major, gsc->release.minor,
231
+
gsc->release.patch, gsc->release.build);
232
+
return -EINVAL;
233
+
}
234
+
235
+
if (min_ver.major) {
217
236
bool too_old = false;
218
237
219
-
/*
220
-
* ARL requires a newer firmware than MTL did (102.0.10.1878) but the
221
-
* firmware is actually common. So, need to do an explicit version check
222
-
* here rather than using a separate table entry. And if the older
223
-
* MTL-only version is found, then just don't use GSC rather than aborting
224
-
* the driver load.
225
-
*/
226
-
if (gsc->release.major < 102) {
238
+
if (gsc->release.minor < min_ver.minor) {
227
239
too_old = true;
228
-
} else if (gsc->release.major == 102) {
229
-
if (gsc->release.minor == 0) {
230
-
if (gsc->release.patch < 10) {
240
+
} else if (gsc->release.minor == min_ver.minor) {
241
+
if (gsc->release.patch < min_ver.patch) {
242
+
too_old = true;
243
+
} else if (gsc->release.patch == min_ver.patch) {
244
+
if (gsc->release.build < min_ver.build)
231
245
too_old = true;
232
-
} else if (gsc->release.patch == 10) {
233
-
if (gsc->release.build < 1878)
234
-
too_old = true;
235
-
}
236
246
}
237
247
}
238
248
239
249
if (too_old) {
240
-
gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least 102.0.10.1878",
250
+
gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least %d.%d.%d.%d",
241
251
gsc->release.major, gsc->release.minor,
242
-
gsc->release.patch, gsc->release.build);
252
+
gsc->release.patch, gsc->release.build,
253
+
min_ver.major, min_ver.minor,
254
+
min_ver.patch, min_ver.build);
243
255
return -EINVAL;
244
256
}
245
257
}
+6
-2
drivers/gpu/drm/i915/i915_drv.h
+6
-2
drivers/gpu/drm/i915/i915_drv.h
···
540
540
#define IS_LUNARLAKE(i915) (0 && i915)
541
541
#define IS_BATTLEMAGE(i915) (0 && i915)
542
542
543
-
#define IS_ARROWLAKE(i915) \
544
-
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
543
+
#define IS_ARROWLAKE_H(i915) \
544
+
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H)
545
+
#define IS_ARROWLAKE_U(i915) \
546
+
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U)
547
+
#define IS_ARROWLAKE_S(i915) \
548
+
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S)
545
549
#define IS_DG2_G10(i915) \
546
550
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
547
551
#define IS_DG2_G11(i915) \
+19
-5
drivers/gpu/drm/i915/intel_device_info.c
+19
-5
drivers/gpu/drm/i915/intel_device_info.c
···
200
200
INTEL_DG2_G12_IDS(ID),
201
201
};
202
202
203
-
static const u16 subplatform_arl_ids[] = {
204
-
INTEL_ARL_IDS(ID),
203
+
static const u16 subplatform_arl_h_ids[] = {
204
+
INTEL_ARL_H_IDS(ID),
205
+
};
206
+
207
+
static const u16 subplatform_arl_u_ids[] = {
208
+
INTEL_ARL_U_IDS(ID),
209
+
};
210
+
211
+
static const u16 subplatform_arl_s_ids[] = {
212
+
INTEL_ARL_S_IDS(ID),
205
213
};
206
214
207
215
static bool find_devid(u16 id, const u16 *p, unsigned int num)
···
269
261
} else if (find_devid(devid, subplatform_g12_ids,
270
262
ARRAY_SIZE(subplatform_g12_ids))) {
271
263
mask = BIT(INTEL_SUBPLATFORM_G12);
272
-
} else if (find_devid(devid, subplatform_arl_ids,
273
-
ARRAY_SIZE(subplatform_arl_ids))) {
274
-
mask = BIT(INTEL_SUBPLATFORM_ARL);
264
+
} else if (find_devid(devid, subplatform_arl_h_ids,
265
+
ARRAY_SIZE(subplatform_arl_h_ids))) {
266
+
mask = BIT(INTEL_SUBPLATFORM_ARL_H);
267
+
} else if (find_devid(devid, subplatform_arl_u_ids,
268
+
ARRAY_SIZE(subplatform_arl_u_ids))) {
269
+
mask = BIT(INTEL_SUBPLATFORM_ARL_U);
270
+
} else if (find_devid(devid, subplatform_arl_s_ids,
271
+
ARRAY_SIZE(subplatform_arl_s_ids))) {
272
+
mask = BIT(INTEL_SUBPLATFORM_ARL_S);
275
273
}
276
274
277
275
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
+3
-1
drivers/gpu/drm/i915/intel_device_info.h
+3
-1
drivers/gpu/drm/i915/intel_device_info.h
···
128
128
#define INTEL_SUBPLATFORM_RPLU 2
129
129
130
130
/* MTL */
131
-
#define INTEL_SUBPLATFORM_ARL 0
131
+
#define INTEL_SUBPLATFORM_ARL_H 0
132
+
#define INTEL_SUBPLATFORM_ARL_U 1
133
+
#define INTEL_SUBPLATFORM_ARL_S 2
132
134
133
135
enum intel_ppgtt_type {
134
136
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
+36
-25
drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c
+36
-25
drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c
···
992
992
ctrl->data = data;
993
993
994
994
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
995
-
if (ret == -EAGAIN && ctrl->retryTimeMs) {
995
+
if ((ret == -EAGAIN || ret == -EBUSY) && ctrl->retryTimeMs) {
996
996
/*
997
997
* Device (likely an eDP panel) isn't ready yet, wait for the time specified
998
998
* by GSP before retrying again
···
1060
1060
NV0073_CTRL_DP_AUXCH_CTRL_PARAMS *ctrl;
1061
1061
u8 size = *psize;
1062
1062
int ret;
1063
+
int retries;
1063
1064
1064
-
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, NV0073_CTRL_CMD_DP_AUXCH_CTRL, sizeof(*ctrl));
1065
-
if (IS_ERR(ctrl))
1066
-
return PTR_ERR(ctrl);
1065
+
for (retries = 0; retries < 3; ++retries) {
1066
+
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, NV0073_CTRL_CMD_DP_AUXCH_CTRL, sizeof(*ctrl));
1067
+
if (IS_ERR(ctrl))
1068
+
return PTR_ERR(ctrl);
1067
1069
1068
-
ctrl->subDeviceInstance = 0;
1069
-
ctrl->displayId = BIT(outp->index);
1070
-
ctrl->bAddrOnly = !size;
1071
-
ctrl->cmd = type;
1072
-
if (ctrl->bAddrOnly) {
1073
-
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, REQ_TYPE, WRITE);
1074
-
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, I2C_MOT, FALSE);
1070
+
ctrl->subDeviceInstance = 0;
1071
+
ctrl->displayId = BIT(outp->index);
1072
+
ctrl->bAddrOnly = !size;
1073
+
ctrl->cmd = type;
1074
+
if (ctrl->bAddrOnly) {
1075
+
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, REQ_TYPE, WRITE);
1076
+
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, I2C_MOT, FALSE);
1077
+
}
1078
+
ctrl->addr = addr;
1079
+
ctrl->size = !ctrl->bAddrOnly ? (size - 1) : 0;
1080
+
memcpy(ctrl->data, data, size);
1081
+
1082
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
1083
+
if ((ret == -EAGAIN || ret == -EBUSY) && ctrl->retryTimeMs) {
1084
+
/*
1085
+
* Device (likely an eDP panel) isn't ready yet, wait for the time specified
1086
+
* by GSP before retrying again
1087
+
*/
1088
+
nvkm_debug(&disp->engine.subdev,
1089
+
"Waiting %dms for GSP LT panel delay before retrying in AUX\n",
1090
+
ctrl->retryTimeMs);
1091
+
msleep(ctrl->retryTimeMs);
1092
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1093
+
} else {
1094
+
memcpy(data, ctrl->data, size);
1095
+
*psize = ctrl->size;
1096
+
ret = ctrl->replyType;
1097
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1098
+
break;
1099
+
}
1075
1100
}
1076
-
ctrl->addr = addr;
1077
-
ctrl->size = !ctrl->bAddrOnly ? (size - 1) : 0;
1078
-
memcpy(ctrl->data, data, size);
1079
-
1080
-
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
1081
-
if (ret) {
1082
-
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1083
-
return ret;
1084
-
}
1085
-
1086
-
memcpy(data, ctrl->data, size);
1087
-
*psize = ctrl->size;
1088
-
ret = ctrl->replyType;
1089
-
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1090
1101
return ret;
1091
1102
}
1092
1103
+6
-5
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
+6
-5
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
···
89
89
nvkm_falcon_fw_dtor_sigs(fw);
90
90
}
91
91
92
-
/* after last write to the img, sync dma mappings */
93
-
dma_sync_single_for_device(fw->fw.device->dev,
94
-
fw->fw.phys,
95
-
sg_dma_len(&fw->fw.mem.sgl),
96
-
DMA_TO_DEVICE);
97
92
98
93
FLCNFW_DBG(fw, "resetting");
99
94
fw->func->reset(fw);
···
99
104
if (ret)
100
105
goto done;
101
106
}
107
+
108
+
/* after last write to the img, sync dma mappings */
109
+
dma_sync_single_for_device(fw->fw.device->dev,
110
+
fw->fw.phys,
111
+
sg_dma_len(&fw->fw.mem.sgl),
112
+
DMA_TO_DEVICE);
102
113
103
114
ret = fw->func->load(fw);
104
115
if (ret)
+3
-3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
···
78
78
switch (rpc_status) {
79
79
case 0x55: /* NV_ERR_NOT_READY */
80
80
case 0x66: /* NV_ERR_TIMEOUT_RETRY */
81
-
return -EAGAIN;
81
+
return -EBUSY;
82
82
case 0x51: /* NV_ERR_NO_MEMORY */
83
83
return -ENOMEM;
84
84
default:
···
601
601
602
602
if (rpc->status) {
603
603
ret = ERR_PTR(r535_rpc_status_to_errno(rpc->status));
604
-
if (PTR_ERR(ret) != -EAGAIN)
604
+
if (PTR_ERR(ret) != -EAGAIN && PTR_ERR(ret) != -EBUSY)
605
605
nvkm_error(&gsp->subdev, "RM_ALLOC: 0x%x\n", rpc->status);
606
606
} else {
607
607
ret = repc ? rpc->params : NULL;
···
660
660
661
661
if (rpc->status) {
662
662
ret = r535_rpc_status_to_errno(rpc->status);
663
-
if (ret != -EAGAIN)
663
+
if (ret != -EAGAIN && ret != -EBUSY)
664
664
nvkm_error(&gsp->subdev, "cli:0x%08x obj:0x%08x ctrl cmd:0x%08x failed: 0x%08x\n",
665
665
object->client->object.handle, object->handle, rpc->cmd, rpc->status);
666
666
}
+2
drivers/gpu/drm/panthor/panthor_mmu.c
+2
drivers/gpu/drm/panthor/panthor_mmu.c
+4
-4
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+4
-4
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
···
1093
1093
if (!plane->state->fb)
1094
1094
return -EINVAL;
1095
1095
1096
-
if (state)
1097
-
crtc_state = drm_atomic_get_existing_crtc_state(state,
1098
-
new_plane_state->crtc);
1099
-
else /* Special case for asynchronous cursor updates. */
1096
+
crtc_state = drm_atomic_get_existing_crtc_state(state, new_plane_state->crtc);
1097
+
1098
+
/* Special case for asynchronous cursor updates. */
1099
+
if (!crtc_state)
1100
1100
crtc_state = plane->crtc->state;
1101
1101
1102
1102
return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
+2
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+2
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
···
1265
1265
struct vmw_framebuffer_surface *vfbs = vmw_framebuffer_to_vfbs(fb);
1266
1266
struct vmw_bo *bo = vmw_user_object_buffer(&vfbs->uo);
1267
1267
1268
+
if (WARN_ON(!bo))
1269
+
return -EINVAL;
1268
1270
return drm_gem_handle_create(file_priv, &bo->tbo.base, handle);
1269
1271
}
1270
1272
+23
-20
drivers/gpu/drm/xe/xe_bo.c
+23
-20
drivers/gpu/drm/xe/xe_bo.c
···
886
886
if (WARN_ON(!xe_bo_is_pinned(bo)))
887
887
return -EINVAL;
888
888
889
-
if (WARN_ON(!xe_bo_is_vram(bo)))
890
-
return -EINVAL;
889
+
if (!xe_bo_is_vram(bo))
890
+
return 0;
891
891
892
892
ret = ttm_bo_mem_space(&bo->ttm, &placement, &new_mem, &ctx);
893
893
if (ret)
···
937
937
.interruptible = false,
938
938
};
939
939
struct ttm_resource *new_mem;
940
+
struct ttm_place *place = &bo->placements[0];
940
941
int ret;
941
942
942
943
xe_bo_assert_held(bo);
···
948
947
if (WARN_ON(!xe_bo_is_pinned(bo)))
949
948
return -EINVAL;
950
949
951
-
if (WARN_ON(xe_bo_is_vram(bo) || !bo->ttm.ttm))
950
+
if (WARN_ON(xe_bo_is_vram(bo)))
952
951
return -EINVAL;
952
+
953
+
if (WARN_ON(!bo->ttm.ttm && !xe_bo_is_stolen(bo)))
954
+
return -EINVAL;
955
+
956
+
if (!mem_type_is_vram(place->mem_type))
957
+
return 0;
953
958
954
959
ret = ttm_bo_mem_space(&bo->ttm, &bo->placement, &new_mem, &ctx);
955
960
if (ret)
···
1726
1719
1727
1720
int xe_bo_pin(struct xe_bo *bo)
1728
1721
{
1722
+
struct ttm_place *place = &bo->placements[0];
1729
1723
struct xe_device *xe = xe_bo_device(bo);
1730
1724
int err;
1731
1725
···
1757
1749
*/
1758
1750
if (IS_DGFX(xe) && !(IS_ENABLED(CONFIG_DRM_XE_DEBUG) &&
1759
1751
bo->flags & XE_BO_FLAG_INTERNAL_TEST)) {
1760
-
struct ttm_place *place = &(bo->placements[0]);
1761
-
1762
1752
if (mem_type_is_vram(place->mem_type)) {
1763
1753
xe_assert(xe, place->flags & TTM_PL_FLAG_CONTIGUOUS);
1764
1754
1765
1755
place->fpfn = (xe_bo_addr(bo, 0, PAGE_SIZE) -
1766
1756
vram_region_gpu_offset(bo->ttm.resource)) >> PAGE_SHIFT;
1767
1757
place->lpfn = place->fpfn + (bo->size >> PAGE_SHIFT);
1768
-
1769
-
spin_lock(&xe->pinned.lock);
1770
-
list_add_tail(&bo->pinned_link, &xe->pinned.kernel_bo_present);
1771
-
spin_unlock(&xe->pinned.lock);
1772
1758
}
1759
+
}
1760
+
1761
+
if (mem_type_is_vram(place->mem_type) || bo->flags & XE_BO_FLAG_GGTT) {
1762
+
spin_lock(&xe->pinned.lock);
1763
+
list_add_tail(&bo->pinned_link, &xe->pinned.kernel_bo_present);
1764
+
spin_unlock(&xe->pinned.lock);
1773
1765
}
1774
1766
1775
1767
ttm_bo_pin(&bo->ttm);
···
1817
1809
1818
1810
void xe_bo_unpin(struct xe_bo *bo)
1819
1811
{
1812
+
struct ttm_place *place = &bo->placements[0];
1820
1813
struct xe_device *xe = xe_bo_device(bo);
1821
1814
1822
1815
xe_assert(xe, !bo->ttm.base.import_attach);
1823
1816
xe_assert(xe, xe_bo_is_pinned(bo));
1824
1817
1825
-
if (IS_DGFX(xe) && !(IS_ENABLED(CONFIG_DRM_XE_DEBUG) &&
1826
-
bo->flags & XE_BO_FLAG_INTERNAL_TEST)) {
1827
-
struct ttm_place *place = &(bo->placements[0]);
1828
-
1829
-
if (mem_type_is_vram(place->mem_type)) {
1830
-
spin_lock(&xe->pinned.lock);
1831
-
xe_assert(xe, !list_empty(&bo->pinned_link));
1832
-
list_del_init(&bo->pinned_link);
1833
-
spin_unlock(&xe->pinned.lock);
1834
-
}
1818
+
if (mem_type_is_vram(place->mem_type) || bo->flags & XE_BO_FLAG_GGTT) {
1819
+
spin_lock(&xe->pinned.lock);
1820
+
xe_assert(xe, !list_empty(&bo->pinned_link));
1821
+
list_del_init(&bo->pinned_link);
1822
+
spin_unlock(&xe->pinned.lock);
1835
1823
}
1836
-
1837
1824
ttm_bo_unpin(&bo->ttm);
1838
1825
}
1839
1826
+12
-8
drivers/gpu/drm/xe/xe_bo_evict.c
+12
-8
drivers/gpu/drm/xe/xe_bo_evict.c
···
34
34
u8 id;
35
35
int ret;
36
36
37
-
if (!IS_DGFX(xe))
38
-
return 0;
39
-
40
37
/* User memory */
41
-
for (mem_type = XE_PL_VRAM0; mem_type <= XE_PL_VRAM1; ++mem_type) {
38
+
for (mem_type = XE_PL_TT; mem_type <= XE_PL_VRAM1; ++mem_type) {
42
39
struct ttm_resource_manager *man =
43
40
ttm_manager_type(bdev, mem_type);
41
+
42
+
/*
43
+
* On igpu platforms with flat CCS we need to ensure we save and restore any CCS
44
+
* state since this state lives inside graphics stolen memory which doesn't survive
45
+
* hibernation.
46
+
*
47
+
* This can be further improved by only evicting objects that we know have actually
48
+
* used a compression enabled PAT index.
49
+
*/
50
+
if (mem_type == XE_PL_TT && (IS_DGFX(xe) || !xe_device_has_flat_ccs(xe)))
51
+
continue;
44
52
45
53
if (man) {
46
54
ret = ttm_resource_manager_evict_all(bdev, man);
···
133
125
struct xe_bo *bo;
134
126
int ret;
135
127
136
-
if (!IS_DGFX(xe))
137
-
return 0;
138
-
139
128
spin_lock(&xe->pinned.lock);
140
129
for (;;) {
141
130
bo = list_first_entry_or_null(&xe->pinned.evicted,
···
164
159
* should setup the iosys map.
165
160
*/
166
161
xe_assert(xe, !iosys_map_is_null(&bo->vmap));
167
-
xe_assert(xe, xe_bo_is_vram(bo));
168
162
169
163
xe_bo_put(bo);
170
164
+2
-2
drivers/gpu/drm/xe/xe_exec.c
+2
-2
drivers/gpu/drm/xe/xe_exec.c
···
203
203
write_locked = false;
204
204
}
205
205
if (err)
206
-
goto err_syncs;
206
+
goto err_hw_exec_mode;
207
207
208
208
if (write_locked) {
209
209
err = xe_vm_userptr_pin(vm);
210
210
downgrade_write(&vm->lock);
211
211
write_locked = false;
212
212
if (err)
213
-
goto err_hw_exec_mode;
213
+
goto err_unlock_list;
214
214
}
215
215
216
216
if (!args->num_batch_buffer) {
+2
drivers/gpu/drm/xe/xe_oa.c
+2
drivers/gpu/drm/xe/xe_oa.c
···
1206
1206
struct xe_oa_stream *stream = file->private_data;
1207
1207
struct xe_gt *gt = stream->gt;
1208
1208
1209
+
xe_pm_runtime_get(gt_to_xe(gt));
1209
1210
mutex_lock(>->oa.gt_lock);
1210
1211
xe_oa_destroy_locked(stream);
1211
1212
mutex_unlock(>->oa.gt_lock);
1213
+
xe_pm_runtime_put(gt_to_xe(gt));
1212
1214
1213
1215
/* Release the reference the OA stream kept on the driver */
1214
1216
drm_dev_put(>_to_xe(gt)->drm);
+15
-4
include/drm/intel/i915_pciids.h
+15
-4
include/drm/intel/i915_pciids.h
···
771
771
INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
772
772
INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
773
773
774
-
/* MTL */
775
-
#define INTEL_ARL_IDS(MACRO__, ...) \
776
-
MACRO__(0x7D41, ## __VA_ARGS__), \
774
+
/* ARL */
775
+
#define INTEL_ARL_H_IDS(MACRO__, ...) \
777
776
MACRO__(0x7D51, ## __VA_ARGS__), \
778
-
MACRO__(0x7D67, ## __VA_ARGS__), \
779
777
MACRO__(0x7DD1, ## __VA_ARGS__)
780
778
779
+
#define INTEL_ARL_U_IDS(MACRO__, ...) \
780
+
MACRO__(0x7D41, ## __VA_ARGS__) \
781
+
782
+
#define INTEL_ARL_S_IDS(MACRO__, ...) \
783
+
MACRO__(0x7D67, ## __VA_ARGS__), \
784
+
MACRO__(0xB640, ## __VA_ARGS__)
785
+
786
+
#define INTEL_ARL_IDS(MACRO__, ...) \
787
+
INTEL_ARL_H_IDS(MACRO__, ## __VA_ARGS__), \
788
+
INTEL_ARL_U_IDS(MACRO__, ## __VA_ARGS__), \
789
+
INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
790
+
791
+
/* MTL */
781
792
#define INTEL_MTL_IDS(MACRO__, ...) \
782
793
INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \
783
794
MACRO__(0x7D40, ## __VA_ARGS__), \