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drm/amd: include rrmt mode for mes_v12_1

Implement rrmt for misc read/write regs ops in mes_v12.
This covers LOCAL/REMOTE XCD and LOCAL/REMOTE AID.

v2: fix comments (Alex)

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Alex Sierra and committed by
Alex Deucher f8692d2f e5fc897b

+49
+42
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
··· 44 44 #define MES_EOP_SIZE 2048 45 45 46 46 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 47 + #define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ 48 + #define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ 49 + #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 50 + #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 51 + #define XCC_MID_MASK 0x41000000 52 + 53 + #define NORMALIZE_XCC_REG_OFFSET(offset) \ 54 + (offset & 0x3FFFF) 47 55 48 56 static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring) 49 57 { ··· 485 477 &mes_status_pkt, sizeof(mes_status_pkt), 486 478 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 487 479 } 480 + static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset) 481 + { 482 + /* Check xcc reg offset range */ 483 + uint32_t xcc = (reg_offset & XCC_MID_MASK) ? 4 : 0; 484 + /* Each XCC has two register ranges. 485 + * These are represented in reg_offset[17:16] 486 + */ 487 + return ((reg_offset >> 16) & 0x3) + xcc; 488 + } 489 + 490 + static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, 491 + struct RRMT_OPTION *rrmt_opt) 492 + { 493 + uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 494 + 495 + if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 496 + ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) { 497 + rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg); 498 + rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ? 499 + MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; 500 + } else { 501 + rrmt_opt->mode = MES_RRMT_MODE_LOCAL_REMOTE_AID; 502 + } 503 + } 488 504 489 505 static int mes_v12_1_misc_op(struct amdgpu_mes *mes, 490 506 struct mes_misc_op_input *input) ··· 532 500 misc_pkt.opcode = MESAPI_MISC__READ_REG; 533 501 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 534 502 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 503 + mes_v12_1_get_rrmt(input->read_reg.reg_offset, input->xcc_id, 504 + &misc_pkt.read_reg.rrmt_opt); 535 505 break; 536 506 case MES_MISC_OP_WRITE_REG: 537 507 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 538 508 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 539 509 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 510 + mes_v12_1_get_rrmt(input->write_reg.reg_offset, input->xcc_id, 511 + &misc_pkt.write_reg.rrmt_opt); 540 512 break; 541 513 case MES_MISC_OP_WRM_REG_WAIT: 542 514 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; ··· 549 513 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 550 514 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 551 515 misc_pkt.wait_reg_mem.reg_offset2 = 0; 516 + mes_v12_1_get_rrmt(input->wrm_reg.reg0, input->xcc_id, 517 + &misc_pkt.wait_reg_mem.rrmt_opt1); 552 518 break; 553 519 case MES_MISC_OP_WRM_REG_WR_WAIT: 554 520 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; ··· 559 521 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 560 522 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 561 523 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 524 + mes_v12_1_get_rrmt(input->wrm_reg.reg0, input->xcc_id, 525 + &misc_pkt.wait_reg_mem.rrmt_opt1); 526 + mes_v12_1_get_rrmt(input->wrm_reg.reg1, input->xcc_id, 527 + &misc_pkt.wait_reg_mem.rrmt_opt2); 562 528 break; 563 529 case MES_MISC_OP_SET_SHADER_DEBUGGER: 564 530 pipe = AMDGPU_MES_SCHED_PIPE;
+7
drivers/gpu/drm/amd/include/mes_v12_api_def.h
··· 71 71 MES_SCH_API_MAX = 0xFF 72 72 }; 73 73 74 + enum MES_RRMT_MODE { 75 + MES_RRMT_MODE_LOCAL_XCD, 76 + MES_RRMT_MODE_LOCAL_REMOTE_AID, 77 + MES_RRMT_MODE_REMOTE_XCD, 78 + MES_RRMT_MODE_REMOTE_MID 79 + }; 80 + 74 81 union MES_API_HEADER { 75 82 struct { 76 83 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */