Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
PCI/IDE: Add Address Association Register setup for downstream MMIO
The address ranges for downstream Address Association Registers need to
cover memory addresses for all functions (PFs/VFs/downstream devices)
managed by a Device Security Manager (DSM). The proposed solution is get
the memory (32-bit only) range and prefetchable-memory (64-bit capable)
range from the immediate ancestor downstream port (either the direct-attach
RP or deepest switch port when switch attached).
Similar to RID association, address associations will be set by default if
hardware sets 'Number of Address Association Register Blocks' in the
'Selective IDE Stream Capability Register' to a non-zero value. TSM drivers
can opt-out of the settings by zero'ing out unwanted / unsupported address
ranges. E.g. TDX Connect only supports prefetachable (64-bit capable)
memory ranges for the Address Association setting.
If the immediate downstream port provides both a memory range and
prefetchable-memory range, but the IDE partner port only provides 1 Address
Association Register block then the TSM driver can pick which range to
associate, or let the PCI core prioritize memory.
Note, the Address Association Register setup for upstream requests is still
uncertain so is not included.
Co-developed-by: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
Co-developed-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20251114010227.567693-1-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
authored by
Xu Yilun
and committed by
Dan Williams
f86e5139
c16af019
+145
-9
+108
-9
drivers/pci/ide.c
+108
-9
drivers/pci/ide.c
···
155
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{
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/* EP, RP, + HB Stream allocation */
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struct stream_index __stream[PCI_IDE_HB + 1];
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+
struct pci_bus_region pref_assoc = { 0, -1 };
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+
struct pci_bus_region mem_assoc = { 0, -1 };
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+
struct resource *mem, *pref;
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struct pci_host_bridge *hb;
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-
struct pci_dev *rp;
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struct pci_dev *rp, *br;
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int num_vf, rid_end;
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if (!pci_is_pcie(pdev))
···
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else
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rid_end = pci_dev_id(pdev);
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+
br = pci_upstream_bridge(pdev);
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+
if (!br)
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return NULL;
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+
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/*
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* Check if the device consumes memory and/or prefetch-memory. Setup
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+
* downstream address association ranges for each.
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+
*/
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mem = pci_resource_n(br, PCI_BRIDGE_MEM_WINDOW);
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pref = pci_resource_n(br, PCI_BRIDGE_PREF_MEM_WINDOW);
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if (resource_assigned(mem))
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pcibios_resource_to_bus(br->bus, &mem_assoc, mem);
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if (resource_assigned(pref))
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pcibios_resource_to_bus(br->bus, &pref_assoc, pref);
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+
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*ide = (struct pci_ide) {
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.pdev = pdev,
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.partner = {
···
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.rid_start = pci_dev_id(rp),
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.rid_end = pci_dev_id(rp),
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.stream_index = no_free_ptr(ep_stream)->stream_index,
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+
/* Disable upstream address association */
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.mem_assoc = { 0, -1 },
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.pref_assoc = { 0, -1 },
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},
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[PCI_IDE_RP] = {
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.rid_start = pci_dev_id(pdev),
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.rid_end = rid_end,
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.stream_index = no_free_ptr(rp_stream)->stream_index,
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+
.mem_assoc = mem_assoc,
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.pref_assoc = pref_assoc,
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},
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},
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.host_bridge_stream = no_free_ptr(hb_stream)->stream_index,
···
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val);
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}
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+
#define SEL_ADDR1_LOWER GENMASK(31, 20)
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#define SEL_ADDR_UPPER GENMASK_ULL(63, 32)
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#define PREP_PCI_IDE_SEL_ADDR1(base, limit) \
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(FIELD_PREP(PCI_IDE_SEL_ADDR_1_VALID, 1) | \
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FIELD_PREP(PCI_IDE_SEL_ADDR_1_BASE_LOW, \
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FIELD_GET(SEL_ADDR1_LOWER, (base))) | \
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FIELD_PREP(PCI_IDE_SEL_ADDR_1_LIMIT_LOW, \
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FIELD_GET(SEL_ADDR1_LOWER, (limit))))
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+
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static void mem_assoc_to_regs(struct pci_bus_region *region,
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struct pci_ide_regs *regs, int idx)
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+
{
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/* convert to u64 range for bitfield size checks */
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struct range r = { region->start, region->end };
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+
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regs->addr[idx].assoc1 = PREP_PCI_IDE_SEL_ADDR1(r.start, r.end);
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regs->addr[idx].assoc2 = FIELD_GET(SEL_ADDR_UPPER, r.end);
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regs->addr[idx].assoc3 = FIELD_GET(SEL_ADDR_UPPER, r.start);
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}
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+
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/**
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* pci_ide_stream_to_regs() - convert IDE settings to association register values
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* @pdev: PCIe device object for either a Root Port or Endpoint Partner Port
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* @ide: registered IDE settings descriptor
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* @regs: output register values
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*/
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static void pci_ide_stream_to_regs(struct pci_dev *pdev, struct pci_ide *ide,
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struct pci_ide_regs *regs)
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{
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struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide);
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int assoc_idx = 0;
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+
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memset(regs, 0, sizeof(*regs));
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+
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if (!settings)
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return;
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+
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regs->rid1 = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT, settings->rid_end);
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+
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regs->rid2 = FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) |
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FIELD_PREP(PCI_IDE_SEL_RID_2_BASE, settings->rid_start) |
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FIELD_PREP(PCI_IDE_SEL_RID_2_SEG, pci_ide_domain(pdev));
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+
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if (pdev->nr_ide_mem && pci_bus_region_size(&settings->mem_assoc)) {
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mem_assoc_to_regs(&settings->mem_assoc, regs, assoc_idx);
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assoc_idx++;
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}
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+
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if (pdev->nr_ide_mem > assoc_idx &&
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pci_bus_region_size(&settings->pref_assoc)) {
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mem_assoc_to_regs(&settings->pref_assoc, regs, assoc_idx);
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assoc_idx++;
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}
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+
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regs->nr_addr = assoc_idx;
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}
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+
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/**
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* pci_ide_stream_setup() - program settings to Selective IDE Stream registers
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* @pdev: PCIe device object for either a Root Port or Endpoint Partner Port
···
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void pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide)
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{
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struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide);
401
+
struct pci_ide_regs regs;
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int pos;
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-
u32 val;
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404
if (!settings)
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return;
486
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+
pci_ide_stream_to_regs(pdev, ide, ®s);
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+
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pos = sel_ide_offset(pdev, settings);
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-
val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT, settings->rid_end);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, val);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, regs.rid1);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, regs.rid2);
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-
val = FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) |
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FIELD_PREP(PCI_IDE_SEL_RID_2_BASE, settings->rid_start) |
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FIELD_PREP(PCI_IDE_SEL_RID_2_SEG, pci_ide_domain(pdev));
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for (int i = 0; i < regs.nr_addr; i++) {
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i),
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regs.addr[i].assoc1);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i),
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regs.addr[i].assoc2);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i),
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regs.addr[i].assoc3);
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}
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-
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val);
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/* clear extra unused address association blocks */
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for (int i = regs.nr_addr; i < pdev->nr_ide_mem; i++) {
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 0);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 0);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 0);
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}
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/*
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* Setup control register early for devices that expect
···
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void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide)
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{
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struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide);
531
-
int pos;
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+
int pos, i;
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if (!settings)
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return;
···
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pos = sel_ide_offset(pdev, settings);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0);
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+
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for (i = 0; i < pdev->nr_ide_mem; i++) {
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 0);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 0);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 0);
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}
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+
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, 0);
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pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, 0);
541
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settings->setup = 0;
+32
include/linux/pci-ide.h
+32
include/linux/pci-ide.h
···
28
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* @rid_start: Partner Port Requester ID range start
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* @rid_end: Partner Port Requester ID range end
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* @stream_index: Selective IDE Stream Register Block selection
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+
* @mem_assoc: PCI bus memory address association for targeting peer partner
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* @pref_assoc: PCI bus prefetchable memory address association for
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* targeting peer partner
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* @default_stream: Endpoint uses this stream for all upstream TLPs regardless of
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* address and RID association registers
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* @setup: flag to track whether to run pci_ide_stream_teardown() for this
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* partner slot
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* @enable: flag whether to run pci_ide_stream_disable() for this partner slot
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*
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* By default, pci_ide_stream_alloc() initializes @mem_assoc and @pref_assoc
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* with the immediate ancestor downstream port memory ranges (i.e. Type 1
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* Configuration Space Header values). Caller may zero size ({0, -1}) the range
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* to drop it from consideration at pci_ide_stream_setup() time.
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*/
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struct pci_ide_partner {
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u16 rid_start;
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u16 rid_end;
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u8 stream_index;
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+
struct pci_bus_region mem_assoc;
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+
struct pci_bus_region pref_assoc;
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unsigned int default_stream:1;
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unsigned int setup:1;
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unsigned int enable:1;
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+
};
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+
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/**
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* struct pci_ide_regs - Hardware register association settings for Selective
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* IDE Streams
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* @rid1: IDE RID Association Register 1
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* @rid2: IDE RID Association Register 2
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* @addr: Up to two address association blocks (IDE Address Association Register
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* 1 through 3) for MMIO and prefetchable MMIO
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* @nr_addr: Number of address association blocks initialized
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*
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* See pci_ide_stream_to_regs()
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*/
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struct pci_ide_regs {
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u32 rid1;
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u32 rid2;
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struct {
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u32 assoc1;
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u32 assoc2;
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u32 assoc3;
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+
} addr[2];
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+
int nr_addr;
44
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};
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/**
+5
include/linux/pci.h
+5
include/linux/pci.h
···
870
870
pci_bus_addr_t end;
871
871
};
872
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+
static inline pci_bus_addr_t pci_bus_region_size(const struct pci_bus_region *region)
874
+
{
875
+
return region->end - region->start + 1;
876
+
}
877
+
873
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struct pci_dynids {
874
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spinlock_t lock; /* Protects list, index */
875
880
struct list_head list; /* For IDs added at runtime */