Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma

+14

drivers/dma/amba-pl08x.c

··· 97 97 98 98 #define DRIVER_NAME "pl08xdmac" 99 99 100 + #define PL80X_DMA_BUSWIDTHS \ 101 + BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 102 + BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 103 + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 104 + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) 105 + 100 106 static struct amba_driver pl08x_amba_driver; 101 107 struct pl08x_driver_data; 102 108 ··· 2076 2070 pl08x->memcpy.device_pause = pl08x_pause; 2077 2071 pl08x->memcpy.device_resume = pl08x_resume; 2078 2072 pl08x->memcpy.device_terminate_all = pl08x_terminate_all; 2073 + pl08x->memcpy.src_addr_widths = PL80X_DMA_BUSWIDTHS; 2074 + pl08x->memcpy.dst_addr_widths = PL80X_DMA_BUSWIDTHS; 2075 + pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM); 2076 + pl08x->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 2079 2077 2080 2078 /* Initialize slave engine */ 2081 2079 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); ··· 2096 2086 pl08x->slave.device_pause = pl08x_pause; 2097 2087 pl08x->slave.device_resume = pl08x_resume; 2098 2088 pl08x->slave.device_terminate_all = pl08x_terminate_all; 2089 + pl08x->slave.src_addr_widths = PL80X_DMA_BUSWIDTHS; 2090 + pl08x->slave.dst_addr_widths = PL80X_DMA_BUSWIDTHS; 2091 + pl08x->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2092 + pl08x->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 2099 2093 2100 2094 /* Get the platform data */ 2101 2095 pl08x->pd = dev_get_platdata(&adev->dev);

+114 -74

drivers/dma/at_hdmac.c

··· 238 238 } 239 239 240 240 /* 241 - * atc_get_current_descriptors - 242 - * locate the descriptor which equal to physical address in DSCR 243 - * @atchan: the channel we want to start 244 - * @dscr_addr: physical descriptor address in DSCR 241 + * atc_get_desc_by_cookie - get the descriptor of a cookie 242 + * @atchan: the DMA channel 243 + * @cookie: the cookie to get the descriptor for 245 244 */ 246 - static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan, 247 - u32 dscr_addr) 245 + static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan, 246 + dma_cookie_t cookie) 248 247 { 249 - struct at_desc *desc, *_desc, *child, *desc_cur = NULL; 248 + struct at_desc *desc, *_desc; 249 + 250 + list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) { 251 + if (desc->txd.cookie == cookie) 252 + return desc; 253 + } 250 254 251 255 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { 252 - if (desc->lli.dscr == dscr_addr) { 253 - desc_cur = desc; 254 - break; 255 - } 256 - 257 - list_for_each_entry(child, &desc->tx_list, desc_node) { 258 - if (child->lli.dscr == dscr_addr) { 259 - desc_cur = child; 260 - break; 261 - } 262 - } 256 + if (desc->txd.cookie == cookie) 257 + return desc; 263 258 } 264 259 265 - return desc_cur; 260 + return NULL; 266 261 } 267 262 268 - /* 269 - * atc_get_bytes_left - 270 - * Get the number of bytes residue in dma buffer, 271 - * @chan: the channel we want to start 263 + /** 264 + * atc_calc_bytes_left - calculates the number of bytes left according to the 265 + * value read from CTRLA. 266 + * 267 + * @current_len: the number of bytes left before reading CTRLA 268 + * @ctrla: the value of CTRLA 269 + * @desc: the descriptor containing the transfer width 272 270 */ 273 - static int atc_get_bytes_left(struct dma_chan *chan) 271 + static inline int atc_calc_bytes_left(int current_len, u32 ctrla, 272 + struct at_desc *desc) 273 + { 274 + return current_len - ((ctrla & ATC_BTSIZE_MAX) << desc->tx_width); 275 + } 276 + 277 + /** 278 + * atc_calc_bytes_left_from_reg - calculates the number of bytes left according 279 + * to the current value of CTRLA. 280 + * 281 + * @current_len: the number of bytes left before reading CTRLA 282 + * @atchan: the channel to read CTRLA for 283 + * @desc: the descriptor containing the transfer width 284 + */ 285 + static inline int atc_calc_bytes_left_from_reg(int current_len, 286 + struct at_dma_chan *atchan, struct at_desc *desc) 287 + { 288 + u32 ctrla = channel_readl(atchan, CTRLA); 289 + 290 + return atc_calc_bytes_left(current_len, ctrla, desc); 291 + } 292 + 293 + /** 294 + * atc_get_bytes_left - get the number of bytes residue for a cookie 295 + * @chan: DMA channel 296 + * @cookie: transaction identifier to check status of 297 + */ 298 + static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) 274 299 { 275 300 struct at_dma_chan *atchan = to_at_dma_chan(chan); 276 - struct at_dma *atdma = to_at_dma(chan->device); 277 - int chan_id = atchan->chan_common.chan_id; 278 301 struct at_desc *desc_first = atc_first_active(atchan); 279 - struct at_desc *desc_cur; 280 - int ret = 0, count = 0; 302 + struct at_desc *desc; 303 + int ret; 304 + u32 ctrla, dscr; 281 305 282 306 /* 283 - * Initialize necessary values in the first time. 284 - * remain_desc record remain desc length. 307 + * If the cookie doesn't match to the currently running transfer then 308 + * we can return the total length of the associated DMA transfer, 309 + * because it is still queued. 285 310 */ 286 - if (atchan->remain_desc == 0) 287 - /* First descriptor embedds the transaction length */ 288 - atchan->remain_desc = desc_first->len; 311 + desc = atc_get_desc_by_cookie(atchan, cookie); 312 + if (desc == NULL) 313 + return -EINVAL; 314 + else if (desc != desc_first) 315 + return desc->total_len; 289 316 290 - /* 291 - * This happens when current descriptor transfer complete. 292 - * The residual buffer size should reduce current descriptor length. 293 - */ 294 - if (unlikely(test_bit(ATC_IS_BTC, &atchan->status))) { 295 - clear_bit(ATC_IS_BTC, &atchan->status); 296 - desc_cur = atc_get_current_descriptors(atchan, 297 - channel_readl(atchan, DSCR)); 298 - if (!desc_cur) { 299 - ret = -EINVAL; 300 - goto out; 301 - } 317 + /* cookie matches to the currently running transfer */ 318 + ret = desc_first->total_len; 302 319 303 - count = (desc_cur->lli.ctrla & ATC_BTSIZE_MAX) 304 - << desc_first->tx_width; 305 - if (atchan->remain_desc < count) { 306 - ret = -EINVAL; 307 - goto out; 308 - } 320 + if (desc_first->lli.dscr) { 321 + /* hardware linked list transfer */ 309 322 310 - atchan->remain_desc -= count; 311 - ret = atchan->remain_desc; 312 - } else { 313 323 /* 314 - * Get residual bytes when current 315 - * descriptor transfer in progress. 324 + * Calculate the residue by removing the length of the child 325 + * descriptors already transferred from the total length. 326 + * To get the current child descriptor we can use the value of 327 + * the channel's DSCR register and compare it against the value 328 + * of the hardware linked list structure of each child 329 + * descriptor. 316 330 */ 317 - count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX) 318 - << (desc_first->tx_width); 319 - ret = atchan->remain_desc - count; 320 - } 321 - /* 322 - * Check fifo empty. 323 - */ 324 - if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) 325 - atc_issue_pending(chan); 326 331 327 - out: 332 + ctrla = channel_readl(atchan, CTRLA); 333 + rmb(); /* ensure CTRLA is read before DSCR */ 334 + dscr = channel_readl(atchan, DSCR); 335 + 336 + /* for the first descriptor we can be more accurate */ 337 + if (desc_first->lli.dscr == dscr) 338 + return atc_calc_bytes_left(ret, ctrla, desc_first); 339 + 340 + ret -= desc_first->len; 341 + list_for_each_entry(desc, &desc_first->tx_list, desc_node) { 342 + if (desc->lli.dscr == dscr) 343 + break; 344 + 345 + ret -= desc->len; 346 + } 347 + 348 + /* 349 + * For the last descriptor in the chain we can calculate 350 + * the remaining bytes using the channel's register. 351 + * Note that the transfer width of the first and last 352 + * descriptor may differ. 353 + */ 354 + if (!desc->lli.dscr) 355 + ret = atc_calc_bytes_left_from_reg(ret, atchan, desc); 356 + } else { 357 + /* single transfer */ 358 + ret = atc_calc_bytes_left_from_reg(ret, atchan, desc_first); 359 + } 360 + 328 361 return ret; 329 362 } 330 363 ··· 572 539 /* Give information to tasklet */ 573 540 set_bit(ATC_IS_ERROR, &atchan->status); 574 541 } 575 - if (pending & AT_DMA_BTC(i)) 576 - set_bit(ATC_IS_BTC, &atchan->status); 577 542 tasklet_schedule(&atchan->tasklet); 578 543 ret = IRQ_HANDLED; 579 544 } ··· 684 653 desc->lli.ctrlb = ctrlb; 685 654 686 655 desc->txd.cookie = 0; 656 + desc->len = xfer_count << src_width; 687 657 688 658 atc_desc_chain(&first, &prev, desc); 689 659 } 690 660 691 661 /* First descriptor of the chain embedds additional information */ 692 662 first->txd.cookie = -EBUSY; 693 - first->len = len; 663 + first->total_len = len; 664 + 665 + /* set transfer width for the calculation of the residue */ 694 666 first->tx_width = src_width; 667 + prev->tx_width = src_width; 695 668 696 669 /* set end-of-link to the last link descriptor of list*/ 697 670 set_desc_eol(desc); ··· 787 752 | ATC_SRC_WIDTH(mem_width) 788 753 | len >> mem_width; 789 754 desc->lli.ctrlb = ctrlb; 755 + desc->len = len; 790 756 791 757 atc_desc_chain(&first, &prev, desc); 792 758 total_len += len; ··· 828 792 | ATC_DST_WIDTH(mem_width) 829 793 | len >> reg_width; 830 794 desc->lli.ctrlb = ctrlb; 795 + desc->len = len; 831 796 832 797 atc_desc_chain(&first, &prev, desc); 833 798 total_len += len; ··· 843 806 844 807 /* First descriptor of the chain embedds additional information */ 845 808 first->txd.cookie = -EBUSY; 846 - first->len = total_len; 809 + first->total_len = total_len; 810 + 811 + /* set transfer width for the calculation of the residue */ 847 812 first->tx_width = reg_width; 813 + prev->tx_width = reg_width; 848 814 849 815 /* first link descriptor of list is responsible of flags */ 850 816 first->txd.flags = flags; /* client is in control of this ack */ ··· 912 872 | ATC_FC_MEM2PER 913 873 | ATC_SIF(atchan->mem_if) 914 874 | ATC_DIF(atchan->per_if); 875 + desc->len = period_len; 915 876 break; 916 877 917 878 case DMA_DEV_TO_MEM: ··· 924 883 | ATC_FC_PER2MEM 925 884 | ATC_SIF(atchan->per_if) 926 885 | ATC_DIF(atchan->mem_if); 886 + desc->len = period_len; 927 887 break; 928 888 929 889 default: ··· 1006 964 1007 965 /* First descriptor of the chain embedds additional information */ 1008 966 first->txd.cookie = -EBUSY; 1009 - first->len = buf_len; 967 + first->total_len = buf_len; 1010 968 first->tx_width = reg_width; 1011 969 1012 970 return &first->txd; ··· 1160 1118 spin_lock_irqsave(&atchan->lock, flags); 1161 1119 1162 1120 /* Get number of bytes left in the active transactions */ 1163 - bytes = atc_get_bytes_left(chan); 1121 + bytes = atc_get_bytes_left(chan, cookie); 1164 1122 1165 1123 spin_unlock_irqrestore(&atchan->lock, flags); 1166 1124 ··· 1256 1214 1257 1215 spin_lock_irqsave(&atchan->lock, flags); 1258 1216 atchan->descs_allocated = i; 1259 - atchan->remain_desc = 0; 1260 1217 list_splice(&tmp_list, &atchan->free_list); 1261 1218 dma_cookie_init(chan); 1262 1219 spin_unlock_irqrestore(&atchan->lock, flags); ··· 1298 1257 list_splice_init(&atchan->free_list, &list); 1299 1258 atchan->descs_allocated = 0; 1300 1259 atchan->status = 0; 1301 - atchan->remain_desc = 0; 1302 1260 1303 1261 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); 1304 1262 }

+3 -4

drivers/dma/at_hdmac_regs.h

··· 181 181 * @at_lli: hardware lli structure 182 182 * @txd: support for the async_tx api 183 183 * @desc_node: node on the channed descriptors list 184 - * @len: total transaction bytecount 184 + * @len: descriptor byte count 185 185 * @tx_width: transfer width 186 + * @total_len: total transaction byte count 186 187 */ 187 188 struct at_desc { 188 189 /* FIRST values the hardware uses */ ··· 195 194 struct list_head desc_node; 196 195 size_t len; 197 196 u32 tx_width; 197 + size_t total_len; 198 198 }; 199 199 200 200 static inline struct at_desc * ··· 215 213 enum atc_status { 216 214 ATC_IS_ERROR = 0, 217 215 ATC_IS_PAUSED = 1, 218 - ATC_IS_BTC = 2, 219 216 ATC_IS_CYCLIC = 24, 220 217 }; 221 218 ··· 232 231 * @save_cfg: configuration register that is saved on suspend/resume cycle 233 232 * @save_dscr: for cyclic operations, preserve next descriptor address in 234 233 * the cyclic list on suspend/resume cycle 235 - * @remain_desc: to save remain desc length 236 234 * @dma_sconfig: configuration for slave transfers, passed via 237 235 * .device_config 238 236 * @lock: serializes enqueue/dequeue operations to descriptors lists ··· 251 251 struct tasklet_struct tasklet; 252 252 u32 save_cfg; 253 253 u32 save_dscr; 254 - u32 remain_desc; 255 254 struct dma_slave_config dma_sconfig; 256 255 257 256 spinlock_t lock;

+4 -1

drivers/dma/dw/platform.c

··· 26 26 27 27 #include "internal.h" 28 28 29 + #define DRV_NAME "dw_dmac" 30 + 29 31 static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec, 30 32 struct of_dma *ofdma) 31 33 { ··· 286 284 .remove = dw_remove, 287 285 .shutdown = dw_shutdown, 288 286 .driver = { 289 - .name = "dw_dmac", 287 + .name = DRV_NAME, 290 288 .pm = &dw_dev_pm_ops, 291 289 .of_match_table = of_match_ptr(dw_dma_of_id_table), 292 290 .acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table), ··· 307 305 308 306 MODULE_LICENSE("GPL v2"); 309 307 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver"); 308 + MODULE_ALIAS("platform:" DRV_NAME);

+4 -3

drivers/dma/imx-sdma.c

··· 531 531 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 532 532 } 533 533 534 + /* Set bits of CONFIG register with dynamic context switching */ 535 + if (readl(sdma->regs + SDMA_H_CONFIG) == 0) 536 + writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); 537 + 534 538 return ret ? 0 : -ETIMEDOUT; 535 539 } 536 540 ··· 1397 1393 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1398 1394 1399 1395 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1400 - 1401 - /* Set bits of CONFIG register with given context switching mode */ 1402 - writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); 1403 1396 1404 1397 /* Initializes channel's priorities */ 1405 1398 sdma_set_channel_priority(&sdma->channel[0], 7);

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