Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: mt6359: Add ready register index and mask to channel data
In preparation for adding support for the AUXADC block found in
the MT6363 PMIC, add the ready register index and mask to the
mtk_pmic_auxadc_chan structure, populate those in the channel
description for all of the already supported SoCs and make use
of them in the .read_imp() callbacks.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250703141146.171431-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
AngeloGioacchino Del Regno
and committed by
Jonathan Cameron
f8bb423f
00da77d1
+65
-53
+65
-53
drivers/iio/adc/mt6359-auxadc.c
+65
-53
drivers/iio/adc/mt6359-auxadc.c
···
101
101
* struct mtk_pmic_auxadc_chan - PMIC AUXADC channel data
102
102
* @req_idx: Request register number
103
103
* @req_mask: Bitmask to activate a channel
104
+
* @rdy_idx: Readiness register number
105
+
* @rdy_mask: Bitmask to determine channel readiness
104
106
* @num_samples: Number of AUXADC samples for averaging
105
107
* @r_ratio: Resistance ratio fractional
106
108
*/
107
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struct mtk_pmic_auxadc_chan {
108
110
u8 req_idx;
109
111
u16 req_mask;
112
+
u8 rdy_idx;
113
+
u16 rdy_mask;
110
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u16 num_samples;
111
115
struct u8_fract r_ratio;
112
116
};
···
134
130
const u16 *regs;
135
131
u16 sec_unlock_key;
136
132
u8 imp_adc_num;
137
-
int (*read_imp)(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat);
133
+
int (*read_imp)(struct mt6359_auxadc *adc_dev,
134
+
const struct iio_chan_spec *chan, int *vbat, int *ibat);
138
135
};
139
136
140
-
#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _samples, _rnum, _rdiv) \
137
+
#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \
138
+
_samples, _rnum, _rdiv) \
141
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[PMIC_AUXADC_CHAN_##_ch_idx] = { \
142
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.req_idx = _req_idx, \
143
141
.req_mask = BIT(_req_bit), \
142
+
.rdy_idx = _rdy_idx, \
143
+
.rdy_mask = BIT(_rdy_bit), \
144
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.num_samples = _samples, \
145
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.r_ratio = { _rnum, _rdiv } \
146
146
}
···
185
177
};
186
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187
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static const struct mtk_pmic_auxadc_chan mt6357_auxadc_ch_desc[] = {
188
-
MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1),
189
-
MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, 128, 3, 1),
190
-
MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1),
191
-
MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 1, 1),
192
-
MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1),
193
-
MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1),
194
-
MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1),
195
-
MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1),
196
-
MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1),
197
-
MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 1, 1),
198
-
MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, 8, 1, 1),
199
-
MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, 8, 1, 1),
180
+
MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
181
+
MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
182
+
MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
183
+
MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
184
+
MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
185
+
MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
186
+
MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1),
187
+
MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1),
188
+
MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1),
189
+
MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
190
+
MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
191
+
MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
200
192
201
193
/* Battery impedance channels */
202
-
MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 3, 1),
194
+
MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
203
195
};
204
196
205
197
static const u16 mt6357_auxadc_regs[] = {
···
232
224
};
233
225
234
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static const struct mtk_pmic_auxadc_chan mt6358_auxadc_ch_desc[] = {
235
-
MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1),
236
-
MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1),
237
-
MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 2, 1),
238
-
MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1),
239
-
MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1),
240
-
MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2),
241
-
MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1),
242
-
MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1),
243
-
MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1),
244
-
MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 2, 1),
245
-
MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1),
246
-
MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1),
247
-
MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1),
227
+
MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
228
+
MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
229
+
MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 2, 1),
230
+
MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
231
+
MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
232
+
MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP0, 8, 8, 3, 2),
233
+
MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1),
234
+
MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1),
235
+
MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1),
236
+
MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 2, 1),
237
+
MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
238
+
MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
239
+
MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
248
240
249
241
/* Battery impedance channels */
250
-
MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2),
242
+
MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 7, 2),
251
243
};
252
244
253
245
static const u16 mt6358_auxadc_regs[] = {
···
280
272
};
281
273
282
274
static const struct mtk_pmic_auxadc_chan mt6359_auxadc_ch_desc[] = {
283
-
MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 7, 2),
284
-
MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 5, 2),
285
-
MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1),
286
-
MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1),
287
-
MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2),
288
-
MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1),
289
-
MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1),
290
-
MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1),
291
-
MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 5, 2),
292
-
MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1),
293
-
MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1),
294
-
MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1),
275
+
MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
276
+
MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8, 5, 2),
277
+
MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
278
+
MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15 ,8, 1, 1),
279
+
MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3, 2),
280
+
MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 128, 1, 1),
281
+
MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, 256, 1, 1),
282
+
MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP1, 15, 16, 1, 1),
283
+
MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP1, 15, 8, 5, 2),
284
+
MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
285
+
MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
286
+
MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
295
287
296
288
/* Battery impedance channels */
297
-
MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2),
298
-
MTK_PMIC_ADC_CHAN(IBAT, 0, 0, 128, 7, 2),
289
+
MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
290
+
MTK_PMIC_ADC_CHAN(IBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
299
291
};
300
292
301
293
static const u16 mt6359_auxadc_regs[] = {
···
321
313
regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN);
322
314
}
323
315
324
-
static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev)
316
+
static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev, const struct iio_chan_spec *chan)
325
317
{
326
318
const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
319
+
const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index];
327
320
struct regmap *regmap = adc_dev->regmap;
328
321
u32 val;
329
322
int ret;
···
332
323
regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN);
333
324
regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN);
334
325
335
-
ret = regmap_read_poll_timeout(adc_dev->regmap, cinfo->regs[PMIC_AUXADC_IMP0],
336
-
val, val & MT6358_IMP0_IRQ_RDY,
326
+
ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx],
327
+
val, val & desc->rdy_mask,
337
328
IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US);
338
329
if (ret) {
339
330
mt6358_stop_imp_conv(adc_dev);
···
343
334
return 0;
344
335
}
345
336
346
-
static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat)
337
+
static int mt6358_read_imp(struct mt6359_auxadc *adc_dev,
338
+
const struct iio_chan_spec *chan, int *vbat, int *ibat)
347
339
{
348
340
const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
349
341
struct regmap *regmap = adc_dev->regmap;
···
352
342
u32 val_v;
353
343
int ret;
354
344
355
-
ret = mt6358_start_imp_conv(adc_dev);
345
+
ret = mt6358_start_imp_conv(adc_dev, chan);
356
346
if (ret)
357
347
return ret;
358
348
···
369
359
return 0;
370
360
}
371
361
372
-
static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat)
362
+
static int mt6359_read_imp(struct mt6359_auxadc *adc_dev,
363
+
const struct iio_chan_spec *chan, int *vbat, int *ibat)
373
364
{
374
365
const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
366
+
const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index];
375
367
struct regmap *regmap = adc_dev->regmap;
376
368
u32 val, val_v, val_i;
377
369
int ret;
378
370
379
371
/* Start conversion */
380
372
regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN);
381
-
ret = regmap_read_poll_timeout(regmap, cinfo->regs[PMIC_AUXADC_IMP1],
382
-
val, val & MT6359_IMP1_IRQ_RDY,
373
+
ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx],
374
+
val, val & desc->rdy_mask,
383
375
IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US);
384
376
385
377
/* Stop conversion regardless of the result */
···
518
506
scoped_guard(mutex, &adc_dev->lock) {
519
507
switch (chan->scan_index) {
520
508
case PMIC_AUXADC_CHAN_IBAT:
521
-
ret = adc_dev->chip_info->read_imp(adc_dev, NULL, val);
509
+
ret = adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val);
522
510
break;
523
511
case PMIC_AUXADC_CHAN_VBAT:
524
-
ret = adc_dev->chip_info->read_imp(adc_dev, val, NULL);
512
+
ret = adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL);
525
513
break;
526
514
default:
527
515
ret = mt6359_auxadc_read_adc(adc_dev, chan, val);