tjh.dev / kernel
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Merge tag 'drm-fixes-2021-03-26' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"As expected last week things were overly quiet so this week things
seem to have caught up. It still isn't too major.

msm and amdgpu lead the size here, the msm fixes are pretty varied
across the driver, the amdgpu one is mostly the S0ix fixes with some
other minor ones. Otherwise there are a few i915 fixes and one each
for nouveau, etnaviv and rcar-du.

msm:
- pll fixes
- shutdown hook fix
- runtime resume fix
- clear_oob fix
- kms locking fix
- display aux retry fix

rcar-du:
- warn_on in encoder init fix

etnaviv:
- Use FOLL_FORCE and FOLL_LONGTERM

i915:
- DisplayPort LTTPR fixes around link training and limiting it
according to supported spec version.
- Fix enabled_planes bitmask to really represent only logically
enabled planes.
- Fix DSS CTL registers for ICL DSI transcoders
- Fix the GT fence revocation runtime PM logic.

nouveau:
- cursor size regression fix

amdgpu:
- S0ix fixes
- Add PCI ID
- Polaris PCIe DPM fix
- Display fix for high refresh rate monitors"

* tag 'drm-fixes-2021-03-26' of git://anongit.freedesktop.org/drm/drm: (37 commits)
drm/nouveau/kms/nve4-nv108: Limit cursors to 128x128
drm/i915: Fix the GT fence revocation runtime PM logic
drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x
drm/amdgpu: Add additional Sienna Cichlid PCI ID
drm/amd/pm: workaround for audio noise issue
drm/i915/dsc: fix DSS CTL register usage for ICL DSI transcoders
drm/i915: Fix enabled_planes bitmask
drm/i915: Disable LTTPR support when the LTTPR rev < 1.4
drm/i915: Disable LTTPR support when the DPCD rev < 1.4
drm/i915/ilk-glk: Fix link training on links with LTTPRs
drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume
drm/amdgpu: skip kfd suspend/resume for S0ix
drm/amdgpu: drop S0ix checks around CG/PG in suspend
drm/amdgpu: skip CG/PG for gfx during S0ix
drm/amdgpu: update comments about s0ix suspend/resume
drm/amdgpu/swsmu: skip gfx cgpg on s0ix suspend
drm/amdgpu: re-enable suspend phase 2 for S0ix
drm/amdgpu: move s0ix check into amdgpu_device_ip_suspend_phase2 (v3)
drm/amdgpu: clean up non-DC suspend/resume handling
drm/amdgpu: don't evict vram on APUs for suspend to ram (v4)
...

Linus Torvalds f944d061 57a90062

+616 -265
+3 -7
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 1007 1007 1008 1008 /* s3/s4 mask */ 1009 1009 bool in_suspend; 1010 - bool in_hibernate; 1011 - 1012 - /* 1013 - * The combination flag in_poweroff_reboot_com used to identify the poweroff 1014 - * and reboot opt in the s0i3 system-wide suspend. 1015 - */ 1016 - bool in_poweroff_reboot_com; 1010 + bool in_s3; 1011 + bool in_s4; 1012 + bool in_s0ix; 1017 1013 1018 1014 atomic_t in_gpu_reset; 1019 1015 enum pp_mp1_state mp1_state;
+34 -98
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 2371 2371 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; 2372 2372 if (!adev->ip_blocks[i].status.late_initialized) 2373 2373 continue; 2374 + /* skip CG for GFX on S0ix */ 2375 + if (adev->in_s0ix && 2376 + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) 2377 + continue; 2374 2378 /* skip CG for VCE/UVD, it's handled specially */ 2375 2379 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && 2376 2380 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && ··· 2405 2401 for (j = 0; j < adev->num_ip_blocks; j++) { 2406 2402 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; 2407 2403 if (!adev->ip_blocks[i].status.late_initialized) 2404 + continue; 2405 + /* skip PG for GFX on S0ix */ 2406 + if (adev->in_s0ix && 2407 + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) 2408 2408 continue; 2409 2409 /* skip CG for VCE/UVD, it's handled specially */ 2410 2410 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && ··· 2686 2678 { 2687 2679 int i, r; 2688 2680 2689 - if (adev->in_poweroff_reboot_com || 2690 - !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) { 2691 - amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 2692 - amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 2693 - } 2681 + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 2682 + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 2694 2683 2695 2684 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 2696 2685 if (!adev->ip_blocks[i].status.valid) ··· 2727 2722 { 2728 2723 int i, r; 2729 2724 2725 + if (adev->in_s0ix) 2726 + amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); 2727 + 2730 2728 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 2731 2729 if (!adev->ip_blocks[i].status.valid) 2732 2730 continue; ··· 2742 2734 adev->ip_blocks[i].status.hw = false; 2743 2735 continue; 2744 2736 } 2737 + 2738 + /* skip suspend of gfx and psp for S0ix 2739 + * gfx is in gfxoff state, so on resume it will exit gfxoff just 2740 + * like at runtime. PSP is also part of the always on hardware 2741 + * so no need to suspend it. 2742 + */ 2743 + if (adev->in_s0ix && 2744 + (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || 2745 + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)) 2746 + continue; 2747 + 2745 2748 /* XXX handle errors */ 2746 2749 r = adev->ip_blocks[i].version->funcs->suspend(adev); 2747 2750 /* XXX handle errors */ ··· 3692 3673 */ 3693 3674 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 3694 3675 { 3695 - struct amdgpu_device *adev; 3696 - struct drm_crtc *crtc; 3697 - struct drm_connector *connector; 3698 - struct drm_connector_list_iter iter; 3676 + struct amdgpu_device *adev = drm_to_adev(dev); 3699 3677 int r; 3700 - 3701 - adev = drm_to_adev(dev); 3702 3678 3703 3679 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 3704 3680 return 0; ··· 3706 3692 3707 3693 cancel_delayed_work_sync(&adev->delayed_init_work); 3708 3694 3709 - if (!amdgpu_device_has_dc_support(adev)) { 3710 - /* turn off display hw */ 3711 - drm_modeset_lock_all(dev); 3712 - drm_connector_list_iter_begin(dev, &iter); 3713 - drm_for_each_connector_iter(connector, &iter) 3714 - drm_helper_connector_dpms(connector, 3715 - DRM_MODE_DPMS_OFF); 3716 - drm_connector_list_iter_end(&iter); 3717 - drm_modeset_unlock_all(dev); 3718 - /* unpin the front buffers and cursors */ 3719 - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3720 - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3721 - struct drm_framebuffer *fb = crtc->primary->fb; 3722 - struct amdgpu_bo *robj; 3723 - 3724 - if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 3725 - struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 3726 - r = amdgpu_bo_reserve(aobj, true); 3727 - if (r == 0) { 3728 - amdgpu_bo_unpin(aobj); 3729 - amdgpu_bo_unreserve(aobj); 3730 - } 3731 - } 3732 - 3733 - if (fb == NULL || fb->obj[0] == NULL) { 3734 - continue; 3735 - } 3736 - robj = gem_to_amdgpu_bo(fb->obj[0]); 3737 - /* don't unpin kernel fb objects */ 3738 - if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { 3739 - r = amdgpu_bo_reserve(robj, true); 3740 - if (r == 0) { 3741 - amdgpu_bo_unpin(robj); 3742 - amdgpu_bo_unreserve(robj); 3743 - } 3744 - } 3745 - } 3746 - } 3747 - 3748 3695 amdgpu_ras_suspend(adev); 3749 3696 3750 3697 r = amdgpu_device_ip_suspend_phase1(adev); 3751 3698 3752 - amdgpu_amdkfd_suspend(adev, adev->in_runpm); 3699 + if (!adev->in_s0ix) 3700 + amdgpu_amdkfd_suspend(adev, adev->in_runpm); 3753 3701 3754 3702 /* evict vram memory */ 3755 3703 amdgpu_bo_evict_vram(adev); 3756 3704 3757 3705 amdgpu_fence_driver_suspend(adev); 3758 3706 3759 - if (adev->in_poweroff_reboot_com || 3760 - !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) 3761 - r = amdgpu_device_ip_suspend_phase2(adev); 3762 - else 3763 - amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); 3707 + r = amdgpu_device_ip_suspend_phase2(adev); 3764 3708 /* evict remaining vram memory 3765 3709 * This second call to evict vram is to evict the gart page table 3766 3710 * using the CPU. ··· 3740 3768 */ 3741 3769 int amdgpu_device_resume(struct drm_device *dev, bool fbcon) 3742 3770 { 3743 - struct drm_connector *connector; 3744 - struct drm_connector_list_iter iter; 3745 3771 struct amdgpu_device *adev = drm_to_adev(dev); 3746 - struct drm_crtc *crtc; 3747 3772 int r = 0; 3748 3773 3749 3774 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 3750 3775 return 0; 3751 3776 3752 - if (amdgpu_acpi_is_s0ix_supported(adev)) 3777 + if (adev->in_s0ix) 3753 3778 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry); 3754 3779 3755 3780 /* post card */ ··· 3771 3802 queue_delayed_work(system_wq, &adev->delayed_init_work, 3772 3803 msecs_to_jiffies(AMDGPU_RESUME_MS)); 3773 3804 3774 - if (!amdgpu_device_has_dc_support(adev)) { 3775 - /* pin cursors */ 3776 - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3777 - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3778 - 3779 - if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 3780 - struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 3781 - r = amdgpu_bo_reserve(aobj, true); 3782 - if (r == 0) { 3783 - r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 3784 - if (r != 0) 3785 - dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); 3786 - amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 3787 - amdgpu_bo_unreserve(aobj); 3788 - } 3789 - } 3790 - } 3805 + if (!adev->in_s0ix) { 3806 + r = amdgpu_amdkfd_resume(adev, adev->in_runpm); 3807 + if (r) 3808 + return r; 3791 3809 } 3792 - r = amdgpu_amdkfd_resume(adev, adev->in_runpm); 3793 - if (r) 3794 - return r; 3795 3810 3796 3811 /* Make sure IB tests flushed */ 3797 3812 flush_delayed_work(&adev->delayed_init_work); 3798 3813 3799 - /* blat the mode back in */ 3800 - if (fbcon) { 3801 - if (!amdgpu_device_has_dc_support(adev)) { 3802 - /* pre DCE11 */ 3803 - drm_helper_resume_force_mode(dev); 3804 - 3805 - /* turn on display hw */ 3806 - drm_modeset_lock_all(dev); 3807 - 3808 - drm_connector_list_iter_begin(dev, &iter); 3809 - drm_for_each_connector_iter(connector, &iter) 3810 - drm_helper_connector_dpms(connector, 3811 - DRM_MODE_DPMS_ON); 3812 - drm_connector_list_iter_end(&iter); 3813 - 3814 - drm_modeset_unlock_all(dev); 3815 - } 3814 + if (fbcon) 3816 3815 amdgpu_fbdev_set_suspend(adev, 0); 3817 - } 3818 3816 3819 3817 drm_kms_helper_poll_enable(dev); 3820 3818
+89
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 1310 1310 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1311 1311 stime, etime, mode); 1312 1312 } 1313 + 1314 + int amdgpu_display_suspend_helper(struct amdgpu_device *adev) 1315 + { 1316 + struct drm_device *dev = adev_to_drm(adev); 1317 + struct drm_crtc *crtc; 1318 + struct drm_connector *connector; 1319 + struct drm_connector_list_iter iter; 1320 + int r; 1321 + 1322 + /* turn off display hw */ 1323 + drm_modeset_lock_all(dev); 1324 + drm_connector_list_iter_begin(dev, &iter); 1325 + drm_for_each_connector_iter(connector, &iter) 1326 + drm_helper_connector_dpms(connector, 1327 + DRM_MODE_DPMS_OFF); 1328 + drm_connector_list_iter_end(&iter); 1329 + drm_modeset_unlock_all(dev); 1330 + /* unpin the front buffers and cursors */ 1331 + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1332 + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1333 + struct drm_framebuffer *fb = crtc->primary->fb; 1334 + struct amdgpu_bo *robj; 1335 + 1336 + if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1337 + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1338 + r = amdgpu_bo_reserve(aobj, true); 1339 + if (r == 0) { 1340 + amdgpu_bo_unpin(aobj); 1341 + amdgpu_bo_unreserve(aobj); 1342 + } 1343 + } 1344 + 1345 + if (fb == NULL || fb->obj[0] == NULL) { 1346 + continue; 1347 + } 1348 + robj = gem_to_amdgpu_bo(fb->obj[0]); 1349 + /* don't unpin kernel fb objects */ 1350 + if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { 1351 + r = amdgpu_bo_reserve(robj, true); 1352 + if (r == 0) { 1353 + amdgpu_bo_unpin(robj); 1354 + amdgpu_bo_unreserve(robj); 1355 + } 1356 + } 1357 + } 1358 + return r; 1359 + } 1360 + 1361 + int amdgpu_display_resume_helper(struct amdgpu_device *adev) 1362 + { 1363 + struct drm_device *dev = adev_to_drm(adev); 1364 + struct drm_connector *connector; 1365 + struct drm_connector_list_iter iter; 1366 + struct drm_crtc *crtc; 1367 + int r; 1368 + 1369 + /* pin cursors */ 1370 + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1371 + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1372 + 1373 + if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1374 + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1375 + r = amdgpu_bo_reserve(aobj, true); 1376 + if (r == 0) { 1377 + r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 1378 + if (r != 0) 1379 + dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); 1380 + amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 1381 + amdgpu_bo_unreserve(aobj); 1382 + } 1383 + } 1384 + } 1385 + 1386 + drm_helper_resume_force_mode(dev); 1387 + 1388 + /* turn on display hw */ 1389 + drm_modeset_lock_all(dev); 1390 + 1391 + drm_connector_list_iter_begin(dev, &iter); 1392 + drm_for_each_connector_iter(connector, &iter) 1393 + drm_helper_connector_dpms(connector, 1394 + DRM_MODE_DPMS_ON); 1395 + drm_connector_list_iter_end(&iter); 1396 + 1397 + drm_modeset_unlock_all(dev); 1398 + 1399 + return 0; 1400 + } 1401 +
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
··· 47 47 const struct drm_format_info * 48 48 amdgpu_lookup_format_info(u32 format, uint64_t modifier); 49 49 50 + int amdgpu_display_suspend_helper(struct amdgpu_device *adev); 51 + int amdgpu_display_resume_helper(struct amdgpu_device *adev); 52 + 50 53 #endif
+19 -12
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 1107 1107 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1108 1108 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1109 1109 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1110 + {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1110 1111 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1111 1112 1112 1113 /* Van Gogh */ ··· 1275 1274 */ 1276 1275 if (!amdgpu_passthrough(adev)) 1277 1276 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1278 - adev->in_poweroff_reboot_com = true; 1279 1277 amdgpu_device_ip_suspend(adev); 1280 - adev->in_poweroff_reboot_com = false; 1281 1278 adev->mp1_state = PP_MP1_STATE_NONE; 1282 1279 } 1283 1280 1284 1281 static int amdgpu_pmops_suspend(struct device *dev) 1285 1282 { 1286 1283 struct drm_device *drm_dev = dev_get_drvdata(dev); 1284 + struct amdgpu_device *adev = drm_to_adev(drm_dev); 1285 + int r; 1287 1286 1288 - return amdgpu_device_suspend(drm_dev, true); 1287 + if (amdgpu_acpi_is_s0ix_supported(adev)) 1288 + adev->in_s0ix = true; 1289 + adev->in_s3 = true; 1290 + r = amdgpu_device_suspend(drm_dev, true); 1291 + adev->in_s3 = false; 1292 + 1293 + return r; 1289 1294 } 1290 1295 1291 1296 static int amdgpu_pmops_resume(struct device *dev) 1292 1297 { 1293 1298 struct drm_device *drm_dev = dev_get_drvdata(dev); 1299 + struct amdgpu_device *adev = drm_to_adev(drm_dev); 1300 + int r; 1294 1301 1295 - return amdgpu_device_resume(drm_dev, true); 1302 + r = amdgpu_device_resume(drm_dev, true); 1303 + if (amdgpu_acpi_is_s0ix_supported(adev)) 1304 + adev->in_s0ix = false; 1305 + return r; 1296 1306 } 1297 1307 1298 1308 static int amdgpu_pmops_freeze(struct device *dev) ··· 1312 1300 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1313 1301 int r; 1314 1302 1315 - adev->in_hibernate = true; 1303 + adev->in_s4 = true; 1316 1304 r = amdgpu_device_suspend(drm_dev, true); 1317 - adev->in_hibernate = false; 1305 + adev->in_s4 = false; 1318 1306 if (r) 1319 1307 return r; 1320 1308 return amdgpu_asic_reset(adev); ··· 1330 1318 static int amdgpu_pmops_poweroff(struct device *dev) 1331 1319 { 1332 1320 struct drm_device *drm_dev = dev_get_drvdata(dev); 1333 - struct amdgpu_device *adev = drm_to_adev(drm_dev); 1334 - int r; 1335 1321 1336 - adev->in_poweroff_reboot_com = true; 1337 - r = amdgpu_device_suspend(drm_dev, true); 1338 - adev->in_poweroff_reboot_com = false; 1339 - return r; 1322 + return amdgpu_device_suspend(drm_dev, true); 1340 1323 } 1341 1324 1342 1325 static int amdgpu_pmops_restore(struct device *dev)
+2 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 1028 1028 { 1029 1029 struct ttm_resource_manager *man; 1030 1030 1031 - /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1032 - #ifndef CONFIG_HIBERNATION 1033 - if (adev->flags & AMD_IS_APU) { 1034 - /* Useless to evict on IGP chips */ 1031 + if (adev->in_s3 && (adev->flags & AMD_IS_APU)) { 1032 + /* No need to evict vram on APUs for suspend to ram */ 1035 1033 return 0; 1036 1034 } 1037 - #endif 1038 1035 1039 1036 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1040 1037 return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
+8 -1
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 2897 2897 static int dce_v10_0_suspend(void *handle) 2898 2898 { 2899 2899 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2900 + int r; 2901 + 2902 + r = amdgpu_display_suspend_helper(adev); 2903 + if (r) 2904 + return r; 2900 2905 2901 2906 adev->mode_info.bl_level = 2902 2907 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); ··· 2926 2921 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2927 2922 bl_level); 2928 2923 } 2924 + if (ret) 2925 + return ret; 2929 2926 2930 - return ret; 2927 + return amdgpu_display_resume_helper(adev); 2931 2928 } 2932 2929 2933 2930 static bool dce_v10_0_is_idle(void *handle)
+8 -1
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 3027 3027 static int dce_v11_0_suspend(void *handle) 3028 3028 { 3029 3029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3030 + int r; 3031 + 3032 + r = amdgpu_display_suspend_helper(adev); 3033 + if (r) 3034 + return r; 3030 3035 3031 3036 adev->mode_info.bl_level = 3032 3037 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); ··· 3056 3051 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3057 3052 bl_level); 3058 3053 } 3054 + if (ret) 3055 + return ret; 3059 3056 3060 - return ret; 3057 + return amdgpu_display_resume_helper(adev); 3061 3058 } 3062 3059 3063 3060 static bool dce_v11_0_is_idle(void *handle)
+7 -1
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 2770 2770 static int dce_v6_0_suspend(void *handle) 2771 2771 { 2772 2772 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2773 + int r; 2773 2774 2775 + r = amdgpu_display_suspend_helper(adev); 2776 + if (r) 2777 + return r; 2774 2778 adev->mode_info.bl_level = 2775 2779 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2776 2780 ··· 2798 2794 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2799 2795 bl_level); 2800 2796 } 2797 + if (ret) 2798 + return ret; 2801 2799 2802 - return ret; 2800 + return amdgpu_display_resume_helper(adev); 2803 2801 } 2804 2802 2805 2803 static bool dce_v6_0_is_idle(void *handle)
+8 -1
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 2796 2796 static int dce_v8_0_suspend(void *handle) 2797 2797 { 2798 2798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2799 + int r; 2800 + 2801 + r = amdgpu_display_suspend_helper(adev); 2802 + if (r) 2803 + return r; 2799 2804 2800 2805 adev->mode_info.bl_level = 2801 2806 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); ··· 2825 2820 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2826 2821 bl_level); 2827 2822 } 2823 + if (ret) 2824 + return ret; 2828 2825 2829 - return ret; 2826 + return amdgpu_display_resume_helper(adev); 2830 2827 } 2831 2828 2832 2829 static bool dce_v8_0_is_idle(void *handle)
+14 -1
drivers/gpu/drm/amd/amdgpu/dce_virtual.c
··· 39 39 #include "dce_v11_0.h" 40 40 #include "dce_virtual.h" 41 41 #include "ivsrcid/ivsrcid_vislands30.h" 42 + #include "amdgpu_display.h" 42 43 43 44 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666 44 45 ··· 492 491 493 492 static int dce_virtual_suspend(void *handle) 494 493 { 494 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 495 + int r; 496 + 497 + r = amdgpu_display_suspend_helper(adev); 498 + if (r) 499 + return r; 495 500 return dce_virtual_hw_fini(handle); 496 501 } 497 502 498 503 static int dce_virtual_resume(void *handle) 499 504 { 500 - return dce_virtual_hw_init(handle); 505 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 506 + int r; 507 + 508 + r = dce_virtual_hw_init(handle); 509 + if (r) 510 + return r; 511 + return amdgpu_display_resume_helper(adev); 501 512 } 502 513 503 514 static bool dce_virtual_is_idle(void *handle)
+54
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
··· 587 587 tmp, MC_CG_ARB_FREQ_F0); 588 588 } 589 589 590 + static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr) 591 + { 592 + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 593 + uint16_t pcie_gen = 0; 594 + 595 + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 && 596 + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4) 597 + pcie_gen = 3; 598 + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 && 599 + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 600 + pcie_gen = 2; 601 + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 && 602 + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2) 603 + pcie_gen = 1; 604 + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 && 605 + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1) 606 + pcie_gen = 0; 607 + 608 + return pcie_gen; 609 + } 610 + 611 + static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr) 612 + { 613 + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 614 + uint16_t pcie_width = 0; 615 + 616 + if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 617 + pcie_width = 16; 618 + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 619 + pcie_width = 12; 620 + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 621 + pcie_width = 8; 622 + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 623 + pcie_width = 4; 624 + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 625 + pcie_width = 2; 626 + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 627 + pcie_width = 1; 628 + 629 + return pcie_width; 630 + } 631 + 590 632 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 591 633 { 592 634 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); ··· 725 683 PP_Min_PCIEGen), 726 684 get_pcie_lane_support(data->pcie_lane_cap, 727 685 PP_Max_PCIELane)); 686 + 687 + if (data->pcie_dpm_key_disabled) 688 + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 689 + data->dpm_table.pcie_speed_table.count, 690 + smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr)); 728 691 } 729 692 return 0; 730 693 } ··· 1294 1247 PPSMC_MSG_PCIeDPM_Enable, 1295 1248 NULL)), 1296 1249 "Failed to enable pcie DPM during DPM Start Function!", 1250 + return -EINVAL); 1251 + } else { 1252 + PP_ASSERT_WITH_CODE( 1253 + (0 == smum_send_msg_to_smc(hwmgr, 1254 + PPSMC_MSG_PCIeDPM_Disable, 1255 + NULL)), 1256 + "Failed to disble pcie DPM during DPM Start Function!", 1297 1257 return -EINVAL); 1298 1258 } 1299 1259
+62 -10
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
··· 54 54 #include "smuio/smuio_9_0_offset.h" 55 55 #include "smuio/smuio_9_0_sh_mask.h" 56 56 57 + #define smnPCIE_LC_SPEED_CNTL 0x11140290 58 + #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 59 + 57 60 #define HBM_MEMORY_CHANNEL_WIDTH 128 58 61 59 62 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; ··· 446 443 if (PP_CAP(PHM_PlatformCaps_VCEDPM)) 447 444 data->smu_features[GNLD_DPM_VCE].supported = true; 448 445 449 - if (!data->registry_data.pcie_dpm_key_disabled) 450 - data->smu_features[GNLD_DPM_LINK].supported = true; 446 + data->smu_features[GNLD_DPM_LINK].supported = true; 451 447 452 448 if (!data->registry_data.dcefclk_dpm_key_disabled) 453 449 data->smu_features[GNLD_DPM_DCEFCLK].supported = true; ··· 1544 1542 1545 1543 if (pp_table->PcieLaneCount[i] > pcie_width) 1546 1544 pp_table->PcieLaneCount[i] = pcie_width; 1545 + } 1546 + 1547 + if (data->registry_data.pcie_dpm_key_disabled) { 1548 + for (i = 0; i < NUM_LINK_LEVELS; i++) { 1549 + pp_table->PcieGenSpeed[i] = pcie_gen; 1550 + pp_table->PcieLaneCount[i] = pcie_width; 1551 + } 1547 1552 } 1548 1553 1549 1554 return 0; ··· 2973 2964 return -1); 2974 2965 data->smu_features[GNLD_ACDC].enabled = true; 2975 2966 } 2967 + } 2968 + 2969 + if (data->registry_data.pcie_dpm_key_disabled) { 2970 + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2971 + false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap), 2972 + "Attempt to Disable Link DPM feature Failed!", return -EINVAL); 2973 + data->smu_features[GNLD_DPM_LINK].enabled = false; 2974 + data->smu_features[GNLD_DPM_LINK].supported = false; 2976 2975 } 2977 2976 2978 2977 return 0; ··· 4601 4584 return 0; 4602 4585 } 4603 4586 4587 + static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 4588 + { 4589 + struct amdgpu_device *adev = hwmgr->adev; 4590 + 4591 + return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 4592 + PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 4593 + >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 4594 + } 4595 + 4596 + static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 4597 + { 4598 + struct amdgpu_device *adev = hwmgr->adev; 4599 + 4600 + return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 4601 + PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 4602 + >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 4603 + } 4604 + 4604 4605 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, 4605 4606 enum pp_clock_type type, char *buf) 4606 4607 { ··· 4627 4592 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4628 4593 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4629 4594 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4630 - struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); 4631 4595 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4596 + uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4597 + PPTable_t *pptable = &(data->smc_state_table.pp_table); 4632 4598 4633 4599 int i, now, size = 0, count = 0; 4634 4600 ··· 4686 4650 "*" : ""); 4687 4651 break; 4688 4652 case PP_PCIE: 4689 - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex, &now); 4653 + current_gen_speed = 4654 + vega10_get_current_pcie_link_speed_level(hwmgr); 4655 + current_lane_width = 4656 + vega10_get_current_pcie_link_width_level(hwmgr); 4657 + for (i = 0; i < NUM_LINK_LEVELS; i++) { 4658 + gen_speed = pptable->PcieGenSpeed[i]; 4659 + lane_width = pptable->PcieLaneCount[i]; 4690 4660 4691 - for (i = 0; i < pcie_table->count; i++) 4692 - size += sprintf(buf + size, "%d: %s %s\n", i, 4693 - (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" : 4694 - (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" : 4695 - (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "", 4696 - (i == now) ? "*" : ""); 4661 + size += sprintf(buf + size, "%d: %s %s %s\n", i, 4662 + (gen_speed == 0) ? "2.5GT/s," : 4663 + (gen_speed == 1) ? "5.0GT/s," : 4664 + (gen_speed == 2) ? "8.0GT/s," : 4665 + (gen_speed == 3) ? "16.0GT/s," : "", 4666 + (lane_width == 1) ? "x1" : 4667 + (lane_width == 2) ? "x2" : 4668 + (lane_width == 3) ? "x4" : 4669 + (lane_width == 4) ? "x8" : 4670 + (lane_width == 5) ? "x12" : 4671 + (lane_width == 6) ? "x16" : "", 4672 + (current_gen_speed == gen_speed) && 4673 + (current_lane_width == lane_width) ? 4674 + "*" : ""); 4675 + } 4697 4676 break; 4677 + 4698 4678 case OD_SCLK: 4699 4679 if (hwmgr->od_enabled) { 4700 4680 size = sprintf(buf, "%s:\n", "OD_SCLK");
+24
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
··· 133 133 data->registry_data.auto_wattman_debug = 0; 134 134 data->registry_data.auto_wattman_sample_period = 100; 135 135 data->registry_data.auto_wattman_threshold = 50; 136 + data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 136 137 } 137 138 138 139 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) ··· 540 539 pp_table->PcieLaneCount[i] = pcie_width_arg; 541 540 } 542 541 542 + /* override to the highest if it's disabled from ppfeaturmask */ 543 + if (data->registry_data.pcie_dpm_key_disabled) { 544 + for (i = 0; i < NUM_LINK_LEVELS; i++) { 545 + smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width; 546 + ret = smum_send_msg_to_smc_with_parameter(hwmgr, 547 + PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 548 + NULL); 549 + PP_ASSERT_WITH_CODE(!ret, 550 + "[OverridePcieParameters] Attempt to override pcie params failed!", 551 + return ret); 552 + 553 + pp_table->PcieGenSpeed[i] = pcie_gen; 554 + pp_table->PcieLaneCount[i] = pcie_width; 555 + } 556 + ret = vega12_enable_smc_features(hwmgr, 557 + false, 558 + data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap); 559 + PP_ASSERT_WITH_CODE(!ret, 560 + "Attempt to Disable DPM LINK Failed!", 561 + return ret); 562 + data->smu_features[GNLD_DPM_LINK].enabled = false; 563 + data->smu_features[GNLD_DPM_LINK].supported = false; 564 + } 543 565 return 0; 544 566 } 545 567
+25
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
··· 171 171 data->registry_data.gfxoff_controlled_by_driver = 1; 172 172 data->gfxoff_allowed = false; 173 173 data->counter_gfxoff = 0; 174 + data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 174 175 } 175 176 176 177 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr) ··· 883 882 /* update the pptable */ 884 883 pp_table->PcieGenSpeed[i] = pcie_gen_arg; 885 884 pp_table->PcieLaneCount[i] = pcie_width_arg; 885 + } 886 + 887 + /* override to the highest if it's disabled from ppfeaturmask */ 888 + if (data->registry_data.pcie_dpm_key_disabled) { 889 + for (i = 0; i < NUM_LINK_LEVELS; i++) { 890 + smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width; 891 + ret = smum_send_msg_to_smc_with_parameter(hwmgr, 892 + PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 893 + NULL); 894 + PP_ASSERT_WITH_CODE(!ret, 895 + "[OverridePcieParameters] Attempt to override pcie params failed!", 896 + return ret); 897 + 898 + pp_table->PcieGenSpeed[i] = pcie_gen; 899 + pp_table->PcieLaneCount[i] = pcie_width; 900 + } 901 + ret = vega20_enable_smc_features(hwmgr, 902 + false, 903 + data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap); 904 + PP_ASSERT_WITH_CODE(!ret, 905 + "Attempt to Disable DPM LINK Failed!", 906 + return ret); 907 + data->smu_features[GNLD_DPM_LINK].enabled = false; 908 + data->smu_features[GNLD_DPM_LINK].supported = false; 886 909 } 887 910 888 911 return 0;
+3 -2
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 1294 1294 bool use_baco = !smu->is_apu && 1295 1295 ((amdgpu_in_reset(adev) && 1296 1296 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1297 - ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev))); 1297 + ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1298 1298 1299 1299 /* 1300 1300 * For custom pptable uploading, skip the DPM features ··· 1431 1431 1432 1432 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1433 1433 1434 - if (smu->is_apu) 1434 + /* skip CGPG when in S0ix */ 1435 + if (smu->is_apu && !adev->in_s0ix) 1435 1436 smu_set_gfx_cgpg(&adev->smu, false); 1436 1437 1437 1438 return 0;
+2 -1
drivers/gpu/drm/etnaviv/etnaviv_gem.c
··· 689 689 struct page **pages = pvec + pinned; 690 690 691 691 ret = pin_user_pages_fast(ptr, num_pages, 692 - !userptr->ro ? FOLL_WRITE : 0, pages); 692 + FOLL_WRITE | FOLL_FORCE | FOLL_LONGTERM, 693 + pages); 693 694 if (ret < 0) { 694 695 unpin_user_pages(pvec, pinned); 695 696 kvfree(pvec);
+3 -2
drivers/gpu/drm/i915/display/intel_atomic_plane.c
··· 317 317 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc) 318 318 return 0; 319 319 320 - new_crtc_state->enabled_planes |= BIT(plane->id); 321 - 322 320 ret = plane->check_plane(new_crtc_state, new_plane_state); 323 321 if (ret) 324 322 return ret; 323 + 324 + if (fb) 325 + new_crtc_state->enabled_planes |= BIT(plane->id); 325 326 326 327 /* FIXME pre-g4x don't work like this */ 327 328 if (new_plane_state->uapi.visible)
+1 -3
drivers/gpu/drm/i915/display/intel_dp.c
··· 3619 3619 { 3620 3620 int ret; 3621 3621 3622 - intel_dp_lttpr_init(intel_dp); 3623 - 3624 - if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) 3622 + if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 3625 3623 return false; 3626 3624 3627 3625 /*
+7
drivers/gpu/drm/i915/display/intel_dp_aux.c
··· 133 133 else 134 134 precharge = 5; 135 135 136 + /* Max timeout value on G4x-BDW: 1.6ms */ 136 137 if (IS_BROADWELL(dev_priv)) 137 138 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 138 139 else ··· 160 159 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 161 160 u32 ret; 162 161 162 + /* 163 + * Max timeout values: 164 + * SKL-GLK: 1.6ms 165 + * CNL: 3.2ms 166 + * ICL+: 4ms 167 + */ 163 168 ret = DP_AUX_CH_CTL_SEND_BUSY | 164 169 DP_AUX_CH_CTL_DONE | 165 170 DP_AUX_CH_CTL_INTERRUPT |
+2 -8
drivers/gpu/drm/i915/display/intel_vdsc.c
··· 1014 1014 { 1015 1015 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1016 1016 1017 - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) 1018 - return DSS_CTL1; 1019 - 1020 - return ICL_PIPE_DSS_CTL1(pipe); 1017 + return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL1(pipe) : DSS_CTL1; 1021 1018 } 1022 1019 1023 1020 static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state) 1024 1021 { 1025 1022 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1026 1023 1027 - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) 1028 - return DSS_CTL2; 1029 - 1030 - return ICL_PIPE_DSS_CTL2(pipe); 1024 + return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2; 1031 1025 } 1032 1026 1033 1027 void intel_dsc_enable(struct intel_encoder *encoder,
+12 -1
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
··· 316 316 WRITE_ONCE(fence->vma, NULL); 317 317 vma->fence = NULL; 318 318 319 - with_intel_runtime_pm_if_in_use(fence_to_uncore(fence)->rpm, wakeref) 319 + /* 320 + * Skip the write to HW if and only if the device is currently 321 + * suspended. 322 + * 323 + * If the driver does not currently hold a wakeref (if_in_use == 0), 324 + * the device may currently be runtime suspended, or it may be woken 325 + * up before the suspend takes place. If the device is not suspended 326 + * (powered down) and we skip clearing the fence register, the HW is 327 + * left in an undefined state where we may end up with multiple 328 + * registers overlapping. 329 + */ 330 + with_intel_runtime_pm_if_active(fence_to_uncore(fence)->rpm, wakeref) 320 331 fence_write(fence); 321 332 } 322 333
+24 -5
drivers/gpu/drm/i915/intel_runtime_pm.c
··· 412 412 } 413 413 414 414 /** 415 - * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 415 + * __intel_runtime_pm_get_if_active - grab a runtime pm reference if device is active 416 416 * @rpm: the intel_runtime_pm structure 417 + * @ignore_usecount: get a ref even if dev->power.usage_count is 0 417 418 * 418 419 * This function grabs a device-level runtime pm reference if the device is 419 - * already in use and ensures that it is powered up. It is illegal to try 420 - * and access the HW should intel_runtime_pm_get_if_in_use() report failure. 420 + * already active and ensures that it is powered up. It is illegal to try 421 + * and access the HW should intel_runtime_pm_get_if_active() report failure. 422 + * 423 + * If @ignore_usecount=true, a reference will be acquired even if there is no 424 + * user requiring the device to be powered up (dev->power.usage_count == 0). 425 + * If the function returns false in this case then it's guaranteed that the 426 + * device's runtime suspend hook has been called already or that it will be 427 + * called (and hence it's also guaranteed that the device's runtime resume 428 + * hook will be called eventually). 421 429 * 422 430 * Any runtime pm reference obtained by this function must have a symmetric 423 431 * call to intel_runtime_pm_put() to release the reference again. ··· 433 425 * Returns: the wakeref cookie to pass to intel_runtime_pm_put(), evaluates 434 426 * as True if the wakeref was acquired, or False otherwise. 435 427 */ 436 - intel_wakeref_t intel_runtime_pm_get_if_in_use(struct intel_runtime_pm *rpm) 428 + static intel_wakeref_t __intel_runtime_pm_get_if_active(struct intel_runtime_pm *rpm, 429 + bool ignore_usecount) 437 430 { 438 431 if (IS_ENABLED(CONFIG_PM)) { 439 432 /* ··· 443 434 * function, since the power state is undefined. This applies 444 435 * atm to the late/early system suspend/resume handlers. 445 436 */ 446 - if (pm_runtime_get_if_in_use(rpm->kdev) <= 0) 437 + if (pm_runtime_get_if_active(rpm->kdev, ignore_usecount) <= 0) 447 438 return 0; 448 439 } 449 440 450 441 intel_runtime_pm_acquire(rpm, true); 451 442 452 443 return track_intel_runtime_pm_wakeref(rpm); 444 + } 445 + 446 + intel_wakeref_t intel_runtime_pm_get_if_in_use(struct intel_runtime_pm *rpm) 447 + { 448 + return __intel_runtime_pm_get_if_active(rpm, false); 449 + } 450 + 451 + intel_wakeref_t intel_runtime_pm_get_if_active(struct intel_runtime_pm *rpm) 452 + { 453 + return __intel_runtime_pm_get_if_active(rpm, true); 453 454 } 454 455 455 456 /**
+5
drivers/gpu/drm/i915/intel_runtime_pm.h
··· 177 177 178 178 intel_wakeref_t intel_runtime_pm_get(struct intel_runtime_pm *rpm); 179 179 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct intel_runtime_pm *rpm); 180 + intel_wakeref_t intel_runtime_pm_get_if_active(struct intel_runtime_pm *rpm); 180 181 intel_wakeref_t intel_runtime_pm_get_noresume(struct intel_runtime_pm *rpm); 181 182 intel_wakeref_t intel_runtime_pm_get_raw(struct intel_runtime_pm *rpm); 182 183 ··· 187 186 188 187 #define with_intel_runtime_pm_if_in_use(rpm, wf) \ 189 188 for ((wf) = intel_runtime_pm_get_if_in_use(rpm); (wf); \ 189 + intel_runtime_pm_put((rpm), (wf)), (wf) = 0) 190 + 191 + #define with_intel_runtime_pm_if_active(rpm, wf) \ 192 + for ((wf) = intel_runtime_pm_get_if_active(rpm); (wf); \ 190 193 intel_runtime_pm_put((rpm), (wf)), (wf) = 0) 191 194 192 195 void intel_runtime_pm_put_unchecked(struct intel_runtime_pm *rpm);
+1 -1
drivers/gpu/drm/msm/adreno/a5xx_power.c
··· 304 304 /* Set up the limits management */ 305 305 if (adreno_is_a530(adreno_gpu)) 306 306 a530_lm_setup(gpu); 307 - else 307 + else if (adreno_is_a540(adreno_gpu)) 308 308 a540_lm_setup(gpu); 309 309 310 310 /* Set up SP/TP power collpase */
+1 -1
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
··· 339 339 else 340 340 bit = a6xx_gmu_oob_bits[state].ack_new; 341 341 342 - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit); 342 + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); 343 343 } 344 344 345 345 /* Enable CPU control of SPTP power power collapse */
+72 -36
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 522 522 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 523 523 } 524 524 525 - static void a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 525 + /* 526 + * Check that the microcode version is new enough to include several key 527 + * security fixes. Return true if the ucode is safe. 528 + */ 529 + static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 526 530 struct drm_gem_object *obj) 527 531 { 532 + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 533 + struct msm_gpu *gpu = &adreno_gpu->base; 528 534 u32 *buf = msm_gem_get_vaddr(obj); 535 + bool ret = false; 529 536 530 537 if (IS_ERR(buf)) 531 - return; 538 + return false; 532 539 533 540 /* 534 - * If the lowest nibble is 0xa that is an indication that this microcode 535 - * has been patched. The actual version is in dword [3] but we only care 536 - * about the patchlevel which is the lowest nibble of dword [3] 537 - * 538 - * Otherwise check that the firmware is greater than or equal to 1.90 539 - * which was the first version that had this fix built in 541 + * Targets up to a640 (a618, a630 and a640) need to check for a 542 + * microcode version that is patched to support the whereami opcode or 543 + * one that is new enough to include it by default. 540 544 */ 541 - if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) 542 - a6xx_gpu->has_whereami = true; 543 - else if ((buf[0] & 0xfff) > 0x190) 544 - a6xx_gpu->has_whereami = true; 545 + if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) || 546 + adreno_is_a640(adreno_gpu)) { 547 + /* 548 + * If the lowest nibble is 0xa that is an indication that this 549 + * microcode has been patched. The actual version is in dword 550 + * [3] but we only care about the patchlevel which is the lowest 551 + * nibble of dword [3] 552 + * 553 + * Otherwise check that the firmware is greater than or equal 554 + * to 1.90 which was the first version that had this fix built 555 + * in 556 + */ 557 + if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 558 + (buf[0] & 0xfff) >= 0x190) { 559 + a6xx_gpu->has_whereami = true; 560 + ret = true; 561 + goto out; 562 + } 545 563 564 + DRM_DEV_ERROR(&gpu->pdev->dev, 565 + "a630 SQE ucode is too old. Have version %x need at least %x\n", 566 + buf[0] & 0xfff, 0x190); 567 + } else { 568 + /* 569 + * a650 tier targets don't need whereami but still need to be 570 + * equal to or newer than 1.95 for other security fixes 571 + */ 572 + if (adreno_is_a650(adreno_gpu)) { 573 + if ((buf[0] & 0xfff) >= 0x195) { 574 + ret = true; 575 + goto out; 576 + } 577 + 578 + DRM_DEV_ERROR(&gpu->pdev->dev, 579 + "a650 SQE ucode is too old. Have version %x need at least %x\n", 580 + buf[0] & 0xfff, 0x195); 581 + } 582 + 583 + /* 584 + * When a660 is added those targets should return true here 585 + * since those have all the critical security fixes built in 586 + * from the start 587 + */ 588 + } 589 + out: 546 590 msm_gem_put_vaddr(obj); 591 + return ret; 547 592 } 548 593 549 594 static int a6xx_ucode_init(struct msm_gpu *gpu) ··· 611 566 } 612 567 613 568 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 614 - a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo); 569 + if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 570 + msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 571 + drm_gem_object_put(a6xx_gpu->sqe_bo); 572 + 573 + a6xx_gpu->sqe_bo = NULL; 574 + return -EPERM; 575 + } 615 576 } 616 577 617 578 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO, ··· 1401 1350 u32 revn) 1402 1351 { 1403 1352 struct opp_table *opp_table; 1404 - struct nvmem_cell *cell; 1405 1353 u32 supp_hw = UINT_MAX; 1406 - void *buf; 1354 + u16 speedbin; 1355 + int ret; 1407 1356 1408 - cell = nvmem_cell_get(dev, "speed_bin"); 1409 - /* 1410 - * -ENOENT means that the platform doesn't support speedbin which is 1411 - * fine 1412 - */ 1413 - if (PTR_ERR(cell) == -ENOENT) 1414 - return 0; 1415 - else if (IS_ERR(cell)) { 1357 + ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin); 1358 + if (ret) { 1416 1359 DRM_DEV_ERROR(dev, 1417 - "failed to read speed-bin. Some OPPs may not be supported by hardware"); 1360 + "failed to read speed-bin (%d). Some OPPs may not be supported by hardware", 1361 + ret); 1418 1362 goto done; 1419 1363 } 1364 + speedbin = le16_to_cpu(speedbin); 1420 1365 1421 - buf = nvmem_cell_read(cell, NULL); 1422 - if (IS_ERR(buf)) { 1423 - nvmem_cell_put(cell); 1424 - DRM_DEV_ERROR(dev, 1425 - "failed to read speed-bin. Some OPPs may not be supported by hardware"); 1426 - goto done; 1427 - } 1428 - 1429 - supp_hw = fuse_to_supp_hw(dev, revn, *((u32 *) buf)); 1430 - 1431 - kfree(buf); 1432 - nvmem_cell_put(cell); 1366 + supp_hw = fuse_to_supp_hw(dev, revn, speedbin); 1433 1367 1434 1368 done: 1435 1369 opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);
+7 -5
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
··· 43 43 #define DPU_DEBUGFS_DIR "msm_dpu" 44 44 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 45 45 46 + #define MIN_IB_BW 400000000ULL /* Min ib vote 400MB */ 47 + 46 48 static int dpu_kms_hw_init(struct msm_kms *kms); 47 49 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 48 50 ··· 933 931 DPU_DEBUG("REG_DMA is not defined"); 934 932 } 935 933 934 + if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) 935 + dpu_kms_parse_data_bus_icc_path(dpu_kms); 936 + 936 937 pm_runtime_get_sync(&dpu_kms->pdev->dev); 937 938 938 939 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); ··· 1036 1031 } 1037 1032 1038 1033 dpu_vbif_init_memtypes(dpu_kms); 1039 - 1040 - if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) 1041 - dpu_kms_parse_data_bus_icc_path(dpu_kms); 1042 1034 1043 1035 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1044 1036 ··· 1193 1191 1194 1192 ddev = dpu_kms->dev; 1195 1193 1194 + WARN_ON(!(dpu_kms->num_paths)); 1196 1195 /* Min vote of BW is required before turning on AXI clk */ 1197 1196 for (i = 0; i < dpu_kms->num_paths; i++) 1198 - icc_set_bw(dpu_kms->path[i], 0, 1199 - dpu_kms->catalog->perf.min_dram_ib); 1197 + icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW)); 1200 1198 1201 1199 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); 1202 1200 if (rc) {
+7
drivers/gpu/drm/msm/dp/dp_aux.c
··· 32 32 struct drm_dp_aux dp_aux; 33 33 }; 34 34 35 + #define MAX_AUX_RETRIES 5 36 + 35 37 static const char *dp_aux_get_error(u32 aux_error) 36 38 { 37 39 switch (aux_error) { ··· 379 377 ret = dp_aux_cmd_fifo_tx(aux, msg); 380 378 381 379 if (ret < 0) { 380 + if (aux->native) { 381 + aux->retry_cnt++; 382 + if (!(aux->retry_cnt % MAX_AUX_RETRIES)) 383 + dp_catalog_aux_update_cfg(aux->catalog); 384 + } 382 385 usleep_range(400, 500); /* at least 400us to next try */ 383 386 goto unlock_exit; 384 387 }
+1 -1
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
··· 163 163 break; 164 164 case MSM_DSI_PHY_7NM: 165 165 case MSM_DSI_PHY_7NM_V4_1: 166 - pll = msm_dsi_pll_7nm_init(pdev, id); 166 + pll = msm_dsi_pll_7nm_init(pdev, type, id); 167 167 break; 168 168 default: 169 169 pll = ERR_PTR(-ENXIO);
+4 -2
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
··· 117 117 } 118 118 #endif 119 119 #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY 120 - struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id); 120 + struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, 121 + enum msm_dsi_phy_type type, int id); 121 122 #else 122 123 static inline struct msm_dsi_pll * 123 - msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) 124 + msm_dsi_pll_7nm_init(struct platform_device *pdev, 125 + enum msm_dsi_phy_type type, int id) 124 126 { 125 127 return ERR_PTR(-ENODEV); 126 128 }
+6 -5
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
··· 325 325 pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); 326 326 pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); 327 327 pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); 328 - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); 328 + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); 329 329 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); 330 330 pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ 331 331 pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); ··· 509 509 { 510 510 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); 511 511 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); 512 + struct dsi_pll_config *config = &pll_7nm->pll_configuration; 512 513 void __iomem *base = pll_7nm->mmio; 513 514 u64 ref_clk = pll_7nm->vco_ref_clk_rate; 514 515 u64 vco_rate = 0x0; ··· 530 529 /* 531 530 * TODO: 532 531 * 1. Assumes prescaler is disabled 533 - * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits) 534 532 */ 535 - multiplier = 1 << 18; 533 + multiplier = 1 << config->frac_bits; 536 534 pll_freq = dec * (ref_clk * 2); 537 535 tmp64 = (ref_clk * 2 * frac); 538 536 pll_freq += div_u64(tmp64, multiplier); ··· 852 852 return ret; 853 853 } 854 854 855 - struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) 855 + struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, 856 + enum msm_dsi_phy_type type, int id) 856 857 { 857 858 struct dsi_pll_7nm *pll_7nm; 858 859 struct msm_dsi_pll *pll; ··· 886 885 pll = &pll_7nm->base; 887 886 pll->min_rate = 1000000000UL; 888 887 pll->max_rate = 3500000000UL; 889 - if (pll->type == MSM_DSI_PHY_7NM_V4_1) { 888 + if (type == MSM_DSI_PHY_7NM_V4_1) { 890 889 pll->min_rate = 600000000UL; 891 890 pll->max_rate = (unsigned long)5000000000ULL; 892 891 /* workaround for max rate overflowing on 32-bit builds: */
+5 -2
drivers/gpu/drm/msm/msm_atomic.c
··· 57 57 58 58 static void lock_crtcs(struct msm_kms *kms, unsigned int crtc_mask) 59 59 { 60 + int crtc_index; 60 61 struct drm_crtc *crtc; 61 62 62 - for_each_crtc_mask(kms->dev, crtc, crtc_mask) 63 - mutex_lock(&kms->commit_lock[drm_crtc_index(crtc)]); 63 + for_each_crtc_mask(kms->dev, crtc, crtc_mask) { 64 + crtc_index = drm_crtc_index(crtc); 65 + mutex_lock_nested(&kms->commit_lock[crtc_index], crtc_index); 66 + } 64 67 } 65 68 66 69 static void unlock_crtcs(struct msm_kms *kms, unsigned int crtc_mask)
+12
drivers/gpu/drm/msm/msm_drv.c
··· 1072 1072 static int __maybe_unused msm_pm_prepare(struct device *dev) 1073 1073 { 1074 1074 struct drm_device *ddev = dev_get_drvdata(dev); 1075 + struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1076 + 1077 + if (!priv || !priv->kms) 1078 + return 0; 1075 1079 1076 1080 return drm_mode_config_helper_suspend(ddev); 1077 1081 } ··· 1083 1079 static void __maybe_unused msm_pm_complete(struct device *dev) 1084 1080 { 1085 1081 struct drm_device *ddev = dev_get_drvdata(dev); 1082 + struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1083 + 1084 + if (!priv || !priv->kms) 1085 + return; 1086 1086 1087 1087 drm_mode_config_helper_resume(ddev); 1088 1088 } ··· 1319 1311 static void msm_pdev_shutdown(struct platform_device *pdev) 1320 1312 { 1321 1313 struct drm_device *drm = platform_get_drvdata(pdev); 1314 + struct msm_drm_private *priv = drm ? drm->dev_private : NULL; 1315 + 1316 + if (!priv || !priv->kms) 1317 + return; 1322 1318 1323 1319 drm_atomic_helper_shutdown(drm); 1324 1320 }
+1 -1
drivers/gpu/drm/msm/msm_fence.c
··· 45 45 int ret; 46 46 47 47 if (fence > fctx->last_fence) { 48 - DRM_ERROR("%s: waiting on invalid fence: %u (of %u)\n", 48 + DRM_ERROR_RATELIMITED("%s: waiting on invalid fence: %u (of %u)\n", 49 49 fctx->name, fence, fctx->last_fence); 50 50 return -EINVAL; 51 51 }
+2 -6
drivers/gpu/drm/msm/msm_kms.h
··· 157 157 * from the crtc's pending_timer close to end of the frame: 158 158 */ 159 159 struct mutex commit_lock[MAX_CRTCS]; 160 - struct lock_class_key commit_lock_keys[MAX_CRTCS]; 161 160 unsigned pending_crtc_mask; 162 161 struct msm_pending_timer pending_timers[MAX_CRTCS]; 163 162 }; ··· 166 167 { 167 168 unsigned i, ret; 168 169 169 - for (i = 0; i < ARRAY_SIZE(kms->commit_lock); i++) { 170 - lockdep_register_key(&kms->commit_lock_keys[i]); 171 - __mutex_init(&kms->commit_lock[i], "&kms->commit_lock[i]", 172 - &kms->commit_lock_keys[i]); 173 - } 170 + for (i = 0; i < ARRAY_SIZE(kms->commit_lock); i++) 171 + mutex_init(&kms->commit_lock[i]); 174 172 175 173 kms->funcs = funcs; 176 174
+12 -1
drivers/gpu/drm/nouveau/dispnv50/disp.c
··· 2693 2693 else 2694 2694 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2695 2695 2696 - if (disp->disp->object.oclass >= GK104_DISP) { 2696 + /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later 2697 + * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The 2698 + * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to 2699 + * small page allocations in prepare_fb(). When this is implemented, we should also force 2700 + * large pages (128K) for ovly fbs in order to fix Kepler ovlys. 2701 + * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using 2702 + * large pages. 2703 + */ 2704 + if (disp->disp->object.oclass >= GM107_DISP) { 2697 2705 dev->mode_config.cursor_width = 256; 2698 2706 dev->mode_config.cursor_height = 256; 2707 + } else if (disp->disp->object.oclass >= GK104_DISP) { 2708 + dev->mode_config.cursor_width = 128; 2709 + dev->mode_config.cursor_height = 128; 2699 2710 } else { 2700 2711 dev->mode_config.cursor_width = 64; 2701 2712 dev->mode_config.cursor_height = 64;
+6 -25
drivers/gpu/drm/rcar-du/rcar_du_encoder.c
··· 48 48 static const struct drm_encoder_funcs rcar_du_encoder_funcs = { 49 49 }; 50 50 51 - static void rcar_du_encoder_release(struct drm_device *dev, void *res) 52 - { 53 - struct rcar_du_encoder *renc = res; 54 - 55 - drm_encoder_cleanup(&renc->base); 56 - kfree(renc); 57 - } 58 - 59 51 int rcar_du_encoder_init(struct rcar_du_device *rcdu, 60 52 enum rcar_du_output output, 61 53 struct device_node *enc_node) 62 54 { 63 55 struct rcar_du_encoder *renc; 64 56 struct drm_bridge *bridge; 65 - int ret; 66 57 67 58 /* 68 59 * Locate the DRM bridge from the DT node. For the DPAD outputs, if the ··· 92 101 return -ENOLINK; 93 102 } 94 103 95 - renc = kzalloc(sizeof(*renc), GFP_KERNEL); 96 - if (renc == NULL) 97 - return -ENOMEM; 98 - 99 - renc->output = output; 100 - 101 104 dev_dbg(rcdu->dev, "initializing encoder %pOF for output %u\n", 102 105 enc_node, output); 103 106 104 - ret = drm_encoder_init(&rcdu->ddev, &renc->base, &rcar_du_encoder_funcs, 105 - DRM_MODE_ENCODER_NONE, NULL); 106 - if (ret < 0) { 107 - kfree(renc); 108 - return ret; 109 - } 107 + renc = drmm_encoder_alloc(&rcdu->ddev, struct rcar_du_encoder, base, 108 + &rcar_du_encoder_funcs, DRM_MODE_ENCODER_NONE, 109 + NULL); 110 + if (!renc) 111 + return -ENOMEM; 110 112 111 - ret = drmm_add_action_or_reset(&rcdu->ddev, rcar_du_encoder_release, 112 - renc); 113 - if (ret) 114 - return ret; 113 + renc->output = output; 115 114 116 115 /* 117 116 * Attach the bridge to the encoder. The bridge will create the