+2794 -9

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

reviewed

··· 32 32 #include "resource.h" 33 33 #include "dc_dmub_srv.h" 34 34 #include "dc_state_priv.h" 35 35 + #include "opp.h" 36 36 + #include "dsc.h" 37 37 + #include "dchubbub.h" 38 38 + #include "dccg.h" 39 39 + #include "abm.h" 40 40 + #include "dcn10/dcn10_hubbub.h" 35 41 36 42 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 37 43 #define MAX_NUM_MCACHE 8 ··· 790 784 while (current_mpc_pipe) { 791 785 if (current_mpc_pipe->plane_state) { 792 786 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) { 793 793 - block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe; 787 787 + block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp; 794 788 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate; 795 789 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL; 796 790 (*num_steps)++; ··· 955 949 params->pipe_control_lock_params.lock); 956 950 break; 957 951 case HUBP_SET_FLIP_CONTROL_GSL: 958 958 - dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx, 959 959 - params->set_flip_control_gsl_params.flip_immediate); 952 952 + params->set_flip_control_gsl_params.hubp->funcs->hubp_set_flip_control_surface_gsl( 953 953 + params->set_flip_control_gsl_params.hubp, 954 954 + params->set_flip_control_gsl_params.flip_immediate); 960 955 break; 961 956 case HUBP_PROGRAM_TRIPLEBUFFER: 962 957 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc, ··· 1018 1011 case DMUB_HW_CONTROL_LOCK_FAST: 1019 1012 dc->hwss.dmub_hw_control_lock_fast(params); 1020 1013 break; 1014 1014 + case HUBP_PROGRAM_SURFACE_CONFIG: 1015 1015 + hwss_program_surface_config(params); 1016 1016 + break; 1017 1017 + case HUBP_PROGRAM_MCACHE_ID: 1018 1018 + hwss_program_mcache_id_and_split_coordinate(params); 1019 1019 + break; 1021 1020 case PROGRAM_CURSOR_UPDATE_NOW: 1022 1021 dc->hwss.program_cursor_offload_now( 1023 1022 params->program_cursor_update_now_params.dc, 1024 1023 params->program_cursor_update_now_params.pipe_ctx); 1025 1024 break; 1025 1025 + case HUBP_WAIT_PIPE_READ_START: 1026 1026 + params->hubp_wait_pipe_read_start_params.hubp->funcs->hubp_wait_pipe_read_start( 1027 1027 + params->hubp_wait_pipe_read_start_params.hubp); 1028 1028 + break; 1029 1029 + case HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM: 1030 1030 + dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx); 1031 1031 + break; 1032 1032 + case HWS_UPDATE_PHANTOM_VP_POSITION: 1033 1033 + dc->hwss.update_phantom_vp_position(params->update_phantom_vp_position_params.dc, 1034 1034 + params->update_phantom_vp_position_params.context, 1035 1035 + params->update_phantom_vp_position_params.pipe_ctx); 1036 1036 + break; 1037 1037 + case OPTC_SET_ODM_COMBINE: 1038 1038 + hwss_set_odm_combine(params); 1039 1039 + break; 1040 1040 + case OPTC_SET_ODM_BYPASS: 1041 1041 + hwss_set_odm_bypass(params); 1042 1042 + break; 1043 1043 + case OPP_PIPE_CLOCK_CONTROL: 1044 1044 + hwss_opp_pipe_clock_control(params); 1045 1045 + break; 1046 1046 + case OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL: 1047 1047 + hwss_opp_program_left_edge_extra_pixel(params); 1048 1048 + break; 1049 1049 + case DCCG_SET_DTO_DSCCLK: 1050 1050 + hwss_dccg_set_dto_dscclk(params); 1051 1051 + break; 1052 1052 + case DSC_SET_CONFIG: 1053 1053 + hwss_dsc_set_config(params); 1054 1054 + break; 1055 1055 + case DSC_ENABLE: 1056 1056 + hwss_dsc_enable(params); 1057 1057 + break; 1058 1058 + case TG_SET_DSC_CONFIG: 1059 1059 + hwss_tg_set_dsc_config(params); 1060 1060 + break; 1061 1061 + case DSC_DISCONNECT: 1062 1062 + hwss_dsc_disconnect(params); 1063 1063 + break; 1064 1064 + case DSC_READ_STATE: 1065 1065 + hwss_dsc_read_state(params); 1066 1066 + break; 1067 1067 + case DSC_CALCULATE_AND_SET_CONFIG: 1068 1068 + hwss_dsc_calculate_and_set_config(params); 1069 1069 + break; 1070 1070 + case DSC_ENABLE_WITH_OPP: 1071 1071 + hwss_dsc_enable_with_opp(params); 1072 1072 + break; 1073 1073 + case TG_PROGRAM_GLOBAL_SYNC: 1074 1074 + hwss_tg_program_global_sync(params); 1075 1075 + break; 1076 1076 + case TG_WAIT_FOR_STATE: 1077 1077 + hwss_tg_wait_for_state(params); 1078 1078 + break; 1079 1079 + case TG_SET_VTG_PARAMS: 1080 1080 + hwss_tg_set_vtg_params(params); 1081 1081 + break; 1082 1082 + case TG_SETUP_VERTICAL_INTERRUPT2: 1083 1083 + hwss_tg_setup_vertical_interrupt2(params); 1084 1084 + break; 1085 1085 + case DPP_SET_HDR_MULTIPLIER: 1086 1086 + hwss_dpp_set_hdr_multiplier(params); 1087 1087 + break; 1088 1088 + case HUBP_PROGRAM_DET_SIZE: 1089 1089 + hwss_program_det_size(params); 1090 1090 + break; 1091 1091 + case HUBP_PROGRAM_DET_SEGMENTS: 1092 1092 + hwss_program_det_segments(params); 1093 1093 + break; 1094 1094 + case OPP_SET_DYN_EXPANSION: 1095 1095 + hwss_opp_set_dyn_expansion(params); 1096 1096 + break; 1097 1097 + case OPP_PROGRAM_FMT: 1098 1098 + hwss_opp_program_fmt(params); 1099 1099 + break; 1100 1100 + case OPP_PROGRAM_BIT_DEPTH_REDUCTION: 1101 1101 + hwss_opp_program_bit_depth_reduction(params); 1102 1102 + break; 1103 1103 + case OPP_SET_DISP_PATTERN_GENERATOR: 1104 1104 + hwss_opp_set_disp_pattern_generator(params); 1105 1105 + break; 1106 1106 + case ABM_SET_PIPE: 1107 1107 + hwss_set_abm_pipe(params); 1108 1108 + break; 1109 1109 + case ABM_SET_LEVEL: 1110 1110 + hwss_set_abm_level(params); 1111 1111 + break; 1112 1112 + case ABM_SET_IMMEDIATE_DISABLE: 1113 1113 + hwss_set_abm_immediate_disable(params); 1114 1114 + break; 1115 1115 + case MPC_REMOVE_MPCC: 1116 1116 + hwss_mpc_remove_mpcc(params); 1117 1117 + break; 1118 1118 + case OPP_SET_MPCC_DISCONNECT_PENDING: 1119 1119 + hwss_opp_set_mpcc_disconnect_pending(params); 1120 1120 + break; 1121 1121 + case DC_SET_OPTIMIZED_REQUIRED: 1122 1122 + hwss_dc_set_optimized_required(params); 1123 1123 + break; 1124 1124 + case HUBP_DISCONNECT: 1125 1125 + hwss_hubp_disconnect(params); 1126 1126 + break; 1127 1127 + case HUBBUB_FORCE_PSTATE_CHANGE_CONTROL: 1128 1128 + hwss_hubbub_force_pstate_change_control(params); 1129 1129 + break; 1130 1130 + case TG_ENABLE_CRTC: 1131 1131 + hwss_tg_enable_crtc(params); 1132 1132 + break; 1133 1133 + case TG_SET_GSL: 1134 1134 + hwss_tg_set_gsl(params); 1135 1135 + break; 1136 1136 + case TG_SET_GSL_SOURCE_SELECT: 1137 1137 + hwss_tg_set_gsl_source_select(params); 1138 1138 + break; 1139 1139 + case HUBP_WAIT_FLIP_PENDING: 1140 1140 + hwss_hubp_wait_flip_pending(params); 1141 1141 + break; 1142 1142 + case TG_WAIT_DOUBLE_BUFFER_PENDING: 1143 1143 + hwss_tg_wait_double_buffer_pending(params); 1144 1144 + break; 1145 1145 + case UPDATE_FORCE_PSTATE: 1146 1146 + hwss_update_force_pstate(params); 1147 1147 + break; 1148 1148 + case HUBBUB_APPLY_DEDCN21_147_WA: 1149 1149 + hwss_hubbub_apply_dedcn21_147_wa(params); 1150 1150 + break; 1151 1151 + case HUBBUB_ALLOW_SELF_REFRESH_CONTROL: 1152 1152 + hwss_hubbub_allow_self_refresh_control(params); 1153 1153 + break; 1154 1154 + case TG_GET_FRAME_COUNT: 1155 1155 + hwss_tg_get_frame_count(params); 1156 1156 + break; 1157 1157 + case MPC_SET_DWB_MUX: 1158 1158 + hwss_mpc_set_dwb_mux(params); 1159 1159 + break; 1160 1160 + case MPC_DISABLE_DWB_MUX: 1161 1161 + hwss_mpc_disable_dwb_mux(params); 1162 1162 + break; 1163 1163 + case MCIF_WB_CONFIG_BUF: 1164 1164 + hwss_mcif_wb_config_buf(params); 1165 1165 + break; 1166 1166 + case MCIF_WB_CONFIG_ARB: 1167 1167 + hwss_mcif_wb_config_arb(params); 1168 1168 + break; 1169 1169 + case MCIF_WB_ENABLE: 1170 1170 + hwss_mcif_wb_enable(params); 1171 1171 + break; 1172 1172 + case MCIF_WB_DISABLE: 1173 1173 + hwss_mcif_wb_disable(params); 1174 1174 + break; 1175 1175 + case DWBC_ENABLE: 1176 1176 + hwss_dwbc_enable(params); 1177 1177 + break; 1178 1178 + case DWBC_DISABLE: 1179 1179 + hwss_dwbc_disable(params); 1180 1180 + break; 1181 1181 + case DWBC_UPDATE: 1182 1182 + hwss_dwbc_update(params); 1183 1183 + break; 1184 1184 + case HUBP_UPDATE_MALL_SEL: 1185 1185 + hwss_hubp_update_mall_sel(params); 1186 1186 + break; 1187 1187 + case HUBP_PREPARE_SUBVP_BUFFERING: 1188 1188 + hwss_hubp_prepare_subvp_buffering(params); 1189 1189 + break; 1190 1190 + case HUBP_SET_BLANK_EN: 1191 1191 + hwss_hubp_set_blank_en(params); 1192 1192 + break; 1193 1193 + case HUBP_DISABLE_CONTROL: 1194 1194 + hwss_hubp_disable_control(params); 1195 1195 + break; 1196 1196 + case HUBBUB_SOFT_RESET: 1197 1197 + hwss_hubbub_soft_reset(params); 1198 1198 + break; 1199 1199 + case HUBP_CLK_CNTL: 1200 1200 + hwss_hubp_clk_cntl(params); 1201 1201 + break; 1202 1202 + case HUBP_INIT: 1203 1203 + hwss_hubp_init(params); 1204 1204 + break; 1205 1205 + case HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS: 1206 1206 + hwss_hubp_set_vm_system_aperture_settings(params); 1207 1207 + break; 1208 1208 + case HUBP_SET_FLIP_INT: 1209 1209 + hwss_hubp_set_flip_int(params); 1210 1210 + break; 1211 1211 + case DPP_DPPCLK_CONTROL: 1212 1212 + hwss_dpp_dppclk_control(params); 1213 1213 + break; 1214 1214 + case DISABLE_PHANTOM_CRTC: 1215 1215 + hwss_disable_phantom_crtc(params); 1216 1216 + break; 1217 1217 + case DSC_PG_STATUS: 1218 1218 + hwss_dsc_pg_status(params); 1219 1219 + break; 1220 1220 + case DSC_WAIT_DISCONNECT_PENDING_CLEAR: 1221 1221 + hwss_dsc_wait_disconnect_pending_clear(params); 1222 1222 + break; 1223 1223 + case DSC_DISABLE: 1224 1224 + hwss_dsc_disable(params); 1225 1225 + break; 1226 1226 + case DCCG_SET_REF_DSCCLK: 1227 1227 + hwss_dccg_set_ref_dscclk(params); 1228 1228 + break; 1229 1229 + case DPP_PG_CONTROL: 1230 1230 + hwss_dpp_pg_control(params); 1231 1231 + break; 1232 1232 + case HUBP_PG_CONTROL: 1233 1233 + hwss_hubp_pg_control(params); 1234 1234 + break; 1235 1235 + case HUBP_RESET: 1236 1236 + hwss_hubp_reset(params); 1237 1237 + break; 1238 1238 + case DPP_RESET: 1239 1239 + hwss_dpp_reset(params); 1240 1240 + break; 1241 1241 + case DPP_ROOT_CLOCK_CONTROL: 1242 1242 + hwss_dpp_root_clock_control(params); 1243 1243 + break; 1244 1244 + case DC_IP_REQUEST_CNTL: 1245 1245 + hwss_dc_ip_request_cntl(params); 1246 1246 + break; 1247 1247 + case DCCG_UPDATE_DPP_DTO: 1248 1248 + hwss_dccg_update_dpp_dto(params); 1249 1249 + break; 1250 1250 + case HUBP_VTG_SEL: 1251 1251 + hwss_hubp_vtg_sel(params); 1252 1252 + break; 1253 1253 + case HUBP_SETUP2: 1254 1254 + hwss_hubp_setup2(params); 1255 1255 + break; 1256 1256 + case HUBP_SETUP: 1257 1257 + hwss_hubp_setup(params); 1258 1258 + break; 1259 1259 + case HUBP_SET_UNBOUNDED_REQUESTING: 1260 1260 + hwss_hubp_set_unbounded_requesting(params); 1261 1261 + break; 1262 1262 + case HUBP_SETUP_INTERDEPENDENT2: 1263 1263 + hwss_hubp_setup_interdependent2(params); 1264 1264 + break; 1265 1265 + case HUBP_SETUP_INTERDEPENDENT: 1266 1266 + hwss_hubp_setup_interdependent(params); 1267 1267 + break; 1268 1268 + case DPP_SET_CURSOR_MATRIX: 1269 1269 + hwss_dpp_set_cursor_matrix(params); 1270 1270 + break; 1271 1271 + case MPC_UPDATE_BLENDING: 1272 1272 + hwss_mpc_update_blending(params); 1273 1273 + break; 1274 1274 + case MPC_ASSERT_IDLE_MPCC: 1275 1275 + hwss_mpc_assert_idle_mpcc(params); 1276 1276 + break; 1277 1277 + case MPC_INSERT_PLANE: 1278 1278 + hwss_mpc_insert_plane(params); 1279 1279 + break; 1280 1280 + case DPP_SET_SCALER: 1281 1281 + hwss_dpp_set_scaler(params); 1282 1282 + break; 1283 1283 + case HUBP_MEM_PROGRAM_VIEWPORT: 1284 1284 + hwss_hubp_mem_program_viewport(params); 1285 1285 + break; 1286 1286 + case SET_CURSOR_ATTRIBUTE: 1287 1287 + hwss_set_cursor_attribute(params); 1288 1288 + break; 1289 1289 + case SET_CURSOR_POSITION: 1290 1290 + hwss_set_cursor_position(params); 1291 1291 + break; 1292 1292 + case SET_CURSOR_SDR_WHITE_LEVEL: 1293 1293 + hwss_set_cursor_sdr_white_level(params); 1294 1294 + break; 1295 1295 + case PROGRAM_OUTPUT_CSC: 1296 1296 + hwss_program_output_csc(params); 1297 1297 + break; 1298 1298 + case HUBP_SET_BLANK: 1299 1299 + hwss_hubp_set_blank(params); 1300 1300 + break; 1301 1301 + case PHANTOM_HUBP_POST_ENABLE: 1302 1302 + hwss_phantom_hubp_post_enable(params); 1303 1303 + break; 1026 1304 default: 1027 1305 ASSERT(false); 1028 1306 break; 1029 1307 } 1308 1308 + } 1309 1309 + } 1310 1310 + 1311 1311 + /** 1312 1312 + * Helper function to add OPTC pipe control lock to block sequence 1313 1313 + */ 1314 1314 + void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, 1315 1315 + struct dc *dc, 1316 1316 + struct pipe_ctx *pipe_ctx, 1317 1317 + bool lock) 1318 1318 + { 1319 1319 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1320 1320 + seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc; 1321 1321 + seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; 1322 1322 + seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.lock = lock; 1323 1323 + seq_state->steps[*seq_state->num_steps].func = OPTC_PIPE_CONTROL_LOCK; 1324 1324 + (*seq_state->num_steps)++; 1325 1325 + } 1326 1326 + } 1327 1327 + 1328 1328 + /** 1329 1329 + * Helper function to add HUBP set flip control GSL to block sequence 1330 1330 + */ 1331 1331 + void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, 1332 1332 + struct hubp *hubp, 1333 1333 + bool flip_immediate) 1334 1334 + { 1335 1335 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1336 1336 + seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp; 1337 1337 + seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.flip_immediate = flip_immediate; 1338 1338 + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_CONTROL_GSL; 1339 1339 + (*seq_state->num_steps)++; 1340 1340 + } 1341 1341 + } 1342 1342 + 1343 1343 + /** 1344 1344 + * Helper function to add HUBP program triplebuffer to block sequence 1345 1345 + */ 1346 1346 + void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, 1347 1347 + struct dc *dc, 1348 1348 + struct pipe_ctx *pipe_ctx, 1349 1349 + bool enableTripleBuffer) 1350 1350 + { 1351 1351 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1352 1352 + seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.dc = dc; 1353 1353 + seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx; 1354 1354 + seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.enableTripleBuffer = enableTripleBuffer; 1355 1355 + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER; 1356 1356 + (*seq_state->num_steps)++; 1357 1357 + } 1358 1358 + } 1359 1359 + 1360 1360 + /** 1361 1361 + * Helper function to add HUBP update plane address to block sequence 1362 1362 + */ 1363 1363 + void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, 1364 1364 + struct dc *dc, 1365 1365 + struct pipe_ctx *pipe_ctx) 1366 1366 + { 1367 1367 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1368 1368 + seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.dc = dc; 1369 1369 + seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx; 1370 1370 + seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_PLANE_ADDR; 1371 1371 + (*seq_state->num_steps)++; 1372 1372 + } 1373 1373 + } 1374 1374 + 1375 1375 + /** 1376 1376 + * Helper function to add DPP set input transfer function to block sequence 1377 1377 + */ 1378 1378 + void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, 1379 1379 + struct dc *dc, 1380 1380 + struct pipe_ctx *pipe_ctx, 1381 1381 + struct dc_plane_state *plane_state) 1382 1382 + { 1383 1383 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1384 1384 + seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.dc = dc; 1385 1385 + seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx; 1386 1386 + seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state; 1387 1387 + seq_state->steps[*seq_state->num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC; 1388 1388 + (*seq_state->num_steps)++; 1389 1389 + } 1390 1390 + } 1391 1391 + 1392 1392 + /** 1393 1393 + * Helper function to add DPP program gamut remap to block sequence 1394 1394 + */ 1395 1395 + void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, 1396 1396 + struct pipe_ctx *pipe_ctx) 1397 1397 + { 1398 1398 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1399 1399 + seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx; 1400 1400 + seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_GAMUT_REMAP; 1401 1401 + (*seq_state->num_steps)++; 1402 1402 + } 1403 1403 + } 1404 1404 + 1405 1405 + /** 1406 1406 + * Helper function to add DPP program bias and scale to block sequence 1407 1407 + */ 1408 1408 + void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx) 1409 1409 + { 1410 1410 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1411 1411 + seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx; 1412 1412 + seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE; 1413 1413 + (*seq_state->num_steps)++; 1414 1414 + } 1415 1415 + } 1416 1416 + 1417 1417 + /** 1418 1418 + * Helper function to add OPTC program manual trigger to block sequence 1419 1419 + */ 1420 1420 + void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, 1421 1421 + struct pipe_ctx *pipe_ctx) 1422 1422 + { 1423 1423 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1424 1424 + seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx; 1425 1425 + seq_state->steps[*seq_state->num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER; 1426 1426 + (*seq_state->num_steps)++; 1427 1427 + } 1428 1428 + } 1429 1429 + 1430 1430 + /** 1431 1431 + * Helper function to add DPP set output transfer function to block sequence 1432 1432 + */ 1433 1433 + void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, 1434 1434 + struct dc *dc, 1435 1435 + struct pipe_ctx *pipe_ctx, 1436 1436 + struct dc_stream_state *stream) 1437 1437 + { 1438 1438 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1439 1439 + seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc; 1440 1440 + seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx; 1441 1441 + seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.stream = stream; 1442 1442 + seq_state->steps[*seq_state->num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC; 1443 1443 + (*seq_state->num_steps)++; 1444 1444 + } 1445 1445 + } 1446 1446 + 1447 1447 + /** 1448 1448 + * Helper function to add MPC update visual confirm to block sequence 1449 1449 + */ 1450 1450 + void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, 1451 1451 + struct dc *dc, 1452 1452 + struct pipe_ctx *pipe_ctx, 1453 1453 + int mpcc_id) 1454 1454 + { 1455 1455 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1456 1456 + seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.dc = dc; 1457 1457 + seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx; 1458 1458 + seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id; 1459 1459 + seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_VISUAL_CONFIRM; 1460 1460 + (*seq_state->num_steps)++; 1461 1461 + } 1462 1462 + } 1463 1463 + 1464 1464 + /** 1465 1465 + * Helper function to add MPC power on MPC mem PWR to block sequence 1466 1466 + */ 1467 1467 + void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, 1468 1468 + struct mpc *mpc, 1469 1469 + int mpcc_id, 1470 1470 + bool power_on) 1471 1471 + { 1472 1472 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1473 1473 + seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc; 1474 1474 + seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id; 1475 1475 + seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.power_on = power_on; 1476 1476 + seq_state->steps[*seq_state->num_steps].func = MPC_POWER_ON_MPC_MEM_PWR; 1477 1477 + (*seq_state->num_steps)++; 1478 1478 + } 1479 1479 + } 1480 1480 + 1481 1481 + /** 1482 1482 + * Helper function to add MPC set output CSC to block sequence 1483 1483 + */ 1484 1484 + void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, 1485 1485 + struct mpc *mpc, 1486 1486 + int opp_id, 1487 1487 + const uint16_t *regval, 1488 1488 + enum mpc_output_csc_mode ocsc_mode) 1489 1489 + { 1490 1490 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1491 1491 + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.mpc = mpc; 1492 1492 + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.opp_id = opp_id; 1493 1493 + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.regval = regval; 1494 1494 + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.ocsc_mode = ocsc_mode; 1495 1495 + seq_state->steps[*seq_state->num_steps].func = MPC_SET_OUTPUT_CSC; 1496 1496 + (*seq_state->num_steps)++; 1497 1497 + } 1498 1498 + } 1499 1499 + 1500 1500 + /** 1501 1501 + * Helper function to add MPC set OCSC default to block sequence 1502 1502 + */ 1503 1503 + void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, 1504 1504 + struct mpc *mpc, 1505 1505 + int opp_id, 1506 1506 + enum dc_color_space colorspace, 1507 1507 + enum mpc_output_csc_mode ocsc_mode) 1508 1508 + { 1509 1509 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1510 1510 + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.mpc = mpc; 1511 1511 + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.opp_id = opp_id; 1512 1512 + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.color_space = colorspace; 1513 1513 + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.ocsc_mode = ocsc_mode; 1514 1514 + seq_state->steps[*seq_state->num_steps].func = MPC_SET_OCSC_DEFAULT; 1515 1515 + (*seq_state->num_steps)++; 1516 1516 + } 1517 1517 + } 1518 1518 + 1519 1519 + /** 1520 1520 + * Helper function to add DMUB send DMCUB command to block sequence 1521 1521 + */ 1522 1522 + void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, 1523 1523 + struct dc_context *ctx, 1524 1524 + union dmub_rb_cmd *cmd, 1525 1525 + enum dm_dmub_wait_type wait_type) 1526 1526 + { 1527 1527 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1528 1528 + seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.ctx = ctx; 1529 1529 + seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.cmd = cmd; 1530 1530 + seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.wait_type = wait_type; 1531 1531 + seq_state->steps[*seq_state->num_steps].func = DMUB_SEND_DMCUB_CMD; 1532 1532 + (*seq_state->num_steps)++; 1533 1533 + } 1534 1534 + } 1535 1535 + 1536 1536 + /** 1537 1537 + * Helper function to add DMUB SubVP save surface address to block sequence 1538 1538 + */ 1539 1539 + void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, 1540 1540 + struct dc_dmub_srv *dc_dmub_srv, 1541 1541 + struct dc_plane_address *addr, 1542 1542 + uint8_t subvp_index) 1543 1543 + { 1544 1544 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1545 1545 + seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc_dmub_srv; 1546 1546 + seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.addr = addr; 1547 1547 + seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.subvp_index = subvp_index; 1548 1548 + seq_state->steps[*seq_state->num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR; 1549 1549 + (*seq_state->num_steps)++; 1550 1550 + } 1551 1551 + } 1552 1552 + 1553 1553 + /** 1554 1554 + * Helper function to add HUBP wait for DCC meta propagation to block sequence 1555 1555 + */ 1556 1556 + void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, 1557 1557 + struct dc *dc, 1558 1558 + struct pipe_ctx *top_pipe_to_program) 1559 1559 + { 1560 1560 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1561 1561 + seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; 1562 1562 + seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program; 1563 1563 + seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; 1564 1564 + (*seq_state->num_steps)++; 1565 1565 + } 1566 1566 + } 1567 1567 + 1568 1568 + /** 1569 1569 + * Helper function to add HUBP wait pipe read start to block sequence 1570 1570 + */ 1571 1571 + void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, 1572 1572 + struct hubp *hubp) 1573 1573 + { 1574 1574 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1575 1575 + seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp; 1576 1576 + seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_PIPE_READ_START; 1577 1577 + (*seq_state->num_steps)++; 1578 1578 + } 1579 1579 + } 1580 1580 + 1581 1581 + /** 1582 1582 + * Helper function to add HWS apply update flags for phantom to block sequence 1583 1583 + */ 1584 1584 + void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, 1585 1585 + struct pipe_ctx *pipe_ctx) 1586 1586 + { 1587 1587 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1588 1588 + seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx; 1589 1589 + seq_state->steps[*seq_state->num_steps].func = HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM; 1590 1590 + (*seq_state->num_steps)++; 1591 1591 + } 1592 1592 + } 1593 1593 + 1594 1594 + /** 1595 1595 + * Helper function to add HWS update phantom VP position to block sequence 1596 1596 + */ 1597 1597 + void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, 1598 1598 + struct dc *dc, 1599 1599 + struct dc_state *context, 1600 1600 + struct pipe_ctx *pipe_ctx) 1601 1601 + { 1602 1602 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1603 1603 + seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.dc = dc; 1604 1604 + seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.context = context; 1605 1605 + seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx; 1606 1606 + seq_state->steps[*seq_state->num_steps].func = HWS_UPDATE_PHANTOM_VP_POSITION; 1607 1607 + (*seq_state->num_steps)++; 1608 1608 + } 1609 1609 + } 1610 1610 + 1611 1611 + /** 1612 1612 + * Helper function to add OPTC set ODM combine to block sequence 1613 1613 + */ 1614 1614 + void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, 1615 1615 + struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, 1616 1616 + int odm_slice_width, int last_odm_slice_width) 1617 1617 + { 1618 1618 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1619 1619 + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.tg = tg; 1620 1620 + memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES); 1621 1621 + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_head_count = opp_head_count; 1622 1622 + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.odm_slice_width = odm_slice_width; 1623 1623 + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.last_odm_slice_width = last_odm_slice_width; 1624 1624 + seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_COMBINE; 1625 1625 + (*seq_state->num_steps)++; 1626 1626 + } 1627 1627 + } 1628 1628 + 1629 1629 + /** 1630 1630 + * Helper function to add OPTC set ODM bypass to block sequence 1631 1631 + */ 1632 1632 + void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, 1633 1633 + struct timing_generator *tg, struct dc_crtc_timing *timing) 1634 1634 + { 1635 1635 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1636 1636 + seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.tg = tg; 1637 1637 + seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.timing = timing; 1638 1638 + seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_BYPASS; 1639 1639 + (*seq_state->num_steps)++; 1030 1640 } 1031 1641 } 1032 1642 ··· 1654 1030 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type; 1655 1031 1656 1032 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type); 1033 1033 + } 1034 1034 + 1035 1035 + /** 1036 1036 + * Helper function to add TG program global sync to block sequence 1037 1037 + */ 1038 1038 + void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, 1039 1039 + struct timing_generator *tg, 1040 1040 + int vready_offset, 1041 1041 + unsigned int vstartup_lines, 1042 1042 + unsigned int vupdate_offset_pixels, 1043 1043 + unsigned int vupdate_vupdate_width_pixels, 1044 1044 + unsigned int pstate_keepout_start_lines) 1045 1045 + { 1046 1046 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1047 1047 + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.tg = tg; 1048 1048 + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vready_offset = vready_offset; 1049 1049 + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vstartup_lines = vstartup_lines; 1050 1050 + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_offset_pixels = vupdate_offset_pixels; 1051 1051 + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_vupdate_width_pixels = vupdate_vupdate_width_pixels; 1052 1052 + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.pstate_keepout_start_lines = pstate_keepout_start_lines; 1053 1053 + seq_state->steps[*seq_state->num_steps].func = TG_PROGRAM_GLOBAL_SYNC; 1054 1054 + (*seq_state->num_steps)++; 1055 1055 + } 1056 1056 + } 1057 1057 + 1058 1058 + /** 1059 1059 + * Helper function to add TG wait for state to block sequence 1060 1060 + */ 1061 1061 + void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, 1062 1062 + struct timing_generator *tg, 1063 1063 + enum crtc_state state) 1064 1064 + { 1065 1065 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1066 1066 + seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.tg = tg; 1067 1067 + seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.state = state; 1068 1068 + seq_state->steps[*seq_state->num_steps].func = TG_WAIT_FOR_STATE; 1069 1069 + (*seq_state->num_steps)++; 1070 1070 + } 1071 1071 + } 1072 1072 + 1073 1073 + /** 1074 1074 + * Helper function to add TG set VTG params to block sequence 1075 1075 + */ 1076 1076 + void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, 1077 1077 + struct timing_generator *tg, 1078 1078 + struct dc_crtc_timing *dc_crtc_timing, 1079 1079 + bool program_fp2) 1080 1080 + { 1081 1081 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1082 1082 + seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.tg = tg; 1083 1083 + seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing; 1084 1084 + seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.program_fp2 = program_fp2; 1085 1085 + seq_state->steps[*seq_state->num_steps].func = TG_SET_VTG_PARAMS; 1086 1086 + (*seq_state->num_steps)++; 1087 1087 + } 1088 1088 + } 1089 1089 + 1090 1090 + /** 1091 1091 + * Helper function to add TG setup vertical interrupt2 to block sequence 1092 1092 + */ 1093 1093 + void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, 1094 1094 + struct timing_generator *tg, int start_line) 1095 1095 + { 1096 1096 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1097 1097 + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.tg = tg; 1098 1098 + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.start_line = start_line; 1099 1099 + seq_state->steps[*seq_state->num_steps].func = TG_SETUP_VERTICAL_INTERRUPT2; 1100 1100 + (*seq_state->num_steps)++; 1101 1101 + } 1102 1102 + } 1103 1103 + 1104 1104 + /** 1105 1105 + * Helper function to add DPP set HDR multiplier to block sequence 1106 1106 + */ 1107 1107 + void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, 1108 1108 + struct dpp *dpp, uint32_t hw_mult) 1109 1109 + { 1110 1110 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1111 1111 + seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp; 1112 1112 + seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.hw_mult = hw_mult; 1113 1113 + seq_state->steps[*seq_state->num_steps].func = DPP_SET_HDR_MULTIPLIER; 1114 1114 + (*seq_state->num_steps)++; 1115 1115 + } 1116 1116 + } 1117 1117 + 1118 1118 + /** 1119 1119 + * Helper function to add HUBP program DET size to block sequence 1120 1120 + */ 1121 1121 + void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, 1122 1122 + struct hubbub *hubbub, 1123 1123 + unsigned int hubp_inst, 1124 1124 + unsigned int det_buffer_size_kb) 1125 1125 + { 1126 1126 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1127 1127 + seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubbub = hubbub; 1128 1128 + seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubp_inst = hubp_inst; 1129 1129 + seq_state->steps[*seq_state->num_steps].params.program_det_size_params.det_buffer_size_kb = det_buffer_size_kb; 1130 1130 + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SIZE; 1131 1131 + (*seq_state->num_steps)++; 1132 1132 + } 1133 1133 + } 1134 1134 + 1135 1135 + void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, 1136 1136 + struct hubp *hubp, 1137 1137 + struct dml2_hubp_pipe_mcache_regs *mcache_regs) 1138 1138 + { 1139 1139 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1140 1140 + seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp; 1141 1141 + seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.mcache_regs = mcache_regs; 1142 1142 + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_MCACHE_ID; 1143 1143 + (*seq_state->num_steps)++; 1144 1144 + } 1145 1145 + } 1146 1146 + 1147 1147 + void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, 1148 1148 + struct hubbub *hubbub, 1149 1149 + bool enable, 1150 1150 + bool wait) 1151 1151 + { 1152 1152 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1153 1153 + seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.hubbub = hubbub; 1154 1154 + seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.enable = enable; 1155 1155 + seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.wait = wait; 1156 1156 + seq_state->steps[*seq_state->num_steps].func = HUBBUB_FORCE_PSTATE_CHANGE_CONTROL; 1157 1157 + (*seq_state->num_steps)++; 1158 1158 + } 1159 1159 + } 1160 1160 + 1161 1161 + /** 1162 1162 + * Helper function to add HUBP program DET segments to block sequence 1163 1163 + */ 1164 1164 + void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, 1165 1165 + struct hubbub *hubbub, 1166 1166 + unsigned int hubp_inst, 1167 1167 + unsigned int det_size) 1168 1168 + { 1169 1169 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1170 1170 + seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubbub = hubbub; 1171 1171 + seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubp_inst = hubp_inst; 1172 1172 + seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.det_size = det_size; 1173 1173 + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SEGMENTS; 1174 1174 + (*seq_state->num_steps)++; 1175 1175 + } 1176 1176 + } 1177 1177 + 1178 1178 + /** 1179 1179 + * Helper function to add OPP set dynamic expansion to block sequence 1180 1180 + */ 1181 1181 + void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, 1182 1182 + struct output_pixel_processor *opp, 1183 1183 + enum dc_color_space color_space, 1184 1184 + enum dc_color_depth color_depth, 1185 1185 + enum signal_type signal) 1186 1186 + { 1187 1187 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1188 1188 + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.opp = opp; 1189 1189 + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_space = color_space; 1190 1190 + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_depth = color_depth; 1191 1191 + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.signal = signal; 1192 1192 + seq_state->steps[*seq_state->num_steps].func = OPP_SET_DYN_EXPANSION; 1193 1193 + (*seq_state->num_steps)++; 1194 1194 + } 1195 1195 + } 1196 1196 + 1197 1197 + /** 1198 1198 + * Helper function to add OPP program FMT to block sequence 1199 1199 + */ 1200 1200 + void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, 1201 1201 + struct output_pixel_processor *opp, 1202 1202 + struct bit_depth_reduction_params *fmt_bit_depth, 1203 1203 + struct clamping_and_pixel_encoding_params *clamping) 1204 1204 + { 1205 1205 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1206 1206 + seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.opp = opp; 1207 1207 + seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.fmt_bit_depth = fmt_bit_depth; 1208 1208 + seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.clamping = clamping; 1209 1209 + seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_FMT; 1210 1210 + (*seq_state->num_steps)++; 1211 1211 + } 1212 1212 + } 1213 1213 + 1214 1214 + void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, 1215 1215 + struct output_pixel_processor *opp, 1216 1216 + enum dc_pixel_encoding pixel_encoding, 1217 1217 + bool is_otg_master) 1218 1218 + { 1219 1219 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1220 1220 + seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL; 1221 1221 + seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.opp = opp; 1222 1222 + seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.pixel_encoding = pixel_encoding; 1223 1223 + seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.is_otg_master = is_otg_master; 1224 1224 + (*seq_state->num_steps)++; 1225 1225 + } 1226 1226 + } 1227 1227 + 1228 1228 + /** 1229 1229 + * Helper function to add ABM set pipe to block sequence 1230 1230 + */ 1231 1231 + void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, 1232 1232 + struct dc *dc, 1233 1233 + struct pipe_ctx *pipe_ctx) 1234 1234 + { 1235 1235 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1236 1236 + seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.dc = dc; 1237 1237 + seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx; 1238 1238 + seq_state->steps[*seq_state->num_steps].func = ABM_SET_PIPE; 1239 1239 + (*seq_state->num_steps)++; 1240 1240 + } 1241 1241 + } 1242 1242 + 1243 1243 + /** 1244 1244 + * Helper function to add ABM set level to block sequence 1245 1245 + */ 1246 1246 + void hwss_add_abm_set_level(struct block_sequence_state *seq_state, 1247 1247 + struct abm *abm, 1248 1248 + uint32_t abm_level) 1249 1249 + { 1250 1250 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1251 1251 + seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm = abm; 1252 1252 + seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm_level = abm_level; 1253 1253 + seq_state->steps[*seq_state->num_steps].func = ABM_SET_LEVEL; 1254 1254 + (*seq_state->num_steps)++; 1255 1255 + } 1256 1256 + } 1257 1257 + 1258 1258 + /** 1259 1259 + * Helper function to add TG enable CRTC to block sequence 1260 1260 + */ 1261 1261 + void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, 1262 1262 + struct timing_generator *tg) 1263 1263 + { 1264 1264 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1265 1265 + seq_state->steps[*seq_state->num_steps].params.tg_enable_crtc_params.tg = tg; 1266 1266 + seq_state->steps[*seq_state->num_steps].func = TG_ENABLE_CRTC; 1267 1267 + (*seq_state->num_steps)++; 1268 1268 + } 1269 1269 + } 1270 1270 + 1271 1271 + /** 1272 1272 + * Helper function to add HUBP wait flip pending to block sequence 1273 1273 + */ 1274 1274 + void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, 1275 1275 + struct hubp *hubp, 1276 1276 + unsigned int timeout_us, 1277 1277 + unsigned int polling_interval_us) 1278 1278 + { 1279 1279 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1280 1280 + seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp; 1281 1281 + seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.timeout_us = timeout_us; 1282 1282 + seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.polling_interval_us = polling_interval_us; 1283 1283 + seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FLIP_PENDING; 1284 1284 + (*seq_state->num_steps)++; 1285 1285 + } 1286 1286 + } 1287 1287 + 1288 1288 + /** 1289 1289 + * Helper function to add TG wait double buffer pending to block sequence 1290 1290 + */ 1291 1291 + void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, 1292 1292 + struct timing_generator *tg, 1293 1293 + unsigned int timeout_us, 1294 1294 + unsigned int polling_interval_us) 1295 1295 + { 1296 1296 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1297 1297 + seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.tg = tg; 1298 1298 + seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.timeout_us = timeout_us; 1299 1299 + seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.polling_interval_us = polling_interval_us; 1300 1300 + seq_state->steps[*seq_state->num_steps].func = TG_WAIT_DOUBLE_BUFFER_PENDING; 1301 1301 + (*seq_state->num_steps)++; 1302 1302 + } 1657 1303 } 1658 1304 1659 1305 void hwss_program_manual_trigger(union block_sequence_params *params) ··· 1951 1057 plane_state->input_csc_color_matrix, 1952 1058 plane_state->color_space, 1953 1059 NULL); 1954 1954 - } 1955 1955 - 1956 1956 - if (dpp && dpp->funcs->set_cursor_matrix) { 1957 1957 - dpp->funcs->set_cursor_matrix(dpp, 1958 1958 - plane_state->color_space, 1959 1959 - plane_state->cursor_csc_color_matrix); 1960 1060 } 1961 1061 } 1962 1062 ··· 2012 1124 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index; 2013 1125 2014 1126 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index); 1127 1127 + } 1128 1128 + 1129 1129 + void hwss_program_surface_config(union block_sequence_params *params) 1130 1130 + { 1131 1131 + struct hubp *hubp = params->program_surface_config_params.hubp; 1132 1132 + enum surface_pixel_format format = params->program_surface_config_params.format; 1133 1133 + struct dc_tiling_info *tiling_info = params->program_surface_config_params.tiling_info; 1134 1134 + struct plane_size size = params->program_surface_config_params.plane_size; 1135 1135 + enum dc_rotation_angle rotation = params->program_surface_config_params.rotation; 1136 1136 + struct dc_plane_dcc_param *dcc = params->program_surface_config_params.dcc; 1137 1137 + bool horizontal_mirror = params->program_surface_config_params.horizontal_mirror; 1138 1138 + int compat_level = params->program_surface_config_params.compat_level; 1139 1139 + 1140 1140 + hubp->funcs->hubp_program_surface_config( 1141 1141 + hubp, 1142 1142 + format, 1143 1143 + tiling_info, 1144 1144 + &size, 1145 1145 + rotation, 1146 1146 + dcc, 1147 1147 + horizontal_mirror, 1148 1148 + compat_level); 1149 1149 + 1150 1150 + hubp->power_gated = false; 1151 1151 + } 1152 1152 + 1153 1153 + void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params) 1154 1154 + { 1155 1155 + struct hubp *hubp = params->program_mcache_id_and_split_coordinate.hubp; 1156 1156 + struct dml2_hubp_pipe_mcache_regs *mcache_regs = params->program_mcache_id_and_split_coordinate.mcache_regs; 1157 1157 + 1158 1158 + hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs); 1159 1159 + 2015 1160 } 2016 1161 2017 1162 void get_surface_tile_visual_confirm_color( ··· 2196 1275 /* perform outstanding post update programming */ 2197 1276 if (dc->hwss.program_outstanding_updates) 2198 1277 dc->hwss.program_outstanding_updates(dc, dc_context); 1278 1278 + } 1279 1279 + 1280 1280 + void hwss_set_odm_combine(union block_sequence_params *params) 1281 1281 + { 1282 1282 + struct timing_generator *tg = params->set_odm_combine_params.tg; 1283 1283 + int *opp_inst = params->set_odm_combine_params.opp_inst; 1284 1284 + int opp_head_count = params->set_odm_combine_params.opp_head_count; 1285 1285 + int odm_slice_width = params->set_odm_combine_params.odm_slice_width; 1286 1286 + int last_odm_slice_width = params->set_odm_combine_params.last_odm_slice_width; 1287 1287 + 1288 1288 + if (tg && tg->funcs->set_odm_combine) 1289 1289 + tg->funcs->set_odm_combine(tg, opp_inst, opp_head_count, 1290 1290 + odm_slice_width, last_odm_slice_width); 1291 1291 + } 1292 1292 + 1293 1293 + void hwss_set_odm_bypass(union block_sequence_params *params) 1294 1294 + { 1295 1295 + struct timing_generator *tg = params->set_odm_bypass_params.tg; 1296 1296 + const struct dc_crtc_timing *timing = params->set_odm_bypass_params.timing; 1297 1297 + 1298 1298 + if (tg && tg->funcs->set_odm_bypass) 1299 1299 + tg->funcs->set_odm_bypass(tg, timing); 1300 1300 + } 1301 1301 + 1302 1302 + void hwss_opp_pipe_clock_control(union block_sequence_params *params) 1303 1303 + { 1304 1304 + struct output_pixel_processor *opp = params->opp_pipe_clock_control_params.opp; 1305 1305 + bool enable = params->opp_pipe_clock_control_params.enable; 1306 1306 + 1307 1307 + if (opp && opp->funcs->opp_pipe_clock_control) 1308 1308 + opp->funcs->opp_pipe_clock_control(opp, enable); 1309 1309 + } 1310 1310 + 1311 1311 + void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params) 1312 1312 + { 1313 1313 + struct output_pixel_processor *opp = params->opp_program_left_edge_extra_pixel_params.opp; 1314 1314 + enum dc_pixel_encoding pixel_encoding = params->opp_program_left_edge_extra_pixel_params.pixel_encoding; 1315 1315 + bool is_otg_master = params->opp_program_left_edge_extra_pixel_params.is_otg_master; 1316 1316 + 1317 1317 + if (opp && opp->funcs->opp_program_left_edge_extra_pixel) 1318 1318 + opp->funcs->opp_program_left_edge_extra_pixel(opp, pixel_encoding, is_otg_master); 1319 1319 + } 1320 1320 + 1321 1321 + void hwss_dccg_set_dto_dscclk(union block_sequence_params *params) 1322 1322 + { 1323 1323 + struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg; 1324 1324 + int inst = params->dccg_set_dto_dscclk_params.inst; 1325 1325 + int num_slices_h = params->dccg_set_dto_dscclk_params.num_slices_h; 1326 1326 + 1327 1327 + if (dccg && dccg->funcs->set_dto_dscclk) 1328 1328 + dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h); 1329 1329 + } 1330 1330 + 1331 1331 + void hwss_dsc_set_config(union block_sequence_params *params) 1332 1332 + { 1333 1333 + struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc; 1334 1334 + struct dsc_config *dsc_cfg = params->dsc_set_config_params.dsc_cfg; 1335 1335 + struct dsc_optc_config *dsc_optc_cfg = params->dsc_set_config_params.dsc_optc_cfg; 1336 1336 + 1337 1337 + if (dsc && dsc->funcs->dsc_set_config) 1338 1338 + dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); 1339 1339 + } 1340 1340 + 1341 1341 + void hwss_dsc_enable(union block_sequence_params *params) 1342 1342 + { 1343 1343 + struct display_stream_compressor *dsc = params->dsc_enable_params.dsc; 1344 1344 + int opp_inst = params->dsc_enable_params.opp_inst; 1345 1345 + 1346 1346 + if (dsc && dsc->funcs->dsc_enable) 1347 1347 + dsc->funcs->dsc_enable(dsc, opp_inst); 1348 1348 + } 1349 1349 + 1350 1350 + void hwss_tg_set_dsc_config(union block_sequence_params *params) 1351 1351 + { 1352 1352 + struct timing_generator *tg = params->tg_set_dsc_config_params.tg; 1353 1353 + enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED; 1354 1354 + uint32_t bytes_per_pixel = 0; 1355 1355 + uint32_t slice_width = 0; 1356 1356 + 1357 1357 + if (params->tg_set_dsc_config_params.enable) { 1358 1358 + struct dsc_optc_config *dsc_optc_cfg = params->tg_set_dsc_config_params.dsc_optc_cfg; 1359 1359 + if (dsc_optc_cfg) { 1360 1360 + bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel; 1361 1361 + slice_width = dsc_optc_cfg->slice_width; 1362 1362 + optc_dsc_mode = dsc_optc_cfg->is_pixel_format_444 ? 1363 1363 + OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1364 1364 + } 1365 1365 + } 1366 1366 + 1367 1367 + if (tg && tg->funcs->set_dsc_config) 1368 1368 + tg->funcs->set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width); 1369 1369 + } 1370 1370 + 1371 1371 + void hwss_dsc_disconnect(union block_sequence_params *params) 1372 1372 + { 1373 1373 + struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc; 1374 1374 + 1375 1375 + if (dsc && dsc->funcs->dsc_disconnect) 1376 1376 + dsc->funcs->dsc_disconnect(dsc); 1377 1377 + } 1378 1378 + 1379 1379 + void hwss_dsc_read_state(union block_sequence_params *params) 1380 1380 + { 1381 1381 + struct display_stream_compressor *dsc = params->dsc_read_state_params.dsc; 1382 1382 + struct dcn_dsc_state *dsc_state = params->dsc_read_state_params.dsc_state; 1383 1383 + 1384 1384 + if (dsc && dsc->funcs->dsc_read_state) 1385 1385 + dsc->funcs->dsc_read_state(dsc, dsc_state); 1386 1386 + } 1387 1387 + 1388 1388 + void hwss_dsc_calculate_and_set_config(union block_sequence_params *params) 1389 1389 + { 1390 1390 + struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx; 1391 1391 + struct pipe_ctx *top_pipe = pipe_ctx; 1392 1392 + bool enable = params->dsc_calculate_and_set_config_params.enable; 1393 1393 + int opp_cnt = params->dsc_calculate_and_set_config_params.opp_cnt; 1394 1394 + 1395 1395 + struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1396 1396 + struct dc_stream_state *stream = pipe_ctx->stream; 1397 1397 + 1398 1398 + if (!dsc || !enable) 1399 1399 + return; 1400 1400 + 1401 1401 + /* Calculate DSC configuration - extracted from dcn32_update_dsc_on_stream */ 1402 1402 + struct dsc_config dsc_cfg; 1403 1403 + 1404 1404 + while (top_pipe->prev_odm_pipe) 1405 1405 + top_pipe = top_pipe->prev_odm_pipe; 1406 1406 + 1407 1407 + dsc_cfg.pic_width = (stream->timing.h_addressable + top_pipe->dsc_padding_params.dsc_hactive_padding + 1408 1408 + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1409 1409 + dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1410 1410 + dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1411 1411 + dsc_cfg.color_depth = stream->timing.display_color_depth; 1412 1412 + dsc_cfg.is_odm = top_pipe->next_odm_pipe ? true : false; 1413 1413 + dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1414 1414 + dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1415 1415 + dsc_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding; 1416 1416 + 1417 1417 + /* Set DSC configuration */ 1418 1418 + if (dsc->funcs->dsc_set_config) 1419 1419 + dsc->funcs->dsc_set_config(dsc, &dsc_cfg, 1420 1420 + &params->dsc_calculate_and_set_config_params.dsc_optc_cfg); 1421 1421 + } 1422 1422 + 1423 1423 + void hwss_dsc_enable_with_opp(union block_sequence_params *params) 1424 1424 + { 1425 1425 + struct pipe_ctx *pipe_ctx = params->dsc_enable_with_opp_params.pipe_ctx; 1426 1426 + struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1427 1427 + 1428 1428 + if (dsc && dsc->funcs->dsc_enable) 1429 1429 + dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1430 1430 + } 1431 1431 + 1432 1432 + void hwss_tg_program_global_sync(union block_sequence_params *params) 1433 1433 + { 1434 1434 + struct timing_generator *tg = params->tg_program_global_sync_params.tg; 1435 1435 + int vready_offset = params->tg_program_global_sync_params.vready_offset; 1436 1436 + unsigned int vstartup_lines = params->tg_program_global_sync_params.vstartup_lines; 1437 1437 + unsigned int vupdate_offset_pixels = params->tg_program_global_sync_params.vupdate_offset_pixels; 1438 1438 + unsigned int vupdate_vupdate_width_pixels = params->tg_program_global_sync_params.vupdate_vupdate_width_pixels; 1439 1439 + unsigned int pstate_keepout_start_lines = params->tg_program_global_sync_params.pstate_keepout_start_lines; 1440 1440 + 1441 1441 + if (tg->funcs->program_global_sync) { 1442 1442 + tg->funcs->program_global_sync(tg, vready_offset, vstartup_lines, 1443 1443 + vupdate_offset_pixels, vupdate_vupdate_width_pixels, pstate_keepout_start_lines); 1444 1444 + } 1445 1445 + } 1446 1446 + 1447 1447 + void hwss_tg_wait_for_state(union block_sequence_params *params) 1448 1448 + { 1449 1449 + struct timing_generator *tg = params->tg_wait_for_state_params.tg; 1450 1450 + enum crtc_state state = params->tg_wait_for_state_params.state; 1451 1451 + 1452 1452 + if (tg->funcs->wait_for_state) { 1453 1453 + tg->funcs->wait_for_state(tg, state); 1454 1454 + } 1455 1455 + } 1456 1456 + 1457 1457 + void hwss_tg_set_vtg_params(union block_sequence_params *params) 1458 1458 + { 1459 1459 + struct timing_generator *tg = params->tg_set_vtg_params_params.tg; 1460 1460 + struct dc_crtc_timing *timing = params->tg_set_vtg_params_params.timing; 1461 1461 + bool program_fp2 = params->tg_set_vtg_params_params.program_fp2; 1462 1462 + 1463 1463 + if (tg->funcs->set_vtg_params) { 1464 1464 + tg->funcs->set_vtg_params(tg, timing, program_fp2); 1465 1465 + } 1466 1466 + } 1467 1467 + 1468 1468 + void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params) 1469 1469 + { 1470 1470 + struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg; 1471 1471 + int start_line = params->tg_setup_vertical_interrupt2_params.start_line; 1472 1472 + 1473 1473 + if (tg->funcs->setup_vertical_interrupt2) { 1474 1474 + tg->funcs->setup_vertical_interrupt2(tg, start_line); 1475 1475 + } 1476 1476 + } 1477 1477 + 1478 1478 + void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params) 1479 1479 + { 1480 1480 + struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp; 1481 1481 + uint32_t hw_mult = params->dpp_set_hdr_multiplier_params.hw_mult; 1482 1482 + 1483 1483 + if (dpp->funcs->dpp_set_hdr_multiplier) { 1484 1484 + dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult); 1485 1485 + } 1486 1486 + } 1487 1487 + 1488 1488 + void hwss_program_det_size(union block_sequence_params *params) 1489 1489 + { 1490 1490 + struct hubbub *hubbub = params->program_det_size_params.hubbub; 1491 1491 + unsigned int hubp_inst = params->program_det_size_params.hubp_inst; 1492 1492 + unsigned int det_buffer_size_kb = params->program_det_size_params.det_buffer_size_kb; 1493 1493 + 1494 1494 + if (hubbub->funcs->program_det_size) { 1495 1495 + hubbub->funcs->program_det_size(hubbub, hubp_inst, det_buffer_size_kb); 1496 1496 + } 1497 1497 + } 1498 1498 + 1499 1499 + void hwss_program_det_segments(union block_sequence_params *params) 1500 1500 + { 1501 1501 + struct hubbub *hubbub = params->program_det_segments_params.hubbub; 1502 1502 + unsigned int hubp_inst = params->program_det_segments_params.hubp_inst; 1503 1503 + unsigned int det_size = params->program_det_segments_params.det_size; 1504 1504 + 1505 1505 + if (hubbub->funcs->program_det_segments) { 1506 1506 + hubbub->funcs->program_det_segments(hubbub, hubp_inst, det_size); 1507 1507 + } 1508 1508 + } 1509 1509 + 1510 1510 + void hwss_opp_set_dyn_expansion(union block_sequence_params *params) 1511 1511 + { 1512 1512 + struct output_pixel_processor *opp = params->opp_set_dyn_expansion_params.opp; 1513 1513 + enum dc_color_space color_space = params->opp_set_dyn_expansion_params.color_space; 1514 1514 + enum dc_color_depth color_depth = params->opp_set_dyn_expansion_params.color_depth; 1515 1515 + enum signal_type signal = params->opp_set_dyn_expansion_params.signal; 1516 1516 + 1517 1517 + if (opp->funcs->opp_set_dyn_expansion) { 1518 1518 + opp->funcs->opp_set_dyn_expansion(opp, color_space, color_depth, signal); 1519 1519 + } 1520 1520 + } 1521 1521 + 1522 1522 + void hwss_opp_program_fmt(union block_sequence_params *params) 1523 1523 + { 1524 1524 + struct output_pixel_processor *opp = params->opp_program_fmt_params.opp; 1525 1525 + struct bit_depth_reduction_params *fmt_bit_depth = params->opp_program_fmt_params.fmt_bit_depth; 1526 1526 + struct clamping_and_pixel_encoding_params *clamping = params->opp_program_fmt_params.clamping; 1527 1527 + 1528 1528 + if (opp->funcs->opp_program_fmt) { 1529 1529 + opp->funcs->opp_program_fmt(opp, fmt_bit_depth, clamping); 1530 1530 + } 1531 1531 + } 1532 1532 + 1533 1533 + void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params) 1534 1534 + { 1535 1535 + struct output_pixel_processor *opp = params->opp_program_bit_depth_reduction_params.opp; 1536 1536 + bool use_default_params = params->opp_program_bit_depth_reduction_params.use_default_params; 1537 1537 + struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx; 1538 1538 + struct bit_depth_reduction_params bit_depth_params; 1539 1539 + 1540 1540 + if (use_default_params) { 1541 1541 + memset(&bit_depth_params, 0, sizeof(bit_depth_params)); 1542 1542 + } else { 1543 1543 + resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params); 1544 1544 + } 1545 1545 + 1546 1546 + if (opp->funcs->opp_program_bit_depth_reduction) { 1547 1547 + opp->funcs->opp_program_bit_depth_reduction(opp, &bit_depth_params); 1548 1548 + } 1549 1549 + } 1550 1550 + 1551 1551 + void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params) 1552 1552 + { 1553 1553 + struct output_pixel_processor *opp = params->opp_set_disp_pattern_generator_params.opp; 1554 1554 + enum controller_dp_test_pattern test_pattern = params->opp_set_disp_pattern_generator_params.test_pattern; 1555 1555 + enum controller_dp_color_space color_space = params->opp_set_disp_pattern_generator_params.color_space; 1556 1556 + enum dc_color_depth color_depth = params->opp_set_disp_pattern_generator_params.color_depth; 1557 1557 + struct tg_color *solid_color = params->opp_set_disp_pattern_generator_params.use_solid_color ? 1558 1558 + &params->opp_set_disp_pattern_generator_params.solid_color : NULL; 1559 1559 + int width = params->opp_set_disp_pattern_generator_params.width; 1560 1560 + int height = params->opp_set_disp_pattern_generator_params.height; 1561 1561 + int offset = params->opp_set_disp_pattern_generator_params.offset; 1562 1562 + 1563 1563 + if (opp && opp->funcs->opp_set_disp_pattern_generator) { 1564 1564 + opp->funcs->opp_set_disp_pattern_generator(opp, test_pattern, color_space, 1565 1565 + color_depth, solid_color, width, height, offset); 1566 1566 + } 1567 1567 + } 1568 1568 + 1569 1569 + void hwss_set_abm_pipe(union block_sequence_params *params) 1570 1570 + { 1571 1571 + struct dc *dc = params->set_abm_pipe_params.dc; 1572 1572 + struct pipe_ctx *pipe_ctx = params->set_abm_pipe_params.pipe_ctx; 1573 1573 + 1574 1574 + dc->hwss.set_pipe(pipe_ctx); 1575 1575 + } 1576 1576 + 1577 1577 + void hwss_set_abm_level(union block_sequence_params *params) 1578 1578 + { 1579 1579 + struct abm *abm = params->set_abm_level_params.abm; 1580 1580 + unsigned int abm_level = params->set_abm_level_params.abm_level; 1581 1581 + 1582 1582 + if (abm->funcs->set_abm_level) { 1583 1583 + abm->funcs->set_abm_level(abm, abm_level); 1584 1584 + } 1585 1585 + } 1586 1586 + 1587 1587 + void hwss_set_abm_immediate_disable(union block_sequence_params *params) 1588 1588 + { 1589 1589 + struct dc *dc = params->set_abm_immediate_disable_params.dc; 1590 1590 + struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx; 1591 1591 + 1592 1592 + if (dc && dc->hwss.set_abm_immediate_disable) { 1593 1593 + dc->hwss.set_abm_immediate_disable(pipe_ctx); 1594 1594 + } 1595 1595 + } 1596 1596 + 1597 1597 + void hwss_mpc_remove_mpcc(union block_sequence_params *params) 1598 1598 + { 1599 1599 + struct mpc *mpc = params->mpc_remove_mpcc_params.mpc; 1600 1600 + struct mpc_tree *mpc_tree_params = params->mpc_remove_mpcc_params.mpc_tree_params; 1601 1601 + struct mpcc *mpcc_to_remove = params->mpc_remove_mpcc_params.mpcc_to_remove; 1602 1602 + 1603 1603 + mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); 1604 1604 + } 1605 1605 + 1606 1606 + void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params) 1607 1607 + { 1608 1608 + struct output_pixel_processor *opp = params->opp_set_mpcc_disconnect_pending_params.opp; 1609 1609 + int mpcc_inst = params->opp_set_mpcc_disconnect_pending_params.mpcc_inst; 1610 1610 + bool pending = params->opp_set_mpcc_disconnect_pending_params.pending; 1611 1611 + 1612 1612 + opp->mpcc_disconnect_pending[mpcc_inst] = pending; 1613 1613 + } 1614 1614 + 1615 1615 + void hwss_dc_set_optimized_required(union block_sequence_params *params) 1616 1616 + { 1617 1617 + struct dc *dc = params->dc_set_optimized_required_params.dc; 1618 1618 + bool optimized_required = params->dc_set_optimized_required_params.optimized_required; 1619 1619 + 1620 1620 + dc->optimized_required = optimized_required; 1621 1621 + } 1622 1622 + 1623 1623 + void hwss_hubp_disconnect(union block_sequence_params *params) 1624 1624 + { 1625 1625 + struct hubp *hubp = params->hubp_disconnect_params.hubp; 1626 1626 + 1627 1627 + if (hubp->funcs->hubp_disconnect) 1628 1628 + hubp->funcs->hubp_disconnect(hubp); 1629 1629 + } 1630 1630 + 1631 1631 + void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params) 1632 1632 + { 1633 1633 + struct hubbub *hubbub = params->hubbub_force_pstate_change_control_params.hubbub; 1634 1634 + bool enable = params->hubbub_force_pstate_change_control_params.enable; 1635 1635 + bool wait = params->hubbub_force_pstate_change_control_params.wait; 1636 1636 + 1637 1637 + if (hubbub->funcs->force_pstate_change_control) { 1638 1638 + hubbub->funcs->force_pstate_change_control(hubbub, enable, wait); 1639 1639 + /* Add delay when enabling pstate change control */ 1640 1640 + if (enable) 1641 1641 + udelay(500); 1642 1642 + } 1643 1643 + } 1644 1644 + 1645 1645 + void hwss_tg_enable_crtc(union block_sequence_params *params) 1646 1646 + { 1647 1647 + struct timing_generator *tg = params->tg_enable_crtc_params.tg; 1648 1648 + 1649 1649 + if (tg->funcs->enable_crtc) 1650 1650 + tg->funcs->enable_crtc(tg); 1651 1651 + } 1652 1652 + 1653 1653 + void hwss_tg_set_gsl(union block_sequence_params *params) 1654 1654 + { 1655 1655 + struct timing_generator *tg = params->tg_set_gsl_params.tg; 1656 1656 + struct gsl_params *gsl = &params->tg_set_gsl_params.gsl; 1657 1657 + 1658 1658 + if (tg->funcs->set_gsl) 1659 1659 + tg->funcs->set_gsl(tg, gsl); 1660 1660 + } 1661 1661 + 1662 1662 + void hwss_tg_set_gsl_source_select(union block_sequence_params *params) 1663 1663 + { 1664 1664 + struct timing_generator *tg = params->tg_set_gsl_source_select_params.tg; 1665 1665 + int group_idx = params->tg_set_gsl_source_select_params.group_idx; 1666 1666 + uint32_t gsl_ready_signal = params->tg_set_gsl_source_select_params.gsl_ready_signal; 1667 1667 + 1668 1668 + if (tg->funcs->set_gsl_source_select) 1669 1669 + tg->funcs->set_gsl_source_select(tg, group_idx, gsl_ready_signal); 1670 1670 + } 1671 1671 + 1672 1672 + void hwss_hubp_wait_flip_pending(union block_sequence_params *params) 1673 1673 + { 1674 1674 + struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp; 1675 1675 + unsigned int timeout_us = params->hubp_wait_flip_pending_params.timeout_us; 1676 1676 + unsigned int polling_interval_us = params->hubp_wait_flip_pending_params.polling_interval_us; 1677 1677 + int j = 0; 1678 1678 + 1679 1679 + for (j = 0; j < timeout_us / polling_interval_us 1680 1680 + && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1681 1681 + udelay(polling_interval_us); 1682 1682 + } 1683 1683 + 1684 1684 + void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params) 1685 1685 + { 1686 1686 + struct timing_generator *tg = params->tg_wait_double_buffer_pending_params.tg; 1687 1687 + unsigned int timeout_us = params->tg_wait_double_buffer_pending_params.timeout_us; 1688 1688 + unsigned int polling_interval_us = params->tg_wait_double_buffer_pending_params.polling_interval_us; 1689 1689 + int j = 0; 1690 1690 + 1691 1691 + if (tg->funcs->get_optc_double_buffer_pending) { 1692 1692 + for (j = 0; j < timeout_us / polling_interval_us 1693 1693 + && tg->funcs->get_optc_double_buffer_pending(tg); j++) 1694 1694 + udelay(polling_interval_us); 1695 1695 + } 1696 1696 + } 1697 1697 + 1698 1698 + void hwss_update_force_pstate(union block_sequence_params *params) 1699 1699 + { 1700 1700 + struct dc *dc = params->update_force_pstate_params.dc; 1701 1701 + struct dc_state *context = params->update_force_pstate_params.context; 1702 1702 + struct dce_hwseq *hwseq = dc->hwseq; 1703 1703 + 1704 1704 + if (hwseq->funcs.update_force_pstate) 1705 1705 + hwseq->funcs.update_force_pstate(dc, context); 1706 1706 + } 1707 1707 + 1708 1708 + void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params) 1709 1709 + { 1710 1710 + struct hubbub *hubbub = params->hubbub_apply_dedcn21_147_wa_params.hubbub; 1711 1711 + 1712 1712 + hubbub->funcs->apply_DEDCN21_147_wa(hubbub); 1713 1713 + } 1714 1714 + 1715 1715 + void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params) 1716 1716 + { 1717 1717 + struct hubbub *hubbub = params->hubbub_allow_self_refresh_control_params.hubbub; 1718 1718 + bool allow = params->hubbub_allow_self_refresh_control_params.allow; 1719 1719 + 1720 1720 + hubbub->funcs->allow_self_refresh_control(hubbub, allow); 1721 1721 + 1722 1722 + if (!allow && params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied) 1723 1723 + *params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = true; 1724 1724 + } 1725 1725 + 1726 1726 + void hwss_tg_get_frame_count(union block_sequence_params *params) 1727 1727 + { 1728 1728 + struct timing_generator *tg = params->tg_get_frame_count_params.tg; 1729 1729 + unsigned int *frame_count = params->tg_get_frame_count_params.frame_count; 1730 1730 + 1731 1731 + *frame_count = tg->funcs->get_frame_count(tg); 1732 1732 + } 1733 1733 + 1734 1734 + void hwss_mpc_set_dwb_mux(union block_sequence_params *params) 1735 1735 + { 1736 1736 + struct mpc *mpc = params->mpc_set_dwb_mux_params.mpc; 1737 1737 + int dwb_id = params->mpc_set_dwb_mux_params.dwb_id; 1738 1738 + int mpcc_id = params->mpc_set_dwb_mux_params.mpcc_id; 1739 1739 + 1740 1740 + if (mpc->funcs->set_dwb_mux) 1741 1741 + mpc->funcs->set_dwb_mux(mpc, dwb_id, mpcc_id); 1742 1742 + } 1743 1743 + 1744 1744 + void hwss_mpc_disable_dwb_mux(union block_sequence_params *params) 1745 1745 + { 1746 1746 + struct mpc *mpc = params->mpc_disable_dwb_mux_params.mpc; 1747 1747 + unsigned int dwb_id = params->mpc_disable_dwb_mux_params.dwb_id; 1748 1748 + 1749 1749 + if (mpc->funcs->disable_dwb_mux) 1750 1750 + mpc->funcs->disable_dwb_mux(mpc, dwb_id); 1751 1751 + } 1752 1752 + 1753 1753 + void hwss_mcif_wb_config_buf(union block_sequence_params *params) 1754 1754 + { 1755 1755 + struct mcif_wb *mcif_wb = params->mcif_wb_config_buf_params.mcif_wb; 1756 1756 + struct mcif_buf_params *mcif_buf_params = params->mcif_wb_config_buf_params.mcif_buf_params; 1757 1757 + unsigned int dest_height = params->mcif_wb_config_buf_params.dest_height; 1758 1758 + 1759 1759 + if (mcif_wb->funcs->config_mcif_buf) 1760 1760 + mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, dest_height); 1761 1761 + } 1762 1762 + 1763 1763 + void hwss_mcif_wb_config_arb(union block_sequence_params *params) 1764 1764 + { 1765 1765 + struct mcif_wb *mcif_wb = params->mcif_wb_config_arb_params.mcif_wb; 1766 1766 + struct mcif_arb_params *mcif_arb_params = params->mcif_wb_config_arb_params.mcif_arb_params; 1767 1767 + 1768 1768 + if (mcif_wb->funcs->config_mcif_arb) 1769 1769 + mcif_wb->funcs->config_mcif_arb(mcif_wb, mcif_arb_params); 1770 1770 + } 1771 1771 + 1772 1772 + void hwss_mcif_wb_enable(union block_sequence_params *params) 1773 1773 + { 1774 1774 + struct mcif_wb *mcif_wb = params->mcif_wb_enable_params.mcif_wb; 1775 1775 + 1776 1776 + if (mcif_wb->funcs->enable_mcif) 1777 1777 + mcif_wb->funcs->enable_mcif(mcif_wb); 1778 1778 + } 1779 1779 + 1780 1780 + void hwss_mcif_wb_disable(union block_sequence_params *params) 1781 1781 + { 1782 1782 + struct mcif_wb *mcif_wb = params->mcif_wb_disable_params.mcif_wb; 1783 1783 + 1784 1784 + if (mcif_wb->funcs->disable_mcif) 1785 1785 + mcif_wb->funcs->disable_mcif(mcif_wb); 1786 1786 + } 1787 1787 + 1788 1788 + void hwss_dwbc_enable(union block_sequence_params *params) 1789 1789 + { 1790 1790 + struct dwbc *dwb = params->dwbc_enable_params.dwb; 1791 1791 + struct dc_dwb_params *dwb_params = params->dwbc_enable_params.dwb_params; 1792 1792 + 1793 1793 + if (dwb->funcs->enable) 1794 1794 + dwb->funcs->enable(dwb, dwb_params); 1795 1795 + } 1796 1796 + 1797 1797 + void hwss_dwbc_disable(union block_sequence_params *params) 1798 1798 + { 1799 1799 + struct dwbc *dwb = params->dwbc_disable_params.dwb; 1800 1800 + 1801 1801 + if (dwb->funcs->disable) 1802 1802 + dwb->funcs->disable(dwb); 1803 1803 + } 1804 1804 + 1805 1805 + void hwss_dwbc_update(union block_sequence_params *params) 1806 1806 + { 1807 1807 + struct dwbc *dwb = params->dwbc_update_params.dwb; 1808 1808 + struct dc_dwb_params *dwb_params = params->dwbc_update_params.dwb_params; 1809 1809 + 1810 1810 + if (dwb->funcs->update) 1811 1811 + dwb->funcs->update(dwb, dwb_params); 1812 1812 + } 1813 1813 + 1814 1814 + void hwss_hubp_update_mall_sel(union block_sequence_params *params) 1815 1815 + { 1816 1816 + struct hubp *hubp = params->hubp_update_mall_sel_params.hubp; 1817 1817 + uint32_t mall_sel = params->hubp_update_mall_sel_params.mall_sel; 1818 1818 + bool cache_cursor = params->hubp_update_mall_sel_params.cache_cursor; 1819 1819 + 1820 1820 + if (hubp && hubp->funcs->hubp_update_mall_sel) 1821 1821 + hubp->funcs->hubp_update_mall_sel(hubp, mall_sel, cache_cursor); 1822 1822 + } 1823 1823 + 1824 1824 + void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params) 1825 1825 + { 1826 1826 + struct hubp *hubp = params->hubp_prepare_subvp_buffering_params.hubp; 1827 1827 + bool enable = params->hubp_prepare_subvp_buffering_params.enable; 1828 1828 + 1829 1829 + if (hubp && hubp->funcs->hubp_prepare_subvp_buffering) 1830 1830 + hubp->funcs->hubp_prepare_subvp_buffering(hubp, enable); 1831 1831 + } 1832 1832 + 1833 1833 + void hwss_hubp_set_blank_en(union block_sequence_params *params) 1834 1834 + { 1835 1835 + struct hubp *hubp = params->hubp_set_blank_en_params.hubp; 1836 1836 + bool enable = params->hubp_set_blank_en_params.enable; 1837 1837 + 1838 1838 + if (hubp && hubp->funcs->set_hubp_blank_en) 1839 1839 + hubp->funcs->set_hubp_blank_en(hubp, enable); 1840 1840 + } 1841 1841 + 1842 1842 + void hwss_hubp_disable_control(union block_sequence_params *params) 1843 1843 + { 1844 1844 + struct hubp *hubp = params->hubp_disable_control_params.hubp; 1845 1845 + bool disable = params->hubp_disable_control_params.disable; 1846 1846 + 1847 1847 + if (hubp && hubp->funcs->hubp_disable_control) 1848 1848 + hubp->funcs->hubp_disable_control(hubp, disable); 1849 1849 + } 1850 1850 + 1851 1851 + void hwss_hubbub_soft_reset(union block_sequence_params *params) 1852 1852 + { 1853 1853 + struct hubbub *hubbub = params->hubbub_soft_reset_params.hubbub; 1854 1854 + bool reset = params->hubbub_soft_reset_params.reset; 1855 1855 + 1856 1856 + if (hubbub) 1857 1857 + params->hubbub_soft_reset_params.hubbub_soft_reset(hubbub, reset); 1858 1858 + } 1859 1859 + 1860 1860 + void hwss_hubp_clk_cntl(union block_sequence_params *params) 1861 1861 + { 1862 1862 + struct hubp *hubp = params->hubp_clk_cntl_params.hubp; 1863 1863 + bool enable = params->hubp_clk_cntl_params.enable; 1864 1864 + 1865 1865 + if (hubp && hubp->funcs->hubp_clk_cntl) { 1866 1866 + hubp->funcs->hubp_clk_cntl(hubp, enable); 1867 1867 + hubp->power_gated = !enable; 1868 1868 + } 1869 1869 + } 1870 1870 + 1871 1871 + void hwss_hubp_init(union block_sequence_params *params) 1872 1872 + { 1873 1873 + struct hubp *hubp = params->hubp_init_params.hubp; 1874 1874 + 1875 1875 + if (hubp && hubp->funcs->hubp_init) { 1876 1876 + hubp->funcs->hubp_init(hubp); 1877 1877 + } 1878 1878 + } 1879 1879 + 1880 1880 + void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params) 1881 1881 + { 1882 1882 + struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp; 1883 1883 + //struct vm_system_aperture_param *apt = &params->hubp_set_vm_system_aperture_settings_params.apt; 1884 1884 + struct vm_system_aperture_param apt; 1885 1885 + 1886 1886 + apt.sys_default = params->hubp_set_vm_system_aperture_settings_params.sys_default; 1887 1887 + apt.sys_high = params->hubp_set_vm_system_aperture_settings_params.sys_high; 1888 1888 + apt.sys_low = params->hubp_set_vm_system_aperture_settings_params.sys_low; 1889 1889 + 1890 1890 + if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings) { 1891 1891 + //hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, apt); 1892 1892 + hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); 1893 1893 + } 1894 1894 + } 1895 1895 + 1896 1896 + void hwss_hubp_set_flip_int(union block_sequence_params *params) 1897 1897 + { 1898 1898 + struct hubp *hubp = params->hubp_set_flip_int_params.hubp; 1899 1899 + 1900 1900 + if (hubp && hubp->funcs->hubp_set_flip_int) { 1901 1901 + hubp->funcs->hubp_set_flip_int(hubp); 1902 1902 + } 1903 1903 + } 1904 1904 + 1905 1905 + void hwss_dpp_dppclk_control(union block_sequence_params *params) 1906 1906 + { 1907 1907 + struct dpp *dpp = params->dpp_dppclk_control_params.dpp; 1908 1908 + bool dppclk_div = params->dpp_dppclk_control_params.dppclk_div; 1909 1909 + bool enable = params->dpp_dppclk_control_params.enable; 1910 1910 + 1911 1911 + if (dpp && dpp->funcs->dpp_dppclk_control) 1912 1912 + dpp->funcs->dpp_dppclk_control(dpp, dppclk_div, enable); 1913 1913 + } 1914 1914 + 1915 1915 + void hwss_disable_phantom_crtc(union block_sequence_params *params) 1916 1916 + { 1917 1917 + struct timing_generator *tg = params->disable_phantom_crtc_params.tg; 1918 1918 + 1919 1919 + if (tg && tg->funcs->disable_phantom_crtc) 1920 1920 + tg->funcs->disable_phantom_crtc(tg); 1921 1921 + } 1922 1922 + 1923 1923 + void hwss_dsc_pg_status(union block_sequence_params *params) 1924 1924 + { 1925 1925 + struct dce_hwseq *hws = params->dsc_pg_status_params.hws; 1926 1926 + int dsc_inst = params->dsc_pg_status_params.dsc_inst; 1927 1927 + 1928 1928 + if (hws && hws->funcs.dsc_pg_status) 1929 1929 + params->dsc_pg_status_params.is_ungated = hws->funcs.dsc_pg_status(hws, dsc_inst); 1930 1930 + } 1931 1931 + 1932 1932 + void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params) 1933 1933 + { 1934 1934 + struct display_stream_compressor *dsc = params->dsc_wait_disconnect_pending_clear_params.dsc; 1935 1935 + 1936 1936 + if (!params->dsc_wait_disconnect_pending_clear_params.is_ungated) 1937 1937 + return; 1938 1938 + if (*params->dsc_wait_disconnect_pending_clear_params.is_ungated == false) 1939 1939 + return; 1940 1940 + 1941 1941 + if (dsc && dsc->funcs->dsc_wait_disconnect_pending_clear) 1942 1942 + dsc->funcs->dsc_wait_disconnect_pending_clear(dsc); 1943 1943 + } 1944 1944 + 1945 1945 + void hwss_dsc_disable(union block_sequence_params *params) 1946 1946 + { 1947 1947 + struct display_stream_compressor *dsc = params->dsc_disable_params.dsc; 1948 1948 + 1949 1949 + if (!params->dsc_disable_params.is_ungated) 1950 1950 + return; 1951 1951 + if (*params->dsc_disable_params.is_ungated == false) 1952 1952 + return; 1953 1953 + 1954 1954 + if (dsc && dsc->funcs->dsc_disable) 1955 1955 + dsc->funcs->dsc_disable(dsc); 1956 1956 + } 1957 1957 + 1958 1958 + void hwss_dccg_set_ref_dscclk(union block_sequence_params *params) 1959 1959 + { 1960 1960 + struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; 1961 1961 + int dsc_inst = params->dccg_set_ref_dscclk_params.dsc_inst; 1962 1962 + 1963 1963 + if (!params->dccg_set_ref_dscclk_params.is_ungated) 1964 1964 + return; 1965 1965 + if (*params->dccg_set_ref_dscclk_params.is_ungated == false) 1966 1966 + return; 1967 1967 + 1968 1968 + if (dccg && dccg->funcs->set_ref_dscclk) 1969 1969 + dccg->funcs->set_ref_dscclk(dccg, dsc_inst); 1970 1970 + } 1971 1971 + 1972 1972 + void hwss_dpp_pg_control(union block_sequence_params *params) 1973 1973 + { 1974 1974 + struct dce_hwseq *hws = params->dpp_pg_control_params.hws; 1975 1975 + unsigned int dpp_inst = params->dpp_pg_control_params.dpp_inst; 1976 1976 + bool power_on = params->dpp_pg_control_params.power_on; 1977 1977 + 1978 1978 + if (hws->funcs.dpp_pg_control) 1979 1979 + hws->funcs.dpp_pg_control(hws, dpp_inst, power_on); 1980 1980 + } 1981 1981 + 1982 1982 + void hwss_hubp_pg_control(union block_sequence_params *params) 1983 1983 + { 1984 1984 + struct dce_hwseq *hws = params->hubp_pg_control_params.hws; 1985 1985 + unsigned int hubp_inst = params->hubp_pg_control_params.hubp_inst; 1986 1986 + bool power_on = params->hubp_pg_control_params.power_on; 1987 1987 + 1988 1988 + if (hws->funcs.hubp_pg_control) 1989 1989 + hws->funcs.hubp_pg_control(hws, hubp_inst, power_on); 1990 1990 + } 1991 1991 + 1992 1992 + void hwss_hubp_reset(union block_sequence_params *params) 1993 1993 + { 1994 1994 + struct hubp *hubp = params->hubp_reset_params.hubp; 1995 1995 + 1996 1996 + if (hubp && hubp->funcs->hubp_reset) 1997 1997 + hubp->funcs->hubp_reset(hubp); 1998 1998 + } 1999 1999 + 2000 2000 + void hwss_dpp_reset(union block_sequence_params *params) 2001 2001 + { 2002 2002 + struct dpp *dpp = params->dpp_reset_params.dpp; 2003 2003 + 2004 2004 + if (dpp && dpp->funcs->dpp_reset) 2005 2005 + dpp->funcs->dpp_reset(dpp); 2006 2006 + } 2007 2007 + 2008 2008 + void hwss_dpp_root_clock_control(union block_sequence_params *params) 2009 2009 + { 2010 2010 + struct dce_hwseq *hws = params->dpp_root_clock_control_params.hws; 2011 2011 + unsigned int dpp_inst = params->dpp_root_clock_control_params.dpp_inst; 2012 2012 + bool clock_on = params->dpp_root_clock_control_params.clock_on; 2013 2013 + 2014 2014 + if (hws->funcs.dpp_root_clock_control) 2015 2015 + hws->funcs.dpp_root_clock_control(hws, dpp_inst, clock_on); 2016 2016 + } 2017 2017 + 2018 2018 + void hwss_dc_ip_request_cntl(union block_sequence_params *params) 2019 2019 + { 2020 2020 + struct dc *dc = params->dc_ip_request_cntl_params.dc; 2021 2021 + bool enable = params->dc_ip_request_cntl_params.enable; 2022 2022 + struct dce_hwseq *hws = dc->hwseq; 2023 2023 + 2024 2024 + if (hws->funcs.dc_ip_request_cntl) 2025 2025 + hws->funcs.dc_ip_request_cntl(dc, enable); 2026 2026 + } 2027 2027 + 2028 2028 + void hwss_dccg_update_dpp_dto(union block_sequence_params *params) 2029 2029 + { 2030 2030 + struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg; 2031 2031 + int dpp_inst = params->dccg_update_dpp_dto_params.dpp_inst; 2032 2032 + int dppclk_khz = params->dccg_update_dpp_dto_params.dppclk_khz; 2033 2033 + 2034 2034 + if (dccg && dccg->funcs->update_dpp_dto) 2035 2035 + dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz); 2036 2036 + } 2037 2037 + 2038 2038 + void hwss_hubp_vtg_sel(union block_sequence_params *params) 2039 2039 + { 2040 2040 + struct hubp *hubp = params->hubp_vtg_sel_params.hubp; 2041 2041 + uint32_t otg_inst = params->hubp_vtg_sel_params.otg_inst; 2042 2042 + 2043 2043 + if (hubp && hubp->funcs->hubp_vtg_sel) 2044 2044 + hubp->funcs->hubp_vtg_sel(hubp, otg_inst); 2045 2045 + } 2046 2046 + 2047 2047 + void hwss_hubp_setup2(union block_sequence_params *params) 2048 2048 + { 2049 2049 + struct hubp *hubp = params->hubp_setup2_params.hubp; 2050 2050 + struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs; 2051 2051 + union dml2_global_sync_programming *global_sync = params->hubp_setup2_params.global_sync; 2052 2052 + struct dc_crtc_timing *timing = params->hubp_setup2_params.timing; 2053 2053 + 2054 2054 + if (hubp && hubp->funcs->hubp_setup2) 2055 2055 + hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing); 2056 2056 + } 2057 2057 + 2058 2058 + void hwss_hubp_setup(union block_sequence_params *params) 2059 2059 + { 2060 2060 + struct hubp *hubp = params->hubp_setup_params.hubp; 2061 2061 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_params.dlg_regs; 2062 2062 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_params.ttu_regs; 2063 2063 + struct _vcs_dpi_display_rq_regs_st *rq_regs = params->hubp_setup_params.rq_regs; 2064 2064 + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest = params->hubp_setup_params.pipe_dest; 2065 2065 + 2066 2066 + if (hubp && hubp->funcs->hubp_setup) 2067 2067 + hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); 2068 2068 + } 2069 2069 + 2070 2070 + void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params) 2071 2071 + { 2072 2072 + struct hubp *hubp = params->hubp_set_unbounded_requesting_params.hubp; 2073 2073 + bool unbounded_req = params->hubp_set_unbounded_requesting_params.unbounded_req; 2074 2074 + 2075 2075 + if (hubp && hubp->funcs->set_unbounded_requesting) 2076 2076 + hubp->funcs->set_unbounded_requesting(hubp, unbounded_req); 2077 2077 + } 2078 2078 + 2079 2079 + void hwss_hubp_setup_interdependent2(union block_sequence_params *params) 2080 2080 + { 2081 2081 + struct hubp *hubp = params->hubp_setup_interdependent2_params.hubp; 2082 2082 + struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs; 2083 2083 + 2084 2084 + if (hubp && hubp->funcs->hubp_setup_interdependent2) 2085 2085 + hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs); 2086 2086 + } 2087 2087 + 2088 2088 + void hwss_hubp_setup_interdependent(union block_sequence_params *params) 2089 2089 + { 2090 2090 + struct hubp *hubp = params->hubp_setup_interdependent_params.hubp; 2091 2091 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_interdependent_params.dlg_regs; 2092 2092 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_interdependent_params.ttu_regs; 2093 2093 + 2094 2094 + if (hubp && hubp->funcs->hubp_setup_interdependent) 2095 2095 + hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs); 2096 2096 + } 2097 2097 + 2098 2098 + void hwss_dpp_set_cursor_matrix(union block_sequence_params *params) 2099 2099 + { 2100 2100 + struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp; 2101 2101 + enum dc_color_space color_space = params->dpp_set_cursor_matrix_params.color_space; 2102 2102 + struct dc_csc_transform *cursor_csc_color_matrix = params->dpp_set_cursor_matrix_params.cursor_csc_color_matrix; 2103 2103 + 2104 2104 + if (dpp && dpp->funcs->set_cursor_matrix) 2105 2105 + dpp->funcs->set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix); 2106 2106 + } 2107 2107 + 2108 2108 + void hwss_mpc_update_mpcc(union block_sequence_params *params) 2109 2109 + { 2110 2110 + struct dc *dc = params->mpc_update_mpcc_params.dc; 2111 2111 + struct pipe_ctx *pipe_ctx = params->mpc_update_mpcc_params.pipe_ctx; 2112 2112 + struct dce_hwseq *hws = dc->hwseq; 2113 2113 + 2114 2114 + if (hws->funcs.update_mpcc) 2115 2115 + hws->funcs.update_mpcc(dc, pipe_ctx); 2116 2116 + } 2117 2117 + 2118 2118 + void hwss_mpc_update_blending(union block_sequence_params *params) 2119 2119 + { 2120 2120 + struct mpc *mpc = params->mpc_update_blending_params.mpc; 2121 2121 + struct mpcc_blnd_cfg *blnd_cfg = &params->mpc_update_blending_params.blnd_cfg; 2122 2122 + int mpcc_id = params->mpc_update_blending_params.mpcc_id; 2123 2123 + 2124 2124 + if (mpc && mpc->funcs->update_blending) 2125 2125 + mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id); 2126 2126 + } 2127 2127 + 2128 2128 + void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params) 2129 2129 + { 2130 2130 + struct mpc *mpc = params->mpc_assert_idle_mpcc_params.mpc; 2131 2131 + //struct pipe_ctx *pipe_ctx = params->mpc_assert_idle_mpcc_params.pipe_ctx; 2132 2132 + int mpcc_id = params->mpc_assert_idle_mpcc_params.mpcc_id; 2133 2133 + 2134 2134 + if (mpc && mpc->funcs->wait_for_idle) 2135 2135 + mpc->funcs->wait_for_idle(mpc, mpcc_id); 2136 2136 + 2137 2137 + //pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_id] = false; 2138 2138 + } 2139 2139 + 2140 2140 + void hwss_mpc_insert_plane(union block_sequence_params *params) 2141 2141 + { 2142 2142 + struct mpc *mpc = params->mpc_insert_plane_params.mpc; 2143 2143 + struct mpc_tree *tree = params->mpc_insert_plane_params.mpc_tree_params; 2144 2144 + struct mpcc_blnd_cfg *blnd_cfg = &params->mpc_insert_plane_params.blnd_cfg; 2145 2145 + struct mpcc_sm_cfg *sm_cfg = params->mpc_insert_plane_params.sm_cfg; 2146 2146 + struct mpcc *insert_above_mpcc = params->mpc_insert_plane_params.insert_above_mpcc; 2147 2147 + int mpcc_id = params->mpc_insert_plane_params.mpcc_id; 2148 2148 + int dpp_id = params->mpc_insert_plane_params.dpp_id; 2149 2149 + 2150 2150 + if (mpc && mpc->funcs->insert_plane) 2151 2151 + mpc->funcs->insert_plane(mpc, tree, blnd_cfg, sm_cfg, insert_above_mpcc, 2152 2152 + dpp_id, mpcc_id); 2153 2153 + } 2154 2154 + 2155 2155 + void hwss_dpp_set_scaler(union block_sequence_params *params) 2156 2156 + { 2157 2157 + struct dpp *dpp = params->dpp_set_scaler_params.dpp; 2158 2158 + const struct scaler_data *scl_data = params->dpp_set_scaler_params.scl_data; 2159 2159 + 2160 2160 + if (dpp && dpp->funcs->dpp_set_scaler) 2161 2161 + dpp->funcs->dpp_set_scaler(dpp, scl_data); 2162 2162 + } 2163 2163 + 2164 2164 + void hwss_hubp_mem_program_viewport(union block_sequence_params *params) 2165 2165 + { 2166 2166 + struct hubp *hubp = params->hubp_mem_program_viewport_params.hubp; 2167 2167 + const struct rect *viewport = params->hubp_mem_program_viewport_params.viewport; 2168 2168 + const struct rect *viewport_c = params->hubp_mem_program_viewport_params.viewport_c; 2169 2169 + 2170 2170 + if (hubp && hubp->funcs->mem_program_viewport) 2171 2171 + hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c); 2172 2172 + } 2173 2173 + 2174 2174 + void hwss_set_cursor_attribute(union block_sequence_params *params) 2175 2175 + { 2176 2176 + struct dc *dc = params->set_cursor_attribute_params.dc; 2177 2177 + struct pipe_ctx *pipe_ctx = params->set_cursor_attribute_params.pipe_ctx; 2178 2178 + 2179 2179 + if (dc && dc->hwss.set_cursor_attribute) 2180 2180 + dc->hwss.set_cursor_attribute(pipe_ctx); 2181 2181 + } 2182 2182 + 2183 2183 + void hwss_set_cursor_position(union block_sequence_params *params) 2184 2184 + { 2185 2185 + struct dc *dc = params->set_cursor_position_params.dc; 2186 2186 + struct pipe_ctx *pipe_ctx = params->set_cursor_position_params.pipe_ctx; 2187 2187 + 2188 2188 + if (dc && dc->hwss.set_cursor_position) 2189 2189 + dc->hwss.set_cursor_position(pipe_ctx); 2190 2190 + } 2191 2191 + 2192 2192 + void hwss_set_cursor_sdr_white_level(union block_sequence_params *params) 2193 2193 + { 2194 2194 + struct dc *dc = params->set_cursor_sdr_white_level_params.dc; 2195 2195 + struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx; 2196 2196 + 2197 2197 + if (dc && dc->hwss.set_cursor_sdr_white_level) 2198 2198 + dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 2199 2199 + } 2200 2200 + 2201 2201 + void hwss_program_output_csc(union block_sequence_params *params) 2202 2202 + { 2203 2203 + struct dc *dc = params->program_output_csc_params.dc; 2204 2204 + struct pipe_ctx *pipe_ctx = params->program_output_csc_params.pipe_ctx; 2205 2205 + enum dc_color_space colorspace = params->program_output_csc_params.colorspace; 2206 2206 + uint16_t *matrix = params->program_output_csc_params.matrix; 2207 2207 + int opp_id = params->program_output_csc_params.opp_id; 2208 2208 + 2209 2209 + if (dc && dc->hwss.program_output_csc) 2210 2210 + dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id); 2211 2211 + } 2212 2212 + 2213 2213 + void hwss_hubp_set_blank(union block_sequence_params *params) 2214 2214 + { 2215 2215 + struct hubp *hubp = params->hubp_set_blank_params.hubp; 2216 2216 + bool blank = params->hubp_set_blank_params.blank; 2217 2217 + 2218 2218 + if (hubp && hubp->funcs->set_blank) 2219 2219 + hubp->funcs->set_blank(hubp, blank); 2220 2220 + } 2221 2221 + 2222 2222 + void hwss_phantom_hubp_post_enable(union block_sequence_params *params) 2223 2223 + { 2224 2224 + struct hubp *hubp = params->phantom_hubp_post_enable_params.hubp; 2225 2225 + 2226 2226 + if (hubp && hubp->funcs->phantom_hubp_post_enable) 2227 2227 + hubp->funcs->phantom_hubp_post_enable(hubp); 2228 2228 + } 2229 2229 + 2230 2230 + void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, 2231 2231 + struct dccg *dccg, int inst, int num_slices_h) 2232 2232 + { 2233 2233 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2234 2234 + seq_state->steps[*seq_state->num_steps].func = DCCG_SET_DTO_DSCCLK; 2235 2235 + seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg; 2236 2236 + seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.inst = inst; 2237 2237 + seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h; 2238 2238 + (*seq_state->num_steps)++; 2239 2239 + } 2240 2240 + } 2241 2241 + 2242 2242 + void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, 2243 2243 + struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt) 2244 2244 + { 2245 2245 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2246 2246 + seq_state->steps[*seq_state->num_steps].func = DSC_CALCULATE_AND_SET_CONFIG; 2247 2247 + seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx; 2248 2248 + seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.enable = enable; 2249 2249 + seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt; 2250 2250 + (*seq_state->num_steps)++; 2251 2251 + } 2252 2252 + } 2253 2253 + 2254 2254 + void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, 2255 2255 + struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove) 2256 2256 + { 2257 2257 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2258 2258 + seq_state->steps[*seq_state->num_steps].func = MPC_REMOVE_MPCC; 2259 2259 + seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc = mpc; 2260 2260 + seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc_tree_params = mpc_tree_params; 2261 2261 + seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpcc_to_remove = mpcc_to_remove; 2262 2262 + (*seq_state->num_steps)++; 2263 2263 + } 2264 2264 + } 2265 2265 + 2266 2266 + void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, 2267 2267 + struct output_pixel_processor *opp, int mpcc_inst, bool pending) 2268 2268 + { 2269 2269 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2270 2270 + seq_state->steps[*seq_state->num_steps].func = OPP_SET_MPCC_DISCONNECT_PENDING; 2271 2271 + seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.opp = opp; 2272 2272 + seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst; 2273 2273 + seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.pending = pending; 2274 2274 + (*seq_state->num_steps)++; 2275 2275 + } 2276 2276 + } 2277 2277 + 2278 2278 + void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, 2279 2279 + struct hubp *hubp) 2280 2280 + { 2281 2281 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2282 2282 + seq_state->steps[*seq_state->num_steps].func = HUBP_DISCONNECT; 2283 2283 + seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp; 2284 2284 + (*seq_state->num_steps)++; 2285 2285 + } 2286 2286 + } 2287 2287 + 2288 2288 + void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, 2289 2289 + struct pipe_ctx *pipe_ctx) 2290 2290 + { 2291 2291 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2292 2292 + seq_state->steps[*seq_state->num_steps].func = DSC_ENABLE_WITH_OPP; 2293 2293 + seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx; 2294 2294 + (*seq_state->num_steps)++; 2295 2295 + } 2296 2296 + } 2297 2297 + 2298 2298 + void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, 2299 2299 + struct timing_generator *tg, struct dsc_optc_config *dsc_optc_cfg, bool enable) 2300 2300 + { 2301 2301 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2302 2302 + seq_state->steps[*seq_state->num_steps].func = TG_SET_DSC_CONFIG; 2303 2303 + seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.tg = tg; 2304 2304 + seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg; 2305 2305 + seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.enable = enable; 2306 2306 + (*seq_state->num_steps)++; 2307 2307 + } 2308 2308 + } 2309 2309 + 2310 2310 + void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, 2311 2311 + struct display_stream_compressor *dsc) 2312 2312 + { 2313 2313 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2314 2314 + seq_state->steps[*seq_state->num_steps].func = DSC_DISCONNECT; 2315 2315 + seq_state->steps[*seq_state->num_steps].params.dsc_disconnect_params.dsc = dsc; 2316 2316 + (*seq_state->num_steps)++; 2317 2317 + } 2318 2318 + } 2319 2319 + 2320 2320 + void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, 2321 2321 + struct dc *dc, bool optimized_required) 2322 2322 + { 2323 2323 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2324 2324 + seq_state->steps[*seq_state->num_steps].func = DC_SET_OPTIMIZED_REQUIRED; 2325 2325 + seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.dc = dc; 2326 2326 + seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.optimized_required = optimized_required; 2327 2327 + (*seq_state->num_steps)++; 2328 2328 + } 2329 2329 + } 2330 2330 + 2331 2331 + void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, 2332 2332 + struct dc *dc, struct pipe_ctx *pipe_ctx) 2333 2333 + { 2334 2334 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2335 2335 + seq_state->steps[*seq_state->num_steps].func = ABM_SET_IMMEDIATE_DISABLE; 2336 2336 + seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.dc = dc; 2337 2337 + seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx; 2338 2338 + (*seq_state->num_steps)++; 2339 2339 + } 2340 2340 + } 2341 2341 + 2342 2342 + void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, 2343 2343 + struct output_pixel_processor *opp, 2344 2344 + enum controller_dp_test_pattern test_pattern, 2345 2345 + enum controller_dp_color_space color_space, 2346 2346 + enum dc_color_depth color_depth, 2347 2347 + struct tg_color solid_color, 2348 2348 + bool use_solid_color, 2349 2349 + int width, 2350 2350 + int height, 2351 2351 + int offset) 2352 2352 + { 2353 2353 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2354 2354 + seq_state->steps[*seq_state->num_steps].func = OPP_SET_DISP_PATTERN_GENERATOR; 2355 2355 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.opp = opp; 2356 2356 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.test_pattern = test_pattern; 2357 2357 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_space = color_space; 2358 2358 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_depth = color_depth; 2359 2359 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.solid_color = solid_color; 2360 2360 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.use_solid_color = use_solid_color; 2361 2361 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.width = width; 2362 2362 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.height = height; 2363 2363 + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.offset = offset; 2364 2364 + (*seq_state->num_steps)++; 2365 2365 + } 2366 2366 + } 2367 2367 + 2368 2368 + /** 2369 2369 + * Helper function to add MPC update blending to block sequence 2370 2370 + */ 2371 2371 + void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, 2372 2372 + struct mpc *mpc, 2373 2373 + struct mpcc_blnd_cfg blnd_cfg, 2374 2374 + int mpcc_id) 2375 2375 + { 2376 2376 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2377 2377 + seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_BLENDING; 2378 2378 + seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpc = mpc; 2379 2379 + seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.blnd_cfg = blnd_cfg; 2380 2380 + seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpcc_id = mpcc_id; 2381 2381 + (*seq_state->num_steps)++; 2382 2382 + } 2383 2383 + } 2384 2384 + 2385 2385 + /** 2386 2386 + * Helper function to add MPC insert plane to block sequence 2387 2387 + */ 2388 2388 + void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, 2389 2389 + struct mpc *mpc, 2390 2390 + struct mpc_tree *mpc_tree_params, 2391 2391 + struct mpcc_blnd_cfg blnd_cfg, 2392 2392 + struct mpcc_sm_cfg *sm_cfg, 2393 2393 + struct mpcc *insert_above_mpcc, 2394 2394 + int dpp_id, 2395 2395 + int mpcc_id) 2396 2396 + { 2397 2397 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2398 2398 + seq_state->steps[*seq_state->num_steps].func = MPC_INSERT_PLANE; 2399 2399 + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc = mpc; 2400 2400 + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc_tree_params = mpc_tree_params; 2401 2401 + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.blnd_cfg = blnd_cfg; 2402 2402 + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.sm_cfg = sm_cfg; 2403 2403 + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.insert_above_mpcc = insert_above_mpcc; 2404 2404 + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.dpp_id = dpp_id; 2405 2405 + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpcc_id = mpcc_id; 2406 2406 + (*seq_state->num_steps)++; 2407 2407 + } 2408 2408 + } 2409 2409 + 2410 2410 + /** 2411 2411 + * Helper function to add MPC assert idle MPCC to block sequence 2412 2412 + */ 2413 2413 + void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, 2414 2414 + struct mpc *mpc, 2415 2415 + int mpcc_id) 2416 2416 + { 2417 2417 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2418 2418 + seq_state->steps[*seq_state->num_steps].func = MPC_ASSERT_IDLE_MPCC; 2419 2419 + seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc; 2420 2420 + seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpcc_id = mpcc_id; 2421 2421 + (*seq_state->num_steps)++; 2422 2422 + } 2423 2423 + } 2424 2424 + 2425 2425 + /** 2426 2426 + * Helper function to add HUBP set blank to block sequence 2427 2427 + */ 2428 2428 + void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, 2429 2429 + struct hubp *hubp, 2430 2430 + bool blank) 2431 2431 + { 2432 2432 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2433 2433 + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK; 2434 2434 + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp; 2435 2435 + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.blank = blank; 2436 2436 + (*seq_state->num_steps)++; 2437 2437 + } 2438 2438 + } 2439 2439 + 2440 2440 + void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, 2441 2441 + struct output_pixel_processor *opp, 2442 2442 + bool use_default_params, 2443 2443 + struct pipe_ctx *pipe_ctx) 2444 2444 + { 2445 2445 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2446 2446 + seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_BIT_DEPTH_REDUCTION; 2447 2447 + seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.opp = opp; 2448 2448 + seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params; 2449 2449 + seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx; 2450 2450 + (*seq_state->num_steps)++; 2451 2451 + } 2452 2452 + } 2453 2453 + 2454 2454 + void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, 2455 2455 + struct dc *dc, 2456 2456 + bool enable) 2457 2457 + { 2458 2458 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2459 2459 + seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL; 2460 2460 + seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc; 2461 2461 + seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.enable = enable; 2462 2462 + (*seq_state->num_steps)++; 2463 2463 + } 2464 2464 + } 2465 2465 + 2466 2466 + void hwss_add_dwbc_update(struct block_sequence_state *seq_state, 2467 2467 + struct dwbc *dwb, 2468 2468 + struct dc_dwb_params *dwb_params) 2469 2469 + { 2470 2470 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2471 2471 + seq_state->steps[*seq_state->num_steps].func = DWBC_UPDATE; 2472 2472 + seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb = dwb; 2473 2473 + seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb_params = dwb_params; 2474 2474 + (*seq_state->num_steps)++; 2475 2475 + } 2476 2476 + } 2477 2477 + 2478 2478 + void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, 2479 2479 + struct mcif_wb *mcif_wb, 2480 2480 + struct mcif_buf_params *mcif_buf_params, 2481 2481 + unsigned int dest_height) 2482 2482 + { 2483 2483 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2484 2484 + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_BUF; 2485 2485 + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_wb = mcif_wb; 2486 2486 + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_buf_params = mcif_buf_params; 2487 2487 + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.dest_height = dest_height; 2488 2488 + (*seq_state->num_steps)++; 2489 2489 + } 2490 2490 + } 2491 2491 + 2492 2492 + void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, 2493 2493 + struct mcif_wb *mcif_wb, 2494 2494 + struct mcif_arb_params *mcif_arb_params) 2495 2495 + { 2496 2496 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2497 2497 + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_ARB; 2498 2498 + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_wb = mcif_wb; 2499 2499 + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_arb_params = mcif_arb_params; 2500 2500 + (*seq_state->num_steps)++; 2501 2501 + } 2502 2502 + } 2503 2503 + 2504 2504 + void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, 2505 2505 + struct mcif_wb *mcif_wb) 2506 2506 + { 2507 2507 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2508 2508 + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_ENABLE; 2509 2509 + seq_state->steps[*seq_state->num_steps].params.mcif_wb_enable_params.mcif_wb = mcif_wb; 2510 2510 + (*seq_state->num_steps)++; 2511 2511 + } 2512 2512 + } 2513 2513 + 2514 2514 + void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, 2515 2515 + struct mcif_wb *mcif_wb) 2516 2516 + { 2517 2517 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2518 2518 + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_DISABLE; 2519 2519 + seq_state->steps[*seq_state->num_steps].params.mcif_wb_disable_params.mcif_wb = mcif_wb; 2520 2520 + (*seq_state->num_steps)++; 2521 2521 + } 2522 2522 + } 2523 2523 + 2524 2524 + void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, 2525 2525 + struct mpc *mpc, 2526 2526 + int dwb_id, 2527 2527 + int mpcc_id) 2528 2528 + { 2529 2529 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2530 2530 + seq_state->steps[*seq_state->num_steps].func = MPC_SET_DWB_MUX; 2531 2531 + seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpc = mpc; 2532 2532 + seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.dwb_id = dwb_id; 2533 2533 + seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpcc_id = mpcc_id; 2534 2534 + (*seq_state->num_steps)++; 2535 2535 + } 2536 2536 + } 2537 2537 + 2538 2538 + void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, 2539 2539 + struct mpc *mpc, 2540 2540 + unsigned int dwb_id) 2541 2541 + { 2542 2542 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2543 2543 + seq_state->steps[*seq_state->num_steps].func = MPC_DISABLE_DWB_MUX; 2544 2544 + seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc; 2545 2545 + seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.dwb_id = dwb_id; 2546 2546 + (*seq_state->num_steps)++; 2547 2547 + } 2548 2548 + } 2549 2549 + 2550 2550 + void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, 2551 2551 + struct dwbc *dwb, 2552 2552 + struct dc_dwb_params *dwb_params) 2553 2553 + { 2554 2554 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2555 2555 + seq_state->steps[*seq_state->num_steps].func = DWBC_ENABLE; 2556 2556 + seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb = dwb; 2557 2557 + seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb_params = dwb_params; 2558 2558 + (*seq_state->num_steps)++; 2559 2559 + } 2560 2560 + } 2561 2561 + 2562 2562 + void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, 2563 2563 + struct dwbc *dwb) 2564 2564 + { 2565 2565 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2566 2566 + seq_state->steps[*seq_state->num_steps].func = DWBC_DISABLE; 2567 2567 + seq_state->steps[*seq_state->num_steps].params.dwbc_disable_params.dwb = dwb; 2568 2568 + (*seq_state->num_steps)++; 2569 2569 + } 2570 2570 + } 2571 2571 + 2572 2572 + void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, 2573 2573 + struct timing_generator *tg, 2574 2574 + struct gsl_params gsl) 2575 2575 + { 2576 2576 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2577 2577 + seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL; 2578 2578 + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.tg = tg; 2579 2579 + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.gsl = gsl; 2580 2580 + (*seq_state->num_steps)++; 2581 2581 + } 2582 2582 + } 2583 2583 + 2584 2584 + void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, 2585 2585 + struct timing_generator *tg, 2586 2586 + int group_idx, 2587 2587 + uint32_t gsl_ready_signal) 2588 2588 + { 2589 2589 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2590 2590 + seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL_SOURCE_SELECT; 2591 2591 + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.tg = tg; 2592 2592 + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx; 2593 2593 + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.gsl_ready_signal = gsl_ready_signal; 2594 2594 + (*seq_state->num_steps)++; 2595 2595 + } 2596 2596 + } 2597 2597 + 2598 2598 + void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, 2599 2599 + struct hubp *hubp, 2600 2600 + uint32_t mall_sel, 2601 2601 + bool cache_cursor) 2602 2602 + { 2603 2603 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2604 2604 + seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_MALL_SEL; 2605 2605 + seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp; 2606 2606 + seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.mall_sel = mall_sel; 2607 2607 + seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.cache_cursor = cache_cursor; 2608 2608 + (*seq_state->num_steps)++; 2609 2609 + } 2610 2610 + } 2611 2611 + 2612 2612 + void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, 2613 2613 + struct hubp *hubp, 2614 2614 + bool enable) 2615 2615 + { 2616 2616 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2617 2617 + seq_state->steps[*seq_state->num_steps].func = HUBP_PREPARE_SUBVP_BUFFERING; 2618 2618 + seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp; 2619 2619 + seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.enable = enable; 2620 2620 + (*seq_state->num_steps)++; 2621 2621 + } 2622 2622 + } 2623 2623 + 2624 2624 + void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, 2625 2625 + struct hubp *hubp, 2626 2626 + bool enable) 2627 2627 + { 2628 2628 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2629 2629 + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK_EN; 2630 2630 + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp; 2631 2631 + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.enable = enable; 2632 2632 + (*seq_state->num_steps)++; 2633 2633 + } 2634 2634 + } 2635 2635 + 2636 2636 + void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, 2637 2637 + struct hubp *hubp, 2638 2638 + bool disable) 2639 2639 + { 2640 2640 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2641 2641 + seq_state->steps[*seq_state->num_steps].func = HUBP_DISABLE_CONTROL; 2642 2642 + seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp; 2643 2643 + seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.disable = disable; 2644 2644 + (*seq_state->num_steps)++; 2645 2645 + } 2646 2646 + } 2647 2647 + 2648 2648 + void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, 2649 2649 + struct hubbub *hubbub, 2650 2650 + void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), 2651 2651 + bool reset) 2652 2652 + { 2653 2653 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2654 2654 + seq_state->steps[*seq_state->num_steps].func = HUBBUB_SOFT_RESET; 2655 2655 + seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub = hubbub; 2656 2656 + seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub_soft_reset = hubbub_soft_reset; 2657 2657 + seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.reset = reset; 2658 2658 + (*seq_state->num_steps)++; 2659 2659 + } 2660 2660 + } 2661 2661 + 2662 2662 + void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, 2663 2663 + struct hubp *hubp, 2664 2664 + bool enable) 2665 2665 + { 2666 2666 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2667 2667 + seq_state->steps[*seq_state->num_steps].func = HUBP_CLK_CNTL; 2668 2668 + seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp; 2669 2669 + seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.enable = enable; 2670 2670 + (*seq_state->num_steps)++; 2671 2671 + } 2672 2672 + } 2673 2673 + 2674 2674 + void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, 2675 2675 + struct dpp *dpp, 2676 2676 + bool dppclk_div, 2677 2677 + bool enable) 2678 2678 + { 2679 2679 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2680 2680 + seq_state->steps[*seq_state->num_steps].func = DPP_DPPCLK_CONTROL; 2681 2681 + seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp; 2682 2682 + seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dppclk_div = dppclk_div; 2683 2683 + seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.enable = enable; 2684 2684 + (*seq_state->num_steps)++; 2685 2685 + } 2686 2686 + } 2687 2687 + 2688 2688 + void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, 2689 2689 + struct timing_generator *tg) 2690 2690 + { 2691 2691 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2692 2692 + seq_state->steps[*seq_state->num_steps].func = DISABLE_PHANTOM_CRTC; 2693 2693 + seq_state->steps[*seq_state->num_steps].params.disable_phantom_crtc_params.tg = tg; 2694 2694 + (*seq_state->num_steps)++; 2695 2695 + } 2696 2696 + } 2697 2697 + 2698 2698 + void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, 2699 2699 + struct dce_hwseq *hws, 2700 2700 + int dsc_inst, 2701 2701 + bool is_ungated) 2702 2702 + { 2703 2703 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2704 2704 + seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS; 2705 2705 + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws; 2706 2706 + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst; 2707 2707 + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.is_ungated = is_ungated; 2708 2708 + (*seq_state->num_steps)++; 2709 2709 + } 2710 2710 + } 2711 2711 + 2712 2712 + void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, 2713 2713 + struct display_stream_compressor *dsc, 2714 2714 + bool *is_ungated) 2715 2715 + { 2716 2716 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2717 2717 + seq_state->steps[*seq_state->num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR; 2718 2718 + seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc; 2719 2719 + seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated; 2720 2720 + (*seq_state->num_steps)++; 2721 2721 + } 2722 2722 + } 2723 2723 + 2724 2724 + void hwss_add_dsc_disable(struct block_sequence_state *seq_state, 2725 2725 + struct display_stream_compressor *dsc, 2726 2726 + bool *is_ungated) 2727 2727 + { 2728 2728 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2729 2729 + seq_state->steps[*seq_state->num_steps].func = DSC_DISABLE; 2730 2730 + seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc; 2731 2731 + seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.is_ungated = is_ungated; 2732 2732 + (*seq_state->num_steps)++; 2733 2733 + } 2734 2734 + } 2735 2735 + 2736 2736 + void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, 2737 2737 + struct dccg *dccg, 2738 2738 + int dsc_inst, 2739 2739 + bool *is_ungated) 2740 2740 + { 2741 2741 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2742 2742 + seq_state->steps[*seq_state->num_steps].func = DCCG_SET_REF_DSCCLK; 2743 2743 + seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg; 2744 2744 + seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst; 2745 2745 + seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated; 2746 2746 + (*seq_state->num_steps)++; 2747 2747 + } 2748 2748 + } 2749 2749 + 2750 2750 + void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, 2751 2751 + struct dce_hwseq *hws, 2752 2752 + unsigned int dpp_inst, 2753 2753 + bool clock_on) 2754 2754 + { 2755 2755 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2756 2756 + seq_state->steps[*seq_state->num_steps].func = DPP_ROOT_CLOCK_CONTROL; 2757 2757 + seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.hws = hws; 2758 2758 + seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst; 2759 2759 + seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.clock_on = clock_on; 2760 2760 + (*seq_state->num_steps)++; 2761 2761 + } 2762 2762 + } 2763 2763 + 2764 2764 + void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, 2765 2765 + struct dce_hwseq *hws, 2766 2766 + unsigned int dpp_inst, 2767 2767 + bool power_on) 2768 2768 + { 2769 2769 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2770 2770 + seq_state->steps[*seq_state->num_steps].func = DPP_PG_CONTROL; 2771 2771 + seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.hws = hws; 2772 2772 + seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst; 2773 2773 + seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.power_on = power_on; 2774 2774 + (*seq_state->num_steps)++; 2775 2775 + } 2776 2776 + } 2777 2777 + 2778 2778 + void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, 2779 2779 + struct dce_hwseq *hws, 2780 2780 + unsigned int hubp_inst, 2781 2781 + bool power_on) 2782 2782 + { 2783 2783 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2784 2784 + seq_state->steps[*seq_state->num_steps].func = HUBP_PG_CONTROL; 2785 2785 + seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hws = hws; 2786 2786 + seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hubp_inst = hubp_inst; 2787 2787 + seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.power_on = power_on; 2788 2788 + (*seq_state->num_steps)++; 2789 2789 + } 2790 2790 + } 2791 2791 + 2792 2792 + void hwss_add_hubp_init(struct block_sequence_state *seq_state, 2793 2793 + struct hubp *hubp) 2794 2794 + { 2795 2795 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2796 2796 + seq_state->steps[*seq_state->num_steps].func = HUBP_INIT; 2797 2797 + seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp; 2798 2798 + (*seq_state->num_steps)++; 2799 2799 + } 2800 2800 + } 2801 2801 + 2802 2802 + void hwss_add_hubp_reset(struct block_sequence_state *seq_state, 2803 2803 + struct hubp *hubp) 2804 2804 + { 2805 2805 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2806 2806 + seq_state->steps[*seq_state->num_steps].func = HUBP_RESET; 2807 2807 + seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp; 2808 2808 + (*seq_state->num_steps)++; 2809 2809 + } 2810 2810 + } 2811 2811 + 2812 2812 + void hwss_add_dpp_reset(struct block_sequence_state *seq_state, 2813 2813 + struct dpp *dpp) 2814 2814 + { 2815 2815 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2816 2816 + seq_state->steps[*seq_state->num_steps].func = DPP_RESET; 2817 2817 + seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp; 2818 2818 + (*seq_state->num_steps)++; 2819 2819 + } 2820 2820 + } 2821 2821 + 2822 2822 + void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, 2823 2823 + struct output_pixel_processor *opp, 2824 2824 + bool enable) 2825 2825 + { 2826 2826 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2827 2827 + seq_state->steps[*seq_state->num_steps].func = OPP_PIPE_CLOCK_CONTROL; 2828 2828 + seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.opp = opp; 2829 2829 + seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.enable = enable; 2830 2830 + (*seq_state->num_steps)++; 2831 2831 + } 2832 2832 + } 2833 2833 + 2834 2834 + void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, 2835 2835 + struct hubp *hubp, 2836 2836 + uint64_t sys_default, 2837 2837 + uint64_t sys_low, 2838 2838 + uint64_t sys_high) 2839 2839 + { 2840 2840 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2841 2841 + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS; 2842 2842 + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp; 2843 2843 + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default; 2844 2844 + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low; 2845 2845 + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high; 2846 2846 + (*seq_state->num_steps)++; 2847 2847 + } 2848 2848 + } 2849 2849 + 2850 2850 + void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, 2851 2851 + struct hubp *hubp) 2852 2852 + { 2853 2853 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2854 2854 + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_INT; 2855 2855 + seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp; 2856 2856 + (*seq_state->num_steps)++; 2857 2857 + } 2858 2858 + } 2859 2859 + 2860 2860 + void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, 2861 2861 + struct dccg *dccg, 2862 2862 + int dpp_inst, 2863 2863 + int dppclk_khz) 2864 2864 + { 2865 2865 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2866 2866 + seq_state->steps[*seq_state->num_steps].func = DCCG_UPDATE_DPP_DTO; 2867 2867 + seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg; 2868 2868 + seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dpp_inst = dpp_inst; 2869 2869 + seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dppclk_khz = dppclk_khz; 2870 2870 + (*seq_state->num_steps)++; 2871 2871 + } 2872 2872 + } 2873 2873 + 2874 2874 + void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, 2875 2875 + struct hubp *hubp, 2876 2876 + uint32_t otg_inst) 2877 2877 + { 2878 2878 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2879 2879 + seq_state->steps[*seq_state->num_steps].func = HUBP_VTG_SEL; 2880 2880 + seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp; 2881 2881 + seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst; 2882 2882 + (*seq_state->num_steps)++; 2883 2883 + } 2884 2884 + } 2885 2885 + 2886 2886 + void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, 2887 2887 + struct hubp *hubp, 2888 2888 + struct dml2_dchub_per_pipe_register_set *hubp_regs, 2889 2889 + union dml2_global_sync_programming *global_sync, 2890 2890 + struct dc_crtc_timing *timing) 2891 2891 + { 2892 2892 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2893 2893 + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP2; 2894 2894 + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp; 2895 2895 + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs; 2896 2896 + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.global_sync = global_sync; 2897 2897 + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.timing = timing; 2898 2898 + (*seq_state->num_steps)++; 2899 2899 + } 2900 2900 + } 2901 2901 + 2902 2902 + void hwss_add_hubp_setup(struct block_sequence_state *seq_state, 2903 2903 + struct hubp *hubp, 2904 2904 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 2905 2905 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 2906 2906 + struct _vcs_dpi_display_rq_regs_st *rq_regs, 2907 2907 + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 2908 2908 + { 2909 2909 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2910 2910 + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP; 2911 2911 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp; 2912 2912 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs; 2913 2913 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.ttu_regs = ttu_regs; 2914 2914 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs; 2915 2915 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.pipe_dest = pipe_dest; 2916 2916 + (*seq_state->num_steps)++; 2917 2917 + } 2918 2918 + } 2919 2919 + 2920 2920 + void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, 2921 2921 + struct hubp *hubp, 2922 2922 + bool unbounded_req) 2923 2923 + { 2924 2924 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2925 2925 + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_UNBOUNDED_REQUESTING; 2926 2926 + seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp; 2927 2927 + seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.unbounded_req = unbounded_req; 2928 2928 + (*seq_state->num_steps)++; 2929 2929 + } 2930 2930 + } 2931 2931 + 2932 2932 + void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, 2933 2933 + struct hubp *hubp, 2934 2934 + struct dml2_dchub_per_pipe_register_set *hubp_regs) 2935 2935 + { 2936 2936 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2937 2937 + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT2; 2938 2938 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp; 2939 2939 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs; 2940 2940 + (*seq_state->num_steps)++; 2941 2941 + } 2942 2942 + } 2943 2943 + 2944 2944 + void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, 2945 2945 + struct hubp *hubp, 2946 2946 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 2947 2947 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs) 2948 2948 + { 2949 2949 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2950 2950 + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT; 2951 2951 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp; 2952 2952 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs; 2953 2953 + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs; 2954 2954 + (*seq_state->num_steps)++; 2955 2955 + } 2956 2956 + } 2957 2957 + 2958 2958 + void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, 2959 2959 + struct hubp *hubp, 2960 2960 + enum surface_pixel_format format, 2961 2961 + struct dc_tiling_info *tiling_info, 2962 2962 + struct plane_size plane_size, 2963 2963 + enum dc_rotation_angle rotation, 2964 2964 + struct dc_plane_dcc_param *dcc, 2965 2965 + bool horizontal_mirror, 2966 2966 + int compat_level) 2967 2967 + { 2968 2968 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2969 2969 + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_SURFACE_CONFIG; 2970 2970 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp; 2971 2971 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.format = format; 2972 2972 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info; 2973 2973 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.plane_size = plane_size; 2974 2974 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.rotation = rotation; 2975 2975 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.dcc = dcc; 2976 2976 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.horizontal_mirror = horizontal_mirror; 2977 2977 + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.compat_level = compat_level; 2978 2978 + (*seq_state->num_steps)++; 2979 2979 + } 2980 2980 + } 2981 2981 + 2982 2982 + void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, 2983 2983 + struct pipe_ctx *pipe_ctx) 2984 2984 + { 2985 2985 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2986 2986 + seq_state->steps[*seq_state->num_steps].func = DPP_SETUP_DPP; 2987 2987 + seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx; 2988 2988 + (*seq_state->num_steps)++; 2989 2989 + } 2990 2990 + } 2991 2991 + 2992 2992 + void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, 2993 2993 + struct dpp *dpp, 2994 2994 + enum dc_color_space color_space, 2995 2995 + struct dc_csc_transform *cursor_csc_color_matrix) 2996 2996 + { 2997 2997 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2998 2998 + seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_MATRIX; 2999 2999 + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp; 3000 3000 + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.color_space = color_space; 3001 3001 + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = cursor_csc_color_matrix; 3002 3002 + (*seq_state->num_steps)++; 3003 3003 + } 3004 3004 + } 3005 3005 + 3006 3006 + void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, 3007 3007 + struct dpp *dpp, 3008 3008 + const struct scaler_data *scl_data) 3009 3009 + { 3010 3010 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3011 3011 + seq_state->steps[*seq_state->num_steps].func = DPP_SET_SCALER; 3012 3012 + seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp; 3013 3013 + seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.scl_data = scl_data; 3014 3014 + (*seq_state->num_steps)++; 3015 3015 + } 3016 3016 + } 3017 3017 + 3018 3018 + void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, 3019 3019 + struct hubp *hubp, 3020 3020 + const struct rect *viewport, 3021 3021 + const struct rect *viewport_c) 3022 3022 + { 3023 3023 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3024 3024 + seq_state->steps[*seq_state->num_steps].func = HUBP_MEM_PROGRAM_VIEWPORT; 3025 3025 + seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp; 3026 3026 + seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport = viewport; 3027 3027 + seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport_c = viewport_c; 3028 3028 + (*seq_state->num_steps)++; 3029 3029 + } 3030 3030 + } 3031 3031 + 3032 3032 + void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, 3033 3033 + struct dc *dc, 3034 3034 + struct pipe_ctx *pipe_ctx) 3035 3035 + { 3036 3036 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3037 3037 + seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_ATTRIBUTE; 3038 3038 + seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.dc = dc; 3039 3039 + seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx; 3040 3040 + (*seq_state->num_steps)++; 3041 3041 + } 3042 3042 + } 3043 3043 + 3044 3044 + void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, 3045 3045 + struct dc *dc, 3046 3046 + struct pipe_ctx *pipe_ctx) 3047 3047 + { 3048 3048 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3049 3049 + seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_POSITION; 3050 3050 + seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.dc = dc; 3051 3051 + seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx; 3052 3052 + (*seq_state->num_steps)++; 3053 3053 + } 3054 3054 + } 3055 3055 + 3056 3056 + void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, 3057 3057 + struct dc *dc, 3058 3058 + struct pipe_ctx *pipe_ctx) 3059 3059 + { 3060 3060 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3061 3061 + seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; 3062 3062 + seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc; 3063 3063 + seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx; 3064 3064 + (*seq_state->num_steps)++; 3065 3065 + } 3066 3066 + } 3067 3067 + 3068 3068 + void hwss_add_program_output_csc(struct block_sequence_state *seq_state, 3069 3069 + struct dc *dc, 3070 3070 + struct pipe_ctx *pipe_ctx, 3071 3071 + enum dc_color_space colorspace, 3072 3072 + uint16_t *matrix, 3073 3073 + int opp_id) 3074 3074 + { 3075 3075 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3076 3076 + seq_state->steps[*seq_state->num_steps].func = PROGRAM_OUTPUT_CSC; 3077 3077 + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.dc = dc; 3078 3078 + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx; 3079 3079 + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.colorspace = colorspace; 3080 3080 + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.matrix = matrix; 3081 3081 + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.opp_id = opp_id; 3082 3082 + (*seq_state->num_steps)++; 3083 3083 + } 3084 3084 + } 3085 3085 + 3086 3086 + void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, 3087 3087 + struct hubp *hubp) 3088 3088 + { 3089 3089 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3090 3090 + seq_state->steps[*seq_state->num_steps].func = PHANTOM_HUBP_POST_ENABLE; 3091 3091 + seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp; 3092 3092 + (*seq_state->num_steps)++; 3093 3093 + } 3094 3094 + } 3095 3095 + 3096 3096 + void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, 3097 3097 + struct dc *dc, 3098 3098 + struct dc_state *context) 3099 3099 + { 3100 3100 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3101 3101 + seq_state->steps[*seq_state->num_steps].func = UPDATE_FORCE_PSTATE; 3102 3102 + seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.dc = dc; 3103 3103 + seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.context = context; 3104 3104 + (*seq_state->num_steps)++; 3105 3105 + } 3106 3106 + } 3107 3107 + 3108 3108 + void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, 3109 3109 + struct hubbub *hubbub) 3110 3110 + { 3111 3111 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3112 3112 + seq_state->steps[*seq_state->num_steps].func = HUBBUB_APPLY_DEDCN21_147_WA; 3113 3113 + seq_state->steps[*seq_state->num_steps].params.hubbub_apply_dedcn21_147_wa_params.hubbub = hubbub; 3114 3114 + (*seq_state->num_steps)++; 3115 3115 + } 3116 3116 + } 3117 3117 + 3118 3118 + void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, 3119 3119 + struct hubbub *hubbub, 3120 3120 + bool allow, 3121 3121 + bool *disallow_self_refresh_applied) 3122 3122 + { 3123 3123 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3124 3124 + seq_state->steps[*seq_state->num_steps].func = HUBBUB_ALLOW_SELF_REFRESH_CONTROL; 3125 3125 + seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.hubbub = hubbub; 3126 3126 + seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.allow = allow; 3127 3127 + seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = disallow_self_refresh_applied; 3128 3128 + (*seq_state->num_steps)++; 3129 3129 + } 3130 3130 + } 3131 3131 + 3132 3132 + void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, 3133 3133 + struct timing_generator *tg, 3134 3134 + unsigned int *frame_count) 3135 3135 + { 3136 3136 + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3137 3137 + seq_state->steps[*seq_state->num_steps].func = TG_GET_FRAME_COUNT; 3138 3138 + seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.tg = tg; 3139 3139 + seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.frame_count = frame_count; 3140 3140 + (*seq_state->num_steps)++; 3141 3141 + } 2199 3142 }

+1

drivers/gpu/drm/amd/display/dc/dc.h

reviewed

··· 1165 1165 unsigned int auxless_alpm_lfps_t1t2_us; 1166 1166 short auxless_alpm_lfps_t1t2_offset_us; 1167 1167 bool disable_stutter_for_wm_program; 1168 1168 + bool enable_block_sequence_programming; 1168 1169 }; 1169 1170 1170 1171

+1345 -7

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

reviewed

··· 26 26 #include "clk_mgr.h" 27 27 #include "dsc.h" 28 28 #include "link_service.h" 29 29 + #include "custom_float.h" 29 30 30 31 #include "dce/dmub_hw_lock_mgr.h" 31 32 #include "dcn10/dcn10_cm_common.h" 33 33 + #include "dcn10/dcn10_hubbub.h" 32 34 #include "dcn20/dcn20_optc.h" 33 35 #include "dcn30/dcn30_cm_common.h" 34 36 #include "dcn32/dcn32_hwseq.h" ··· 38 36 #include "dcn401/dcn401_resource.h" 39 37 #include "dc_state_priv.h" 40 38 #include "link_enc_cfg.h" 39 39 + #include "../hw_sequencer.h" 41 40 42 41 #define DC_LOGGER_INIT(logger) 43 42 ··· 1604 1601 dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true); 1605 1602 } 1606 1603 1604 1604 + static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_state *context, 1605 1605 + struct pipe_ctx *otg_master, struct block_sequence_state *seq_state) 1606 1606 + { 1607 1607 + struct pipe_ctx *old_pipe; 1608 1608 + struct pipe_ctx *new_pipe; 1609 1609 + struct pipe_ctx *old_opp_heads[MAX_PIPES]; 1610 1610 + struct pipe_ctx *old_otg_master; 1611 1611 + int old_opp_head_count = 0; 1612 1612 + int i; 1613 1613 + 1614 1614 + old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; 1615 1615 + 1616 1616 + if (resource_is_pipe_type(old_otg_master, OTG_MASTER)) { 1617 1617 + old_opp_head_count = resource_get_opp_heads_for_otg_master(old_otg_master, 1618 1618 + &dc->current_state->res_ctx, 1619 1619 + old_opp_heads); 1620 1620 + } else { 1621 1621 + old_otg_master = NULL; 1622 1622 + } 1623 1623 + 1624 1624 + /* Process new DSC configuration if DSC is enabled */ 1625 1625 + if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) { 1626 1626 + struct dc_stream_state *stream = otg_master->stream; 1627 1627 + struct pipe_ctx *odm_pipe; 1628 1628 + int opp_cnt = 1; 1629 1629 + int last_dsc_calc = 0; 1630 1630 + bool should_use_dto_dscclk = (dc->res_pool->dccg->funcs->set_dto_dscclk != NULL) && 1631 1631 + stream->timing.pix_clk_100hz > 480000; 1632 1632 + 1633 1633 + /* Count ODM pipes */ 1634 1634 + for (odm_pipe = otg_master->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1635 1635 + opp_cnt++; 1636 1636 + 1637 1637 + int num_slices_h = stream->timing.dsc_cfg.num_slices_h / opp_cnt; 1638 1638 + 1639 1639 + /* Step 1: Set DTO DSCCLK for main DSC if needed */ 1640 1640 + if (should_use_dto_dscclk) { 1641 1641 + hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg, 1642 1642 + otg_master->stream_res.dsc->inst, num_slices_h); 1643 1643 + } 1644 1644 + 1645 1645 + /* Step 2: Calculate and set DSC config for main DSC */ 1646 1646 + last_dsc_calc = *seq_state->num_steps; 1647 1647 + hwss_add_dsc_calculate_and_set_config(seq_state, otg_master, true, opp_cnt); 1648 1648 + 1649 1649 + /* Step 3: Enable main DSC block */ 1650 1650 + hwss_add_dsc_enable_with_opp(seq_state, otg_master); 1651 1651 + 1652 1652 + /* Step 4: Configure and enable ODM DSC blocks */ 1653 1653 + for (odm_pipe = otg_master->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1654 1654 + if (!odm_pipe->stream_res.dsc) 1655 1655 + continue; 1656 1656 + 1657 1657 + /* Set DTO DSCCLK for ODM DSC if needed */ 1658 1658 + if (should_use_dto_dscclk) { 1659 1659 + hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg, 1660 1660 + odm_pipe->stream_res.dsc->inst, num_slices_h); 1661 1661 + } 1662 1662 + 1663 1663 + /* Calculate and set DSC config for ODM DSC */ 1664 1664 + last_dsc_calc = *seq_state->num_steps; 1665 1665 + hwss_add_dsc_calculate_and_set_config(seq_state, odm_pipe, true, opp_cnt); 1666 1666 + 1667 1667 + /* Enable ODM DSC block */ 1668 1668 + hwss_add_dsc_enable_with_opp(seq_state, odm_pipe); 1669 1669 + } 1670 1670 + 1671 1671 + /* Step 5: Configure DSC in timing generator */ 1672 1672 + hwss_add_tg_set_dsc_config(seq_state, otg_master->stream_res.tg, 1673 1673 + &seq_state->steps[last_dsc_calc].params.dsc_calculate_and_set_config_params.dsc_optc_cfg, true); 1674 1674 + } else if (otg_master->stream_res.dsc && !otg_master->stream->timing.flags.DSC) { 1675 1675 + /* Disable DSC in OPTC */ 1676 1676 + hwss_add_tg_set_dsc_config(seq_state, otg_master->stream_res.tg, NULL, false); 1677 1677 + 1678 1678 + hwss_add_dsc_disconnect(seq_state, otg_master->stream_res.dsc); 1679 1679 + } 1680 1680 + 1681 1681 + /* Disable DSC for old pipes that no longer need it */ 1682 1682 + if (old_otg_master && old_otg_master->stream_res.dsc) { 1683 1683 + for (i = 0; i < old_opp_head_count; i++) { 1684 1684 + old_pipe = old_opp_heads[i]; 1685 1685 + new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx]; 1686 1686 + 1687 1687 + /* If old pipe had DSC but new pipe doesn't, disable the old DSC */ 1688 1688 + if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc) { 1689 1689 + /* Then disconnect DSC block */ 1690 1690 + hwss_add_dsc_disconnect(seq_state, old_pipe->stream_res.dsc); 1691 1691 + } 1692 1692 + } 1693 1693 + } 1694 1694 + } 1695 1695 + 1696 1696 + void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context, 1697 1697 + struct pipe_ctx *otg_master, struct block_sequence_state *seq_state) 1698 1698 + { 1699 1699 + struct pipe_ctx *opp_heads[MAX_PIPES]; 1700 1700 + int opp_inst[MAX_PIPES] = {0}; 1701 1701 + int opp_head_count; 1702 1702 + int odm_slice_width = resource_get_odm_slice_dst_width(otg_master, false); 1703 1703 + int last_odm_slice_width = resource_get_odm_slice_dst_width(otg_master, true); 1704 1704 + int i; 1705 1705 + 1706 1706 + opp_head_count = resource_get_opp_heads_for_otg_master( 1707 1707 + otg_master, &context->res_ctx, opp_heads); 1708 1708 + 1709 1709 + for (i = 0; i < opp_head_count; i++) 1710 1710 + opp_inst[i] = opp_heads[i]->stream_res.opp->inst; 1711 1711 + 1712 1712 + /* Add ODM combine/bypass operation to sequence */ 1713 1713 + if (opp_head_count > 1) { 1714 1714 + hwss_add_optc_set_odm_combine(seq_state, otg_master->stream_res.tg, opp_inst, 1715 1715 + opp_head_count, odm_slice_width, last_odm_slice_width); 1716 1716 + } else { 1717 1717 + hwss_add_optc_set_odm_bypass(seq_state, otg_master->stream_res.tg, &otg_master->stream->timing); 1718 1718 + } 1719 1719 + 1720 1720 + /* Add OPP operations to sequence */ 1721 1721 + for (i = 0; i < opp_head_count; i++) { 1722 1722 + /* Add OPP pipe clock control operation */ 1723 1723 + hwss_add_opp_pipe_clock_control(seq_state, opp_heads[i]->stream_res.opp, true); 1724 1724 + 1725 1725 + /* Add OPP program left edge extra pixel operation */ 1726 1726 + hwss_add_opp_program_left_edge_extra_pixel(seq_state, opp_heads[i]->stream_res.opp, 1727 1727 + opp_heads[i]->stream->timing.pixel_encoding, resource_is_pipe_type(opp_heads[i], OTG_MASTER)); 1728 1728 + } 1729 1729 + 1730 1730 + /* Add DSC update operations to sequence */ 1731 1731 + dcn401_add_dsc_sequence_for_odm_change(dc, context, otg_master, seq_state); 1732 1732 + 1733 1733 + /* Add blank pixel data operation if needed */ 1734 1734 + if (!resource_is_pipe_type(otg_master, DPP_PIPE)) { 1735 1735 + if (dc->hwseq->funcs.blank_pixel_data_sequence) 1736 1736 + dc->hwseq->funcs.blank_pixel_data_sequence( 1737 1737 + dc, otg_master, true, seq_state); 1738 1738 + } 1739 1739 + } 1740 1740 + 1607 1741 void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, 1608 1742 struct dc_link_settings *link_settings) 1609 1743 { ··· 2229 2089 } 2230 2090 } 2231 2091 2092 2092 + /* 2093 2093 + * dcn401_program_pipe_sequence - Sequence-based version of dcn401_program_pipe 2094 2094 + * 2095 2095 + * This function creates a sequence-based version of the original dcn401_program_pipe 2096 2096 + * function. Instead of directly calling hardware programming functions, it appends 2097 2097 + * sequence steps to the provided block_sequence array that can later be executed 2098 2098 + * as part of hwss_execute_sequence. 2099 2099 + * 2100 2100 + */ 2101 2101 + void dcn401_program_pipe_sequence( 2102 2102 + struct dc *dc, 2103 2103 + struct pipe_ctx *pipe_ctx, 2104 2104 + struct dc_state *context, 2105 2105 + struct block_sequence_state *seq_state) 2106 2106 + { 2107 2107 + struct dce_hwseq *hws = dc->hwseq; 2108 2108 + 2109 2109 + /* Only need to unblank on top pipe */ 2110 2110 + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) { 2111 2111 + if (pipe_ctx->update_flags.bits.enable || 2112 2112 + pipe_ctx->update_flags.bits.odm || 2113 2113 + pipe_ctx->stream->update_flags.bits.abm_level) { 2114 2114 + if (dc->hwseq->funcs.blank_pixel_data_sequence) 2115 2115 + dc->hwseq->funcs.blank_pixel_data_sequence(dc, pipe_ctx, 2116 2116 + !pipe_ctx->plane_state || !pipe_ctx->plane_state->visible, 2117 2117 + seq_state); 2118 2118 + } 2119 2119 + } 2120 2120 + 2121 2121 + /* Only update TG on top pipe */ 2122 2122 + if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 2123 2123 + && !pipe_ctx->prev_odm_pipe) { 2124 2124 + 2125 2125 + /* Step 1: Program global sync */ 2126 2126 + hwss_add_tg_program_global_sync(seq_state, pipe_ctx->stream_res.tg, 2127 2127 + dcn401_calculate_vready_offset_for_group(pipe_ctx), 2128 2128 + (unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines, 2129 2129 + (unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels, 2130 2130 + (unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels, 2131 2131 + (unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines); 2132 2132 + 2133 2133 + /* Step 2: Wait for VACTIVE state (if not phantom pipe) */ 2134 2134 + if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) { 2135 2135 + hwss_add_tg_wait_for_state(seq_state, pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 2136 2136 + } 2137 2137 + 2138 2138 + /* Step 3: Set VTG params */ 2139 2139 + hwss_add_tg_set_vtg_params(seq_state, pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 2140 2140 + 2141 2141 + /* Step 4: Setup vupdate interrupt (if available) */ 2142 2142 + if (hws->funcs.setup_vupdate_interrupt) { 2143 2143 + dcn401_setup_vupdate_interrupt_sequence(dc, pipe_ctx, seq_state); 2144 2144 + } 2145 2145 + } 2146 2146 + 2147 2147 + if (pipe_ctx->update_flags.bits.odm) { 2148 2148 + if (hws->funcs.update_odm_sequence) 2149 2149 + hws->funcs.update_odm_sequence(dc, context, pipe_ctx, seq_state); 2150 2150 + } 2151 2151 + 2152 2152 + if (pipe_ctx->update_flags.bits.enable) { 2153 2153 + if (dc->hwss.enable_plane_sequence) 2154 2154 + dc->hwss.enable_plane_sequence(dc, pipe_ctx, context, seq_state); 2155 2155 + } 2156 2156 + 2157 2157 + if (pipe_ctx->update_flags.bits.det_size) { 2158 2158 + if (dc->res_pool->hubbub->funcs->program_det_size) { 2159 2159 + hwss_add_hubp_program_det_size(seq_state, dc->res_pool->hubbub, 2160 2160 + pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 2161 2161 + } 2162 2162 + 2163 2163 + if (dc->res_pool->hubbub->funcs->program_det_segments) { 2164 2164 + hwss_add_hubp_program_det_segments(seq_state, dc->res_pool->hubbub, 2165 2165 + pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size); 2166 2166 + } 2167 2167 + } 2168 2168 + 2169 2169 + if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw || 2170 2170 + pipe_ctx->plane_state->update_flags.raw || 2171 2171 + pipe_ctx->stream->update_flags.raw)) { 2172 2172 + 2173 2173 + if (dc->hwss.update_dchubp_dpp_sequence) 2174 2174 + dc->hwss.update_dchubp_dpp_sequence(dc, pipe_ctx, context, seq_state); 2175 2175 + } 2176 2176 + 2177 2177 + if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable || 2178 2178 + pipe_ctx->plane_state->update_flags.bits.hdr_mult)) { 2179 2179 + 2180 2180 + hws->funcs.set_hdr_multiplier_sequence(pipe_ctx, seq_state); 2181 2181 + } 2182 2182 + 2183 2183 + if (pipe_ctx->plane_state && 2184 2184 + (pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2185 2185 + pipe_ctx->plane_state->update_flags.bits.gamma_change || 2186 2186 + pipe_ctx->plane_state->update_flags.bits.lut_3d || 2187 2187 + pipe_ctx->update_flags.bits.enable)) { 2188 2188 + 2189 2189 + hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->plane_state); 2190 2190 + } 2191 2191 + 2192 2192 + /* dcn10_translate_regamma_to_hw_format takes 750us to finish 2193 2193 + * only do gamma programming for powering on, internal memcmp to avoid 2194 2194 + * updating on slave planes 2195 2195 + */ 2196 2196 + if (pipe_ctx->update_flags.bits.enable || 2197 2197 + pipe_ctx->update_flags.bits.plane_changed || 2198 2198 + pipe_ctx->stream->update_flags.bits.out_tf) { 2199 2199 + hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->stream); 2200 2200 + } 2201 2201 + 2202 2202 + /* If the pipe has been enabled or has a different opp, we 2203 2203 + * should reprogram the fmt. This deals with cases where 2204 2204 + * interation between mpc and odm combine on different streams 2205 2205 + * causes a different pipe to be chosen to odm combine with. 2206 2206 + */ 2207 2207 + if (pipe_ctx->update_flags.bits.enable 2208 2208 + || pipe_ctx->update_flags.bits.opp_changed) { 2209 2209 + 2210 2210 + hwss_add_opp_set_dyn_expansion(seq_state, pipe_ctx->stream_res.opp, COLOR_SPACE_YCBCR601, pipe_ctx->stream->timing.display_color_depth, pipe_ctx->stream->signal); 2211 2211 + 2212 2212 + hwss_add_opp_program_fmt(seq_state, pipe_ctx->stream_res.opp, &pipe_ctx->stream->bit_depth_params, &pipe_ctx->stream->clamping); 2213 2213 + } 2214 2214 + 2215 2215 + /* Set ABM pipe after other pipe configurations done */ 2216 2216 + if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) { 2217 2217 + if (pipe_ctx->stream_res.abm) { 2218 2218 + hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx); 2219 2219 + 2220 2220 + hwss_add_abm_set_level(seq_state, pipe_ctx->stream_res.abm, pipe_ctx->stream->abm_level); 2221 2221 + } 2222 2222 + } 2223 2223 + 2224 2224 + if (pipe_ctx->update_flags.bits.test_pattern_changed) { 2225 2225 + struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp; 2226 2226 + 2227 2227 + hwss_add_opp_program_bit_depth_reduction(seq_state, odm_opp, true, pipe_ctx); 2228 2228 + 2229 2229 + hwss_add_opp_set_disp_pattern_generator(seq_state, odm_opp, pipe_ctx->stream_res.test_pattern_params.test_pattern, pipe_ctx->stream_res.test_pattern_params.color_space, pipe_ctx->stream_res.test_pattern_params.color_depth, (struct tg_color){0}, false, pipe_ctx->stream_res.test_pattern_params.width, pipe_ctx->stream_res.test_pattern_params.height, pipe_ctx->stream_res.test_pattern_params.offset); 2230 2230 + } 2231 2231 + 2232 2232 + } 2233 2233 + 2232 2234 void dcn401_program_front_end_for_ctx( 2233 2235 struct dc *dc, 2234 2236 struct dc_state *context) ··· 2447 2165 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 2448 2166 && context->res_ctx.pipe_ctx[i].stream) 2449 2167 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 2450 2450 - 2451 2168 2452 2169 /* Disconnect mpcc */ 2453 2170 for (i = 0; i < dc->res_pool->pipe_count; i++) ··· 2526 2245 2527 2246 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 2528 2247 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 2529 2529 - !pipe->top_pipe && 2530 2530 - pipe->stream && 2531 2531 - pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 2532 2532 - dc->current_state->stream_status[0].plane_count == 1 && 2533 2533 - context->stream_status[0].plane_count > 1) { 2248 2248 + !pipe->top_pipe && 2249 2249 + pipe->stream && 2250 2250 + pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 2251 2251 + dc->current_state->stream_status[0].plane_count == 1 && 2252 2252 + context->stream_status[0].plane_count > 1) { 2534 2253 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 2535 2254 } 2536 2255 } ··· 2642 2361 */ 2643 2362 if (hwseq->funcs.update_force_pstate) 2644 2363 dc->hwseq->funcs.update_force_pstate(dc, context); 2645 2645 - 2646 2364 /* Only program the MALL registers after all the main and phantom pipes 2647 2365 * are done programming. 2648 2366 */ ··· 3010 2730 p->HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp->use_mall_for_cursor; 3011 2731 3012 2732 cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx); 2733 2733 + } 2734 2734 + 2735 2735 + void dcn401_plane_atomic_power_down_sequence(struct dc *dc, 2736 2736 + struct dpp *dpp, 2737 2737 + struct hubp *hubp, 2738 2738 + struct block_sequence_state *seq_state) 2739 2739 + { 2740 2740 + struct dce_hwseq *hws = dc->hwseq; 2741 2741 + uint32_t org_ip_request_cntl = 0; 2742 2742 + 2743 2743 + DC_LOGGER_INIT(dc->ctx->logger); 2744 2744 + 2745 2745 + /* Check and set DC_IP_REQUEST_CNTL if needed */ 2746 2746 + if (REG(DC_IP_REQUEST_CNTL)) { 2747 2747 + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 2748 2748 + if (org_ip_request_cntl == 0) { 2749 2749 + hwss_add_dc_ip_request_cntl(seq_state, dc, true); 2750 2750 + } 2751 2751 + } 2752 2752 + 2753 2753 + /* DPP power gating control */ 2754 2754 + hwss_add_dpp_pg_control(seq_state, hws, dpp->inst, false); 2755 2755 + 2756 2756 + /* HUBP power gating control */ 2757 2757 + hwss_add_hubp_pg_control(seq_state, hws, hubp->inst, false); 2758 2758 + 2759 2759 + /* HUBP reset */ 2760 2760 + hwss_add_hubp_reset(seq_state, hubp); 2761 2761 + 2762 2762 + /* DPP reset */ 2763 2763 + hwss_add_dpp_reset(seq_state, dpp); 2764 2764 + 2765 2765 + /* Restore DC_IP_REQUEST_CNTL if it was originally 0 */ 2766 2766 + if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL)) { 2767 2767 + hwss_add_dc_ip_request_cntl(seq_state, dc, false); 2768 2768 + } 2769 2769 + 2770 2770 + DC_LOG_DEBUG("Power gated front end %d\n", hubp->inst); 2771 2771 + 2772 2772 + /* DPP root clock control */ 2773 2773 + hwss_add_dpp_root_clock_control(seq_state, hws, dpp->inst, false); 2774 2774 + } 2775 2775 + 2776 2776 + /* trigger HW to start disconnect plane from stream on the next vsync using block sequence */ 2777 2777 + void dcn401_plane_atomic_disconnect_sequence(struct dc *dc, 2778 2778 + struct dc_state *state, 2779 2779 + struct pipe_ctx *pipe_ctx, 2780 2780 + struct block_sequence_state *seq_state) 2781 2781 + { 2782 2782 + struct hubp *hubp = pipe_ctx->plane_res.hubp; 2783 2783 + int dpp_id = pipe_ctx->plane_res.dpp->inst; 2784 2784 + struct mpc *mpc = dc->res_pool->mpc; 2785 2785 + struct mpc_tree *mpc_tree_params; 2786 2786 + struct mpcc *mpcc_to_remove = NULL; 2787 2787 + struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; 2788 2788 + 2789 2789 + mpc_tree_params = &(opp->mpc_tree_params); 2790 2790 + mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id); 2791 2791 + 2792 2792 + /*Already reset*/ 2793 2793 + if (mpcc_to_remove == NULL) 2794 2794 + return; 2795 2795 + 2796 2796 + /* Step 1: Remove MPCC from MPC tree */ 2797 2797 + hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, mpcc_to_remove); 2798 2798 + 2799 2799 + // Phantom pipes have OTG disabled by default, so MPCC_STATUS will never assert idle, 2800 2800 + // so don't wait for MPCC_IDLE in the programming sequence 2801 2801 + if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM) { 2802 2802 + /* Step 2: Set MPCC disconnect pending flag */ 2803 2803 + hwss_add_opp_set_mpcc_disconnect_pending(seq_state, opp, pipe_ctx->plane_res.mpcc_inst, true); 2804 2804 + } 2805 2805 + 2806 2806 + /* Step 3: Set optimized required flag */ 2807 2807 + hwss_add_dc_set_optimized_required(seq_state, dc, true); 2808 2808 + 2809 2809 + /* Step 4: Disconnect HUBP if function exists */ 2810 2810 + if (hubp->funcs->hubp_disconnect) { 2811 2811 + hwss_add_hubp_disconnect(seq_state, hubp); 2812 2812 + } 2813 2813 + 2814 2814 + /* Step 5: Verify pstate change high if debug sanity checks are enabled */ 2815 2815 + if (dc->debug.sanity_checks) { 2816 2816 + dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); 2817 2817 + } 2818 2818 + } 2819 2819 + 2820 2820 + void dcn401_blank_pixel_data_sequence( 2821 2821 + struct dc *dc, 2822 2822 + struct pipe_ctx *pipe_ctx, 2823 2823 + bool blank, 2824 2824 + struct block_sequence_state *seq_state) 2825 2825 + { 2826 2826 + struct tg_color black_color = {0}; 2827 2827 + struct stream_resource *stream_res = &pipe_ctx->stream_res; 2828 2828 + struct dc_stream_state *stream = pipe_ctx->stream; 2829 2829 + enum dc_color_space color_space = stream->output_color_space; 2830 2830 + enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 2831 2831 + enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 2832 2832 + struct pipe_ctx *odm_pipe; 2833 2833 + struct rect odm_slice_src; 2834 2834 + 2835 2835 + if (stream->link->test_pattern_enabled) 2836 2836 + return; 2837 2837 + 2838 2838 + /* get opp dpg blank color */ 2839 2839 + color_space_to_black_color(dc, color_space, &black_color); 2840 2840 + 2841 2841 + if (blank) { 2842 2842 + /* Set ABM immediate disable */ 2843 2843 + hwss_add_abm_set_immediate_disable(seq_state, dc, pipe_ctx); 2844 2844 + 2845 2845 + if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 2846 2846 + test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 2847 2847 + test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 2848 2848 + } 2849 2849 + } else { 2850 2850 + test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 2851 2851 + } 2852 2852 + 2853 2853 + odm_pipe = pipe_ctx; 2854 2854 + 2855 2855 + /* Set display pattern generator for all ODM pipes */ 2856 2856 + while (odm_pipe->next_odm_pipe) { 2857 2857 + odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe); 2858 2858 + 2859 2859 + hwss_add_opp_set_disp_pattern_generator(seq_state, 2860 2860 + odm_pipe->stream_res.opp, 2861 2861 + test_pattern, 2862 2862 + test_pattern_color_space, 2863 2863 + stream->timing.display_color_depth, 2864 2864 + black_color, 2865 2865 + true, 2866 2866 + odm_slice_src.width, 2867 2867 + odm_slice_src.height, 2868 2868 + odm_slice_src.x); 2869 2869 + 2870 2870 + odm_pipe = odm_pipe->next_odm_pipe; 2871 2871 + } 2872 2872 + 2873 2873 + /* Set display pattern generator for final ODM pipe */ 2874 2874 + odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe); 2875 2875 + 2876 2876 + hwss_add_opp_set_disp_pattern_generator(seq_state, 2877 2877 + odm_pipe->stream_res.opp, 2878 2878 + test_pattern, 2879 2879 + test_pattern_color_space, 2880 2880 + stream->timing.display_color_depth, 2881 2881 + black_color, 2882 2882 + true, 2883 2883 + odm_slice_src.width, 2884 2884 + odm_slice_src.height, 2885 2885 + odm_slice_src.x); 2886 2886 + 2887 2887 + /* Handle ABM level setting when not blanking */ 2888 2888 + if (!blank) { 2889 2889 + if (stream_res->abm) { 2890 2890 + /* Set pipe for ABM */ 2891 2891 + hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx); 2892 2892 + 2893 2893 + /* Set ABM level */ 2894 2894 + hwss_add_abm_set_level(seq_state, stream_res->abm, stream->abm_level); 2895 2895 + } 2896 2896 + } 2897 2897 + } 2898 2898 + 2899 2899 + void dcn401_program_all_writeback_pipes_in_tree_sequence( 2900 2900 + struct dc *dc, 2901 2901 + const struct dc_stream_state *stream, 2902 2902 + struct dc_state *context, 2903 2903 + struct block_sequence_state *seq_state) 2904 2904 + { 2905 2905 + struct dwbc *dwb; 2906 2906 + int i_wb, i_pipe; 2907 2907 + 2908 2908 + if (!stream || stream->num_wb_info > dc->res_pool->res_cap->num_dwb) 2909 2909 + return; 2910 2910 + 2911 2911 + /* For each writeback pipe */ 2912 2912 + for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { 2913 2913 + /* Get direct pointer to writeback info */ 2914 2914 + struct dc_writeback_info *wb_info = (struct dc_writeback_info *)&stream->writeback_info[i_wb]; 2915 2915 + int mpcc_inst = -1; 2916 2916 + 2917 2917 + if (wb_info->wb_enabled) { 2918 2918 + /* Get the MPCC instance for writeback_source_plane */ 2919 2919 + for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { 2920 2920 + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; 2921 2921 + 2922 2922 + if (!pipe_ctx->plane_state) 2923 2923 + continue; 2924 2924 + 2925 2925 + if (pipe_ctx->plane_state == wb_info->writeback_source_plane) { 2926 2926 + mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 2927 2927 + break; 2928 2928 + } 2929 2929 + } 2930 2930 + 2931 2931 + if (mpcc_inst == -1) { 2932 2932 + /* Disable writeback pipe and disconnect from MPCC 2933 2933 + * if source plane has been removed 2934 2934 + */ 2935 2935 + dcn401_disable_writeback_sequence(dc, wb_info, seq_state); 2936 2936 + continue; 2937 2937 + } 2938 2938 + 2939 2939 + ASSERT(wb_info->dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); 2940 2940 + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2941 2941 + 2942 2942 + if (dwb->funcs->is_enabled(dwb)) { 2943 2943 + /* Writeback pipe already enabled, only need to update */ 2944 2944 + dcn401_update_writeback_sequence(dc, wb_info, context, seq_state); 2945 2945 + } else { 2946 2946 + /* Enable writeback pipe and connect to MPCC */ 2947 2947 + dcn401_enable_writeback_sequence(dc, wb_info, context, mpcc_inst, seq_state); 2948 2948 + } 2949 2949 + } else { 2950 2950 + /* Disable writeback pipe and disconnect from MPCC */ 2951 2951 + dcn401_disable_writeback_sequence(dc, wb_info, seq_state); 2952 2952 + } 2953 2953 + } 2954 2954 + } 2955 2955 + 2956 2956 + void dcn401_enable_writeback_sequence( 2957 2957 + struct dc *dc, 2958 2958 + struct dc_writeback_info *wb_info, 2959 2959 + struct dc_state *context, 2960 2960 + int mpcc_inst, 2961 2961 + struct block_sequence_state *seq_state) 2962 2962 + { 2963 2963 + struct dwbc *dwb; 2964 2964 + struct mcif_wb *mcif_wb; 2965 2965 + 2966 2966 + if (!wb_info->wb_enabled || wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb) 2967 2967 + return; 2968 2968 + 2969 2969 + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2970 2970 + mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2971 2971 + 2972 2972 + /* Update DWBC with new parameters */ 2973 2973 + hwss_add_dwbc_update(seq_state, dwb, &wb_info->dwb_params); 2974 2974 + 2975 2975 + /* Configure MCIF_WB buffer settings */ 2976 2976 + hwss_add_mcif_wb_config_buf(seq_state, mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2977 2977 + 2978 2978 + /* Configure MCIF_WB arbitration */ 2979 2979 + hwss_add_mcif_wb_config_arb(seq_state, mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2980 2980 + 2981 2981 + /* Enable MCIF_WB */ 2982 2982 + hwss_add_mcif_wb_enable(seq_state, mcif_wb); 2983 2983 + 2984 2984 + /* Set DWB MUX to connect writeback to MPCC */ 2985 2985 + hwss_add_mpc_set_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst, mpcc_inst); 2986 2986 + 2987 2987 + /* Enable DWBC */ 2988 2988 + hwss_add_dwbc_enable(seq_state, dwb, &wb_info->dwb_params); 2989 2989 + } 2990 2990 + 2991 2991 + void dcn401_disable_writeback_sequence( 2992 2992 + struct dc *dc, 2993 2993 + struct dc_writeback_info *wb_info, 2994 2994 + struct block_sequence_state *seq_state) 2995 2995 + { 2996 2996 + struct dwbc *dwb; 2997 2997 + struct mcif_wb *mcif_wb; 2998 2998 + 2999 2999 + if (wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb) 3000 3000 + return; 3001 3001 + 3002 3002 + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 3003 3003 + mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 3004 3004 + 3005 3005 + /* Disable DWBC */ 3006 3006 + hwss_add_dwbc_disable(seq_state, dwb); 3007 3007 + 3008 3008 + /* Disable DWB MUX */ 3009 3009 + hwss_add_mpc_disable_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst); 3010 3010 + 3011 3011 + /* Disable MCIF_WB */ 3012 3012 + hwss_add_mcif_wb_disable(seq_state, mcif_wb); 3013 3013 + } 3014 3014 + 3015 3015 + void dcn401_update_writeback_sequence( 3016 3016 + struct dc *dc, 3017 3017 + struct dc_writeback_info *wb_info, 3018 3018 + struct dc_state *context, 3019 3019 + struct block_sequence_state *seq_state) 3020 3020 + { 3021 3021 + struct dwbc *dwb; 3022 3022 + struct mcif_wb *mcif_wb; 3023 3023 + 3024 3024 + if (!wb_info->wb_enabled || wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb) 3025 3025 + return; 3026 3026 + 3027 3027 + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 3028 3028 + mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 3029 3029 + 3030 3030 + /* Update writeback pipe */ 3031 3031 + hwss_add_dwbc_update(seq_state, dwb, &wb_info->dwb_params); 3032 3032 + 3033 3033 + /* Update MCIF_WB buffer settings if needed */ 3034 3034 + hwss_add_mcif_wb_config_buf(seq_state, mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 3035 3035 + } 3036 3036 + 3037 3037 + static int find_free_gsl_group(const struct dc *dc) 3038 3038 + { 3039 3039 + if (dc->res_pool->gsl_groups.gsl_0 == 0) 3040 3040 + return 1; 3041 3041 + if (dc->res_pool->gsl_groups.gsl_1 == 0) 3042 3042 + return 2; 3043 3043 + if (dc->res_pool->gsl_groups.gsl_2 == 0) 3044 3044 + return 3; 3045 3045 + 3046 3046 + return 0; 3047 3047 + } 3048 3048 + 3049 3049 + void dcn401_setup_gsl_group_as_lock_sequence( 3050 3050 + const struct dc *dc, 3051 3051 + struct pipe_ctx *pipe_ctx, 3052 3052 + bool enable, 3053 3053 + struct block_sequence_state *seq_state) 3054 3054 + { 3055 3055 + struct gsl_params gsl; 3056 3056 + int group_idx; 3057 3057 + 3058 3058 + memset(&gsl, 0, sizeof(struct gsl_params)); 3059 3059 + 3060 3060 + if (enable) { 3061 3061 + /* return if group already assigned since GSL was set up 3062 3062 + * for vsync flip, we would unassign so it can't be "left over" 3063 3063 + */ 3064 3064 + if (pipe_ctx->stream_res.gsl_group > 0) 3065 3065 + return; 3066 3066 + 3067 3067 + group_idx = find_free_gsl_group(dc); 3068 3068 + ASSERT(group_idx != 0); 3069 3069 + pipe_ctx->stream_res.gsl_group = group_idx; 3070 3070 + 3071 3071 + /* set gsl group reg field and mark resource used */ 3072 3072 + switch (group_idx) { 3073 3073 + case 1: 3074 3074 + gsl.gsl0_en = 1; 3075 3075 + dc->res_pool->gsl_groups.gsl_0 = 1; 3076 3076 + break; 3077 3077 + case 2: 3078 3078 + gsl.gsl1_en = 1; 3079 3079 + dc->res_pool->gsl_groups.gsl_1 = 1; 3080 3080 + break; 3081 3081 + case 3: 3082 3082 + gsl.gsl2_en = 1; 3083 3083 + dc->res_pool->gsl_groups.gsl_2 = 1; 3084 3084 + break; 3085 3085 + default: 3086 3086 + BREAK_TO_DEBUGGER(); 3087 3087 + return; // invalid case 3088 3088 + } 3089 3089 + gsl.gsl_master_en = 1; 3090 3090 + } else { 3091 3091 + group_idx = pipe_ctx->stream_res.gsl_group; 3092 3092 + if (group_idx == 0) 3093 3093 + return; // if not in use, just return 3094 3094 + 3095 3095 + pipe_ctx->stream_res.gsl_group = 0; 3096 3096 + 3097 3097 + /* unset gsl group reg field and mark resource free */ 3098 3098 + switch (group_idx) { 3099 3099 + case 1: 3100 3100 + gsl.gsl0_en = 0; 3101 3101 + dc->res_pool->gsl_groups.gsl_0 = 0; 3102 3102 + break; 3103 3103 + case 2: 3104 3104 + gsl.gsl1_en = 0; 3105 3105 + dc->res_pool->gsl_groups.gsl_1 = 0; 3106 3106 + break; 3107 3107 + case 3: 3108 3108 + gsl.gsl2_en = 0; 3109 3109 + dc->res_pool->gsl_groups.gsl_2 = 0; 3110 3110 + break; 3111 3111 + default: 3112 3112 + BREAK_TO_DEBUGGER(); 3113 3113 + return; 3114 3114 + } 3115 3115 + gsl.gsl_master_en = 0; 3116 3116 + } 3117 3117 + 3118 3118 + hwss_add_tg_set_gsl(seq_state, pipe_ctx->stream_res.tg, gsl); 3119 3119 + hwss_add_tg_set_gsl_source_select(seq_state, pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 3120 3120 + } 3121 3121 + 3122 3122 + void dcn401_disable_plane_sequence( 3123 3123 + struct dc *dc, 3124 3124 + struct dc_state *state, 3125 3125 + struct pipe_ctx *pipe_ctx, 3126 3126 + struct block_sequence_state *seq_state) 3127 3127 + { 3128 3128 + bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM; 3129 3129 + struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; 3130 3130 + 3131 3131 + if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 3132 3132 + return; 3133 3133 + 3134 3134 + /* Wait for MPCC disconnect */ 3135 3135 + if (dc->hwss.wait_for_mpcc_disconnect_sequence) 3136 3136 + dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, pipe_ctx, seq_state); 3137 3137 + 3138 3138 + /* In flip immediate with pipe splitting case GSL is used for synchronization 3139 3139 + * so we must disable it when the plane is disabled. 3140 3140 + */ 3141 3141 + if (pipe_ctx->stream_res.gsl_group != 0) { 3142 3142 + dcn401_setup_gsl_group_as_lock_sequence(dc, pipe_ctx, false, seq_state); 3143 3143 + } 3144 3144 + 3145 3145 + /* Update HUBP mall sel */ 3146 3146 + if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel) { 3147 3147 + hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx->plane_res.hubp, 0, false); 3148 3148 + } 3149 3149 + 3150 3150 + /* Set flip control GSL */ 3151 3151 + hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx->plane_res.hubp, false); 3152 3152 + 3153 3153 + /* HUBP clock control */ 3154 3154 + hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, false); 3155 3155 + 3156 3156 + /* DPP clock control */ 3157 3157 + hwss_add_dpp_dppclk_control(seq_state, pipe_ctx->plane_res.dpp, false, false); 3158 3158 + 3159 3159 + /* Plane atomic power down */ 3160 3160 + if (dc->hwseq->funcs.plane_atomic_power_down_sequence) 3161 3161 + dc->hwseq->funcs.plane_atomic_power_down_sequence(dc, pipe_ctx->plane_res.dpp, 3162 3162 + pipe_ctx->plane_res.hubp, seq_state); 3163 3163 + 3164 3164 + pipe_ctx->stream = NULL; 3165 3165 + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 3166 3166 + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 3167 3167 + pipe_ctx->top_pipe = NULL; 3168 3168 + pipe_ctx->bottom_pipe = NULL; 3169 3169 + pipe_ctx->prev_odm_pipe = NULL; 3170 3170 + pipe_ctx->next_odm_pipe = NULL; 3171 3171 + pipe_ctx->plane_state = NULL; 3172 3172 + 3173 3173 + /* Turn back off the phantom OTG after the phantom plane is fully disabled */ 3174 3174 + if (is_phantom && tg && tg->funcs->disable_phantom_crtc) { 3175 3175 + hwss_add_disable_phantom_crtc(seq_state, tg); 3176 3176 + } 3177 3177 + } 3178 3178 + 3179 3179 + void dcn401_post_unlock_reset_opp_sequence( 3180 3180 + struct dc *dc, 3181 3181 + struct pipe_ctx *opp_head, 3182 3182 + struct block_sequence_state *seq_state) 3183 3183 + { 3184 3184 + struct display_stream_compressor *dsc = opp_head->stream_res.dsc; 3185 3185 + struct dccg *dccg = dc->res_pool->dccg; 3186 3186 + 3187 3187 + /* Wait for all DPP pipes in current mpc blending tree completes double 3188 3188 + * buffered disconnection before resetting OPP 3189 3189 + */ 3190 3190 + if (dc->hwss.wait_for_mpcc_disconnect_sequence) 3191 3191 + dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, opp_head, seq_state); 3192 3192 + 3193 3193 + if (dsc) { 3194 3194 + bool *is_ungated = NULL; 3195 3195 + /* Check DSC power gate status */ 3196 3196 + if (dc->hwseq && dc->hwseq->funcs.dsc_pg_status) { 3197 3197 + hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc->inst, false); 3198 3198 + } 3199 3199 + 3200 3200 + /* Seamless update specific where we will postpone non 3201 3201 + * double buffered DSCCLK disable logic in post unlock 3202 3202 + * sequence after DSC is disconnected from OPP but not 3203 3203 + * yet power gated. 3204 3204 + */ 3205 3205 + 3206 3206 + /* DSC wait disconnect pending clear */ 3207 3207 + hwss_add_dsc_wait_disconnect_pending_clear(seq_state, dsc, is_ungated); 3208 3208 + 3209 3209 + /* DSC disable */ 3210 3210 + hwss_add_dsc_disable(seq_state, dsc, is_ungated); 3211 3211 + 3212 3212 + /* Set reference DSCCLK */ 3213 3213 + if (dccg && dccg->funcs->set_ref_dscclk) { 3214 3214 + hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0); 3215 3215 + } 3216 3216 + } 3217 3217 + } 3218 3218 + 3219 3219 + void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable) 3220 3220 + { 3221 3221 + struct dce_hwseq *hws = dc->hwseq; 3222 3222 + 3223 3223 + if (REG(DC_IP_REQUEST_CNTL)) { 3224 3224 + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, enable ? 1 : 0); 3225 3225 + } 3226 3226 + } 3227 3227 + 3228 3228 + void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, 3229 3229 + struct dc_state *context, 3230 3230 + struct block_sequence_state *seq_state) 3231 3231 + { 3232 3232 + struct dce_hwseq *hws = dc->hwseq; 3233 3233 + uint32_t org_ip_request_cntl = 0; 3234 3234 + 3235 3235 + if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp) { 3236 3236 + return; 3237 3237 + } 3238 3238 + 3239 3239 + if (REG(DC_IP_REQUEST_CNTL)) 3240 3240 + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 3241 3241 + 3242 3242 + /* Step 1: DPP root clock control - enable clock */ 3243 3243 + if (hws->funcs.dpp_root_clock_control) { 3244 3244 + hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true); 3245 3245 + } 3246 3246 + 3247 3247 + /* Step 2: Enable DC IP request (if needed) */ 3248 3248 + if (hws->funcs.dc_ip_request_cntl) { 3249 3249 + hwss_add_dc_ip_request_cntl(seq_state, dc, true); 3250 3250 + } 3251 3251 + 3252 3252 + /* Step 3: DPP power gating control - power on */ 3253 3253 + if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.dpp_pg_control) { 3254 3254 + hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true); 3255 3255 + } 3256 3256 + 3257 3257 + /* Step 4: HUBP power gating control - power on */ 3258 3258 + if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.hubp_pg_control) { 3259 3259 + hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true); 3260 3260 + } 3261 3261 + 3262 3262 + /* Step 5: Disable DC IP request (restore state) */ 3263 3263 + if (org_ip_request_cntl == 0 && hws->funcs.dc_ip_request_cntl) { 3264 3264 + hwss_add_dc_ip_request_cntl(seq_state, dc, false); 3265 3265 + } 3266 3266 + 3267 3267 + /* Step 6: HUBP clock control - enable DCFCLK */ 3268 3268 + if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl) { 3269 3269 + hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, true); 3270 3270 + } 3271 3271 + 3272 3272 + /* Step 7: HUBP initialization */ 3273 3273 + if (pipe_ctx->plane_res.hubp->funcs->hubp_init) { 3274 3274 + hwss_add_hubp_init(seq_state, pipe_ctx->plane_res.hubp); 3275 3275 + } 3276 3276 + 3277 3277 + /* Step 8: OPP pipe clock control - enable */ 3278 3278 + if (pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control) { 3279 3279 + hwss_add_opp_pipe_clock_control(seq_state, pipe_ctx->stream_res.opp, true); 3280 3280 + } 3281 3281 + 3282 3282 + /* Step 9: VM system aperture settings */ 3283 3283 + if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) { 3284 3284 + hwss_add_hubp_set_vm_system_aperture_settings(seq_state, pipe_ctx->plane_res.hubp, 0, 3285 3285 + dc->vm_pa_config.system_aperture.start_addr, dc->vm_pa_config.system_aperture.end_addr); 3286 3286 + } 3287 3287 + 3288 3288 + /* Step 10: Flip interrupt setup */ 3289 3289 + if (!pipe_ctx->top_pipe 3290 3290 + && pipe_ctx->plane_state 3291 3291 + && pipe_ctx->plane_state->flip_int_enabled 3292 3292 + && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) { 3293 3293 + hwss_add_hubp_set_flip_int(seq_state, pipe_ctx->plane_res.hubp); 3294 3294 + } 3295 3295 + } 3296 3296 + 3297 3297 + void dcn401_update_dchubp_dpp_sequence(struct dc *dc, 3298 3298 + struct pipe_ctx *pipe_ctx, 3299 3299 + struct dc_state *context, 3300 3300 + struct block_sequence_state *seq_state) 3301 3301 + { 3302 3302 + struct dce_hwseq *hws = dc->hwseq; 3303 3303 + struct hubp *hubp = pipe_ctx->plane_res.hubp; 3304 3304 + struct dpp *dpp = pipe_ctx->plane_res.dpp; 3305 3305 + struct dc_plane_state *plane_state = pipe_ctx->plane_state; 3306 3306 + struct dccg *dccg = dc->res_pool->dccg; 3307 3307 + bool viewport_changed = false; 3308 3308 + enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx); 3309 3309 + 3310 3310 + if (!hubp || !dpp || !plane_state) { 3311 3311 + return; 3312 3312 + } 3313 3313 + 3314 3314 + /* Step 1: DPP DPPCLK control */ 3315 3315 + if (pipe_ctx->update_flags.bits.dppclk) { 3316 3316 + hwss_add_dpp_dppclk_control(seq_state, dpp, false, true); 3317 3317 + } 3318 3318 + 3319 3319 + /* Step 2: DCCG update DPP DTO */ 3320 3320 + if (pipe_ctx->update_flags.bits.enable) { 3321 3321 + hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 3322 3322 + } 3323 3323 + 3324 3324 + /* Step 3: HUBP VTG selection */ 3325 3325 + if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 3326 3326 + hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst); 3327 3327 + 3328 3328 + /* Step 4: HUBP setup (choose setup2 or setup) */ 3329 3329 + if (hubp->funcs->hubp_setup2) { 3330 3330 + hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs, 3331 3331 + &pipe_ctx->global_sync, &pipe_ctx->stream->timing); 3332 3332 + } else if (hubp->funcs->hubp_setup) { 3333 3333 + hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs, 3334 3334 + &pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param); 3335 3335 + } 3336 3336 + } 3337 3337 + 3338 3338 + /* Step 5: Set unbounded requesting */ 3339 3339 + if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting) { 3340 3340 + hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req); 3341 3341 + } 3342 3342 + 3343 3343 + /* Step 6: HUBP interdependent setup */ 3344 3344 + if (pipe_ctx->update_flags.bits.hubp_interdependent) { 3345 3345 + if (hubp->funcs->hubp_setup_interdependent2) { 3346 3346 + hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs); 3347 3347 + } else if (hubp->funcs->hubp_setup_interdependent) { 3348 3348 + hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs); 3349 3349 + } 3350 3350 + } 3351 3351 + 3352 3352 + /* Step 7: DPP setup - input CSC and format setup */ 3353 3353 + if (pipe_ctx->update_flags.bits.enable || 3354 3354 + pipe_ctx->update_flags.bits.plane_changed || 3355 3355 + plane_state->update_flags.bits.bpp_change || 3356 3356 + plane_state->update_flags.bits.input_csc_change || 3357 3357 + plane_state->update_flags.bits.color_space_change || 3358 3358 + plane_state->update_flags.bits.coeff_reduction_change) { 3359 3359 + hwss_add_dpp_setup_dpp(seq_state, pipe_ctx); 3360 3360 + 3361 3361 + /* Step 8: DPP cursor matrix setup */ 3362 3362 + if (dpp->funcs->set_cursor_matrix) { 3363 3363 + hwss_add_dpp_set_cursor_matrix(seq_state, dpp, plane_state->color_space, 3364 3364 + &plane_state->cursor_csc_color_matrix); 3365 3365 + } 3366 3366 + 3367 3367 + /* Step 9: DPP program bias and scale */ 3368 3368 + if (dpp->funcs->dpp_program_bias_and_scale) { 3369 3369 + hwss_add_dpp_program_bias_and_scale(seq_state, pipe_ctx); 3370 3370 + } 3371 3371 + } 3372 3372 + 3373 3373 + /* Step 10: MPCC updates */ 3374 3374 + if (pipe_ctx->update_flags.bits.mpcc || 3375 3375 + pipe_ctx->update_flags.bits.plane_changed || 3376 3376 + plane_state->update_flags.bits.global_alpha_change || 3377 3377 + plane_state->update_flags.bits.per_pixel_alpha_change) { 3378 3378 + 3379 3379 + /* Check if update_mpcc_sequence is implemented and prefer it over single MPC_UPDATE_MPCC step */ 3380 3380 + if (hws->funcs.update_mpcc_sequence) 3381 3381 + hws->funcs.update_mpcc_sequence(dc, pipe_ctx, seq_state); 3382 3382 + } 3383 3383 + 3384 3384 + /* Step 11: DPP scaler setup */ 3385 3385 + if (pipe_ctx->update_flags.bits.scaler || 3386 3386 + plane_state->update_flags.bits.scaling_change || 3387 3387 + plane_state->update_flags.bits.position_change || 3388 3388 + plane_state->update_flags.bits.per_pixel_alpha_change || 3389 3389 + pipe_ctx->stream->update_flags.bits.scaling) { 3390 3390 + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 3391 3391 + ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 3392 3392 + hwss_add_dpp_set_scaler(seq_state, pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 3393 3393 + } 3394 3394 + 3395 3395 + /* Step 12: HUBP viewport programming */ 3396 3396 + if (pipe_ctx->update_flags.bits.viewport || 3397 3397 + (context == dc->current_state && plane_state->update_flags.bits.position_change) || 3398 3398 + (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 3399 3399 + (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 3400 3400 + hwss_add_hubp_mem_program_viewport(seq_state, hubp, 3401 3401 + &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c); 3402 3402 + viewport_changed = true; 3403 3403 + } 3404 3404 + 3405 3405 + /* Step 13: HUBP program mcache if available */ 3406 3406 + if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate) { 3407 3407 + hwss_add_hubp_program_mcache_id(seq_state, hubp, &pipe_ctx->mcache_regs); 3408 3408 + } 3409 3409 + 3410 3410 + /* Step 14: Cursor attribute setup */ 3411 3411 + if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 3412 3412 + pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 3413 3413 + pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 3414 3414 + 3415 3415 + hwss_add_set_cursor_attribute(seq_state, dc, pipe_ctx); 3416 3416 + 3417 3417 + /* Step 15: Cursor position setup */ 3418 3418 + hwss_add_set_cursor_position(seq_state, dc, pipe_ctx); 3419 3419 + 3420 3420 + /* Step 16: Cursor SDR white level */ 3421 3421 + if (dc->hwss.set_cursor_sdr_white_level) { 3422 3422 + hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx); 3423 3423 + } 3424 3424 + } 3425 3425 + 3426 3426 + /* Step 17: Gamut remap and output CSC */ 3427 3427 + if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 3428 3428 + pipe_ctx->update_flags.bits.plane_changed || 3429 3429 + pipe_ctx->stream->update_flags.bits.gamut_remap || 3430 3430 + plane_state->update_flags.bits.gamut_remap_change || 3431 3431 + pipe_ctx->stream->update_flags.bits.out_csc) { 3432 3432 + 3433 3433 + /* Gamut remap */ 3434 3434 + hwss_add_dpp_program_gamut_remap(seq_state, pipe_ctx); 3435 3435 + 3436 3436 + /* Output CSC */ 3437 3437 + hwss_add_program_output_csc(seq_state, dc, pipe_ctx, pipe_ctx->stream->output_color_space, 3438 3438 + pipe_ctx->stream->csc_color_matrix.matrix, hubp->opp_id); 3439 3439 + } 3440 3440 + 3441 3441 + /* Step 18: HUBP surface configuration */ 3442 3442 + if (pipe_ctx->update_flags.bits.enable || 3443 3443 + pipe_ctx->update_flags.bits.plane_changed || 3444 3444 + pipe_ctx->update_flags.bits.opp_changed || 3445 3445 + plane_state->update_flags.bits.pixel_format_change || 3446 3446 + plane_state->update_flags.bits.horizontal_mirror_change || 3447 3447 + plane_state->update_flags.bits.rotation_change || 3448 3448 + plane_state->update_flags.bits.swizzle_change || 3449 3449 + plane_state->update_flags.bits.dcc_change || 3450 3450 + plane_state->update_flags.bits.bpp_change || 3451 3451 + plane_state->update_flags.bits.scaling_change || 3452 3452 + plane_state->update_flags.bits.plane_size_change) { 3453 3453 + struct plane_size size = plane_state->plane_size; 3454 3454 + 3455 3455 + size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 3456 3456 + hwss_add_hubp_program_surface_config(seq_state, hubp, 3457 3457 + plane_state->format, &plane_state->tiling_info, size, 3458 3458 + plane_state->rotation, &plane_state->dcc, 3459 3459 + plane_state->horizontal_mirror, 0); 3460 3460 + hubp->power_gated = false; 3461 3461 + } 3462 3462 + 3463 3463 + /* Step 19: Update plane address (with SubVP support) */ 3464 3464 + if (pipe_ctx->update_flags.bits.enable || 3465 3465 + pipe_ctx->update_flags.bits.plane_changed || 3466 3466 + plane_state->update_flags.bits.addr_update) { 3467 3467 + 3468 3468 + /* SubVP save surface address if needed */ 3469 3469 + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_mall_type == SUBVP_MAIN) { 3470 3470 + hwss_add_dmub_subvp_save_surf_addr(seq_state, dc->ctx->dmub_srv, &pipe_ctx->plane_state->address, pipe_ctx->subvp_index); 3471 3471 + } 3472 3472 + 3473 3473 + /* Update plane address */ 3474 3474 + hwss_add_hubp_update_plane_addr(seq_state, dc, pipe_ctx); 3475 3475 + } 3476 3476 + 3477 3477 + /* Step 20: HUBP set blank - enable plane */ 3478 3478 + if (pipe_ctx->update_flags.bits.enable) { 3479 3479 + hwss_add_hubp_set_blank(seq_state, hubp, false); 3480 3480 + } 3481 3481 + 3482 3482 + /* Step 21: Phantom HUBP post enable */ 3483 3483 + if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable) { 3484 3484 + hwss_add_phantom_hubp_post_enable(seq_state, hubp); 3485 3485 + } 3486 3486 + } 3487 3487 + 3488 3488 + void dcn401_update_mpcc_sequence(struct dc *dc, 3489 3489 + struct pipe_ctx *pipe_ctx, 3490 3490 + struct block_sequence_state *seq_state) 3491 3491 + { 3492 3492 + struct hubp *hubp = pipe_ctx->plane_res.hubp; 3493 3493 + struct mpcc_blnd_cfg blnd_cfg = {0}; 3494 3494 + bool per_pixel_alpha; 3495 3495 + int mpcc_id; 3496 3496 + struct mpcc *new_mpcc; 3497 3497 + struct mpc *mpc = dc->res_pool->mpc; 3498 3498 + struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 3499 3499 + 3500 3500 + if (!hubp || !pipe_ctx->plane_state) { 3501 3501 + return; 3502 3502 + } 3503 3503 + 3504 3504 + per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 3505 3505 + 3506 3506 + /* Initialize blend configuration */ 3507 3507 + blnd_cfg.overlap_only = false; 3508 3508 + blnd_cfg.global_gain = 0xff; 3509 3509 + 3510 3510 + if (per_pixel_alpha) { 3511 3511 + blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 3512 3512 + if (pipe_ctx->plane_state->global_alpha) { 3513 3513 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 3514 3514 + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 3515 3515 + } else { 3516 3516 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 3517 3517 + } 3518 3518 + } else { 3519 3519 + blnd_cfg.pre_multiplied_alpha = false; 3520 3520 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 3521 3521 + } 3522 3522 + 3523 3523 + if (pipe_ctx->plane_state->global_alpha) 3524 3524 + blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 3525 3525 + else 3526 3526 + blnd_cfg.global_alpha = 0xff; 3527 3527 + 3528 3528 + blnd_cfg.background_color_bpc = 4; 3529 3529 + blnd_cfg.bottom_gain_mode = 0; 3530 3530 + blnd_cfg.top_gain = 0x1f000; 3531 3531 + blnd_cfg.bottom_inside_gain = 0x1f000; 3532 3532 + blnd_cfg.bottom_outside_gain = 0x1f000; 3533 3533 + 3534 3534 + if (pipe_ctx->plane_state->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 3535 3535 + blnd_cfg.pre_multiplied_alpha = false; 3536 3536 + 3537 3537 + /* MPCC instance is equal to HUBP instance */ 3538 3538 + mpcc_id = hubp->inst; 3539 3539 + 3540 3540 + /* Step 1: Update blending if no full update needed */ 3541 3541 + if (!pipe_ctx->plane_state->update_flags.bits.full_update && 3542 3542 + !pipe_ctx->update_flags.bits.mpcc) { 3543 3543 + 3544 3544 + /* Update blending configuration */ 3545 3545 + hwss_add_mpc_update_blending(seq_state, mpc, blnd_cfg, mpcc_id); 3546 3546 + 3547 3547 + /* Update visual confirm color */ 3548 3548 + hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id); 3549 3549 + return; 3550 3550 + } 3551 3551 + 3552 3552 + /* Step 2: Get existing MPCC for DPP */ 3553 3553 + new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 3554 3554 + 3555 3555 + /* Step 3: Remove MPCC if being used */ 3556 3556 + if (new_mpcc != NULL) { 3557 3557 + hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, new_mpcc); 3558 3558 + } else { 3559 3559 + /* Step 4: Assert MPCC idle (debug only) */ 3560 3560 + if (dc->debug.sanity_checks) { 3561 3561 + hwss_add_mpc_assert_idle_mpcc(seq_state, mpc, mpcc_id); 3562 3562 + } 3563 3563 + } 3564 3564 + 3565 3565 + /* Step 5: Insert new plane into MPC tree */ 3566 3566 + hwss_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp->inst, mpcc_id); 3567 3567 + 3568 3568 + /* Step 6: Update visual confirm color */ 3569 3569 + hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id); 3570 3570 + 3571 3571 + /* Step 7: Set HUBP OPP and MPCC IDs */ 3572 3572 + hubp->opp_id = pipe_ctx->stream_res.opp->inst; 3573 3573 + hubp->mpcc_id = mpcc_id; 3574 3574 + } 3575 3575 + 3576 3576 + static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) 3577 3577 + { 3578 3578 + int i; 3579 3579 + 3580 3580 + for (i = 0; i < res_pool->pipe_count; i++) { 3581 3581 + if (res_pool->hubps[i]->inst == mpcc_inst) 3582 3582 + return res_pool->hubps[i]; 3583 3583 + } 3584 3584 + ASSERT(false); 3585 3585 + return NULL; 3586 3586 + } 3587 3587 + 3588 3588 + void dcn401_wait_for_mpcc_disconnect_sequence( 3589 3589 + struct dc *dc, 3590 3590 + struct resource_pool *res_pool, 3591 3591 + struct pipe_ctx *pipe_ctx, 3592 3592 + struct block_sequence_state *seq_state) 3593 3593 + { 3594 3594 + int mpcc_inst; 3595 3595 + 3596 3596 + if (dc->debug.sanity_checks) { 3597 3597 + dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); 3598 3598 + } 3599 3599 + 3600 3600 + if (!pipe_ctx->stream_res.opp) 3601 3601 + return; 3602 3602 + 3603 3603 + for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { 3604 3604 + if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { 3605 3605 + struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); 3606 3606 + 3607 3607 + if (pipe_ctx->stream_res.tg && 3608 3608 + pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) { 3609 3609 + hwss_add_mpc_assert_idle_mpcc(seq_state, res_pool->mpc, mpcc_inst); 3610 3610 + } 3611 3611 + pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; 3612 3612 + if (hubp) { 3613 3613 + hwss_add_hubp_set_blank(seq_state, hubp, true); 3614 3614 + } 3615 3615 + } 3616 3616 + } 3617 3617 + 3618 3618 + if (dc->debug.sanity_checks) { 3619 3619 + dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); 3620 3620 + } 3621 3621 + } 3622 3622 + 3623 3623 + void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, 3624 3624 + struct block_sequence_state *seq_state) 3625 3625 + { 3626 3626 + struct timing_generator *tg = pipe_ctx->stream_res.tg; 3627 3627 + int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 3628 3628 + 3629 3629 + if (start_line < 0) 3630 3630 + start_line = 0; 3631 3631 + 3632 3632 + if (tg->funcs->setup_vertical_interrupt2) { 3633 3633 + hwss_add_tg_setup_vertical_interrupt2(seq_state, tg, start_line); 3634 3634 + } 3635 3635 + } 3636 3636 + 3637 3637 + void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx, 3638 3638 + struct block_sequence_state *seq_state) 3639 3639 + { 3640 3640 + struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult; 3641 3641 + uint32_t hw_mult = 0x1f000; // 1.0 default multiplier 3642 3642 + struct custom_float_format fmt; 3643 3643 + 3644 3644 + fmt.exponenta_bits = 6; 3645 3645 + fmt.mantissa_bits = 12; 3646 3646 + fmt.sign = true; 3647 3647 + 3648 3648 + if (!dc_fixpt_eq(multiplier, dc_fixpt_from_int(0))) // check != 0 3649 3649 + convert_to_custom_float_format(multiplier, &fmt, &hw_mult); 3650 3650 + 3651 3651 + hwss_add_dpp_set_hdr_multiplier(seq_state, pipe_ctx->plane_res.dpp, hw_mult); 3652 3652 + } 3653 3653 + 3654 3654 + void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context, 3655 3655 + struct block_sequence_state *seq_state) 3656 3656 + { 3657 3657 + int i; 3658 3658 + unsigned int num_ways = dcn401_calculate_cab_allocation(dc, context); 3659 3659 + bool cache_cursor = false; 3660 3660 + 3661 3661 + // Don't force p-state disallow -- can't block dummy p-state 3662 3662 + 3663 3663 + // Update MALL_SEL register for each pipe (break down update_mall_sel call) 3664 3664 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 3665 3665 + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3666 3666 + struct hubp *hubp = pipe->plane_res.hubp; 3667 3667 + 3668 3668 + if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 3669 3669 + int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 3670 3670 + 3671 3671 + switch (hubp->curs_attr.color_format) { 3672 3672 + case CURSOR_MODE_MONO: 3673 3673 + cursor_size /= 2; 3674 3674 + break; 3675 3675 + case CURSOR_MODE_COLOR_1BIT_AND: 3676 3676 + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 3677 3677 + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 3678 3678 + cursor_size *= 4; 3679 3679 + break; 3680 3680 + 3681 3681 + case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 3682 3682 + case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 3683 3683 + default: 3684 3684 + cursor_size *= 8; 3685 3685 + break; 3686 3686 + } 3687 3687 + 3688 3688 + if (cursor_size > 16384) 3689 3689 + cache_cursor = true; 3690 3690 + 3691 3691 + if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { 3692 3692 + hwss_add_hubp_update_mall_sel(seq_state, hubp, 1, false); 3693 3693 + } else { 3694 3694 + // MALL not supported with Stereo3D 3695 3695 + uint32_t mall_sel = (num_ways <= dc->caps.cache_num_ways && 3696 3696 + pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 3697 3697 + pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 3698 3698 + !pipe->plane_state->address.tmz_surface) ? 2 : 0; 3699 3699 + hwss_add_hubp_update_mall_sel(seq_state, hubp, mall_sel, cache_cursor); 3700 3700 + } 3701 3701 + } 3702 3702 + } 3703 3703 + 3704 3704 + // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 3705 3705 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 3706 3706 + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3707 3707 + struct hubp *hubp = pipe->plane_res.hubp; 3708 3708 + 3709 3709 + if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 3710 3710 + if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) { 3711 3711 + hwss_add_hubp_prepare_subvp_buffering(seq_state, hubp, true); 3712 3712 + } 3713 3713 + } 3714 3714 + } 3715 3715 + } 3716 3716 + 3717 3717 + void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc, 3718 3718 + struct block_sequence_state *seq_state) 3719 3719 + { 3720 3720 + struct hubbub *hubbub = dc->res_pool->hubbub; 3721 3721 + 3722 3722 + if (!hubbub->funcs->verify_allow_pstate_change_high) 3723 3723 + return; 3724 3724 + 3725 3725 + if (!hubbub->funcs->verify_allow_pstate_change_high(hubbub)) { 3726 3726 + /* Attempt hardware workaround force recovery */ 3727 3727 + dcn401_hw_wa_force_recovery_sequence(dc, seq_state); 3728 3728 + } 3729 3729 + } 3730 3730 + 3731 3731 + bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc, 3732 3732 + struct block_sequence_state *seq_state) 3733 3733 + { 3734 3734 + struct hubp *hubp; 3735 3735 + unsigned int i; 3736 3736 + 3737 3737 + if (!dc->debug.recovery_enabled) 3738 3738 + return false; 3739 3739 + 3740 3740 + /* Step 1: Set HUBP_BLANK_EN=1 for all active pipes */ 3741 3741 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 3742 3742 + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 3743 3743 + if (pipe_ctx != NULL) { 3744 3744 + hubp = pipe_ctx->plane_res.hubp; 3745 3745 + if (hubp != NULL && hubp->funcs->set_hubp_blank_en) { 3746 3746 + hwss_add_hubp_set_blank_en(seq_state, hubp, true); 3747 3747 + } 3748 3748 + } 3749 3749 + } 3750 3750 + 3751 3751 + /* Step 2: DCHUBBUB_GLOBAL_SOFT_RESET=1 */ 3752 3752 + hwss_add_hubbub_soft_reset(seq_state, dc->res_pool->hubbub, hubbub1_soft_reset, true); 3753 3753 + 3754 3754 + /* Step 3: Set HUBP_DISABLE=1 for all active pipes */ 3755 3755 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 3756 3756 + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 3757 3757 + if (pipe_ctx != NULL) { 3758 3758 + hubp = pipe_ctx->plane_res.hubp; 3759 3759 + if (hubp != NULL && hubp->funcs->hubp_disable_control) { 3760 3760 + hwss_add_hubp_disable_control(seq_state, hubp, true); 3761 3761 + } 3762 3762 + } 3763 3763 + } 3764 3764 + 3765 3765 + /* Step 4: Set HUBP_DISABLE=0 for all active pipes */ 3766 3766 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 3767 3767 + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 3768 3768 + if (pipe_ctx != NULL) { 3769 3769 + hubp = pipe_ctx->plane_res.hubp; 3770 3770 + if (hubp != NULL && hubp->funcs->hubp_disable_control) { 3771 3771 + hwss_add_hubp_disable_control(seq_state, hubp, false); 3772 3772 + } 3773 3773 + } 3774 3774 + } 3775 3775 + 3776 3776 + /* Step 5: DCHUBBUB_GLOBAL_SOFT_RESET=0 */ 3777 3777 + hwss_add_hubbub_soft_reset(seq_state, dc->res_pool->hubbub, hubbub1_soft_reset, false); 3778 3778 + 3779 3779 + /* Step 6: Set HUBP_BLANK_EN=0 for all active pipes */ 3780 3780 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 3781 3781 + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 3782 3782 + if (pipe_ctx != NULL) { 3783 3783 + hubp = pipe_ctx->plane_res.hubp; 3784 3784 + if (hubp != NULL && hubp->funcs->set_hubp_blank_en) { 3785 3785 + hwss_add_hubp_set_blank_en(seq_state, hubp, false); 3786 3786 + } 3787 3787 + } 3788 3788 + } 3789 3789 + 3790 3790 + return true; 3013 3791 }

+98

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

reviewed

··· 9 9 #include "dc.h" 10 10 #include "dc_stream.h" 11 11 #include "hw_sequencer_private.h" 12 12 + #include "hwss/hw_sequencer.h" 12 13 #include "dcn401/dcn401_dccg.h" 13 14 14 15 struct dc; ··· 83 82 void dcn401_hardware_release(struct dc *dc); 84 83 void dcn401_update_odm(struct dc *dc, struct dc_state *context, 85 84 struct pipe_ctx *otg_master); 85 85 + void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context, 86 86 + struct pipe_ctx *otg_master, struct block_sequence_state *seq_state); 86 87 void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy); 87 88 void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); 88 89 void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock); ··· 100 97 struct dc *dc, 101 98 struct pipe_ctx *pipe_ctx, 102 99 struct dc_state *context); 100 100 + void dcn401_program_pipe_sequence( 101 101 + struct dc *dc, 102 102 + struct pipe_ctx *pipe_ctx, 103 103 + struct dc_state *context, 104 104 + struct block_sequence_state *seq_state); 103 105 void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx); 104 106 void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context); 105 107 void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context); ··· 117 109 void dcn401_plane_atomic_power_down(struct dc *dc, 118 110 struct dpp *dpp, 119 111 struct hubp *hubp); 112 112 + void dcn401_plane_atomic_power_down_sequence(struct dc *dc, 113 113 + struct dpp *dpp, 114 114 + struct hubp *hubp, 115 115 + struct block_sequence_state *seq_state); 116 116 + void dcn401_plane_atomic_disconnect_sequence(struct dc *dc, 117 117 + struct dc_state *state, 118 118 + struct pipe_ctx *pipe_ctx, 119 119 + struct block_sequence_state *seq_state); 120 120 + void dcn401_blank_pixel_data_sequence( 121 121 + struct dc *dc, 122 122 + struct pipe_ctx *pipe_ctx, 123 123 + bool blank, 124 124 + struct block_sequence_state *seq_state); 120 125 void dcn401_initialize_min_clocks(struct dc *dc); 121 126 void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe); 127 127 + 128 128 + void dcn401_program_all_writeback_pipes_in_tree_sequence( 129 129 + struct dc *dc, 130 130 + const struct dc_stream_state *stream, 131 131 + struct dc_state *context, 132 132 + struct block_sequence_state *seq_state); 133 133 + 134 134 + void dcn401_enable_writeback_sequence( 135 135 + struct dc *dc, 136 136 + struct dc_writeback_info *wb_info, 137 137 + struct dc_state *context, 138 138 + int mpcc_inst, 139 139 + struct block_sequence_state *seq_state); 140 140 + 141 141 + void dcn401_disable_writeback_sequence( 142 142 + struct dc *dc, 143 143 + struct dc_writeback_info *wb_info, 144 144 + struct block_sequence_state *seq_state); 145 145 + 146 146 + void dcn401_update_writeback_sequence( 147 147 + struct dc *dc, 148 148 + struct dc_writeback_info *wb_info, 149 149 + struct dc_state *context, 150 150 + struct block_sequence_state *seq_state); 151 151 + 152 152 + void dcn401_setup_gsl_group_as_lock_sequence( 153 153 + const struct dc *dc, 154 154 + struct pipe_ctx *pipe_ctx, 155 155 + bool enable, 156 156 + struct block_sequence_state *seq_state); 157 157 + 158 158 + void dcn401_disable_plane_sequence( 159 159 + struct dc *dc, 160 160 + struct dc_state *state, 161 161 + struct pipe_ctx *pipe_ctx, 162 162 + struct block_sequence_state *seq_state); 163 163 + 164 164 + void dcn401_post_unlock_reset_opp_sequence( 165 165 + struct dc *dc, 166 166 + struct pipe_ctx *opp_head, 167 167 + struct block_sequence_state *seq_state); 168 168 + 169 169 + void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable); 170 170 + 171 171 + void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, 172 172 + struct dc_state *context, 173 173 + struct block_sequence_state *seq_state); 174 174 + 175 175 + void dcn401_update_dchubp_dpp_sequence(struct dc *dc, 176 176 + struct pipe_ctx *pipe_ctx, 177 177 + struct dc_state *context, 178 178 + struct block_sequence_state *seq_state); 179 179 + 180 180 + void dcn401_update_mpcc_sequence(struct dc *dc, 181 181 + struct pipe_ctx *pipe_ctx, 182 182 + struct block_sequence_state *seq_state); 183 183 + 184 184 + void dcn401_wait_for_mpcc_disconnect_sequence( 185 185 + struct dc *dc, 186 186 + struct resource_pool *res_pool, 187 187 + struct pipe_ctx *pipe_ctx, 188 188 + struct block_sequence_state *seq_state); 189 189 + 190 190 + void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, 191 191 + struct block_sequence_state *seq_state); 192 192 + 193 193 + void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx, 194 194 + struct block_sequence_state *seq_state); 195 195 + 196 196 + void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context, 197 197 + struct block_sequence_state *seq_state); 198 198 + 199 199 + void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc, 200 200 + struct block_sequence_state *seq_state); 201 201 + 202 202 + bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc, 203 203 + struct block_sequence_state *seq_state); 122 204 123 205 #endif /* __DC_HWSS_DCN401_H__ */

+17

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

reviewed

··· 39 39 .enable_audio_stream = dce110_enable_audio_stream, 40 40 .disable_audio_stream = dce110_disable_audio_stream, 41 41 .disable_plane = dcn20_disable_plane, 42 42 + .disable_plane_sequence = dcn401_disable_plane_sequence, 42 43 .pipe_control_lock = dcn20_pipe_control_lock, 43 44 .interdependent_update_lock = dcn401_interdependent_update_lock, 44 45 .cursor_lock = dcn10_cursor_lock, ··· 55 54 .get_hw_state = dcn10_get_hw_state, 56 55 .clear_status_bits = dcn10_clear_status_bits, 57 56 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, 57 57 + .wait_for_mpcc_disconnect_sequence = dcn401_wait_for_mpcc_disconnect_sequence, 58 58 .edp_backlight_control = dce110_edp_backlight_control, 59 59 .edp_power_control = dce110_edp_power_control, 60 60 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, ··· 111 109 .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, 112 110 .detect_pipe_changes = dcn401_detect_pipe_changes, 113 111 .enable_plane = dcn20_enable_plane, 112 112 + .enable_plane_sequence = dcn401_enable_plane_sequence, 114 113 .update_dchubp_dpp = dcn20_update_dchubp_dpp, 114 114 + .update_dchubp_dpp_sequence = dcn401_update_dchubp_dpp_sequence, 115 115 .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, 116 116 + .post_unlock_reset_opp_sequence = dcn401_post_unlock_reset_opp_sequence, 116 117 .get_underflow_debug_data = dcn30_get_underflow_debug_data, 117 118 }; 118 119 119 120 static const struct hwseq_private_funcs dcn401_private_funcs = { 120 121 .init_pipes = dcn10_init_pipes, 121 122 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, 123 123 + .plane_atomic_disconnect_sequence = dcn401_plane_atomic_disconnect_sequence, 122 124 .update_mpcc = dcn20_update_mpcc, 125 125 + .update_mpcc_sequence = dcn401_update_mpcc_sequence, 123 126 .set_input_transfer_func = dcn32_set_input_transfer_func, 124 127 .set_output_transfer_func = dcn401_set_output_transfer_func, 125 128 .power_down = dce110_power_down, 126 129 .enable_display_power_gating = dcn10_dummy_display_power_gating, 127 130 .blank_pixel_data = dcn20_blank_pixel_data, 131 131 + .blank_pixel_data_sequence = dcn401_blank_pixel_data_sequence, 128 132 .reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap, 129 133 .enable_stream_timing = dcn401_enable_stream_timing, 130 134 .edp_backlight_control = dce110_edp_backlight_control, 131 135 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, 136 136 + .setup_vupdate_interrupt_sequence = dcn401_setup_vupdate_interrupt_sequence, 132 137 .did_underflow_occur = dcn10_did_underflow_occur, 133 138 .init_blank = dcn32_init_blank, 134 139 .disable_vga = dcn20_disable_vga, 135 140 .bios_golden_init = dcn10_bios_golden_init, 136 141 .plane_atomic_disable = dcn20_plane_atomic_disable, 137 142 .plane_atomic_power_down = dcn401_plane_atomic_power_down, 143 143 + .plane_atomic_power_down_sequence = dcn401_plane_atomic_power_down_sequence, 138 144 .enable_power_gating_plane = dcn32_enable_power_gating_plane, 139 145 .hubp_pg_control = dcn32_hubp_pg_control, 140 146 .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, 147 147 + .program_all_writeback_pipes_in_tree_sequence = dcn401_program_all_writeback_pipes_in_tree_sequence, 141 148 .update_odm = dcn401_update_odm, 149 149 + .update_odm_sequence = dcn401_update_odm_sequence, 142 150 .dsc_pg_control = dcn32_dsc_pg_control, 143 151 .dsc_pg_status = dcn32_dsc_pg_status, 144 152 .set_hdr_multiplier = dcn10_set_hdr_multiplier, 153 153 + .set_hdr_multiplier_sequence = dcn401_set_hdr_multiplier_sequence, 145 154 .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, 155 155 + .verify_allow_pstate_change_high_sequence = dcn401_verify_allow_pstate_change_high_sequence, 146 156 .wait_for_blank_complete = dcn20_wait_for_blank_complete, 147 157 .dccg_init = dcn20_dccg_init, 148 158 .set_mcm_luts = dcn401_set_mcm_luts, 149 159 .program_mall_pipe_config = dcn32_program_mall_pipe_config, 160 160 + .program_mall_pipe_config_sequence = dcn401_program_mall_pipe_config_sequence, 150 161 .update_mall_sel = dcn32_update_mall_sel, 151 162 .calculate_dccg_k1_k2_values = NULL, 152 163 .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, 153 164 .reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe, 154 165 .populate_mcm_luts = NULL, 155 166 .perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock, 167 167 + .program_pipe_sequence = dcn401_program_pipe_sequence, 168 168 + .dc_ip_request_cntl = dcn401_dc_ip_request_cntl, 156 169 }; 157 170 158 171 void dcn401_hw_sequencer_init_functions(struct dc *dc)

+1408 -1

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

reviewed

··· 31 31 #include "inc/hw/opp.h" 32 32 #include "inc/hw/link_encoder.h" 33 33 #include "inc/core_status.h" 34 34 + #include "inc/hw/hw_shared.h" 35 35 + #include "dsc/dsc.h" 34 36 35 37 struct pipe_ctx; 36 38 struct dc_state; ··· 50 48 struct pg_block_update; 51 49 struct drr_params; 52 50 struct dc_underflow_debug_data; 51 51 + struct dsc_optc_config; 52 52 + struct vm_system_aperture_param; 53 53 54 54 struct subvp_pipe_control_lock_fast_params { 55 55 struct dc *dc; ··· 66 62 }; 67 63 68 64 struct set_flip_control_gsl_params { 69 69 - struct pipe_ctx *pipe_ctx; 65 65 + struct hubp *hubp; 70 66 bool flip_immediate; 71 67 }; 72 68 ··· 158 154 bool lock; 159 155 }; 160 156 157 157 + struct program_surface_config_params { 158 158 + struct hubp *hubp; 159 159 + enum surface_pixel_format format; 160 160 + struct dc_tiling_info *tiling_info; 161 161 + struct plane_size plane_size; 162 162 + enum dc_rotation_angle rotation; 163 163 + struct dc_plane_dcc_param *dcc; 164 164 + bool horizontal_mirror; 165 165 + int compat_level; 166 166 + }; 167 167 + 168 168 + struct program_mcache_id_and_split_coordinate { 169 169 + struct hubp *hubp; 170 170 + struct dml2_hubp_pipe_mcache_regs *mcache_regs; 171 171 + }; 172 172 + 161 173 struct program_cursor_update_now_params { 162 174 struct dc *dc; 163 175 struct pipe_ctx *pipe_ctx; 176 176 + }; 177 177 + 178 178 + struct hubp_wait_pipe_read_start_params { 179 179 + struct hubp *hubp; 180 180 + }; 181 181 + 182 182 + struct apply_update_flags_for_phantom_params { 183 183 + struct pipe_ctx *pipe_ctx; 184 184 + }; 185 185 + 186 186 + struct update_phantom_vp_position_params { 187 187 + struct dc *dc; 188 188 + struct pipe_ctx *pipe_ctx; 189 189 + struct dc_state *context; 190 190 + }; 191 191 + 192 192 + struct set_odm_combine_params { 193 193 + struct timing_generator *tg; 194 194 + int opp_inst[MAX_PIPES]; 195 195 + int opp_head_count; 196 196 + int odm_slice_width; 197 197 + int last_odm_slice_width; 198 198 + }; 199 199 + 200 200 + struct set_odm_bypass_params { 201 201 + struct timing_generator *tg; 202 202 + const struct dc_crtc_timing *timing; 203 203 + }; 204 204 + 205 205 + struct opp_pipe_clock_control_params { 206 206 + struct output_pixel_processor *opp; 207 207 + bool enable; 208 208 + }; 209 209 + 210 210 + struct opp_program_left_edge_extra_pixel_params { 211 211 + struct output_pixel_processor *opp; 212 212 + enum dc_pixel_encoding pixel_encoding; 213 213 + bool is_otg_master; 214 214 + }; 215 215 + 216 216 + struct dccg_set_dto_dscclk_params { 217 217 + struct dccg *dccg; 218 218 + int inst; 219 219 + int num_slices_h; 220 220 + }; 221 221 + 222 222 + struct dsc_set_config_params { 223 223 + struct display_stream_compressor *dsc; 224 224 + struct dsc_config *dsc_cfg; 225 225 + struct dsc_optc_config *dsc_optc_cfg; 226 226 + }; 227 227 + 228 228 + struct dsc_enable_params { 229 229 + struct display_stream_compressor *dsc; 230 230 + int opp_inst; 231 231 + }; 232 232 + 233 233 + struct tg_set_dsc_config_params { 234 234 + struct timing_generator *tg; 235 235 + struct dsc_optc_config *dsc_optc_cfg; 236 236 + bool enable; 237 237 + }; 238 238 + 239 239 + struct dsc_disconnect_params { 240 240 + struct display_stream_compressor *dsc; 241 241 + }; 242 242 + 243 243 + struct dsc_read_state_params { 244 244 + struct display_stream_compressor *dsc; 245 245 + struct dcn_dsc_state *dsc_state; 246 246 + }; 247 247 + 248 248 + struct dsc_calculate_and_set_config_params { 249 249 + struct pipe_ctx *pipe_ctx; 250 250 + struct dsc_optc_config dsc_optc_cfg; 251 251 + bool enable; 252 252 + int opp_cnt; 253 253 + }; 254 254 + 255 255 + struct dsc_enable_with_opp_params { 256 256 + struct pipe_ctx *pipe_ctx; 257 257 + }; 258 258 + 259 259 + struct program_tg_params { 260 260 + struct dc *dc; 261 261 + struct pipe_ctx *pipe_ctx; 262 262 + struct dc_state *context; 263 263 + }; 264 264 + 265 265 + struct tg_program_global_sync_params { 266 266 + struct timing_generator *tg; 267 267 + int vready_offset; 268 268 + unsigned int vstartup_lines; 269 269 + unsigned int vupdate_offset_pixels; 270 270 + unsigned int vupdate_vupdate_width_pixels; 271 271 + unsigned int pstate_keepout_start_lines; 272 272 + }; 273 273 + 274 274 + struct tg_wait_for_state_params { 275 275 + struct timing_generator *tg; 276 276 + enum crtc_state state; 277 277 + }; 278 278 + 279 279 + struct tg_set_vtg_params_params { 280 280 + struct timing_generator *tg; 281 281 + struct dc_crtc_timing *timing; 282 282 + bool program_fp2; 283 283 + }; 284 284 + 285 285 + struct tg_set_gsl_params { 286 286 + struct timing_generator *tg; 287 287 + struct gsl_params gsl; 288 288 + }; 289 289 + 290 290 + struct tg_set_gsl_source_select_params { 291 291 + struct timing_generator *tg; 292 292 + int group_idx; 293 293 + uint32_t gsl_ready_signal; 294 294 + }; 295 295 + 296 296 + struct setup_vupdate_interrupt_params { 297 297 + struct dc *dc; 298 298 + struct pipe_ctx *pipe_ctx; 299 299 + }; 300 300 + 301 301 + struct tg_setup_vertical_interrupt2_params { 302 302 + struct timing_generator *tg; 303 303 + int start_line; 304 304 + }; 305 305 + 306 306 + struct dpp_set_hdr_multiplier_params { 307 307 + struct dpp *dpp; 308 308 + uint32_t hw_mult; 309 309 + }; 310 310 + 311 311 + struct program_det_size_params { 312 312 + struct hubbub *hubbub; 313 313 + unsigned int hubp_inst; 314 314 + unsigned int det_buffer_size_kb; 315 315 + }; 316 316 + 317 317 + struct program_det_segments_params { 318 318 + struct hubbub *hubbub; 319 319 + unsigned int hubp_inst; 320 320 + unsigned int det_size; 321 321 + }; 322 322 + 323 323 + struct update_dchubp_dpp_params { 324 324 + struct dc *dc; 325 325 + struct pipe_ctx *pipe_ctx; 326 326 + struct dc_state *context; 327 327 + }; 328 328 + 329 329 + struct opp_set_dyn_expansion_params { 330 330 + struct output_pixel_processor *opp; 331 331 + enum dc_color_space color_space; 332 332 + enum dc_color_depth color_depth; 333 333 + enum signal_type signal; 334 334 + }; 335 335 + 336 336 + struct opp_program_fmt_params { 337 337 + struct output_pixel_processor *opp; 338 338 + struct bit_depth_reduction_params *fmt_bit_depth; 339 339 + struct clamping_and_pixel_encoding_params *clamping; 340 340 + }; 341 341 + 342 342 + struct opp_program_bit_depth_reduction_params { 343 343 + struct output_pixel_processor *opp; 344 344 + bool use_default_params; 345 345 + struct pipe_ctx *pipe_ctx; 346 346 + }; 347 347 + 348 348 + struct opp_set_disp_pattern_generator_params { 349 349 + struct output_pixel_processor *opp; 350 350 + enum controller_dp_test_pattern test_pattern; 351 351 + enum controller_dp_color_space color_space; 352 352 + enum dc_color_depth color_depth; 353 353 + struct tg_color solid_color; 354 354 + bool use_solid_color; 355 355 + int width; 356 356 + int height; 357 357 + int offset; 358 358 + }; 359 359 + 360 360 + struct set_abm_pipe_params { 361 361 + struct dc *dc; 362 362 + struct pipe_ctx *pipe_ctx; 363 363 + }; 364 364 + 365 365 + struct set_abm_level_params { 366 366 + struct abm *abm; 367 367 + unsigned int abm_level; 368 368 + }; 369 369 + 370 370 + struct set_abm_immediate_disable_params { 371 371 + struct dc *dc; 372 372 + struct pipe_ctx *pipe_ctx; 373 373 + }; 374 374 + 375 375 + struct set_disp_pattern_generator_params { 376 376 + struct dc *dc; 377 377 + struct pipe_ctx *pipe_ctx; 378 378 + enum controller_dp_test_pattern test_pattern; 379 379 + enum controller_dp_color_space color_space; 380 380 + enum dc_color_depth color_depth; 381 381 + const struct tg_color *solid_color; 382 382 + int width; 383 383 + int height; 384 384 + int offset; 385 385 + }; 386 386 + 387 387 + struct mpc_update_blending_params { 388 388 + struct mpc *mpc; 389 389 + struct mpcc_blnd_cfg blnd_cfg; 390 390 + int mpcc_id; 391 391 + }; 392 392 + 393 393 + struct mpc_assert_idle_mpcc_params { 394 394 + struct mpc *mpc; 395 395 + int mpcc_id; 396 396 + }; 397 397 + 398 398 + struct mpc_insert_plane_params { 399 399 + struct mpc *mpc; 400 400 + struct mpc_tree *mpc_tree_params; 401 401 + struct mpcc_blnd_cfg blnd_cfg; 402 402 + struct mpcc_sm_cfg *sm_cfg; 403 403 + struct mpcc *insert_above_mpcc; 404 404 + int dpp_id; 405 405 + int mpcc_id; 406 406 + }; 407 407 + 408 408 + struct mpc_remove_mpcc_params { 409 409 + struct mpc *mpc; 410 410 + struct mpc_tree *mpc_tree_params; 411 411 + struct mpcc *mpcc_to_remove; 412 412 + }; 413 413 + 414 414 + struct opp_set_mpcc_disconnect_pending_params { 415 415 + struct output_pixel_processor *opp; 416 416 + int mpcc_inst; 417 417 + bool pending; 418 418 + }; 419 419 + 420 420 + struct dc_set_optimized_required_params { 421 421 + struct dc *dc; 422 422 + bool optimized_required; 423 423 + }; 424 424 + 425 425 + struct hubp_disconnect_params { 426 426 + struct hubp *hubp; 427 427 + }; 428 428 + 429 429 + struct hubbub_force_pstate_change_control_params { 430 430 + struct hubbub *hubbub; 431 431 + bool enable; 432 432 + bool wait; 433 433 + }; 434 434 + 435 435 + struct tg_enable_crtc_params { 436 436 + struct timing_generator *tg; 437 437 + }; 438 438 + 439 439 + struct hubp_wait_flip_pending_params { 440 440 + struct hubp *hubp; 441 441 + unsigned int timeout_us; 442 442 + unsigned int polling_interval_us; 443 443 + }; 444 444 + 445 445 + struct tg_wait_double_buffer_pending_params { 446 446 + struct timing_generator *tg; 447 447 + unsigned int timeout_us; 448 448 + unsigned int polling_interval_us; 449 449 + }; 450 450 + 451 451 + struct update_force_pstate_params { 452 452 + struct dc *dc; 453 453 + struct dc_state *context; 454 454 + }; 455 455 + 456 456 + struct hubbub_apply_dedcn21_147_wa_params { 457 457 + struct hubbub *hubbub; 458 458 + }; 459 459 + 460 460 + struct hubbub_allow_self_refresh_control_params { 461 461 + struct hubbub *hubbub; 462 462 + bool allow; 463 463 + bool *disallow_self_refresh_applied; 464 464 + }; 465 465 + 466 466 + struct tg_get_frame_count_params { 467 467 + struct timing_generator *tg; 468 468 + unsigned int *frame_count; 469 469 + }; 470 470 + 471 471 + struct mpc_set_dwb_mux_params { 472 472 + struct mpc *mpc; 473 473 + int dwb_id; 474 474 + int mpcc_id; 475 475 + }; 476 476 + 477 477 + struct mpc_disable_dwb_mux_params { 478 478 + struct mpc *mpc; 479 479 + unsigned int dwb_id; 480 480 + }; 481 481 + 482 482 + struct mcif_wb_config_buf_params { 483 483 + struct mcif_wb *mcif_wb; 484 484 + struct mcif_buf_params *mcif_buf_params; 485 485 + unsigned int dest_height; 486 486 + }; 487 487 + 488 488 + struct mcif_wb_config_arb_params { 489 489 + struct mcif_wb *mcif_wb; 490 490 + struct mcif_arb_params *mcif_arb_params; 491 491 + }; 492 492 + 493 493 + struct mcif_wb_enable_params { 494 494 + struct mcif_wb *mcif_wb; 495 495 + }; 496 496 + 497 497 + struct mcif_wb_disable_params { 498 498 + struct mcif_wb *mcif_wb; 499 499 + }; 500 500 + 501 501 + struct dwbc_enable_params { 502 502 + struct dwbc *dwb; 503 503 + struct dc_dwb_params *dwb_params; 504 504 + }; 505 505 + 506 506 + struct dwbc_disable_params { 507 507 + struct dwbc *dwb; 508 508 + }; 509 509 + 510 510 + struct dwbc_update_params { 511 511 + struct dwbc *dwb; 512 512 + struct dc_dwb_params *dwb_params; 513 513 + }; 514 514 + 515 515 + struct hubp_update_mall_sel_params { 516 516 + struct hubp *hubp; 517 517 + uint32_t mall_sel; 518 518 + bool cache_cursor; 519 519 + }; 520 520 + 521 521 + struct hubp_prepare_subvp_buffering_params { 522 522 + struct hubp *hubp; 523 523 + bool enable; 524 524 + }; 525 525 + 526 526 + struct hubp_set_blank_en_params { 527 527 + struct hubp *hubp; 528 528 + bool enable; 529 529 + }; 530 530 + 531 531 + struct hubp_disable_control_params { 532 532 + struct hubp *hubp; 533 533 + bool disable; 534 534 + }; 535 535 + 536 536 + struct hubbub_soft_reset_params { 537 537 + struct hubbub *hubbub; 538 538 + void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset); 539 539 + bool reset; 540 540 + }; 541 541 + 542 542 + struct hubp_clk_cntl_params { 543 543 + struct hubp *hubp; 544 544 + bool enable; 545 545 + }; 546 546 + 547 547 + struct hubp_init_params { 548 548 + struct hubp *hubp; 549 549 + }; 550 550 + 551 551 + struct hubp_set_vm_system_aperture_settings_params { 552 552 + struct hubp *hubp; 553 553 + //struct vm_system_aperture_param apt; 554 554 + PHYSICAL_ADDRESS_LOC sys_default; 555 555 + PHYSICAL_ADDRESS_LOC sys_low; 556 556 + PHYSICAL_ADDRESS_LOC sys_high; 557 557 + }; 558 558 + 559 559 + struct hubp_set_flip_int_params { 560 560 + struct hubp *hubp; 561 561 + }; 562 562 + 563 563 + struct dpp_dppclk_control_params { 564 564 + struct dpp *dpp; 565 565 + bool dppclk_div; 566 566 + bool enable; 567 567 + }; 568 568 + 569 569 + struct disable_phantom_crtc_params { 570 570 + struct timing_generator *tg; 571 571 + }; 572 572 + 573 573 + struct dpp_pg_control_params { 574 574 + struct dce_hwseq *hws; 575 575 + unsigned int dpp_inst; 576 576 + bool power_on; 577 577 + }; 578 578 + 579 579 + struct hubp_pg_control_params { 580 580 + struct dce_hwseq *hws; 581 581 + unsigned int hubp_inst; 582 582 + bool power_on; 583 583 + }; 584 584 + 585 585 + struct hubp_reset_params { 586 586 + struct hubp *hubp; 587 587 + }; 588 588 + 589 589 + struct dpp_reset_params { 590 590 + struct dpp *dpp; 591 591 + }; 592 592 + 593 593 + struct dpp_root_clock_control_params { 594 594 + struct dce_hwseq *hws; 595 595 + unsigned int dpp_inst; 596 596 + bool clock_on; 597 597 + }; 598 598 + 599 599 + struct dc_ip_request_cntl_params { 600 600 + struct dc *dc; 601 601 + bool enable; 602 602 + }; 603 603 + 604 604 + struct dsc_pg_status_params { 605 605 + struct dce_hwseq *hws; 606 606 + int dsc_inst; 607 607 + bool is_ungated; 608 608 + }; 609 609 + 610 610 + struct dsc_wait_disconnect_pending_clear_params { 611 611 + struct display_stream_compressor *dsc; 612 612 + bool *is_ungated; 613 613 + }; 614 614 + 615 615 + struct dsc_disable_params { 616 616 + struct display_stream_compressor *dsc; 617 617 + bool *is_ungated; 618 618 + }; 619 619 + 620 620 + struct dccg_set_ref_dscclk_params { 621 621 + struct dccg *dccg; 622 622 + int dsc_inst; 623 623 + bool *is_ungated; 624 624 + }; 625 625 + 626 626 + struct dccg_update_dpp_dto_params { 627 627 + struct dccg *dccg; 628 628 + int dpp_inst; 629 629 + int dppclk_khz; 630 630 + }; 631 631 + 632 632 + struct hubp_vtg_sel_params { 633 633 + struct hubp *hubp; 634 634 + uint32_t otg_inst; 635 635 + }; 636 636 + 637 637 + struct hubp_setup2_params { 638 638 + struct hubp *hubp; 639 639 + struct dml2_dchub_per_pipe_register_set *hubp_regs; 640 640 + union dml2_global_sync_programming *global_sync; 641 641 + struct dc_crtc_timing *timing; 642 642 + }; 643 643 + 644 644 + struct hubp_setup_params { 645 645 + struct hubp *hubp; 646 646 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 647 647 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 648 648 + struct _vcs_dpi_display_rq_regs_st *rq_regs; 649 649 + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest; 650 650 + }; 651 651 + 652 652 + struct hubp_set_unbounded_requesting_params { 653 653 + struct hubp *hubp; 654 654 + bool unbounded_req; 655 655 + }; 656 656 + 657 657 + struct hubp_setup_interdependent2_params { 658 658 + struct hubp *hubp; 659 659 + struct dml2_dchub_per_pipe_register_set *hubp_regs; 660 660 + }; 661 661 + 662 662 + struct hubp_setup_interdependent_params { 663 663 + struct hubp *hubp; 664 664 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 665 665 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 666 666 + }; 667 667 + 668 668 + struct dpp_set_cursor_matrix_params { 669 669 + struct dpp *dpp; 670 670 + enum dc_color_space color_space; 671 671 + struct dc_csc_transform *cursor_csc_color_matrix; 672 672 + }; 673 673 + 674 674 + struct mpc_update_mpcc_params { 675 675 + struct dc *dc; 676 676 + struct pipe_ctx *pipe_ctx; 677 677 + }; 678 678 + 679 679 + struct dpp_set_scaler_params { 680 680 + struct dpp *dpp; 681 681 + const struct scaler_data *scl_data; 682 682 + }; 683 683 + 684 684 + struct hubp_mem_program_viewport_params { 685 685 + struct hubp *hubp; 686 686 + const struct rect *viewport; 687 687 + const struct rect *viewport_c; 688 688 + }; 689 689 + 690 690 + struct hubp_program_mcache_id_and_split_coordinate_params { 691 691 + struct hubp *hubp; 692 692 + struct mcache_regs_struct *mcache_regs; 693 693 + }; 694 694 + 695 695 + struct set_cursor_attribute_params { 696 696 + struct dc *dc; 697 697 + struct pipe_ctx *pipe_ctx; 698 698 + }; 699 699 + 700 700 + struct set_cursor_position_params { 701 701 + struct dc *dc; 702 702 + struct pipe_ctx *pipe_ctx; 703 703 + }; 704 704 + 705 705 + struct set_cursor_sdr_white_level_params { 706 706 + struct dc *dc; 707 707 + struct pipe_ctx *pipe_ctx; 708 708 + }; 709 709 + 710 710 + struct program_output_csc_params { 711 711 + struct dc *dc; 712 712 + struct pipe_ctx *pipe_ctx; 713 713 + enum dc_color_space colorspace; 714 714 + uint16_t *matrix; 715 715 + int opp_id; 716 716 + }; 717 717 + 718 718 + struct hubp_set_blank_params { 719 719 + struct hubp *hubp; 720 720 + bool blank; 721 721 + }; 722 722 + 723 723 + struct phantom_hubp_post_enable_params { 724 724 + struct hubp *hubp; 164 725 }; 165 726 166 727 union block_sequence_params { ··· 748 179 struct subvp_save_surf_addr subvp_save_surf_addr; 749 180 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 750 181 struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; 182 182 + struct program_surface_config_params program_surface_config_params; 183 183 + struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate; 751 184 struct program_cursor_update_now_params program_cursor_update_now_params; 185 185 + struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params; 186 186 + struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params; 187 187 + struct update_phantom_vp_position_params update_phantom_vp_position_params; 188 188 + struct set_odm_combine_params set_odm_combine_params; 189 189 + struct set_odm_bypass_params set_odm_bypass_params; 190 190 + struct opp_pipe_clock_control_params opp_pipe_clock_control_params; 191 191 + struct opp_program_left_edge_extra_pixel_params opp_program_left_edge_extra_pixel_params; 192 192 + struct dccg_set_dto_dscclk_params dccg_set_dto_dscclk_params; 193 193 + struct dsc_set_config_params dsc_set_config_params; 194 194 + struct dsc_enable_params dsc_enable_params; 195 195 + struct tg_set_dsc_config_params tg_set_dsc_config_params; 196 196 + struct dsc_disconnect_params dsc_disconnect_params; 197 197 + struct dsc_read_state_params dsc_read_state_params; 198 198 + struct dsc_calculate_and_set_config_params dsc_calculate_and_set_config_params; 199 199 + struct dsc_enable_with_opp_params dsc_enable_with_opp_params; 200 200 + struct program_tg_params program_tg_params; 201 201 + struct tg_program_global_sync_params tg_program_global_sync_params; 202 202 + struct tg_wait_for_state_params tg_wait_for_state_params; 203 203 + struct tg_set_vtg_params_params tg_set_vtg_params_params; 204 204 + struct tg_setup_vertical_interrupt2_params tg_setup_vertical_interrupt2_params; 205 205 + struct dpp_set_hdr_multiplier_params dpp_set_hdr_multiplier_params; 206 206 + struct tg_set_gsl_params tg_set_gsl_params; 207 207 + struct tg_set_gsl_source_select_params tg_set_gsl_source_select_params; 208 208 + struct setup_vupdate_interrupt_params setup_vupdate_interrupt_params; 209 209 + struct program_det_size_params program_det_size_params; 210 210 + struct program_det_segments_params program_det_segments_params; 211 211 + struct update_dchubp_dpp_params update_dchubp_dpp_params; 212 212 + struct opp_set_dyn_expansion_params opp_set_dyn_expansion_params; 213 213 + struct opp_program_fmt_params opp_program_fmt_params; 214 214 + struct opp_program_bit_depth_reduction_params opp_program_bit_depth_reduction_params; 215 215 + struct opp_set_disp_pattern_generator_params opp_set_disp_pattern_generator_params; 216 216 + struct set_abm_pipe_params set_abm_pipe_params; 217 217 + struct set_abm_level_params set_abm_level_params; 218 218 + struct set_abm_immediate_disable_params set_abm_immediate_disable_params; 219 219 + struct set_disp_pattern_generator_params set_disp_pattern_generator_params; 220 220 + struct mpc_remove_mpcc_params mpc_remove_mpcc_params; 221 221 + struct opp_set_mpcc_disconnect_pending_params opp_set_mpcc_disconnect_pending_params; 222 222 + struct dc_set_optimized_required_params dc_set_optimized_required_params; 223 223 + struct hubp_disconnect_params hubp_disconnect_params; 224 224 + struct hubbub_force_pstate_change_control_params hubbub_force_pstate_change_control_params; 225 225 + struct tg_enable_crtc_params tg_enable_crtc_params; 226 226 + struct hubp_wait_flip_pending_params hubp_wait_flip_pending_params; 227 227 + struct tg_wait_double_buffer_pending_params tg_wait_double_buffer_pending_params; 228 228 + struct update_force_pstate_params update_force_pstate_params; 229 229 + struct hubbub_apply_dedcn21_147_wa_params hubbub_apply_dedcn21_147_wa_params; 230 230 + struct hubbub_allow_self_refresh_control_params hubbub_allow_self_refresh_control_params; 231 231 + struct tg_get_frame_count_params tg_get_frame_count_params; 232 232 + struct mpc_set_dwb_mux_params mpc_set_dwb_mux_params; 233 233 + struct mpc_disable_dwb_mux_params mpc_disable_dwb_mux_params; 234 234 + struct mcif_wb_config_buf_params mcif_wb_config_buf_params; 235 235 + struct mcif_wb_config_arb_params mcif_wb_config_arb_params; 236 236 + struct mcif_wb_enable_params mcif_wb_enable_params; 237 237 + struct mcif_wb_disable_params mcif_wb_disable_params; 238 238 + struct dwbc_enable_params dwbc_enable_params; 239 239 + struct dwbc_disable_params dwbc_disable_params; 240 240 + struct dwbc_update_params dwbc_update_params; 241 241 + struct hubp_update_mall_sel_params hubp_update_mall_sel_params; 242 242 + struct hubp_prepare_subvp_buffering_params hubp_prepare_subvp_buffering_params; 243 243 + struct hubp_set_blank_en_params hubp_set_blank_en_params; 244 244 + struct hubp_disable_control_params hubp_disable_control_params; 245 245 + struct hubbub_soft_reset_params hubbub_soft_reset_params; 246 246 + struct hubp_clk_cntl_params hubp_clk_cntl_params; 247 247 + struct hubp_init_params hubp_init_params; 248 248 + struct hubp_set_vm_system_aperture_settings_params hubp_set_vm_system_aperture_settings_params; 249 249 + struct hubp_set_flip_int_params hubp_set_flip_int_params; 250 250 + struct dpp_dppclk_control_params dpp_dppclk_control_params; 251 251 + struct disable_phantom_crtc_params disable_phantom_crtc_params; 252 252 + struct dpp_pg_control_params dpp_pg_control_params; 253 253 + struct hubp_pg_control_params hubp_pg_control_params; 254 254 + struct hubp_reset_params hubp_reset_params; 255 255 + struct dpp_reset_params dpp_reset_params; 256 256 + struct dpp_root_clock_control_params dpp_root_clock_control_params; 257 257 + struct dc_ip_request_cntl_params dc_ip_request_cntl_params; 258 258 + struct dsc_pg_status_params dsc_pg_status_params; 259 259 + struct dsc_wait_disconnect_pending_clear_params dsc_wait_disconnect_pending_clear_params; 260 260 + struct dsc_disable_params dsc_disable_params; 261 261 + struct dccg_set_ref_dscclk_params dccg_set_ref_dscclk_params; 262 262 + struct dccg_update_dpp_dto_params dccg_update_dpp_dto_params; 263 263 + struct hubp_vtg_sel_params hubp_vtg_sel_params; 264 264 + struct hubp_setup2_params hubp_setup2_params; 265 265 + struct hubp_setup_params hubp_setup_params; 266 266 + struct hubp_set_unbounded_requesting_params hubp_set_unbounded_requesting_params; 267 267 + struct hubp_setup_interdependent2_params hubp_setup_interdependent2_params; 268 268 + struct hubp_setup_interdependent_params hubp_setup_interdependent_params; 269 269 + struct dpp_set_cursor_matrix_params dpp_set_cursor_matrix_params; 270 270 + struct mpc_update_mpcc_params mpc_update_mpcc_params; 271 271 + struct mpc_update_blending_params mpc_update_blending_params; 272 272 + struct mpc_assert_idle_mpcc_params mpc_assert_idle_mpcc_params; 273 273 + struct mpc_insert_plane_params mpc_insert_plane_params; 274 274 + struct dpp_set_scaler_params dpp_set_scaler_params; 275 275 + struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params; 276 276 + struct set_cursor_attribute_params set_cursor_attribute_params; 277 277 + struct set_cursor_position_params set_cursor_position_params; 278 278 + struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params; 279 279 + struct program_output_csc_params program_output_csc_params; 280 280 + struct hubp_set_blank_params hubp_set_blank_params; 281 281 + struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params; 752 282 }; 753 283 754 284 enum block_sequence_func { ··· 863 195 DPP_SETUP_DPP, 864 196 DPP_PROGRAM_BIAS_AND_SCALE, 865 197 DPP_SET_OUTPUT_TRANSFER_FUNC, 198 198 + DPP_SET_HDR_MULTIPLIER, 866 199 MPC_UPDATE_VISUAL_CONFIRM, 867 200 MPC_POWER_ON_MPC_MEM_PWR, 868 201 MPC_SET_OUTPUT_CSC, ··· 871 202 DMUB_SUBVP_SAVE_SURF_ADDR, 872 203 HUBP_WAIT_FOR_DCC_META_PROP, 873 204 DMUB_HW_CONTROL_LOCK_FAST, 205 205 + HUBP_PROGRAM_SURFACE_CONFIG, 206 206 + HUBP_PROGRAM_MCACHE_ID, 874 207 PROGRAM_CURSOR_UPDATE_NOW, 208 208 + HUBP_WAIT_PIPE_READ_START, 209 209 + HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM, 210 210 + HWS_UPDATE_PHANTOM_VP_POSITION, 211 211 + OPTC_SET_ODM_COMBINE, 212 212 + OPTC_SET_ODM_BYPASS, 213 213 + OPP_PIPE_CLOCK_CONTROL, 214 214 + OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL, 215 215 + DCCG_SET_DTO_DSCCLK, 216 216 + DSC_SET_CONFIG, 217 217 + DSC_ENABLE, 218 218 + TG_SET_DSC_CONFIG, 219 219 + DSC_DISCONNECT, 220 220 + DSC_READ_STATE, 221 221 + DSC_CALCULATE_AND_SET_CONFIG, 222 222 + DSC_ENABLE_WITH_OPP, 223 223 + TG_PROGRAM_GLOBAL_SYNC, 224 224 + TG_WAIT_FOR_STATE, 225 225 + TG_SET_VTG_PARAMS, 226 226 + TG_SETUP_VERTICAL_INTERRUPT2, 227 227 + HUBP_PROGRAM_DET_SIZE, 228 228 + HUBP_PROGRAM_DET_SEGMENTS, 229 229 + OPP_SET_DYN_EXPANSION, 230 230 + OPP_PROGRAM_FMT, 231 231 + OPP_PROGRAM_BIT_DEPTH_REDUCTION, 232 232 + OPP_SET_DISP_PATTERN_GENERATOR, 233 233 + ABM_SET_PIPE, 234 234 + ABM_SET_LEVEL, 235 235 + ABM_SET_IMMEDIATE_DISABLE, 236 236 + MPC_REMOVE_MPCC, 237 237 + OPP_SET_MPCC_DISCONNECT_PENDING, 238 238 + DC_SET_OPTIMIZED_REQUIRED, 239 239 + HUBP_DISCONNECT, 240 240 + HUBBUB_FORCE_PSTATE_CHANGE_CONTROL, 241 241 + TG_ENABLE_CRTC, 242 242 + TG_SET_GSL, 243 243 + TG_SET_GSL_SOURCE_SELECT, 244 244 + HUBP_WAIT_FLIP_PENDING, 245 245 + TG_WAIT_DOUBLE_BUFFER_PENDING, 246 246 + UPDATE_FORCE_PSTATE, 247 247 + PROGRAM_MALL_PIPE_CONFIG, 248 248 + HUBBUB_APPLY_DEDCN21_147_WA, 249 249 + HUBBUB_ALLOW_SELF_REFRESH_CONTROL, 250 250 + TG_GET_FRAME_COUNT, 251 251 + MPC_SET_DWB_MUX, 252 252 + MPC_DISABLE_DWB_MUX, 253 253 + MCIF_WB_CONFIG_BUF, 254 254 + MCIF_WB_CONFIG_ARB, 255 255 + MCIF_WB_ENABLE, 256 256 + MCIF_WB_DISABLE, 257 257 + DWBC_ENABLE, 258 258 + DWBC_DISABLE, 259 259 + DWBC_UPDATE, 260 260 + HUBP_UPDATE_MALL_SEL, 261 261 + HUBP_PREPARE_SUBVP_BUFFERING, 262 262 + HUBP_SET_BLANK_EN, 263 263 + HUBP_DISABLE_CONTROL, 264 264 + HUBBUB_SOFT_RESET, 265 265 + HUBP_CLK_CNTL, 266 266 + HUBP_INIT, 267 267 + HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS, 268 268 + HUBP_SET_FLIP_INT, 269 269 + DPP_DPPCLK_CONTROL, 270 270 + DISABLE_PHANTOM_CRTC, 271 271 + DSC_PG_STATUS, 272 272 + DSC_WAIT_DISCONNECT_PENDING_CLEAR, 273 273 + DSC_DISABLE, 274 274 + DCCG_SET_REF_DSCCLK, 275 275 + DPP_PG_CONTROL, 276 276 + HUBP_PG_CONTROL, 277 277 + HUBP_RESET, 278 278 + DPP_RESET, 279 279 + DPP_ROOT_CLOCK_CONTROL, 280 280 + DC_IP_REQUEST_CNTL, 281 281 + DCCG_UPDATE_DPP_DTO, 282 282 + HUBP_VTG_SEL, 283 283 + HUBP_SETUP2, 284 284 + HUBP_SETUP, 285 285 + HUBP_SET_UNBOUNDED_REQUESTING, 286 286 + HUBP_SETUP_INTERDEPENDENT2, 287 287 + HUBP_SETUP_INTERDEPENDENT, 288 288 + DPP_SET_CURSOR_MATRIX, 289 289 + MPC_UPDATE_BLENDING, 290 290 + MPC_ASSERT_IDLE_MPCC, 291 291 + MPC_INSERT_PLANE, 292 292 + DPP_SET_SCALER, 293 293 + HUBP_MEM_PROGRAM_VIEWPORT, 294 294 + SET_CURSOR_ATTRIBUTE, 295 295 + SET_CURSOR_POSITION, 296 296 + SET_CURSOR_SDR_WHITE_LEVEL, 297 297 + PROGRAM_OUTPUT_CSC, 298 298 + HUBP_SET_LEGACY_TILING_COMPAT_LEVEL, 299 299 + HUBP_SET_BLANK, 300 300 + PHANTOM_HUBP_POST_ENABLE, 875 301 /* This must be the last value in this enum, add new ones above */ 876 302 HWSS_BLOCK_SEQUENCE_FUNC_COUNT 877 303 }; ··· 974 210 struct block_sequence { 975 211 union block_sequence_params params; 976 212 enum block_sequence_func func; 213 213 + }; 214 214 + 215 215 + struct block_sequence_state { 216 216 + struct block_sequence *steps; 217 217 + unsigned int *num_steps; 977 218 }; 978 219 979 220 #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) ··· 998 229 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 999 230 struct dc_state *context); 1000 231 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 232 232 + void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx, 233 233 + struct block_sequence_state *seq_state); 1001 234 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 1002 235 void (*apply_ctx_for_surface)(struct dc *dc, 1003 236 const struct dc_stream_state *stream, ··· 1017 246 void (*wait_for_mpcc_disconnect)(struct dc *dc, 1018 247 struct resource_pool *res_pool, 1019 248 struct pipe_ctx *pipe_ctx); 249 249 + void (*wait_for_mpcc_disconnect_sequence)(struct dc *dc, 250 250 + struct resource_pool *res_pool, 251 251 + struct pipe_ctx *pipe_ctx, 252 252 + struct block_sequence_state *seq_state); 1020 253 void (*edp_backlight_control)( 1021 254 struct dc_link *link, 1022 255 bool enable); ··· 1260 485 void (*enable_plane)(struct dc *dc, 1261 486 struct pipe_ctx *pipe_ctx, 1262 487 struct dc_state *context); 488 488 + void (*enable_plane_sequence)(struct dc *dc, 489 489 + struct pipe_ctx *pipe_ctx, 490 490 + struct dc_state *context, 491 491 + struct block_sequence_state *seq_state); 1263 492 void (*update_dchubp_dpp)(struct dc *dc, 1264 493 struct pipe_ctx *pipe_ctx, 1265 494 struct dc_state *context); 495 495 + void (*update_dchubp_dpp_sequence)(struct dc *dc, 496 496 + struct pipe_ctx *pipe_ctx, 497 497 + struct dc_state *context, 498 498 + struct block_sequence_state *seq_state); 1266 499 void (*post_unlock_reset_opp)(struct dc *dc, 1267 500 struct pipe_ctx *opp_head); 501 501 + void (*post_unlock_reset_opp_sequence)( 502 502 + struct dc *dc, 503 503 + struct pipe_ctx *opp_head, 504 504 + struct block_sequence_state *seq_state); 1268 505 void (*get_underflow_debug_data)(const struct dc *dc, 1269 506 struct timing_generator *tg, 1270 507 struct dc_underflow_debug_data *out_data); ··· 1388 601 void hwss_set_ocsc_default(union block_sequence_params *params); 1389 602 1390 603 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 604 604 + 605 605 + void hwss_program_surface_config(union block_sequence_params *params); 606 606 + 607 607 + void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params); 608 608 + 609 609 + void hwss_set_odm_combine(union block_sequence_params *params); 610 610 + 611 611 + void hwss_set_odm_bypass(union block_sequence_params *params); 612 612 + 613 613 + void hwss_opp_pipe_clock_control(union block_sequence_params *params); 614 614 + 615 615 + void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params); 616 616 + 617 617 + void hwss_blank_pixel_data(union block_sequence_params *params); 618 618 + 619 619 + void hwss_dccg_set_dto_dscclk(union block_sequence_params *params); 620 620 + 621 621 + void hwss_dsc_set_config(union block_sequence_params *params); 622 622 + 623 623 + void hwss_dsc_enable(union block_sequence_params *params); 624 624 + 625 625 + void hwss_tg_set_dsc_config(union block_sequence_params *params); 626 626 + 627 627 + void hwss_dsc_disconnect(union block_sequence_params *params); 628 628 + 629 629 + void hwss_dsc_read_state(union block_sequence_params *params); 630 630 + 631 631 + void hwss_dsc_calculate_and_set_config(union block_sequence_params *params); 632 632 + 633 633 + void hwss_dsc_enable_with_opp(union block_sequence_params *params); 634 634 + 635 635 + void hwss_program_tg(union block_sequence_params *params); 636 636 + 637 637 + void hwss_tg_program_global_sync(union block_sequence_params *params); 638 638 + 639 639 + void hwss_tg_wait_for_state(union block_sequence_params *params); 640 640 + 641 641 + void hwss_tg_set_vtg_params(union block_sequence_params *params); 642 642 + 643 643 + void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params); 644 644 + 645 645 + void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params); 646 646 + 647 647 + void hwss_program_det_size(union block_sequence_params *params); 648 648 + 649 649 + void hwss_program_det_segments(union block_sequence_params *params); 650 650 + 651 651 + void hwss_opp_set_dyn_expansion(union block_sequence_params *params); 652 652 + 653 653 + void hwss_opp_program_fmt(union block_sequence_params *params); 654 654 + 655 655 + void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params); 656 656 + 657 657 + void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params); 658 658 + 659 659 + void hwss_set_abm_pipe(union block_sequence_params *params); 660 660 + 661 661 + void hwss_set_abm_level(union block_sequence_params *params); 662 662 + 663 663 + void hwss_set_abm_immediate_disable(union block_sequence_params *params); 664 664 + 665 665 + void hwss_mpc_remove_mpcc(union block_sequence_params *params); 666 666 + 667 667 + void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params); 668 668 + 669 669 + void hwss_dc_set_optimized_required(union block_sequence_params *params); 670 670 + 671 671 + void hwss_hubp_disconnect(union block_sequence_params *params); 672 672 + 673 673 + void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params); 674 674 + 675 675 + void hwss_tg_enable_crtc(union block_sequence_params *params); 676 676 + 677 677 + void hwss_tg_set_gsl(union block_sequence_params *params); 678 678 + 679 679 + void hwss_tg_set_gsl_source_select(union block_sequence_params *params); 680 680 + 681 681 + void hwss_hubp_wait_flip_pending(union block_sequence_params *params); 682 682 + 683 683 + void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params); 684 684 + 685 685 + void hwss_update_force_pstate(union block_sequence_params *params); 686 686 + 687 687 + void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params); 688 688 + 689 689 + void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params); 690 690 + 691 691 + void hwss_tg_get_frame_count(union block_sequence_params *params); 692 692 + 693 693 + void hwss_mpc_set_dwb_mux(union block_sequence_params *params); 694 694 + 695 695 + void hwss_mpc_disable_dwb_mux(union block_sequence_params *params); 696 696 + 697 697 + void hwss_mcif_wb_config_buf(union block_sequence_params *params); 698 698 + 699 699 + void hwss_mcif_wb_config_arb(union block_sequence_params *params); 700 700 + 701 701 + void hwss_mcif_wb_enable(union block_sequence_params *params); 702 702 + 703 703 + void hwss_mcif_wb_disable(union block_sequence_params *params); 704 704 + 705 705 + void hwss_dwbc_enable(union block_sequence_params *params); 706 706 + 707 707 + void hwss_dwbc_disable(union block_sequence_params *params); 708 708 + 709 709 + void hwss_dwbc_update(union block_sequence_params *params); 710 710 + 711 711 + void hwss_hubp_update_mall_sel(union block_sequence_params *params); 712 712 + 713 713 + void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params); 714 714 + 715 715 + void hwss_hubp_set_blank_en(union block_sequence_params *params); 716 716 + 717 717 + void hwss_hubp_disable_control(union block_sequence_params *params); 718 718 + 719 719 + void hwss_hubbub_soft_reset(union block_sequence_params *params); 720 720 + 721 721 + void hwss_hubp_clk_cntl(union block_sequence_params *params); 722 722 + 723 723 + void hwss_hubp_init(union block_sequence_params *params); 724 724 + 725 725 + void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params); 726 726 + 727 727 + void hwss_hubp_set_flip_int(union block_sequence_params *params); 728 728 + 729 729 + void hwss_dpp_dppclk_control(union block_sequence_params *params); 730 730 + 731 731 + void hwss_disable_phantom_crtc(union block_sequence_params *params); 732 732 + 733 733 + void hwss_dsc_pg_status(union block_sequence_params *params); 734 734 + 735 735 + void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params); 736 736 + 737 737 + void hwss_dsc_disable(union block_sequence_params *params); 738 738 + 739 739 + void hwss_dccg_set_ref_dscclk(union block_sequence_params *params); 740 740 + 741 741 + void hwss_dpp_pg_control(union block_sequence_params *params); 742 742 + 743 743 + void hwss_hubp_pg_control(union block_sequence_params *params); 744 744 + 745 745 + void hwss_hubp_reset(union block_sequence_params *params); 746 746 + 747 747 + void hwss_dpp_reset(union block_sequence_params *params); 748 748 + 749 749 + void hwss_dpp_root_clock_control(union block_sequence_params *params); 750 750 + 751 751 + void hwss_dc_ip_request_cntl(union block_sequence_params *params); 752 752 + 753 753 + void hwss_dccg_update_dpp_dto(union block_sequence_params *params); 754 754 + 755 755 + void hwss_hubp_vtg_sel(union block_sequence_params *params); 756 756 + 757 757 + void hwss_hubp_setup2(union block_sequence_params *params); 758 758 + 759 759 + void hwss_hubp_setup(union block_sequence_params *params); 760 760 + 761 761 + void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params); 762 762 + 763 763 + void hwss_hubp_setup_interdependent2(union block_sequence_params *params); 764 764 + 765 765 + void hwss_hubp_setup_interdependent(union block_sequence_params *params); 766 766 + 767 767 + void hwss_dpp_set_cursor_matrix(union block_sequence_params *params); 768 768 + 769 769 + void hwss_mpc_update_mpcc(union block_sequence_params *params); 770 770 + 771 771 + void hwss_mpc_update_blending(union block_sequence_params *params); 772 772 + 773 773 + void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params); 774 774 + 775 775 + void hwss_mpc_insert_plane(union block_sequence_params *params); 776 776 + 777 777 + void hwss_dpp_set_scaler(union block_sequence_params *params); 778 778 + 779 779 + void hwss_hubp_mem_program_viewport(union block_sequence_params *params); 780 780 + 781 781 + void hwss_set_cursor_attribute(union block_sequence_params *params); 782 782 + 783 783 + void hwss_set_cursor_position(union block_sequence_params *params); 784 784 + 785 785 + void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); 786 786 + 787 787 + void hwss_program_output_csc(union block_sequence_params *params); 788 788 + 789 789 + void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params); 790 790 + 791 791 + void hwss_hubp_set_blank(union block_sequence_params *params); 792 792 + 793 793 + void hwss_phantom_hubp_post_enable(union block_sequence_params *params); 794 794 + 795 795 + void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, 796 796 + struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); 797 797 + 798 798 + void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, 799 799 + struct hubp *hubp, bool flip_immediate); 800 800 + 801 801 + void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, 802 802 + struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 803 803 + 804 804 + void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, 805 805 + struct dc *dc, struct pipe_ctx *pipe_ctx); 806 806 + 807 807 + void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, 808 808 + struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state); 809 809 + 810 810 + void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, 811 811 + struct pipe_ctx *pipe_ctx); 812 812 + 813 813 + void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, 814 814 + struct pipe_ctx *pipe_ctx); 815 815 + 816 816 + void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, 817 817 + struct pipe_ctx *pipe_ctx); 818 818 + 819 819 + void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, 820 820 + struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream); 821 821 + 822 822 + void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, 823 823 + struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id); 824 824 + 825 825 + void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, 826 826 + struct mpc *mpc, int mpcc_id, bool power_on); 827 827 + 828 828 + void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, 829 829 + struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); 830 830 + 831 831 + void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, 832 832 + struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode); 833 833 + 834 834 + void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, 835 835 + struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 836 836 + 837 837 + void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, 838 838 + struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index); 839 839 + 840 840 + void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, 841 841 + struct dc *dc, struct pipe_ctx *top_pipe_to_program); 842 842 + 843 843 + void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, 844 844 + struct hubp *hubp); 845 845 + 846 846 + void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, 847 847 + struct pipe_ctx *pipe_ctx); 848 848 + 849 849 + void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, 850 850 + struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 851 851 + 852 852 + void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, 853 853 + struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, 854 854 + int odm_slice_width, int last_odm_slice_width); 855 855 + 856 856 + void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, 857 857 + struct timing_generator *optc, struct dc_crtc_timing *timing); 858 858 + 859 859 + void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, 860 860 + struct timing_generator *tg, 861 861 + int vready_offset, 862 862 + unsigned int vstartup_lines, 863 863 + unsigned int vupdate_offset_pixels, 864 864 + unsigned int vupdate_vupdate_width_pixels, 865 865 + unsigned int pstate_keepout_start_lines); 866 866 + 867 867 + void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, 868 868 + struct timing_generator *tg, enum crtc_state state); 869 869 + 870 870 + void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, 871 871 + struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 872 872 + 873 873 + void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, 874 874 + struct timing_generator *tg, int start_line); 875 875 + 876 876 + void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, 877 877 + struct dpp *dpp, uint32_t hw_mult); 878 878 + 879 879 + void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, 880 880 + struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_buffer_size_kb); 881 881 + 882 882 + void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, 883 883 + struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); 884 884 + 885 885 + void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, 886 886 + struct hubbub *hubbub, bool enable, bool wait); 887 887 + 888 888 + void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, 889 889 + struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_size); 890 890 + 891 891 + void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, 892 892 + struct output_pixel_processor *opp, enum dc_color_space color_sp, 893 893 + enum dc_color_depth color_dpth, enum signal_type signal); 894 894 + 895 895 + void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, 896 896 + struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, 897 897 + struct clamping_and_pixel_encoding_params *clamping); 898 898 + 899 899 + void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, 900 900 + struct dc *dc, struct pipe_ctx *pipe_ctx); 901 901 + 902 902 + void hwss_add_abm_set_level(struct block_sequence_state *seq_state, 903 903 + struct abm *abm, uint32_t abm_level); 904 904 + 905 905 + void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, 906 906 + struct timing_generator *tg); 907 907 + 908 908 + void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, 909 909 + struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us); 910 910 + 911 911 + void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, 912 912 + struct timing_generator *tg, unsigned int timeout_us, unsigned int polling_interval_us); 913 913 + 914 914 + void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, 915 915 + struct dccg *dccg, int inst, int num_slices_h); 916 916 + 917 917 + void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, 918 918 + struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt); 919 919 + 920 920 + void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, 921 921 + struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove); 922 922 + 923 923 + void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, 924 924 + struct output_pixel_processor *opp, int mpcc_inst, bool pending); 925 925 + 926 926 + void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, 927 927 + struct hubp *hubp); 928 928 + 929 929 + void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, 930 930 + struct pipe_ctx *pipe_ctx); 931 931 + 932 932 + void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, 933 933 + struct display_stream_compressor *dsc); 934 934 + 935 935 + void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, 936 936 + struct dc *dc, bool optimized_required); 937 937 + 938 938 + void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, 939 939 + struct dc *dc, struct pipe_ctx *pipe_ctx); 940 940 + 941 941 + void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, 942 942 + struct output_pixel_processor *opp, 943 943 + enum controller_dp_test_pattern test_pattern, 944 944 + enum controller_dp_color_space color_space, 945 945 + enum dc_color_depth color_depth, 946 946 + struct tg_color solid_color, 947 947 + bool use_solid_color, 948 948 + int width, 949 949 + int height, 950 950 + int offset); 951 951 + 952 952 + void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, 953 953 + struct output_pixel_processor *opp, 954 954 + bool use_default_params, 955 955 + struct pipe_ctx *pipe_ctx); 956 956 + 957 957 + void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, 958 958 + struct dc *dc, 959 959 + bool enable); 960 960 + 961 961 + void hwss_add_dwbc_update(struct block_sequence_state *seq_state, 962 962 + struct dwbc *dwb, 963 963 + struct dc_dwb_params *dwb_params); 964 964 + 965 965 + void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, 966 966 + struct mcif_wb *mcif_wb, 967 967 + struct mcif_buf_params *mcif_buf_params, 968 968 + unsigned int dest_height); 969 969 + 970 970 + void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, 971 971 + struct mcif_wb *mcif_wb, 972 972 + struct mcif_arb_params *mcif_arb_params); 973 973 + 974 974 + void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, 975 975 + struct mcif_wb *mcif_wb); 976 976 + 977 977 + void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, 978 978 + struct mcif_wb *mcif_wb); 979 979 + 980 980 + void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, 981 981 + struct mpc *mpc, 982 982 + int dwb_id, 983 983 + int mpcc_id); 984 984 + 985 985 + void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, 986 986 + struct mpc *mpc, 987 987 + unsigned int dwb_id); 988 988 + 989 989 + void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, 990 990 + struct dwbc *dwb, 991 991 + struct dc_dwb_params *dwb_params); 992 992 + 993 993 + void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, 994 994 + struct dwbc *dwb); 995 995 + 996 996 + void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, 997 997 + struct timing_generator *tg, 998 998 + struct gsl_params gsl); 999 999 + 1000 1000 + void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, 1001 1001 + struct timing_generator *tg, 1002 1002 + int group_idx, 1003 1003 + uint32_t gsl_ready_signal); 1004 1004 + 1005 1005 + void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, 1006 1006 + struct hubp *hubp, 1007 1007 + uint32_t mall_sel, 1008 1008 + bool cache_cursor); 1009 1009 + 1010 1010 + void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, 1011 1011 + struct hubp *hubp, 1012 1012 + bool enable); 1013 1013 + 1014 1014 + void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, 1015 1015 + struct hubp *hubp, 1016 1016 + bool enable); 1017 1017 + 1018 1018 + void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, 1019 1019 + struct hubp *hubp, 1020 1020 + bool disable); 1021 1021 + 1022 1022 + void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, 1023 1023 + struct hubbub *hubbub, 1024 1024 + void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), 1025 1025 + bool reset); 1026 1026 + 1027 1027 + void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, 1028 1028 + struct hubp *hubp, 1029 1029 + bool enable); 1030 1030 + 1031 1031 + void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, 1032 1032 + struct dpp *dpp, 1033 1033 + bool dppclk_div, 1034 1034 + bool enable); 1035 1035 + 1036 1036 + void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, 1037 1037 + struct timing_generator *tg); 1038 1038 + 1039 1039 + void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, 1040 1040 + struct dce_hwseq *hws, 1041 1041 + int dsc_inst, 1042 1042 + bool is_ungated); 1043 1043 + 1044 1044 + void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, 1045 1045 + struct display_stream_compressor *dsc, 1046 1046 + bool *is_ungated); 1047 1047 + 1048 1048 + void hwss_add_dsc_disable(struct block_sequence_state *seq_state, 1049 1049 + struct display_stream_compressor *dsc, 1050 1050 + bool *is_ungated); 1051 1051 + 1052 1052 + void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, 1053 1053 + struct dccg *dccg, 1054 1054 + int dsc_inst, 1055 1055 + bool *is_ungated); 1056 1056 + 1057 1057 + void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, 1058 1058 + struct dce_hwseq *hws, 1059 1059 + unsigned int dpp_inst, 1060 1060 + bool clock_on); 1061 1061 + 1062 1062 + void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, 1063 1063 + struct dce_hwseq *hws, 1064 1064 + unsigned int dpp_inst, 1065 1065 + bool power_on); 1066 1066 + 1067 1067 + void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, 1068 1068 + struct dce_hwseq *hws, 1069 1069 + unsigned int hubp_inst, 1070 1070 + bool power_on); 1071 1071 + 1072 1072 + void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, 1073 1073 + struct hubp *hubp, 1074 1074 + bool blank); 1075 1075 + 1076 1076 + void hwss_add_hubp_init(struct block_sequence_state *seq_state, 1077 1077 + struct hubp *hubp); 1078 1078 + 1079 1079 + void hwss_add_hubp_reset(struct block_sequence_state *seq_state, 1080 1080 + struct hubp *hubp); 1081 1081 + 1082 1082 + void hwss_add_dpp_reset(struct block_sequence_state *seq_state, 1083 1083 + struct dpp *dpp); 1084 1084 + 1085 1085 + void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, 1086 1086 + struct output_pixel_processor *opp, 1087 1087 + bool enable); 1088 1088 + 1089 1089 + void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, 1090 1090 + struct hubp *hubp, 1091 1091 + uint64_t sys_default, 1092 1092 + uint64_t sys_low, 1093 1093 + uint64_t sys_high); 1094 1094 + 1095 1095 + void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, 1096 1096 + struct hubp *hubp); 1097 1097 + 1098 1098 + void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, 1099 1099 + struct dccg *dccg, 1100 1100 + int dpp_inst, 1101 1101 + int dppclk_khz); 1102 1102 + 1103 1103 + void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, 1104 1104 + struct hubp *hubp, 1105 1105 + uint32_t otg_inst); 1106 1106 + 1107 1107 + void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, 1108 1108 + struct hubp *hubp, 1109 1109 + struct dml2_dchub_per_pipe_register_set *hubp_regs, 1110 1110 + union dml2_global_sync_programming *global_sync, 1111 1111 + struct dc_crtc_timing *timing); 1112 1112 + 1113 1113 + void hwss_add_hubp_setup(struct block_sequence_state *seq_state, 1114 1114 + struct hubp *hubp, 1115 1115 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 1116 1116 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 1117 1117 + struct _vcs_dpi_display_rq_regs_st *rq_regs, 1118 1118 + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 1119 1119 + 1120 1120 + void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, 1121 1121 + struct hubp *hubp, 1122 1122 + bool unbounded_req); 1123 1123 + 1124 1124 + void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, 1125 1125 + struct hubp *hubp, 1126 1126 + struct dml2_dchub_per_pipe_register_set *hubp_regs); 1127 1127 + 1128 1128 + void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, 1129 1129 + struct hubp *hubp, 1130 1130 + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 1131 1131 + struct _vcs_dpi_display_ttu_regs_st *ttu_regs); 1132 1132 + void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, 1133 1133 + struct hubp *hubp, 1134 1134 + enum surface_pixel_format format, 1135 1135 + struct dc_tiling_info *tiling_info, 1136 1136 + struct plane_size plane_size, 1137 1137 + enum dc_rotation_angle rotation, 1138 1138 + struct dc_plane_dcc_param *dcc, 1139 1139 + bool horizontal_mirror, 1140 1140 + int compat_level); 1141 1141 + 1142 1142 + void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, 1143 1143 + struct pipe_ctx *pipe_ctx); 1144 1144 + 1145 1145 + void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, 1146 1146 + struct dpp *dpp, 1147 1147 + enum dc_color_space color_space, 1148 1148 + struct dc_csc_transform *cursor_csc_color_matrix); 1149 1149 + 1150 1150 + void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, 1151 1151 + struct mpc *mpc, 1152 1152 + struct mpcc_blnd_cfg blnd_cfg, 1153 1153 + int mpcc_id); 1154 1154 + 1155 1155 + void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, 1156 1156 + struct mpc *mpc, 1157 1157 + int mpcc_id); 1158 1158 + 1159 1159 + void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, 1160 1160 + struct mpc *mpc, 1161 1161 + struct mpc_tree *mpc_tree_params, 1162 1162 + struct mpcc_blnd_cfg blnd_cfg, 1163 1163 + struct mpcc_sm_cfg *sm_cfg, 1164 1164 + struct mpcc *insert_above_mpcc, 1165 1165 + int dpp_id, 1166 1166 + int mpcc_id); 1167 1167 + 1168 1168 + void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, 1169 1169 + struct dpp *dpp, 1170 1170 + const struct scaler_data *scl_data); 1171 1171 + 1172 1172 + void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, 1173 1173 + struct hubp *hubp, 1174 1174 + const struct rect *viewport, 1175 1175 + const struct rect *viewport_c); 1176 1176 + 1177 1177 + void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, 1178 1178 + struct dc *dc, 1179 1179 + struct pipe_ctx *pipe_ctx); 1180 1180 + 1181 1181 + void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, 1182 1182 + struct dc *dc, 1183 1183 + struct pipe_ctx *pipe_ctx); 1184 1184 + 1185 1185 + void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, 1186 1186 + struct dc *dc, 1187 1187 + struct pipe_ctx *pipe_ctx); 1188 1188 + 1189 1189 + void hwss_add_program_output_csc(struct block_sequence_state *seq_state, 1190 1190 + struct dc *dc, 1191 1191 + struct pipe_ctx *pipe_ctx, 1192 1192 + enum dc_color_space colorspace, 1193 1193 + uint16_t *matrix, 1194 1194 + int opp_id); 1195 1195 + 1196 1196 + void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, 1197 1197 + struct hubp *hubp); 1198 1198 + 1199 1199 + void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, 1200 1200 + struct dc *dc, 1201 1201 + struct dc_state *context); 1202 1202 + 1203 1203 + void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, 1204 1204 + struct hubbub *hubbub); 1205 1205 + 1206 1206 + void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, 1207 1207 + struct hubbub *hubbub, 1208 1208 + bool allow, 1209 1209 + bool *disallow_self_refresh_applied); 1210 1210 + 1211 1211 + void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, 1212 1212 + struct timing_generator *tg, 1213 1213 + unsigned int *frame_count); 1214 1214 + 1215 1215 + void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, 1216 1216 + struct timing_generator *tg, 1217 1217 + struct dsc_optc_config *dsc_optc_cfg, 1218 1218 + bool enable); 1219 1219 + 1220 1220 + void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, 1221 1221 + struct output_pixel_processor *opp, 1222 1222 + enum dc_pixel_encoding pixel_encoding, 1223 1223 + bool is_otg_master); 1391 1224 1392 1225 #endif /* __DC_HW_SEQUENCER_H__ */

+36

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

reviewed

··· 27 27 #define __DC_HW_SEQUENCER_PRIVATE_H__ 28 28 29 29 #include "dc_types.h" 30 30 + #include "hw_sequencer.h" 30 31 31 32 enum pipe_gating_control { 32 33 PIPE_GATING_CONTROL_DISABLE = 0, ··· 81 80 void (*plane_atomic_disconnect)(struct dc *dc, 82 81 struct dc_state *state, 83 82 struct pipe_ctx *pipe_ctx); 83 83 + void (*plane_atomic_disconnect_sequence)(struct dc *dc, 84 84 + struct dc_state *state, 85 85 + struct pipe_ctx *pipe_ctx, 86 86 + struct block_sequence_state *seq_state); 84 87 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx); 88 88 + void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx, 89 89 + struct block_sequence_state *seq_state); 85 90 bool (*set_input_transfer_func)(struct dc *dc, 86 91 struct pipe_ctx *pipe_ctx, 87 92 const struct dc_plane_state *plane_state); ··· 104 97 void (*blank_pixel_data)(struct dc *dc, 105 98 struct pipe_ctx *pipe_ctx, 106 99 bool blank); 100 100 + void (*blank_pixel_data_sequence)(struct dc *dc, 101 101 + struct pipe_ctx *pipe_ctx, 102 102 + bool blank, 103 103 + struct block_sequence_state *seq_state); 107 104 enum dc_status (*enable_stream_timing)( 108 105 struct pipe_ctx *pipe_ctx, 109 106 struct dc_state *context, ··· 116 105 bool enable); 117 106 void (*setup_vupdate_interrupt)(struct dc *dc, 118 107 struct pipe_ctx *pipe_ctx); 108 108 + void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx, 109 109 + struct block_sequence_state *seq_state); 119 110 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); 120 111 void (*init_blank)(struct dc *dc, struct timing_generator *tg); 121 112 void (*disable_vga)(struct dce_hwseq *hws); ··· 125 112 void (*plane_atomic_power_down)(struct dc *dc, 126 113 struct dpp *dpp, 127 114 struct hubp *hubp); 115 115 + void (*plane_atomic_power_down_sequence)(struct dc *dc, 116 116 + struct dpp *dpp, 117 117 + struct hubp *hubp, 118 118 + struct block_sequence_state *seq_state); 128 119 void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx); 129 120 void (*enable_power_gating_plane)(struct dce_hwseq *hws, 130 121 bool enable); ··· 157 140 unsigned int dsc_inst); 158 141 void (*update_odm)(struct dc *dc, struct dc_state *context, 159 142 struct pipe_ctx *pipe_ctx); 143 143 + void (*update_odm_sequence)(struct dc *dc, struct dc_state *context, 144 144 + struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state); 160 145 void (*program_all_writeback_pipes_in_tree)(struct dc *dc, 161 146 const struct dc_stream_state *stream, 162 147 struct dc_state *context); 148 148 + void (*program_all_writeback_pipes_in_tree_sequence)( 149 149 + struct dc *dc, 150 150 + const struct dc_stream_state *stream, 151 151 + struct dc_state *context, 152 152 + struct block_sequence_state *seq_state); 163 153 bool (*s0i3_golden_init_wa)(struct dc *dc); 164 154 void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); 155 155 + void (*set_hdr_multiplier_sequence)(struct pipe_ctx *pipe_ctx, 156 156 + struct block_sequence_state *seq_state); 165 157 void (*verify_allow_pstate_change_high)(struct dc *dc); 158 158 + void (*verify_allow_pstate_change_high_sequence)(struct dc *dc, 159 159 + struct block_sequence_state *seq_state); 166 160 void (*program_pipe)(struct dc *dc, 167 161 struct pipe_ctx *pipe_ctx, 168 162 struct dc_state *context); 163 163 + void (*program_pipe_sequence)( 164 164 + struct dc *dc, 165 165 + struct pipe_ctx *pipe_ctx, 166 166 + struct dc_state *context, 167 167 + struct block_sequence_state *seq_state); 169 168 bool (*wait_for_blank_complete)(struct output_pixel_processor *opp); 170 169 void (*dccg_init)(struct dce_hwseq *hws); 171 170 bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx, ··· 196 163 void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx, 197 164 struct dc_state *context); 198 165 void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); 166 166 + void (*program_mall_pipe_config_sequence)(struct dc *dc, struct dc_state *context, 167 167 + struct block_sequence_state *seq_state); 199 168 void (*update_force_pstate)(struct dc *dc, struct dc_state *context); 200 169 void (*update_mall_sel)(struct dc *dc, struct dc_state *context); 201 170 unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx, ··· 221 186 void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx); 222 187 void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only); 223 188 void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx); 189 189 + void (*dc_ip_request_cntl)(struct dc *dc, bool enable); 224 190 }; 225 191 226 192 struct dce_hwseq {