tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP

Add clocks, resets and power domains for ADC IP available on the Renesas
RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20241206111337.726244-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Claudiu Beznea and committed by
Geert Uytterhoeven f9627452 548f9a3c

+7
+7
drivers/clk/renesas/r9a08g045-cpg.c
··· 187 187 DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), 188 188 DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), 189 189 DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2), 190 + DEF_FIXED("TSU", R9A08G045_CLK_TSU, CLK_PLL2_DIV2, 1, 8), 190 191 }; 191 192 192 193 static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { ··· 239 238 DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4), 240 239 DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5), 241 240 DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), 241 + DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), 242 + DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), 242 243 DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), 243 244 }; 244 245 ··· 277 274 DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), 278 275 DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), 279 276 DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), 277 + DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0), 278 + DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1), 280 279 DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), 281 280 }; 282 281 ··· 351 346 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0), 352 347 DEF_PD("scif5", R9A08G045_PD_SCIF5, 353 348 DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0), 349 + DEF_PD("adc", R9A08G045_PD_ADC, 350 + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0), 354 351 DEF_PD("vbat", R9A08G045_PD_VBAT, 355 352 DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), 356 353 GENPD_FLAG_ALWAYS_ON),