Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'gpio-v4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO fixes from Linus Walleij:
"A few overdue GPIO patches for the v4.12 kernel.
- Fix debounce logic on the Aspeed platform.
- Fix the "virtual gpio" things on the Intel Crystal Cove.
- Fix the blink counter selection on the MVEBU platform"
* tag 'gpio-v4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
gpio: mvebu: fix gpio bank registration when pwm is used
gpio: mvebu: fix blink counter register selection
MAINTAINERS: remove self from GPIO maintainers
gpio: crystalcove: Do not write regular gpio registers for virtual GPIOs
gpio: aspeed: Don't attempt to debounce if disabled
+47
-20
-1
MAINTAINERS
-1
MAINTAINERS
+3
drivers/gpio/gpio-aspeed.c
+3
drivers/gpio/gpio-aspeed.c
+36
-18
drivers/gpio/gpio-crystalcove.c
+36
-18
drivers/gpio/gpio-crystalcove.c
···
90
90
{
91
91
int reg;
92
92
93
-
if (gpio == 94)
94
-
return GPIOPANELCTL;
93
+
if (gpio >= CRYSTALCOVE_GPIO_NUM) {
94
+
/*
95
+
* Virtual GPIO called from ACPI, for now we only support
96
+
* the panel ctl.
97
+
*/
98
+
switch (gpio) {
99
+
case 0x5e:
100
+
return GPIOPANELCTL;
101
+
default:
102
+
return -EOPNOTSUPP;
103
+
}
104
+
}
95
105
96
106
if (reg_type == CTRL_IN) {
97
107
if (gpio < 8)
···
140
130
static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
141
131
{
142
132
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
133
+
int reg = to_reg(gpio, CTRL_OUT);
143
134
144
-
if (gpio > CRYSTALCOVE_VGPIO_NUM)
135
+
if (reg < 0)
145
136
return 0;
146
137
147
-
return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
148
-
CTLO_INPUT_SET);
138
+
return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
149
139
}
150
140
151
141
static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
152
142
int value)
153
143
{
154
144
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
145
+
int reg = to_reg(gpio, CTRL_OUT);
155
146
156
-
if (gpio > CRYSTALCOVE_VGPIO_NUM)
147
+
if (reg < 0)
157
148
return 0;
158
149
159
-
return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
160
-
CTLO_OUTPUT_SET | value);
150
+
return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
161
151
}
162
152
163
153
static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
164
154
{
165
155
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
166
-
int ret;
167
156
unsigned int val;
157
+
int ret, reg = to_reg(gpio, CTRL_IN);
168
158
169
-
if (gpio > CRYSTALCOVE_VGPIO_NUM)
159
+
if (reg < 0)
170
160
return 0;
171
161
172
-
ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
162
+
ret = regmap_read(cg->regmap, reg, &val);
173
163
if (ret)
174
164
return ret;
175
165
···
180
170
unsigned gpio, int value)
181
171
{
182
172
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
173
+
int reg = to_reg(gpio, CTRL_OUT);
183
174
184
-
if (gpio > CRYSTALCOVE_VGPIO_NUM)
175
+
if (reg < 0)
185
176
return;
186
177
187
178
if (value)
188
-
regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
179
+
regmap_update_bits(cg->regmap, reg, 1, 1);
189
180
else
190
-
regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
181
+
regmap_update_bits(cg->regmap, reg, 1, 0);
191
182
}
192
183
193
184
static int crystalcove_irq_type(struct irq_data *data, unsigned type)
194
185
{
195
186
struct crystalcove_gpio *cg =
196
187
gpiochip_get_data(irq_data_get_irq_chip_data(data));
188
+
189
+
if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
190
+
return 0;
197
191
198
192
switch (type) {
199
193
case IRQ_TYPE_NONE:
···
249
235
struct crystalcove_gpio *cg =
250
236
gpiochip_get_data(irq_data_get_irq_chip_data(data));
251
237
252
-
cg->set_irq_mask = false;
253
-
cg->update |= UPDATE_IRQ_MASK;
238
+
if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
239
+
cg->set_irq_mask = false;
240
+
cg->update |= UPDATE_IRQ_MASK;
241
+
}
254
242
}
255
243
256
244
static void crystalcove_irq_mask(struct irq_data *data)
···
260
244
struct crystalcove_gpio *cg =
261
245
gpiochip_get_data(irq_data_get_irq_chip_data(data));
262
246
263
-
cg->set_irq_mask = true;
264
-
cg->update |= UPDATE_IRQ_MASK;
247
+
if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
248
+
cg->set_irq_mask = true;
249
+
cg->update |= UPDATE_IRQ_MASK;
250
+
}
265
251
}
266
252
267
253
static struct irq_chip crystalcove_irqchip = {
+8
-1
drivers/gpio/gpio-mvebu.c
+8
-1
drivers/gpio/gpio-mvebu.c
···
747
747
set = U32_MAX;
748
748
else
749
749
return -EINVAL;
750
-
writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip));
750
+
writel_relaxed(set, mvebu_gpioreg_blink_counter_select(mvchip));
751
751
752
752
mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
753
753
if (!mvpwm)
···
768
768
mvpwm->chip.dev = dev;
769
769
mvpwm->chip.ops = &mvebu_pwm_ops;
770
770
mvpwm->chip.npwm = mvchip->chip.ngpio;
771
+
/*
772
+
* There may already be some PWM allocated, so we can't force
773
+
* mvpwm->chip.base to a fixed point like mvchip->chip.base.
774
+
* So, we let pwmchip_add() do the numbering and take the next free
775
+
* region.
776
+
*/
777
+
mvpwm->chip.base = -1;
771
778
772
779
spin_lock_init(&mvpwm->lock);
773
780